TWI501362B - Connection structure of multi-shape copper pillar bump and its bump forming method - Google Patents

Description

Polymorph copper pillar bump joint structure and bump forming method thereof

The present invention relates to a bump structure for a semiconductor device, and more particularly to a polymorph copper pillar bump bonding structure and a bump forming method thereof.

Early flip-chip bonding was performed using solder ball bonding, with a possible bump pitch of 130 microns (um). Recently, it has been proposed to use copper pillar bumps (CPB) as wafer-bonded micro contacts. The possible bump spacing is 70 micrometers (um) for wafers without reconfigured circuit layer design. Bonding applications for wafers such as TSV wafer stacks or other micro pitch bumps 3D. When the bump pitch needs to be further reduced, there are problems such as solder bridge and underfill void, and difficulty in designing the substrate wiring.

As shown in FIG. 1, a conventional copper stud bump bonding structure 300 mainly includes a wafer 310 and a substrate 350 bonded below. The wafer 310 has a plurality of pads 311, and a plurality of openings 314 of a surface protection layer 313 expose the pads 311. A plurality of under bump metal pads 320 are formed on the pads 311. A plurality of copper stud bumps 330 are bonded to the under bump metal pads 320. The copper stud bumps 330 are cylindrical or polygonal cylinders, and the joint faces 333 of the copper stud bumps 330 for the solder 340 are equal to the bottom cover areas of the copper stud bumps 330. And the substrate The upper surface 351 of the 350 is provided with a plurality of bump pads 352 and covers a solder mask layer 353. The solder mask layer 353 has a window 354 corresponding to the size of the wafer to expose the plurality of bump pads 352. . Solder 340 is soldered to the bump pads 352 to achieve bonding of the wafer 310 at the substrate 350. When the distance between the copper pillar bumps 330 is required to be further reduced, the solder 340 easily overflows and bridges to the adjacent copper pillar bumps 330 or adjacent to the bump pads 352 to cause an electrical short circuit, and the underfill is also difficult. The gap between the copper stud bumps 330 is filled to create a glue gap. Especially when the distance between the copper stud bumps is less than 60 microns, the wafer bonding yield will be significantly reduced.

In order to solve the above problems, the main object of the present invention is to provide a polymorph copper pillar bump bonding structure and a bump forming method thereof, which can make it easier to fill the underfill between the copper pillar bumps without solder. The problem of bridging is particularly suitable for micro-pitch copper bump bonding structures with copper pillar bumps less than 60 microns apart.

A second object of the present invention is to provide a polymorph copper pillar bump bonding structure and a bump forming method thereof, which can improve the external stress concentration on the bump of the copper pillar bump and cause the upper surface of the substrate to have more Multiple spaces for high-density line layout.

The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The invention discloses a polymorph copper pillar bump bonding structure, which comprises a wafer, a plurality of under bump metal pads, a plurality of copper pillar bumps, a plurality of solders and a substrate. The wafer has a plurality of pads, the pads are disposed on a semiconductor layer, and the semiconductor layer is covered with a surface protection layer having a plurality of first openings to reveal the Solder pad. The under bump metal pads are formed on the pads, and the under bump metal pads have an area larger than the first openings to partially cover the surface protective layer. The copper pillar bumps are disposed on Each of the copper pillar bumps is composed of a bottom layer of the same material and a narrowed column body, and the bottom layer of the pillars is joined to the underlying metal pads of the bumps, and each narrowed column body There is a joint surface smaller than the corresponding pad. The solder is formed on the joint surfaces and is not formed on the pillar bottom layers. The substrate has an upper surface, the upper surface is provided with a plurality of first line segments and covered with a solder mask layer, the solder mask layer having a plurality of second openings to expose the first line segments, The second openings are smaller than the bottom cover area of the bottom layers of the pillars and larger than the joint faces, and the joint faces are aligned in the second openings to allow the solders to be bonded to the first lines Road section. The invention further discloses a bump forming method of the polymorph copper pillar bump bonding structure.

In addition, the present invention further discloses, in different embodiments, a polymorph copper pillar bump bonding structure, which can replace the under bump metal layer as a plating seed layer in the process and the copper pillar bumps and the The problem of metal diffusion between the pads of the wafer is not serious, so the underlying metal pads of the bumps may be omitted, and the thickness of the bottom layers of the pillars is specifically determined to be between the heights of the bumps of the copper pillars. Ten to fifty percent.

The object of the present invention and solving the technical problems thereof can be further achieved by the following technical measures.

In the above-mentioned polymorphic copper stud bump bonding structure, the upper surface of the substrate may further comprise at least one second line segment between the first line segments and covered by the solder mask layer. The upper surface of the substrate is made to have a high density line layout and the solder does not stick to the second line segment.

In the above polymorphic copper pillar bump bonding structure, the height of the narrowed pillars may be greater than the thickness of the pillar bottom layers and greater than the thickness of the solder mask layer, thereby providing a larger bump gap filling space. , enriched with the bottom filling glue. Moreover, the thickness of the bottom layer of the pillars may be between ten and fifty percent of the height of the copper pillar bumps, and the narrowness can be achieved. The horizontal gap between the pillar body and the second openings is smaller than the vertical gap between the pillar bottom layer and the solder mask layer, and the solder is prevented from being extruded and adhered to the pillar bottom layers.

In the above-mentioned polymorphic copper pillar bump bonding structure, the thickness of the pillar bottom layer may be greater than the thickness of the underlying metal pad of the bump to provide a better stress tolerance of the bottom of the copper pillar bump and the same material, and Improve the bottom fracture problem of copper stud bumps.

In the above-mentioned polymorphic copper pillar bump bonding structure, the area of the bonding surfaces of the narrowed pillars may be less than one-half of the bottom coverage area of the pillar bottom layers, and the solder may be reduced in the The overflow of the second opening.

In the above-mentioned polymorphic copper pillar bump bonding structure, the bonding surfaces of the narrowing pillars may be formed with a barrier layer for preventing metal diffusion of the narrowed pillars by the solder. Produces the embrittlement of the tiny column joints.

In the above-mentioned polymorphic copper pillar bump bonding structure, the gap between the pillar bottom layers may be less than one-half of the same cutting width of the pillar bottom layers, and the gap between the narrowed pillars is greater than The narrowed columns are cut in the same direction, so the copper stud bumps can meet the requirements of more advanced micro-pitch copper pillar bumps.

In the above polymorphic copper pillar bump bonding structure, the distance between the copper pillar bumps may be less than 60 micrometers.

10‧‧‧First photoresist

11‧‧‧First photoresist hole

20‧‧‧second photoresist

21‧‧‧Second photoresist hole

30‧‧‧ bottom conduction surface

40‧‧‧ etching mask

100‧‧‧Multiple copper pillar bump joint structure

110‧‧‧ wafer

111‧‧‧ solder pads

112‧‧‧Semiconductor layer

113‧‧‧Surface protection layer

114‧‧‧First opening

120‧‧‧ under bump metal pad

121‧‧‧ under bump metal layer

130‧‧‧ copper pillar bumps

131‧‧ ‧ column bottom

132‧‧‧Narrowing the column

133‧‧‧ joint surface

134‧‧‧ barrier layer

140‧‧‧ solder

150‧‧‧Substrate

151‧‧‧ upper surface

152‧‧‧First line segment

153‧‧‧welding layer

154‧‧‧Second opening

155‧‧‧second line segment

200‧‧‧Multiple copper pillar bump joint structure

300‧‧‧Brond column bump joint structure

310‧‧‧ wafer

311‧‧‧ solder pads

313‧‧‧Surface protection layer

314‧‧‧ openings

320‧‧‧ under bump metal pad

330‧‧‧Bronze bumps

333‧‧‧ joint surface

340‧‧‧ solder

350‧‧‧Substrate

351‧‧‧ upper surface

352‧‧‧Bump pads

353‧‧‧welding layer

354‧‧‧Opening the window

Figure 1 is a partial cross-sectional view of a conventional copper stud bump joint structure.

Figure 2 is a partial cross-sectional view showing a multi-profile copper stud bump joint structure in accordance with a first embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a plurality of possible shapes of copper stud bumps of the polyhedral copper stud bump joint structure according to the first embodiment of the present invention; The top view is schematic.

4 is a schematic view showing a part of a top surface of a substrate of the polymorph copper pillar bump bonding structure according to the first embodiment of the present invention.

5A to 5G are schematic cross-sectional views showing a partial element of each step in the bump forming method of the polymorph copper stud joint structure according to the first embodiment of the present invention.

Figure 6 is a partial cross-sectional view showing another polymorph copper stud bump joint structure in accordance with a second embodiment of the present invention.

7A to 7G are cross-sectional views showing a partial element of each step in the bump forming method of the polymorph copper stud joint structure according to the first embodiment of the present invention.

The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which FIG. The components and combinations related to this case, the components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some size ratios are proportional to other related sizes or have been exaggerated or simplified to provide clearer description of. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated.

According to a first embodiment of the present invention, a polymorph copper stud bump joint structure is illustrated in a partial cross-sectional view of Fig. 2. The polymorph copper stud bump structure 100 includes a wafer 110, a plurality of under bump metal pads 120, a plurality of copper stud bumps 130, a plurality of solders 140, and a substrate 150.

The wafer 110 has a plurality of pads 111 disposed on a semiconductor layer 112. The pads 111 are the wafers The original design endpoint of the integrated circuit component on the active surface of 110 may be a fan-out pad that is connected by a reconfigured circuit layer. Moreover, the semiconductor layer 112 is covered with a surface protection layer 113 having a plurality of first openings 114 to expose the pads 111. The surface protection layer 113 may be a single layer or a plurality of passivation layers or insulating layers made by a wafer process, such as tantalum nitride, benzocyclobutene (BCB), polyimine (PI), or the like.

The under bump metal pads 120 are formed on the pads 111 , and the under bump metal pads 120 have an area larger than the first openings 114 to partially cover the surface protection layer 113 . The under bump metal pads 120 are formed on the wafer 110 by techniques such as physical vapor deposition, chemical vapor deposition, or sputtering of an integrated circuit process and wafer level etching operations. The under bump metal pads 120 may be a multi-layer metal deposition layer, which may be made of titanium copper, tungsten copper or titanium nickel vanadium. Generally, the under bump metal pad 120 has a thickness of 0.5 to 8 micrometers, that is, is not equal to or greater than 10 micrometers, that is, less than one tenth of the height of the copper pillar bumps 130, and includes at least one layer. A barrier material different in material from the copper stud bumps 130.

The copper stud bumps 130 are disposed on the pads 111, and each of the copper stud bumps 130 is composed of a pillar bottom layer 131 of the same material and a narrowed pillar 132. The material of the copper stud bumps 130 may be copper or a copper alloy. In a specific application, the distance between the copper stud bumps 130 may be less than 60 microns. The pillar bottom layer 131 is bonded to the under bump metal pads 120. Generally, the pillar bottom layer 131 may have a thickness greater than the thickness of the under bump metal pads 120 to provide the bottom of the copper pillar bumps 130. The same stress tolerance of the material is used to improve the bottom fracture problem of the conventional copper stud bump. Generally, the thickness of the pillar bottom layer 131 is between ten and fifty percent of the height of the copper pillar bumps 130. Moreover, each of the narrowed columns 132 has a joint surface 133 that is smaller than the corresponding pads 111. In this embodiment, the areas of the joint faces 133 of the narrowed columns 132 may be smaller than the bottom layers of the columns. One-half of the footprint of 131 reduces the overflow of the solder 140 at the second openings 154. The bottom cover area of the pillar bottom layer 131 is such that the pillar bottom layer 131 covers the area of the under bump metal pad 120. In this embodiment, the bottom cover areas of the pillar bottom layers 131 are the same as the bump under metal pads 120. The height of the copper stud bumps 130 is the vertical distance from the surface protection layer 113 to the bumps of the joint surface 133.

FIG. 3 is a schematic top view showing various possible shapes of the copper stud bumps 130. Depending on the requirements of the product, the joint surfaces 133 formed by the narrowed columns 132 of the copper studs 130 and the bottom cover areas of the pillar bottom layers 131 may have different shape changes. As shown in FIG. 3(A), the pillar bottom layers 131 may be circular with a larger diameter, and the joint surfaces 133 of the narrowed pillars 132 may be circular with a smaller diameter. As shown in FIG. 3(B), the pillar bottom layers 131 may be circular with larger diameters, and the joint surfaces 133 of the narrowed pillars 132 may be squares of smaller length and width. As shown in FIG. 3(C), the pillar bottom layers 131 may be squares of a larger length and a width, and the joint surfaces 133 of the narrowed pillars 132 may be circular with a smaller diameter. As shown in FIG. 3D, the pillar bottom layer 131 can be a square of a larger length and a width, and the joint surfaces 133 of the narrowed pillars 132 can be four of a smaller length and a width. Square. Under an ideal condition, regardless of the shape of the pillar bottom layer 131 and the joint surfaces 133, the pillar bottom layers 131 are larger than the corresponding second openings 154 of the solder mask layer 153 of the lower bonding substrate 150, the joint surfaces. The 133 is smaller than the corresponding second opening 154 of the solder mask layer 153 of the lower bonding substrate 150, and the best effect can be achieved.

In addition, the solders 140 are formed on the bonding surfaces 133 and are not formed on the pillar bottom layers 131. The material of the solder 140 may specifically be a lead-free solder such as tin silver or a lead solder. The solder 140 The volume should not be such that the solder 140 forms a spherical shape during reflow, at most a semi-circular surface. Under the area limitation of the joint faces 133, the volume of the solder 140 will be greatly reduced. Preferably, the bonding surfaces 133 of the narrowing columns 132 are formed with a barrier layer 134, such as nickel, and a gold layer is flash-plated on the surface to prevent the soldering of the solder 140. The metal of the column body 132 is diffused to cause an embrittlement of the micro-column joint.

The substrate 150 serves as a carrier for the wafer 110. The substrate 150 can be a small printed circuit board, a ceramic circuit board, a flexible circuit board, a dummy wafer, or a wafer. The substrate 150 has an upper surface 151 which is provided with a plurality of first line segments 152 and is covered with a solder mask layer 153. The solder mask layer 153 has a plurality of second openings 154 to expose the substrate 150. The first line segments 152 are smaller than the bottom cover areas of the pillar bottom layers 131 and larger than the joint surfaces 133. The joint surfaces 133 are aligned with the second openings 154. So that the solder 140 is bonded to the first line segments 152 and does not overflow to the adjacent stud bumps and the adjacent first line segments 152.

FIG. 4 is a schematic view showing a part of the upper surface of the substrate 150. Preferably, as shown in FIGS. 2 and 4, the upper surface 151 of the substrate 150 may further include at least one second line segment 155 between the first line segments 152 and soldered. The cover layer 153 is covered such that the upper surface 151 of the substrate 150 becomes a high density line layout and the solder 140 does not stick to the second line segment 155.

In a preferred embodiment, the height of the narrowed pillars 132 may be greater than the thickness of the pillar bottom layers 131 and greater than the thickness of the solder mask layer 153, thereby providing a larger bump gap filling space. Fill in with Eli's underfill. Moreover, the thickness of the pillar bottom layer 131 may be between ten and fifty percent of the height of the copper pillar bumps 130, and the narrowed pillars 132 to the second openings may be achieved. The horizontal gap of the hole 154 is smaller than the The vertical gap between the pillar bottom layer 131 and the solder mask layer 153 prevents the solder 140 from being extruded and adhered to the pillar bottom layers 131.

In the specific structure, the gap between the pillar bottom layers 131 may be less than one-half of the same cutting width of the pillar bottom layers 131, and the gap between the narrowed pillars 132 is greater than the narrowing. The pillars 132 are cut to the same width, so the copper pillar bumps 130 can meet the requirements of more advanced micro-pitch copper pillar bumps. The distance between the copper pillar bumps 130 is the horizontal distance from the center point of one copper pillar bump 130 to the center point of another adjacent copper pillar bump 130, which is equal to the gap between one pillar bottom layer 131 plus one pillar. The sum of the same cut widths of the bottom layer 131 is also equal to the sum of the gap between the narrowed columns 132 and the same cut width of the narrowed columns 132. Therefore, when the distance between the copper pillar bumps 130 is not more than 60 micrometers (um), the same direction of the pillar bottom layer 131 can be up to 40 micrometers (um), and the gap between the pillar bottom layers 131 The narrowing column 132 can be folded to a width of 30 micrometers (um), and the gap between the narrowed columns 132 can be expanded to Not less than 30 microns (um).

Therefore, the first embodiment of the present invention provides a polymorph copper pillar bump bonding structure 100, which makes it easier to fill the underfill between the copper pillar bumps 130 without bridging the solder 140. The problem of wafer bonding yield can be improved by the problem of adjacent copper pillar bumps 130 and adjacent first wiring segments 152. This structure is particularly suitable for micro-pitch copper pillar bump bonding structures with copper pillar bumps less than 60 micrometers apart. In addition, the external stress is further concentrated on the bump breakage caused by the bottom of the conventional copper stud bump, and the upper surface 151 of the substrate 150 has more space for the high-density line layout.

5A-5G illustrate a method of forming the copper stud bumps 130 of the polymorph copper stud bump structure 100. As shown in FIG. 5A, a wafer 110 is provided having a plurality of pads 111 disposed on a semiconductor layer 112 and covered on the semiconductor layer 112. There is a surface protective layer 113 having a plurality of first openings 114 for exposing the pads 111; and as shown in FIG. 5A, using physical vapor deposition, chemical vapor deposition, or sputtering The plating method forms an under bump metal layer 121 on the pads 111 and the surface protection layer 113. As shown in FIG. 5B, a first photoresist 10 is formed on the under bump metal layer 121, and the first photoresist 10 has a plurality of first lights by photolithography or exposure development. The apertures 11 are sized and positioned to correspond to the pillar bottom layers 131 that are to be formed. As shown in FIG. 5C, the first pattern plating is performed according to the shape of the first photoresist hole 11 and the electrical conduction of the under-metal layer 121 to form a plurality of copper pillar bumps 130. A plurality of column bottom layers 131 are on the under bump metal layer 121. As shown in FIG. 5D, after cleaning and removing the first photoresist 10, a second photoresist 20 is formed on the under bump metal layer 121 and the pillar underlayers 131, and the second photoresist 20 is provided. A plurality of second photoresist holes 21 are sized and positioned to correspond to the narrowed columns 132 that are to be formed. As shown in FIG. 5E, a second patterning is performed according to the shape of the second photoresist holes 21 and the electrical conduction of the under-metal layer 121, to form the copper pillar bumps 130 by electroplating. The plurality of narrowed columns 132 are on the column bottom layers 131. Each of the narrowing columns 132 has a joint surface 133 smaller than the corresponding first opening 114. Thereafter, the same second photoresist 20 can be used for plating. A plurality of solders 140 are formed on the bonding surfaces 133 and are not formed on the pillar bottom layers 131. Before forming the solders 140, a barrier layer 134 is preferably plated on the narrowing pillars 132. . As shown in FIG. 5F, after the second photoresist 20 is removed, the under bump metal layer 121 may be exposed outside the bottom coverage area of the pillar bottom layer 131; after that, the under bump metal may be etched. The layer 121 is formed in a region other than the bottom cover area of the pillar bottom layer 131 to form a plurality of under bump metal pads 120, and the solder 140 may be reflowed into an arc shape (as shown in FIG. 5G).

According to a second embodiment of the present invention, another polymorphic copper stud bump joint structure is illustrated in a partial cross-sectional view of Fig. 6. Elements having the same names as those of the first embodiment will be given the same names, and the detailed structure thereof will not be described. The poly-type copper stud bump bonding structure 200 includes a wafer 110, a plurality of copper stud bumps 130, a plurality of solders 140, and a substrate 150. Each of the copper stud bumps 130 is composed of a pillar bottom layer 131 of the same material. It is composed of a narrowed column 132. Since the pillar bottom layer 131 can replace the under bump metal layer as a plating seed layer in the process, the metal diffusion problem between the copper pillar bumps 130 and the pads 111 of the wafer 110 is not serious. Therefore, the under bump metal pad can be omitted, and the thickness of the pillar bottom layer 131 is specifically limited to be between ten and fifty percent of the height of the copper pillar bumps 130.

The wafer 110 has a plurality of pads 111. The pads 111 are disposed on a semiconductor layer 112. The semiconductor layer 112 is covered with a surface protection layer 113. The surface protection layer 113 has a plurality of first layers. The holes 114 are opened to expose the pads 111.

The pillar bumps 130 are disposed on the pads 111, and the pillars 131 are bonded to the pads 111. Each of the narrow pillars 132 has a bonding surface 133 smaller than the corresponding pads 111. The thickness of the pillar bottom layer 131 is between ten and fifty percent of the height of the copper pillar bumps 130.

The solders 140 are formed on the bonding surfaces 133 and are not formed on the pillar bottom layers 131. The substrate 150 has an upper surface 151 which is provided with a plurality of first line segments 152 and is covered with a solder mask layer 153. The solder mask layer 153 has a plurality of second openings 154 to expose the substrate 150. The first line segments 152 are smaller than the bottom cover areas of the pillar bottom layers 131 and larger than the joint surfaces 133. The joint surfaces 133 are aligned with the second openings 154. To make the solder 140 Bonded to the first line segments 152.

More specifically, the thickness of the pillar bottom layer 131 is more than 15 to 35 percent of the height of the copper pillar bumps 130. For example, when the height of the copper stud bumps 130 is 40 micrometers (um), the thickness of the pillar bottom layers 131 can be controlled to be 10 micrometers (um).

Therefore, the second embodiment of the present invention provides a polymorph copper pillar bump bonding structure 200, which makes it easier to fill the underfill between the copper pillar bumps 130 without bridging the solder 140. The problem of adjacent copper stud bumps 130 and adjacent first line segments 152 is particularly applicable to micro-pitch copper stud bump joints having a copper pillar bump spacing of less than 60 microns. In addition, the external stress is further concentrated on the bump breakage caused by the bottom of the conventional copper stud bump, and the upper surface 151 of the substrate 150 has more space for the high-density line layout.

7A to 7G illustrate a method of forming the copper stud bumps 130 of the polymorph copper stud bump structure 200. As shown in FIG. 7A, a wafer 110 is provided having a plurality of pads 111 disposed on a semiconductor layer 112, and the semiconductor layer 112 is covered with a surface protection layer 113. The protective layer 113 has a plurality of first openings 114 to expose the pads 111. As shown in FIG. 7B, a pillar bottom conduction surface 30 may be formed on the pads 111 and the surface by vapor deposition, electroless plating (chemical plating), or copper foil thermocompression bonding. On the layer 113, the pillar bottom conducting surface 30 comprises a plurality of pillar bottom layers 131 of a plurality of copper pillar bumps 130 integrally connected, and the thickness of the pillar bottom conducting surface 30 corresponds to the thickness of the pillar bottom layer 131 to be subsequently formed. As shown in FIG. 7C, a photoresist 20 is formed on the pillar bottom conducting surface 30, and the photoresist 20 has a plurality of photoresist apertures 21 corresponding in size and position to the predetermined narrowed pillars. 132. As shown in FIG. 7D, according to the shape of the photoresist holes 21 and the electrical conduction of the pillar bottom conduction surface 30, patterning is performed to form A plurality of narrowed columns 132 of the plurality of copper studs 130 are formed on the bottom conductive surface 30. Each of the narrowed columns 132 has a joint surface 133 smaller than the corresponding first opening 114 and is associated with the column. The bottom conductive surface 30 is made of the same material; after that, a plurality of solders 140 may be formed on the bonding surfaces 133 instead of the pillar bottom conducting surface 30; before forming the solders 140, it is preferable to form a barrier first. Layer 134 is on the narrowed columns 132. As shown in FIG. 7E, a plurality of etch masks 40 are formed by the exposure and development techniques of the photoresist to cover the narrowed pillars 132 and the pillar bottom conductive surfaces 30 around the narrowed pillars 132. The coverage area of the etch masks 40 corresponds to the area of the pillar bottom layer 131 to be formed. As shown in FIG. 7F, under the protection of the etch mask 40, the pillar bottom conducting surface 30 is etched in a region other than the bottom coverage area of the pillar bottom layer 131 to form the pillar bottom layer 131 (eg, 7G is shown), and the solder 140 can be reflowed into an arc shape.

The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention. Any simple modifications, equivalent changes and modifications made without departing from the technical scope of the present invention are still within the technical scope of the present invention.

100‧‧‧Multiple copper pillar bump joint structure

110‧‧‧ wafer

111‧‧‧ solder pads

112‧‧‧Semiconductor layer

113‧‧‧Surface protection layer

114‧‧‧First opening

120‧‧‧ under bump metal pad

130‧‧‧ copper pillar bumps

131‧‧ ‧ column bottom

132‧‧‧Narrowing the column

133‧‧‧ joint surface

134‧‧‧ barrier layer

140‧‧‧ solder

150‧‧‧Substrate

151‧‧‧ upper surface

152‧‧‧First line segment

153‧‧‧welding layer

154‧‧‧Second opening

155‧‧‧second line segment

Claims (15)

A polylithic copper stud bump bonding structure comprising: a wafer having a plurality of pads disposed on a semiconductor layer, and the semiconductor layer is covered with a surface protective layer, the surface protective layer The plurality of first openings are formed to expose the pads; the plurality of under bump metal pads are formed on the pads, and the under bump metal pads have an area larger than the first openings Partially covering the surface protective layer; a plurality of copper stud bumps are disposed on the solder pads, each of the copper stud bumps is composed of a bottom layer of the same material and a narrowed column body, The bottom layer of the pillar is bonded to the under bump metal pads, each narrowed pillar body has a joint surface smaller than the corresponding solder pads; a plurality of solders are formed on the joint surfaces and are not formed on the pillar bottom layers And a substrate having an upper surface, the upper surface is provided with a plurality of first line segments and covered with a solder mask layer, the solder mask layer having a plurality of second openings to expose the first lines a section of the second opening that is smaller than the bottom of the column Bottom coverage area and greater than the plurality of bonding surface, the plurality of bonding lines is aligned within the plurality of second openings, so that the plurality of first solder bonding to the plurality of line segments. The polymorphic copper pillar bump bonding structure according to claim 1, wherein the upper surface of the substrate is further provided with at least one second line segment which is located between the first line segments and is soldered The cover is covered. The polymorph copper stud bump joint structure according to claim 1, wherein the height of the narrowed columns is greater than the thickness of the bottom layer of the pillars and greater than the thickness of the solder mask layer, and the thickness of the pillar bottom layers The height is between ten and fifty percent of the height of the copper stud bumps between. The polymorph copper stud bump joint structure according to claim 3, wherein the thickness of the pillar bottom layer is greater than the thickness of the under bump metal mat. The polymorph copper stud bump joint structure according to claim 1, wherein the area of the joint faces of the narrowed columns is less than one-half of the bottom cover area of the bottom layers of the columns. According to the polymorphic copper pillar bump bonding structure of claim 1, wherein the bonding surfaces of the narrowing cylinders are formed with a barrier layer. According to the polymorphic copper pillar bump joint structure of claim 1, wherein the gap between the bottom layers of the pillars is less than one-half of the same cutting width of the pillar bottom layers, and the narrowed columns are The gap is greater than the same cut width of the narrowed cylinders. The polymorph copper stud bump joint structure according to claim 1, wherein the copper pillar bumps are less than 60 micrometers apart. A method for forming a bump of a polymorph copper bump bonding structure, comprising: providing a wafer having a plurality of pads, wherein the pads are disposed on a semiconductor layer, and the semiconductor layer is covered with a surface protection The surface protective layer has a plurality of first openings for exposing the pads; forming a bump underlying metal layer on the pads and the surface protective layer; forming a plurality of copper stud bumps The bottom layer of the pillar is on the underlying metal layer of the bump; a plurality of narrowed pillars forming the copper pillar bumps are formed on the bottom layer of the pillars, and each narrowed pillar body has a joint smaller than the corresponding first opening The surface is the same material as the bottom layer of the pillars; a plurality of solders are formed on the joint surfaces and are not formed on the bottoms of the pillars And etching a region of the under bump metal layer outside the bottom cover area of the pillar bottom layer to form a plurality of under bump metal pads. The method for forming a bump according to the ninth aspect of the invention, wherein the step of forming the narrowed pillars of the copper pillar bumps on the pillar bottom layer comprises forming a The barrier layer is on the joint faces of the narrowed columns. A polylithic copper stud bump bonding structure comprising: a wafer having a plurality of pads disposed on a semiconductor layer, and the semiconductor layer is covered with a surface protective layer, the surface protective layer The system has a plurality of first openings for exposing the pads; a plurality of copper stud bumps are disposed on the pads, each of the copper studs being composed of a bottom layer and a narrowing column of the same material The bottom layer of the column is joined to the pads, each of the narrowed columns has a joint surface smaller than the corresponding pads, and the thickness of the bottom layers of the columns is between the heights of the copper pillar bumps. Between 10% and 50%; a plurality of solders are formed on the joint surfaces and not formed on the bottom layers of the pillars; and a substrate has an upper surface, the upper surface is provided a plurality of first line segments covered with a solder mask layer, the solder mask layer having a plurality of second openings for exposing the first line segments, the second openings being smaller than the bottom cover of the bottom layers of the columns The area is larger than the joint surfaces, and the joint surfaces are aligned with the first The opening, so that the plurality of first solder bonding to the plurality of line segments. The polymorph copper stud bump joint structure according to claim 11, wherein the thickness of the pillar bottom layer is more than 15 to 35 percent of the height of the copper pillar bumps. The poly-type copper stud bump joint structure according to claim 11, wherein the joint faces of the narrowed columns are formed with a barrier layer. The polymorph copper stud bump joint structure according to claim 11, wherein the copper pillar bumps are less than 60 micrometers apart. A method for forming a bump of a polymorph copper bump bonding structure, comprising: providing a wafer having a plurality of pads, wherein the pads are disposed on a semiconductor layer, and the semiconductor layer is covered with a surface protection a layer, the surface protection layer has a plurality of first openings to expose the pads; a pillar bottom conduction surface is formed on the pads and the surface protection layer, and the pillar bottom conduction surface comprises an integral connection a plurality of column bottom layers of a plurality of copper stud bumps; a plurality of narrowed columns forming the copper stud bumps are formed on the bottom conductive surface of the column, each narrowed column body having a smaller than the corresponding first opening The bonding surface is the same material as the pillar bottom conducting surface; forming a plurality of solders on the bonding surfaces without forming the pillar bottom conducting surface; and pattern etching the pillar bottom conducting surface to form the pillar bottom layers.