TW202315085A - 3d and flash memory device and method of fabricating the same - Google Patents

Abstract

A three-dimensional AND flash memory device includes a stack structure, isolators, channel pillars, source pillars and drain pillars, and charge storage structures. The stack structure is located on a dielectric substrate and includes gate layers and insulating layers alternately stacked with each other. The isolators divide the stack structure into sub-blocks and include walls and slits. The walls include isolation layers and the insulating layers stacked alternately with each other, and the isolation layers are buried in the gate layers. The slits alternate with the walls, and each of the slits extends through the stack structure. The channel pillars extend through the stack structure in each of the sub-blocks. The source pillars and the drain pillars are located in the channel pillars. The charge storage structures are located between the gate layers and the channel pillar.

Description

Three-dimensional AND flash memory device and manufacturing method thereof

The present invention relates to a semiconductor element and its manufacturing method, and in particular to a three-dimensional AND flash memory element and its manufacturing method.

Non-volatile memory has the advantage that the stored data will not disappear after power failure, so it is widely used in personal computers and other electronic devices. The 3D memory commonly used in the industry currently includes Negative OR (NOR) memory and Negative AND (NAND) memory. In addition, another type of three-dimensional memory is an AND memory, which can be applied in a multi-dimensional memory array and has high integration and high area utilization, and has the advantage of fast operation speed. Therefore, the development of three-dimensional memory components has gradually become a current trend.

The invention provides a three-dimensional AND flash memory element and its manufacturing method, which can reduce the tilt or collapse of stacked structures.

An embodiment of the present invention proposes a three-dimensional AND flash memory device, comprising: a stack structure located on a dielectric substrate, wherein the stack structure includes a plurality of gate layers and a plurality of insulating layers stacked alternately with each other; a plurality of A divider, which separates the stacked structure into a plurality of sub-blocks, and the plurality of dividers include: a plurality of stacking walls, including a plurality of separation layers and the plurality of insulating layers stacked alternately with each other, wherein the plurality of separation layers buried in the plurality of gate layers; a plurality of separation slits alternating with the plurality of stack walls, wherein each separation slit extends through the plurality of gate layers of the stack structure and the plurality of insulating layers; a plurality of channel columns extending through the stacked structure of each sub-block; a plurality of source columns and a plurality of drain columns located in the plurality of channel columns, and with the plurality of channel columns The plurality of channel pillars are electrically connected; and a plurality of charge storage structures are located between the plurality of gate layers and the channel pillars.

An embodiment of the present invention provides a three-dimensional AND flash memory device, comprising: forming a stack structure on a dielectric substrate, wherein the stack structure includes a plurality of intermediate layers and a plurality of insulating layers stacked alternately; forming a plurality of channel pillars extending through the stack structure; forming a plurality of source pillars and a plurality of drain poles electrically connected to the plurality of channel pillars in the plurality of channel pillars; patterning the stack structure to forming a plurality of separation trenches in the stack structure, each separation trench extending through the plurality of intermediate layers and the plurality of insulating layers of the stack structure; partially removing the plurality of intermediate layers , to form a plurality of horizontal openings, wherein the portions of the plurality of intermediate layers that are not removed form a plurality of separation layers, and the plurality of separation layers and the plurality of insulating layers form a plurality of stacked walls, the plurality of separation trenches alternate with the plurality of stack walls, and separate the stack structure into a plurality of sub-blocks; a plurality of gate layers are formed in the plurality of horizontal openings, wherein each separation layer is sandwiched between the Between the plurality of gate layers; forming a plurality of charge storage structures, located between the plurality of gate layers and the channel column; and forming a plurality of separation slits in the plurality of separation trenches, wherein the The plurality of separation slits alternate with the plurality of stacking walls, and separate the stacking structure into a plurality of sub-blocks.

Based on the above, in the embodiment of the present invention, the intermediate layer is left as a separator, which can reduce the number of separation trenches, thereby avoiding the collapse of the stacked structure.

The gate of the three-dimensional flash memory is formed by performing a gate replacement process on the intermediate layer in the stacked structure of the insulating layer and the intermediate layer. However, after the interlayer is removed, the stacked structure is poorly structured and supportive, often tilted or collapsed, which leads to misalignment in the subsequent formation of global bit line (GBL) contact windows, resulting in The formed contacts are short-circuited with the top gate layer. In the embodiment of the present invention, part of the middle layer is left as a separation layer, which can form a stacking wall together with insulating layers above and below it. The stack wall can be used as a support structure together with the channel pillar to prevent the stack structure from tilting or collapsing, thus improving the yield and avoiding the short circuit between the contact window and the top gate layer.

Figure 1A shows a circuit diagram of a 3D AND flash memory array according to some embodiments. FIG. 1B shows a top view of a 3D AND flash memory array according to some embodiments. FIG. 1C shows a partial three-dimensional view of the simplified portion of the memory array in FIG. 1B. Fig. 1D shows a cross-sectional view along line I-I' of Fig. 1C. Fig. 1E shows a top view of the line II-II' of Fig. 1C, Fig. 1D.

FIG. 1A is a schematic diagram of two sub-blocks BLOCK ⁽ⁱ⁾ and BLOCK ⁽ⁱ⁺¹⁾ including a vertical AND memory array 10 arranged in columns and rows. The sub-block BLOCK ⁽ⁱ⁾ includes the memory array A ⁽ⁱ⁾ . A column (eg column m+1) of the memory array A ⁽ⁱ⁾ is a set of AND memory cells 20 having a common word line (eg WL ⁽ⁱ⁾ _m+1 ). The AND memory cells 20 of each column (eg column m+1) correspond to a common word line (eg WL ⁽ⁱ⁾ _m+1 ), and are coupled to different source columns (eg SP ⁽ⁱ⁾ _n and SP ⁽ⁱ⁾ _n+1 ) and drain poles (such as DP ⁽ⁱ⁾ _n and DP ⁽ⁱ⁾ _n+1 ), so that the AND memory cell 20 is along a common word line (such as WL ⁽ⁱ⁾ _m+1 ) Logically arranged into a column.

A row (eg row n ⁾ of the memory array A ^{( i} ) is a set of AND memory cells 20 having a common source column (eg SP ^{( i )} _n ) and a common drain column (eg DP ^{( i )} _n ). The AND memory cells 20 in each row (eg row n) correspond to different word lines (eg WL ^{( i )} _m+1 and WL ^{( i )} _m ), and are coupled to a common source column (eg SP ^{( i )} _n ) and a common drain column (such as DP ^{( i )} _n ), so that the AND memory cell 20 is connected along a common source column (such as SP ^{( i )} _n ) and a common drain column (such as DP ^{( i )} _n ) are logically arranged in one line. In a physical layout, the rows or columns may be distorted, arranged in a honeycomb pattern or otherwise, for high density or for other reasons, depending on the fabrication method applied.

In FIG. 1A, in the sub-block BLOCK ⁽ⁱ⁾ , the AND memory cells 20 in the nth row of the memory array A ⁽ⁱ⁾ share a common source column (for example, SP ^{( i )} _n ) and a common drain column. (e.g. DP ^{( i )} _n ). The AND memory cells 20 in row n+1 share a common source column (eg SP ⁽ⁱ⁾ _n+1 ) and a common drain column (eg DP ^{( i )} _n+1 ) and are coupled to a common bit line (eg BL _n+1 ).

In some embodiments, sub-block BLOCK ⁽ⁱ⁺¹⁾ includes memory array A ⁽ⁱ⁺¹⁾ similar to memory array A ⁽ⁱ⁾ in sub-block BLOCK ⁽ i). A column (eg column ^{m+1) of the memory array A (i} +1) is a set of AND memory cells 20 having a common word line (eg WL ⁽ⁱ⁺¹⁾ _m+1 ). The AND memory cells 20 of each column (eg column m+1) correspond to a common word line (eg WL ⁽ⁱ⁺¹⁾ _m+1 ), and are coupled to different source columns (eg SP ^{(i+ 1)} _n and SP ⁽ⁱ⁺¹⁾ _n+1 ) and drain legs (eg DP ⁽ⁱ⁺¹⁾ _n and DP ⁽ⁱ⁺¹⁾ _n+1 ). A row (for example, row n) of memory array A ^{( i+1 )} is an AND with a common source column (for example, SP ^{( i+1 )} _n ) and a common drain column (for example, DP ^{( i+1 )} _n ) A collection of memory units 20 . The AND memory cells 20 in each row (eg row n) correspond to different word lines (eg WL ^{( i+1 )} _m+1 and WL ^{( i+1 )} _m ), and are coupled to a common source column (eg SP ^{( i+1 )} _n ) and a common drain column (eg DP ^{( i+1 )} _n ), so that the AND memory cell 20 is connected to a common source column (eg SP ^{( i+1 )} _n ) Drain posts (eg DP ^{( i+1 )} _n ) are logically arranged in a row.

The sub-blocks BLOCK ⁽ⁱ⁺¹⁾ and the sub-blocks BLOCK ⁽ⁱ⁾ share source lines (such as SL _n and SL _n+1 ) and bit lines (such as BL _n and BL _n+1 ). Therefore, the source line SL _n and the bit line BL _n are coupled to the n-th row of AND memory cells 20 in the AND memory array of the sub-block BLOCK ⁽ⁱ⁾ , and are coupled to the sub-block BLOCK ⁽ⁱ⁺¹⁾ The AND memory unit 20 of the nth row in the AND memory array. Similarly, the source line SL _n+1 and the bit line BL _n+1 are coupled to the n+1th row of AND memory cells 20 in the AND memory array of the sub-block BLOCK ⁽ⁱ⁾ , and are coupled to the sub-block The AND memory unit 20 in the n+1th row of the AND memory array in BLOCK ⁽ⁱ⁺¹⁾ .

Referring to FIG. 1B , the memory array 10 may include a plurality of partitions SEP to divide the gate stack structure 52 into a plurality of sub-blocks B, such as sub-block B1 and sub-block B2 . The partition SEP of the present invention includes a plurality of stacked walls STW and a plurality of separation slits SLT arranged alternately in the Y direction. The stack walls STW are of different insulating material than the separation slots SLT. The insulating material may include an organic insulating material, an inorganic insulating material, or a combination thereof. The stacked wall STW is a stacked structure formed by stacking a plurality of separation layers 56 and a plurality of insulating layers 54 , as shown in FIG. 1D . Materials of the separation layer 56 and the insulating layer 54 are, for example, silicon nitride and silicon oxide. The separation slit SLT is, for example, silicon oxide. Each sub-block B1 and B2 may include a gate stack structure 52 disposed on a dielectric substrate 50, a plurality of channel pillars 16, a plurality of conductor pillars (also referred to as source pillars) 32a and a plurality of conductor pillars (also referred to as source pillars) 32a and a plurality of conductor pillars (also called may be referred to as a drain post) 32b and a plurality of charge storage structures 40, as shown in FIG. 1C.

Referring to FIG. 1B and FIG. 1C , the memory array 10 can be disposed in the back end of line (BEOL) of semiconductor die. For example, the memory array 10 may be disposed in an interconnect structure of a semiconductor die, such as disposed over one or more active devices (eg, transistors) formed on a semiconductor substrate. Therefore, the dielectric substrate 50 is, for example, a dielectric layer, such as a silicon oxide layer, formed above the metal interconnect structure on the silicon substrate. The dielectric substrate 50 may include an array region AR and a stepped region SR.

Referring to FIG. 1B and FIG. 1C , the gate stack structure 52 is formed on the dielectric substrate 50 in the array region AR and the step region SR. The gate stack structure 52 includes a plurality of gate layers (also referred to as word lines) 38 and multiple layers of insulating layers 54 vertically stacked on the surface of the dielectric substrate 50 . In the Z direction, the gate layers 38 are electrically isolated by an insulating layer 54 disposed between them. Gate layer 38 extends in a direction parallel to the surface of dielectric substrate 50 (shown in FIG. 1D ). The gate layer 38 in the stepped region SR may have a stepped structure SC (shown in FIG. 1B ), so that the lower gate layer 38 is longer than the upper gate layer 38 and the end of the lower gate layer 38 extends laterally out of the upper end of gate layer 38 . The contact C1 for connecting the gate layer 38 may land on the end of the gate layer 38 so as to connect each gate layer 38 to each wire.

Referring to FIG. 1B to FIG. 1E , the memory array 10 further includes a plurality of channel pillars 16 . The channel pillar 16 extends continuously through the gate stack structure 52 of the array region AR. In some embodiments, the channel post 16 may have a ring-shaped profile when viewed from above. The material of the channel pillar 16 can be semiconductor, such as undoped polysilicon.

Please refer to FIG. 1C to FIG. 1E, the memory array 10 further includes an insulating filling layer 24, an insulating column 28, a plurality of conductor columns (also called source columns) 32a and a plurality of conductor columns (also called drain columns) 32b. The conductive columns 32 a and 32 b and the insulating column 28 are disposed in the channel column 16 and each extends in a direction perpendicular to the gate layer 38 (ie, the Z direction). The conductive pillars 32 a and 32 b are separated from the insulating pillar 28 by the insulating filling layer 24 , and are electrically coupled to the channel pillar 16 . The conductive pillars 32a and 32b are, for example, doped polysilicon. The insulating pillar 28 is, for example, silicon nitride.

Referring to FIG. 1D , the charge storage structure 40 is disposed between the channel pillar 16 and the multilayer gate layer 38 . The charge storage structure 40 may include a tunneling layer (or called a bandgap engineered tunnel oxide layer) 14 , a charge storage layer 12 and a blocking layer 36 . The charge storage layer 12 is located between the tunneling layer 14 and the blocking layer 36 . In some embodiments, the tunneling layer 14 , the charge storage layer 12 and the blocking layer 36 are, for example, silicon oxide, silicon nitride, and silicon oxide. In some embodiments, a part of the charge storage structure 40 (the tunneling layer 14 ) extends continuously in a direction perpendicular to the gate layer 38 (ie, the Z direction), while another part of the charge storage structure 40 (the charge storage layer 12 and The barrier layer 36) surrounds the gate layer 38, as shown in FIG. 1D

Referring to FIG. 1E , the gate layer 38 and the surrounding charge storage structure 40 , the channel pillar 16 , and the source pillar 32 a and the drain pillar 32 b define the memory cell 20 . The memory unit 20 can perform 1-bit operation or 2-bit operation through different operation methods. For example, when a voltage is applied to the source column 32a and the drain column 32b, since the source column 32a and the drain column 32b are connected to the channel column 16, electrons can be transmitted along the channel column 16 and stored in the entire charge storage In the structure 40, a 1-bit operation can be performed on the memory unit 20 in this way. In addition, for the operation utilizing Fowler-Nordheim tunneling, electrons or holes can be trapped in the charge storage structure 40 between the source post 32a and the drain post 32b. . For source side injection, channel-hot-electron injection, or band-to-band tunneling hot carrier injection, electrons can be Or the holes are locally trapped in the charge storage structure 40 adjacent to one of the two source posts 32a and drain posts 32b, so that the unit cell (SLC, 1 bit) or multiple Bit cell (MLC, greater than or equal to 2 bits) operations.

In operation, a voltage is applied to a selected word line (gate layer) 38 , such as when a corresponding threshold voltage (V _th ) higher than that of the corresponding memory cell 20 is applied, intersecting the selected word line 38 The channel region of the channel column 16 is turned on, allowing current to enter the drain column 32b from the bit line BL _n or BL _n+1 (shown in FIG. 1C ) and flow to the source column 32a (eg , in the direction indicated by the arrow 60 ), finally flows to the source line SL _n or SL _n+1 (shown in FIG. 1C ).

Referring to FIG. 1B , the gate layer 38 is formed by removing the intermediate layer in the stacked structure of the insulating layer 54 and the intermediate layer, and through a gate replacement process. In the present invention, part of the plurality of intermediate layers is left as the spacer layer 56 . The separation layer 56 and the insulating layer 54 are stacked to form a stacking wall STW between the sub-blocks B. As shown in FIG.

The partition layer 56 of the stack wall STW extends continuously in the X direction with the partition slit SLT. In some embodiments, the separation layer 56 of the stack wall STW extends continuously in the array region AR and extends to the step region SR. In some other embodiments, the separation layer 56 of the stack wall STW extends continuously in the array area AR, but does not extend to the stepped area SR. That is, the length L1 of the partition layer 56 of the stack wall STW in the X direction is smaller than or equal to the length L2 of the partition slit SLT in the X direction.

Furthermore, the width W1 of the partition layer 56 of the stack wall STW in the Y direction is smaller than or equal to the width W2 of the partition slit SLT in the Y direction. The height H1 of the partition layer 56 of the stack wall STW in the Z direction is smaller than or equal to the height H2 of the partition slit SLT in the Z direction, as shown in FIG. 1D . Furthermore, the separation layer 56 of the stack wall STW has a different profile than the separation slit SLT. Seen from above, the partition layer 56 of the stack wall STW has a curved profile, while the partition slit SLT is roughly rectangular, as shown in FIG. 1B .

In the present invention, the remaining separation layer 56 can be used together with the insulating layer 54 as the stacking wall STW between the sub-blocks B. Therefore, the separation layer 56 can be used as a supporting structure to reduce the separation used to form the separation slit SLT. The number of trenches prevents the stack structure from toppling or collapsing due to the removal of the intermediate layer during the gate replacement process.

The method of forming the stacked wall STW can be described in detail with reference to FIGS. 2A to 2G and FIGS. 3A to 3E . 2A to 2G are schematic cross-sectional views of a three-dimensional AND flash memory device according to an embodiment of the present invention. 2C to 2G are cross-sectional views of line IV-IV' in FIGS. 3A to 3E . Figures 3A to 3E show top views of the line III-III' of Figures 2C to 2G. FIG. 4 shows a top view of a partition of a three-dimensional AND flash memory device. FIG. 5 shows a perspective view of a three-dimensional AND flash memory device.

Referring to FIG. 2A , a dielectric substrate 100 is provided. The dielectric substrate 100 is, for example, a dielectric layer of a metal interconnect structure formed on a silicon substrate, such as a silicon oxide layer. The dielectric substrate 100 includes an array region AR and a stepped region SR. A stack structure SK1 is formed on the dielectric substrate 100 in the array region AR and the step region SR. The stack structure SK1 can also be called an insulating stack structure SK1. In this embodiment, the stack structure SK1 is composed of insulating layers 104 and intermediate layers 106 stacked on the dielectric substrate 100 in sequence. In other embodiments, the stack structure SK1 may be formed by the intermediate layer 106 and the insulating layer 104 that are sequentially stacked on the dielectric substrate 100 . In addition, in this embodiment, the uppermost layer of the stack structure SK1 is the insulating layer 104 . The insulating layer 104 is, for example, a silicon oxide layer. The middle layer 106 is, for example, a silicon nitride layer. The intermediate layer 106 can be used as a sacrificial layer, which is partially removed in subsequent processes. In this embodiment, the stack structure SK1 has 8 insulating layers 104 and 7 intermediate layers 106 , but the invention is not limited thereto. In other embodiments, more insulating layers 104 and more intermediate layers 106 can be formed according to actual needs.

In some embodiments, before forming the stack structure SK1 , the insulating layer 101 , the stop layer 102 and the conductive layer 103 are first formed on the dielectric substrate 100 . The insulating layer 101 is, for example, silicon oxide. A stopper layer 102 is formed in the insulating layer 101 . The stop layer 102 is, for example, a conductive pattern, such as a polysilicon pattern. The conductive layer 103 is, for example, a grounded polysilicon layer. The conductive layer 103 can also be called a dummy gate, which can be used to close the leakage path.

The stacked structure SK1 is patterned to form a stepped structure SC in the stepped region SR (as shown in FIG. 3A and FIG. 5 ).

Next, referring to FIG. 2B and FIG. 3A , a plurality of openings 108 are formed in the stack structure SK1 of the array area AR. In the present embodiment, the opening 108 extends through the conductive layer 103 , and the bottom surface thereof exposes the stopper layer 102 and the insulating layer 101 , but the invention is not limited thereto. In this embodiment, from the above perspective, the opening 108 has a circular outline, but the invention is not limited thereto. In other embodiments, the opening 108 may have other shaped contours, such as a polygon (not shown).

Referring to FIG. 2B and FIG. 3A , a tunneling layer 114 and a channel column 116 are formed in the opening 108 . The tunneling layer is, for example, a silicon oxide layer. The material of the channel pillar 116 can be a semiconductor, such as undoped polysilicon. The method for forming the tunneling layer 114 and the channel pillar 116 is, for example, forming a tunneling material layer and a channeling material layer on the stack structure SK1 and in the opening 108 . Next, an etch-back process is performed to partially remove the tunneling material layer and the channel material layer to form the tunneling layer 114 and the channel pillar 116 . The tunneling layer 114 and the channel pillar 116 cover the sidewall of the opening 108 , exposing the bottom of the opening 108 . The tunneling layer 114 and the channel pillar 116 can extend through the stack structure SK1 and extend into the insulating layer 101 . The channel column 116 is, for example, ring-shaped in a top view, and may be continuous in its extending direction (eg, in a direction perpendicular to the dielectric substrate 100 ). That is to say, the channel column 116 is integral in its extending direction, and is not divided into a plurality of disconnected parts. In some embodiments, the channel post 116 may have a circular profile viewed from above, but the invention is not limited thereto. In other embodiments, the channel column 116 may also have other shapes (such as polygonal) contours from the above perspective.

In this embodiment, the tunneling layer 114 of the charge storage structure 140 is formed in the opening 108, and the storage layer 112 and the blocking layer 136 of the charge storage structure 140 are formed in the horizontal opening 134 during the gate replacement process. As shown in Figure 2F.

Referring to FIG. 2B and FIG. 3A , an insulating filling layer 124 and insulating pillars 128 are formed in the opening 108 . The material of the insulating filling layer 124 is, for example, silicon oxide; the material of the insulating pillar 128 is, for example, silicon nitride. When the insulating filling layer 124 fills the opening 108 , before it is completely filled and leaves a hole, an insulating material different from the insulating filling layer 124 is filled to completely seal the opening 108 . After the insulating material is etched back to expose the surface of the insulating filling layer 124 through the dry etching or wet etching process, the insulating material remaining in the center of the opening 108 forms the insulating pillar 128 .

Referring to FIG. 2C and FIG. 3A , patterning processes, such as lithography and etching processes, are performed to form holes 130 a and 130 b in the insulating filling layer 124 . During the etching process, the stop layer 102 can be used as an etch stop layer. Therefore, the formed holes 130 a and 130 b extend from the stack structure SK1 to the exposed stop layer 102 . The contour of the hole pattern defined by the patterning process may be tangent to the contour of the insulating pillar 128 . The contour of the hole pattern defined by the patterning process may also exceed the contour of the insulating pillar 128 . Since the etching rate of the insulating pillar 128 is lower than that of the insulating filling layer 124 , the insulating pillar 128 is hardly damaged by etching and remains. In addition, in some embodiments, the contour of the hole pattern defined by the patterning process exceeds the contour of the opening 108 , so that the holes 130 a and 130 b expose part of the top insulating layer 104 of the stacked structure SK1 .

Referring to FIG. 3A , in some embodiments, dummy pillars 118 are also formed in the stepped region SR. The dummy pillar 118 can be used as a supporting pillar in the subsequent gate replacement process. The dummy pillar 118 may be formed simultaneously when the tunneling layer 114 , the channel pillar 116 , the insulating filling layer 124 and the insulating pillar 128 are formed. Dummy pillars 118 may also be additionally formed. The number of dummy columns 118 can be determined according to needs. In some embodiments, the dummy pillars 118 in the step region SR are staggered with each other, and the distance D2 between the dummy pillars 118 in the step region SR is greater than or equal to the distance D1 between the channel pillars 116, and its density is lower than that in the array The density of channel pillars 116 of region AR.

Referring to FIG. 2C and FIG. 3A, conductor posts 132a and 132b are formed in the holes 130a and 130b. The conductor posts 132 a and 132 b can be used as source posts and drain posts respectively, and are electrically connected to the channel posts 116 respectively. The conductive pillars 132a and 132b may be formed by forming a conductive layer on the insulating filling layer 124 and in the holes 130a and 130b, and then etching back. The conductor pillars 132a and 132b are, for example, doped polysilicon. The radial dimensions of the conductor posts 132a and 132b can be the same or different. The line connecting the centers of the conductor columns 132a and 132b may form an acute angle with the Y direction (as shown in FIG. 3A ); or be parallel to the Y direction (not shown), that is, perpendicular to the subsequent separation slit SLT (as shown in FIG. 3E ). Show). In addition, the channel pillars 116 in two adjacent columns may be staggered (as shown in FIG. 3A to FIG. 3E ) or aligned with each other (not shown).

Afterwards, referring to FIGS. 2D to 2G and FIGS. 3B to 3E , a replacement process is performed to replace the multi-layer intermediate layer 106 with a multi-layer gate layer 138 and the like. First, referring to FIG. 2D and FIG. 3B , a patterning process, such as lithography and etching process, is performed on the stack structure SK1 to form a plurality of separation trenches 133 . During the etching process, the conductive layer 103 can be used as an etching stop layer, so that the separation trench 133 exposes the conductive layer 103 .

Referring to FIG. 3B , the separation trench 133 extends along the X direction to divide the stacked structure SK1 of the array region AR and the step region SR into a plurality of blocks TB. Each block TB includes a stack structure SK2 , a plurality of channel pillars 116 , and components located in the plurality of channel pillars 116 , such as conductor pillars 132 a and 132 b , tunneling layer 114 , insulating filling layer 124 and insulating pillar 128 . The area of the block TB of the present invention is more than twice the area of the subsequently formed sub-block B, and has a lower aspect ratio.

Next, referring to FIG. 2E and FIG. 3C , an etching process, such as a wet etching process, is performed to remove part of the multi-layer intermediate layer 106 . The etchant (such as hot phosphoric acid) used in the etching process is injected into the separation trench 133 , and then the contacted portion of the multi-layer intermediate layer 106 is removed. Therefore, the interlayer layers 106 closer to the separation trenches 133 are removed first, and the interlayer layers 106 farther away from the separation trenches 133 are removed slower. During the etching process, when the multi-layer intermediate layer 106 between the channel column 116 and the separation trench 133 is removed, since the materials of the tunneling layer 114 and the intermediate layer 106 are different, the tunneling layer 114 can be used as Etch stop layer to protect the channel pillar 116 . The etching process is continued, and most of the multi-layer intermediate layer 106 is removed by controlling the time mode, so as to form a stacked structure SK3 of a plurality of horizontal openings 134 . The portion of the intermediate layer 106 a farther from the separation trench 133 is left to form the separation layer 156 . The remaining spacer layer 156 is located between the two horizontal openings 134, as shown in Figure 2E.

In some embodiments, the density of the dummy pillars 118 in the stepped region SR is lower, and thus, the etch rate is higher. The density of the channel pillars 116 in the array region AR is relatively high, the flow rate of the etchant is relatively low, and the etching rate is relatively low, and the multi-layer intermediate layer 106 a farthest from the separation trench 133 is left. Therefore, the width of the separation layer 156 in the step region SR and the array region AR is different (not shown). Additionally, in some embodiments, spacer layer 156 has a curved profile. The size of the remaining separation layer 156 can not only be controlled by the etching time, but also can be adjusted by the size and density of the dummy pillars 118 in the step region SR and the size and density of the channel pillars 116 in the array region AR. to control the etch rate of the intermediate layer 106 in the step region SR and the array region AR.

The separation layers 156 and the insulating layers 104 are stacked alternately in the Z direction to form a stacking wall STW. Therefore, the stacking wall STW, together with the channel column 116 and the dummy column 118 can be used as a supporting structure to prevent the stacking structure SK3 from tilting or collapsing, as shown in FIG. 2E and FIG. 3C .

In addition, the block TB is divided into two sub-blocks B (eg, sub-blocks B1 and B2 ) because the multi-layer intermediate layer 106 a and the insulating layer 104 can serve as the stacking wall STW. The position of the stacked wall STW does not need to form the separation trench 133 first, therefore, the number of the separation trench 133 can be reduced, and the block TB with a large cross-sectional area and a small aspect ratio is reserved to avoid the stacking structure of the sub-block B. If the cross-sectional area is too small and the aspect ratio is too large, it will tilt or collapse, as shown in Figure 4 and Figure 5.

Referring to FIG. 2F and FIG. 3D , a multilayer storage layer 112 , a multilayer barrier layer 136 and a gate layer 138 are formed in a plurality of horizontal openings 134 . The storage layer 112 is, for example, silicon nitride. The barrier layer 136 is, for example, a material with a high dielectric constant greater than or equal to 7, such as aluminum oxide (Al ₁ O ₃ ), hafnium oxide (HfO ₂ ), lanthanum oxide (La ₂ O ₅ ), transition metal oxide , lanthanide oxides, or combinations thereof. The gate layer 138 is, for example, tungsten. In some embodiments, before forming the multilayer gate layer 138 , a barrier layer 137 is also formed. The material of the barrier layer 137 is, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or a combination thereof.

The method for forming the storage layer 112, the barrier layer 136, the barrier layer 137, and the gate layer 138 is, for example, sequentially forming a storage material layer, a barrier material layer, a barrier material layer, and a conductor in the separation trench 133 and the horizontal opening 134. material layer, and then perform an etch-back process to remove the storage material layer, the barrier material layer, the barrier material layer and the conductor material layer in the plurality of separation trenches 133, so as to form the storage layer 112 in the plurality of horizontal openings 134 , barrier layer 136 , barrier layer 137 and gate layer 138 . The blocking layer 136 , the tunneling layer 114 and the storage layer 112 are collectively referred to as the charge storage structure 140 . So far, the gate stack structure 150 is formed. The gate stack structure 150 is disposed on the dielectric substrate 100 and includes multiple gate layers 138 and multiple insulating layers 104 stacked alternately. A spacer layer 156 is buried in the gate layer 138 . Two sides of the spacer layer 156 are adjacent to the gate layer 138 , as shown in FIG. 2F .

Referring to FIG. 2G and FIG. 3E , a separation slit SLT is formed in the separation trench 133 . The method for forming the separation slit SLT includes filling the insulating material on the gate stack structure 150 and the separation trench 133 , and then removing excess insulating material on the gate stack structure 150 through an etch-back process or a planarization process. insulating material such as silicon oxide. The separation slit SLT is in contact with the adjacent storage layer 112 , the gate layer 138 and the insulating layer 104 and has an interface 133I. The separation layer 156 in the stack wall STW is in contact with the adjacent storage layer 112 and has an interface 156I; and the insulating layer 104 above and below the separation layer 156 in the stack wall STW extends continuously to the storage layer 112 below. That is, the interface 133I extends continuously in the Z direction; while the interface 156I extends discontinuously in the Z direction. A plurality of stacked walls STW and a plurality of separation slits SLT arranged alternately in the Y direction separate the gate stack structure 150 into a plurality of sub-blocks B. Referring to FIG. The plurality of stack walls STW together with the plurality of separation slits SLT form a partition SEP. The length of the separation layer 156 in the stepped region SR is less than or equal to the length of the separation slit SLT in the stepped region SR, as shown in FIG. 5 .

Referring to FIG. 3E , afterward, a contact window C1 is formed in the stepped region SR. The contact C1 lands on the end of the gate layer 138 of the step region SR and is electrically connected thereto.

The above embodiments are illustrated with 3D AND flash memory. However, the embodiments of the present invention are not limited thereto, and the embodiments of the present invention can also be applied to 3D NOR flash memory or 3D NAND flash memory.

In the embodiment of the present invention, when the gate replacement process is performed, part of the intermediate layer is left as a spacer layer. Therefore, it can be integrated with the existing process without adding process steps, and the process variation can be effectively controlled by the etching process. Furthermore, these spacer layers may form stacked walls together with insulating layers. The stack wall can be used as a support structure together with the channel column to prevent the stack structure from tilting or collapsing, thus improving the yield rate and avoiding misalignment due to the tilt of the stack structure in the subsequent formation of the bit line (GBL) contact window. , thus causing the formed contact window to be short-circuited with the top gate layer.

10. A ⁽ⁱ⁾ , A ⁽ⁱ⁺¹⁾ : memory array 12: charge storage layer 14, 114: tunneling layer 15, 56, 156: separation layer 16, 116: channel column 20: memory unit 24, 124: Insulation filling layer 28, 128: insulating column 32a: source column/conductor column 32b: drain column/conductor column 36, 136: barrier layer 38, 138: gate layer/word line 40, 140: charge storage structure 50 , 100: dielectric substrate 52, 150: gate stack structure 54, 101, 104: insulating layer 60: arrow 102: stop layer 103: conductor layer 106, 106a: intermediate layer 108: opening 112: storage layer 118: dummy Columns 130a, 130b: holes 132a, 132b: conductor columns 133: separation trenches 133I, 156I: interfaces 134: horizontal openings 137: barrier layer AR: array regions B, B1, B2, BLOCK, BLOCK ⁽ⁱ⁾ , BLOCK ^{( i+1)} : sub-block BL _n , BL _n+1 : bit line C1 : contact window D1, D2 : distance SP ^{( i )} _n , SP ⁽ⁱ⁾ _n+1 , SP ^{( i+1 )} _n , SP ⁽ⁱ⁺¹⁾ _n+1 : source pole DP ⁽ⁱ⁾ _n , DP ⁱ⁾ _n+1 , DP ⁱ⁺¹⁾ _n , DP ⁽ⁱ⁺¹⁾ _n+1 : source pole H1, H2: Height X, Y, Z: Direction L1, L2: Length NAND, NOR: D SC: Ladder structure SEP: Divider SK2, SK2, SK3: Stacking structure SLT: Separation slit SR: Ladder area STW: Stacking wall TB: Area Block W1, W2: width WL ⁽ⁱ⁾ _m , WL ⁽ⁱ⁾ _m+1 , WL ⁽ⁱ⁺¹⁾ _m , WL ⁽ⁱ⁺¹⁾ _m+1 : word line X, Y, Z: direction I- I', II-II', III-III', IV-IV': tangent

Figure 1A shows a circuit diagram of a 3D AND flash memory array according to some embodiments. FIG. 1B shows a top view of a 3D AND flash memory array according to some embodiments. FIG. 1C shows a partial three-dimensional view of the simplified portion of the memory array in FIG. 1B. Fig. 1D shows a cross-sectional view along line I-I' of Fig. 1C. Fig. 1E shows a top view of the line II-II' of Fig. 1C, Fig. 1D. 2A to 2G are schematic cross-sectional views of a three-dimensional AND flash memory device according to an embodiment of the present invention. 2C to 2G are cross-sectional views of line IV-IV' in FIGS. 3A to 3E . Figures 3A to 3E show top views of the line III-III' of Figures 2C to 2G. FIG. 4 shows a top view of a partition of a three-dimensional AND flash memory device. FIG. 5 shows a perspective view of a three-dimensional AND flash memory device.

B, B1, B2: sub-blocks

100: Dielectric substrate

101, 104: insulating layer

102: stop layer

103: conductor layer

106a: middle layer

112: storage layer

114: Tunneling layer

116: channel column

124: insulating filling layer

128: Insulation column

132a, 132b: conductor post

133: separation groove

134: horizontal opening

156:Separation layer

SK3: stacked structure

STW: Stacked Wall

III-III': Tangent

Y, Z: direction

Claims (10)

A three-dimensional AND flash memory element, comprising: a stack structure located on the dielectric substrate, wherein the stack structure includes a plurality of gate layers and a plurality of insulating layers alternately stacked on each other; A plurality of partitions, separating the stacked structure into a plurality of sub-blocks, the plurality of partitions comprising: a plurality of stacked walls, including a plurality of spacer layers and the plurality of insulating layers alternately stacked with each other, wherein the plurality of spacer layers are buried in the plurality of gate layers; a plurality of separation slits alternating with the plurality of stack walls, wherein each separation slit extends through the plurality of gate layers and the plurality of insulating layers of the stack structure; a plurality of channel columns extending through the stacked structure of each sub-block; A plurality of source posts and a plurality of drain posts are located in the plurality of channel posts and electrically connected with the plurality of channel posts; and A plurality of charge storage structures are located between the plurality of gate layers and the channel column. The three-dimensional AND flash memory device as claimed in claim 1, wherein each spacer layer has a curved profile. The three-dimensional AND flash memory element as claimed in claim 1, wherein the length of each separation layer is less than or equal to the length of each separation slit; the width of each separation layer is less than or equal to the The width of each separating slit. The three-dimensional AND flash memory device as claimed in claim 1, wherein the material of the plurality of separation layers is different from that of the separation slit. The three-dimensional AND flash memory device according to claim 1, wherein two sides of each spacer layer are adjacent to the plurality of gate layers. The three-dimensional AND flash memory device as claimed in claim 1, wherein each sidewall of the plurality of separation layers is in contact with the charge storage structure. A method for manufacturing a three-dimensional AND flash memory element, comprising: forming a stack structure on the dielectric substrate, wherein the stack structure includes a plurality of intermediate layers and a plurality of insulating layers stacked alternately with each other; forming a plurality of channel columns extending through the stack; forming a plurality of source columns and a plurality of drain columns electrically connected to the plurality of channel columns in the plurality of channel columns; patterning the stack structure to form a plurality of separation trenches in the stack structure, each separation trench extending through the plurality of intermediate layers and the plurality of insulating layers of the stack structure; partially removing the plurality of intermediate layers to form a plurality of horizontal openings, wherein the unremoved portions of the plurality of intermediate layers form a plurality of separation layers, the plurality of separation layers and the plurality of insulating layers forming a plurality of stacked walls, the plurality of separation grooves and the plurality of stacked walls alternate with each other, and separate the stacked structure into a plurality of sub-blocks; forming a plurality of gate layers in the plurality of horizontal openings, wherein each spacer layer is sandwiched between the plurality of gate layers; forming a plurality of charge storage structures between the plurality of gate layers and the channel pillar; and A plurality of separation slits are formed in the plurality of separation trenches, wherein the plurality of separation slits and the plurality of stacking walls alternate with each other, and separate the stacked structure into a plurality of sub-blocks. The manufacturing method of the three-dimensional AND flash memory element as claimed in item 7, wherein the length of each of the separation layers is less than or equal to the length of each separation slit; the width of each separation layer is less than or equal to It is equal to the width of each separating slit. The method for manufacturing a three-dimensional AND flash memory device as claimed in claim 7, wherein the material of the plurality of separation layers is different from the material of the separation slits. The method for manufacturing a three-dimensional AND flash memory device as claimed in claim 7, wherein a plurality of sidewalls of each of the separation layers are exposed to the plurality of horizontal openings.

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