TW202312408A - 扇出封裝 - Google Patents
扇出封裝 Download PDFInfo
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- TW202312408A TW202312408A TW111129492A TW111129492A TW202312408A TW 202312408 A TW202312408 A TW 202312408A TW 111129492 A TW111129492 A TW 111129492A TW 111129492 A TW111129492 A TW 111129492A TW 202312408 A TW202312408 A TW 202312408A
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- die
- redistribution
- side bonding
- semiconductor die
- semiconductor
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- 239000004065 semiconductor Substances 0.000 claims abstract description 350
- 239000000463 material Substances 0.000 claims abstract description 256
- 229910052751 metal Inorganic materials 0.000 claims description 76
- 239000002184 metal Substances 0.000 claims description 76
- 238000002955 isolation Methods 0.000 claims 1
- 230000001568 sexual effect Effects 0.000 claims 1
- 229910000679 solder Inorganic materials 0.000 abstract description 123
- 230000015572 biosynthetic process Effects 0.000 abstract description 5
- 238000009827 uniform distribution Methods 0.000 abstract 1
- 239000000758 substrate Substances 0.000 description 72
- 239000010410 layer Substances 0.000 description 52
- 229920006336 epoxy molding compound Polymers 0.000 description 32
- 238000000034 method Methods 0.000 description 30
- 239000012790 adhesive layer Substances 0.000 description 23
- 150000001875 compounds Chemical class 0.000 description 21
- 238000004806 packaging method and process Methods 0.000 description 16
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 14
- 229910052802 copper Inorganic materials 0.000 description 14
- 239000010949 copper Substances 0.000 description 14
- 239000011159 matrix material Substances 0.000 description 14
- 230000003068 static effect Effects 0.000 description 13
- 238000006243 chemical reaction Methods 0.000 description 9
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 8
- 230000008569 process Effects 0.000 description 8
- 239000000853 adhesive Substances 0.000 description 6
- 230000001070 adhesive effect Effects 0.000 description 6
- 239000007769 metal material Substances 0.000 description 6
- 238000000465 moulding Methods 0.000 description 6
- 239000004593 Epoxy Substances 0.000 description 5
- 239000013078 crystal Substances 0.000 description 5
- 239000003822 epoxy resin Substances 0.000 description 5
- 239000012778 molding material Substances 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 229920000647 polyepoxide Polymers 0.000 description 5
- 238000000137 annealing Methods 0.000 description 4
- 239000000203 mixture Substances 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 4
- 239000007787 solid Substances 0.000 description 4
- 238000009826 distribution Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000000945 filler Substances 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 230000000737 periodic effect Effects 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 238000004380 ashing Methods 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 230000001788 irregular Effects 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 239000011295 pitch Substances 0.000 description 2
- 229920002577 polybenzoxazole Polymers 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000002861 polymer material Substances 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 238000007493 shaping process Methods 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 230000035882 stress Effects 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- 239000004820 Pressure-sensitive adhesive Substances 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 239000002313 adhesive film Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005272 metallurgy Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000004848 polyfunctional curative Substances 0.000 description 1
- NGVDGCNFYWLIFO-UHFFFAOYSA-N pyridoxal 5'-phosphate Chemical compound CC1=NC=C(COP(O)(O)=O)C(C=O)=C1O NGVDGCNFYWLIFO-UHFFFAOYSA-N 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
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- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
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- H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
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- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
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Abstract
一種扇出封裝,包括:一重分布結構、複數個半導體晶粒以及一底部填充材料部分。半導體晶粒包括透過焊料材料部分的各自一組而附接至重分佈側結合結構的各自一子集的晶粒側結合結構的各自一組。底部填充材料部分橫向地環繞半導體晶粒的重分布側結合結構及半導體晶粒的晶粒側結合結構。重分布側結合結構的一子集不結合至半導體晶粒的任何晶粒側結合結構,且被底部填充材料部分橫向地環繞,且用以在底部填充材料部分的形成期間提供底部填充材料的均勻分布。
Description
本揭露實施例係有關於一種半導體結構,特別係有關於一種用於半導體晶粒封裝中底部填充應用的虛設(dummy)金屬結合墊及其形成方法。
扇出型晶圓級封裝(fan-out wafer level package ,FOWLP)和模塑化合物材料部分之間的界面,在後續處理扇出型晶圓級封裝、底部填充材料部分和封裝基板的組件(例如:封裝基板至印刷電路板(printed circuit board,PCB)的附接)期間,承受機械應力。此外,扇出型晶圓級封裝和底部填充材料部分之間的界面在計算裝置內的使用期間會承受機械應力,例如:當扇出型晶圓級封裝在使用期間變熱並且扇出型晶圓級封裝組件的熱膨脹失配導致熱應力時,或者當行動裝置在使用過程中意外掉落造成機械衝擊。裂紋可形成在底部填充材料中,並且可能在半導體晶粒、焊料材料部分、重分布結構及/或半導體晶粒內或封裝基板內的各種介電層中引起額外的裂紋。因此,需要抑制底部填充材料中裂紋的形成。
根據本揭露的一些實施例,一種扇出封裝包括:一重分布結構、複數個半導體晶粒以及一底部填充材料部分。重分布結構在一側上包括複數個第一金屬結合結構。複數個半導體晶粒包括透過複數個凸塊部分而附接至第一金屬結合結構的複數個第二金屬結合結構。底部填充材料部分橫向地環繞第一金屬結合結構及半導體晶粒的第二金屬結合結構。第一金屬結合結構的一子集包括至少一個虛設金屬結合結構,被底部填充材料部分環繞並藉由底部填充材料部分從半導體晶粒及第二金屬結合結構電性隔離。
根據本揭露的另一些實施例,一種晶片封裝結構包括:一扇出封裝以及一封裝基板。扇出封裝包括一重分布結構、複數個半導體晶粒以及一第一底部填充材料部分,重分布結構包括複數個重分佈側結合結構,半導體晶粒包括複數個晶粒側結合結構的各自一組,晶粒側結合結構透過複數個第一焊料材料部分的各自一組而附接至重分布側結合結構的各自一子集,第一底部填充材料部分橫向地環繞重分布側結合結構及半導體晶粒的晶粒側結合結構,其中在平面視角中,重分布側結合結構的一子集位於選自半導體晶粒的一對相鄰的半導體晶粒之間。封裝基板經由複數個第二焊料材料部分的一陣列而附接至扇出封裝。
根據本揭露的又另一些實施例,一種形成晶片封裝結構的方法包括:提供一重分佈結構,包括其上的複數個重分布側結合結構;提供複數個半導體晶粒,包括複數個晶粒側結合結構的各自一組;利用複數個第一焊料材料部分將半導體晶粒結合至重分佈結構,第一焊料材料部分結合至重分布側結合結構的一第一子集中的各自一個重分布側結合結構及至晶粒側結合結構的各自一者,其中重分布側結合結構的一第二子集不結合至半導體晶粒的任何一者;以及繞著第一焊料材料部分、重分布側結合結構及晶粒側結合結構形成一第一底部填充材料部分。
以下的揭露內容提供許多不同的實施例或範例以實施本案的不同特徵。以下的揭露內容敘述各個構件及其排列方式的特定範例,以簡化說明。當然,這些特定的範例並非用以限定。例如,若是本揭露書敘述了一第一特徵形成於一第二特徵之上或上方,即表示其可能包含上述第一特徵與上述第二特徵是直接接觸的實施例,亦可能包含了有附加特徵形成於上述第一特徵與上述第二特徵之間,而使上述第一特徵與第二特徵可能未直接接觸的實施例。另外,以下揭露書不同範例可能重複使用相同的參考符號及/或標記。這些重複係為了簡化與清晰的目的,並非用以限定所討論的不同實施例及/或結構之間有特定的關係。
此外,與空間相關用詞,例如「在…下方」、「下方」、「較低的」、「上方」、「較高的」及類似的用詞,係為了便於描述圖示中一個元件或特徵與另一個(些)元件或特徵之間的關係。除了在圖式中繪示的方位外,這些空間相關用詞意欲包含使用中或操作中的裝置之不同方位。裝置可能被轉向不同方位(旋轉90度或其他方位),則在此使用的空間相關詞也可依此相同解釋。除非另外明確地限定, 具有相同參考符號的每一元件預設為具有相同的材料組成且具有相同厚度範圍內的厚度。
本揭露實施例涉及半導體裝置,特別是在半導體晶粒封裝中,底部填充材料的均勻應用。一般而言,本揭露實施例的方法及結構可用以提供一晶片封裝結構,例如:扇出型晶圓級封裝(FOWLP)或扇出型面板級封裝(fan-out panel level package,FOPLP)。雖然本揭露實施例是利用扇出型晶圓級封裝的配置來描述,本揭露實施例的方法及結構可運用在扇出型面板級封裝的配置上或任何其他扇出型或扇入型封裝配置上。
半導體晶粒和重分布結構上的金屬結合結構可以在底部填充材料的應用期間增加毛細力。 增加的毛細力可以有利地用於增強在晶粒到晶粒間隙或晶粒到封裝間隙(例如:晶粒到晶片尺寸封裝間隙)中的金屬結合結構周圍,底部填充材料分布的均勻性。根據本揭露實施例的一型態,可以使用虛設金屬結合結構及/或虛設焊料材料部分來增強底部填充材料的流動均勻性。透過使用本揭露實施例的增強晶粒間區域中的毛細力的虛設結構,可以避免或減少在晶粒到晶粒間隙或晶粒到封裝間隙內的底部填充材料部分內的空隙形成。
舉例來說,高性能計算(high performance computing,HPC)封裝可包括多個半導體晶粒,包括至少一個單晶片系統(system-on-chip,SoC)晶粒和小晶片內的至少一個高帶寬記憶體(high bandwidth memory,HBM)晶粒,例如:扇出晶圓級封裝。晶粒到晶粒間隙及/或晶粒到晶片尺寸封裝間隙增加了底部填充材料分配步驟的複雜性。在底部填充材料不均勻流動的情況下,空隙可能在間隙區域中的底部填充材料部分內形成。底部填充材料中的這種空隙可能導致焊料橋接或「爆米花」現象,其中焊料材料部分牢固地附接到金屬結合結構。 本揭露實施例的虛設結構可用於避免或減少底部填充材料中的空隙形成。 參照隨附圖式描述了本揭露的方法和結構的各種型態和實施例。
參照第1圖,根據本揭露的一實施例的示例性結構包括一第一載體基板300以及形成在第一載體基板300的前側表面上的複數個重分佈結構920。第一載體基板300可包括光透基板例如:玻璃基板或藍寶石基板。第一載體基板300的直徑可在150毫米至290毫米的範圍內,且第一載體基板300的厚度可在500微米至2000微米的範圍內,但亦可用較小及較大的厚度。替代性地,第一載體基板300可以矩形面板的形式提供。
第一黏著層301可施加在第一載體基板300的前側表面。在一實施例中,第一黏著層301可為光熱轉換(light-to-heat conversion,LTHC)層。光熱轉換層可為以溶劑為基底的塗層,利用旋塗方法施加。光熱轉換層可將紫外光轉換成熱,這可導致光熱轉換層的材料失去黏著性。替代性地,第一黏著層301可包括熱分解黏著材料。舉例來說,第一黏著層301可包括在高溫下分解的壓克力壓敏黏著劑。熱分解黏著材料的脫結(debonding)溫度可在攝氏150度至200度的範圍內。
重分佈結構920可形成在第一黏著層301上方。尤其,重分佈結構920可形成在每一單位面積UA內,單位面積UA是在第一載體基板300上方的二維陣列中重複的重複單元的面積。每一重分佈結構920可包括複數個重分佈介電層922及複數個重分佈布線(wiring)互連件924。重分佈介電層922包括各自的介電聚合物材料例如:聚醯亞胺(polyimide,PI)、苯環丁烯(benzocyclobutene,BCB)、或聚苯噁唑(polybenzobisoxazole,PBO)。其他適合的材料可在本揭露實施例的預期範疇內。每一重分佈介電層922可藉由各自的介電聚合物材料的旋塗及乾燥而形成。每一重分佈介電層922的厚度可在2微米至40微米的範圍內,例如:4微米至20微米。每一重分佈介電層922可被圖案化,舉例來說,藉由施加及圖案化其上方的各自的光阻層,且藉由利用蝕刻製程(例如:異性蝕刻製程)將光阻層中的圖案轉移至重分佈介電層922。後續可移除(例如:藉由灰化)光阻層。
每一重分佈布線互連件924可藉由以濺鍍沉積金屬種晶層、藉由施加及圖案化金屬種晶層上方的光阻層以形成通過光阻層的開口圖案、藉由電鍍金屬填充材料(例如:銅、鎳、或銅及鎳的堆疊)、藉由移除光阻層(例如:藉由灰化)、以及藉由蝕刻位於電鍍金屬填充材料部分之間的部分金屬種晶層而形成。上述金屬種晶層可包括例如:鈦障壁層及銅種晶層的堆疊。鈦障壁層可具有從50奈米至400奈米的範圍中的厚度,且銅種晶層可具有從100奈米至500奈米的範圍中的厚度。用於重分佈布線互連件924的金屬填充材料可包括銅、鎳、或銅及鎳。針對每一重分佈布線互連件924所沉積的金屬填充材料的厚度可在2微米至40微米的範圍內,例如:4微米至10微米,但亦可用更小或更大的厚度。在每一重分佈結構920中布線的等級總數(即,重分佈布線互連件924的等級)可在1至10的範圍內。其他適合的材料可在本揭露實施例的預期範疇內。重分佈結構920的周期性二維陣列(例如:矩形陣列)可形成在第一載體基板300上方。包括所有重分佈結構920的層在本文中稱為重分布結構層。重分布結構層包括重分佈結構920的二維陣列。
參照第2A圖及第2B圖,至少一金屬材料及一第一材料可依序地沉積在重分佈結構920的前側表面上方。至少一金屬材料包括可用於金屬凸塊的材料,例如:銅。至少一金屬材料的厚度可在5微米至60微米的範圍內,例如:10微米至30微米,但亦可用更小或更大的厚度。第一材料可包括適於C2結合的第一材料,例如:用於微凸塊結合。第一材料的厚度可在2微米至30微米的範圍內,例如:4微米至15微米,但亦可用更小或更大的厚度。
第一材料及至少一金屬材料可被圖案化成第一焊料材料部分940的離散陣列及金屬結合結構的陣列,在本文中稱為重分佈側結合結構938的陣列。每一重分佈側結合結構938的陣列形成在各自的單位面積UA內。每一第一焊料材料部分940的陣列形成在各自的單位面積UA內。每一第一焊料材料部分940可具有和下方的重分佈側結合結構938相同的水平剖面形狀。
在一實施例中,重分佈側結合結構938可包括銅及含銅的合金及/或實質上可由銅及含銅的合金組成。其他適合的材料可在本揭露實施例的預期範疇內。重分佈側結合結構938的厚度可在5微米至60微米的範圍內,但亦可用更小或更大的厚度。重分佈側結合結構938可具有矩形、圓邊矩形、圓型、正多邊形、不規則多邊形或任何其他具有封閉緣周的二維曲線形狀的水平剖面形狀。在一實施例中,重分佈側結合結構938可配置用於微凸塊結合(即,C2結合),且可具有在10微米至30微米的範圍內的厚度,但亦可用更小或更大的厚度。在此實施例中,每一重分佈側結合結構938的陣列可形成為微凸塊(例如:銅柱)的陣列,具有10微米至25微米的範圍內的橫向尺寸,且具有20微米至50微米的範圍內的節距。
參照第3A圖及第3B圖,一組至少一個半導體晶粒(半導體晶粒700、半導體晶粒800)可結合至每一重分佈結構920。在一實施例中,重分佈結構920可排列成二維周期性陣列,且多組至少一個半導體晶粒(半導體晶粒700、半導體晶粒800)可結合至重分佈結構920作為多組至少一個半導體晶粒(半導體晶粒700、半導體晶粒800)的二維周期性矩形陣列。每一組至少一個半導體晶粒(半導體晶粒700、半導體晶粒800)包括至少一個半導體晶粒。每一組至少一個半導體晶粒(半導體晶粒700、半導體晶粒800)可包括任何技術領域中已知的一組至少一個半導體晶粒。在一實施例中,每一組至少一個半導體晶粒(半導體晶粒700、半導體晶粒800)可包括複數個半導體晶粒(半導體晶粒700、半導體晶粒800)。舉例來說,每一組至少一個半導體晶粒(半導體晶粒700、半導體晶粒800)可包括至少一個單晶片系統(SoC)晶粒700及/或至少一個記憶體晶粒800。每一單晶片系統晶粒700可包括一應用處理器晶粒、一中央處理單元晶粒、或一圖像處理單元晶粒。在一實施例中,至少一記憶體晶粒800可包括高帶寬記憶體(HBM)晶粒,包括靜態隨機存取記憶體晶粒的垂直堆疊。在一實施例中,至少一個半導體晶粒(半導體晶粒700、半導體晶粒800)可包括至少一個單晶片系統(SoC)晶粒以及包括靜態隨機存取記憶體晶粒(static random access memory,SRAM)的垂直堆疊的高帶寬記憶體(HBM)晶粒,彼此透過微凸塊互連,且被環氧樹脂模製材料封閉框體橫向地環繞。
參照第3A圖及第3B圖,每一半導體晶粒(半導體晶粒700、半導體晶粒800)可包括晶粒側結合結構(晶粒側結合結構780、晶粒側結合結構880)的各自一陣列。舉例來說,每一單晶片系統晶粒700可包括單晶片系統金屬結合結構780的一陣列,且每一半導體晶粒800可包括記憶體晶粒金屬結合結構880的一陣列。每一半導體晶粒(半導體晶粒700、半導體晶粒800)可定位在面向下的位置,使得晶粒側結合結構(晶粒側結合結構780、晶粒側結合結構880)面向第一焊料材料部分940。複數個半導體晶粒(半導體晶粒700、半導體晶粒800)的每一組可放置在各自的單位面積UA內。半導體晶粒(半導體晶粒700、半導體晶粒800)的放置可利用取放設備執行,使得每一晶粒側結合結構(晶粒側結合結構780、晶粒側結合結構880)放置在第一焊料材料部分940的各自一者的頂部表面上。
一般而言,可提供重分佈結構920,包括其上的重分佈側結合結構938,且可提供複數個半導體晶粒(半導體晶粒700、半導體晶粒800),包括各自一組晶粒側結合結構(晶粒側結合結構780、晶粒側結合結構880)。複數個半導體晶粒(半導體晶粒700、半導體晶粒800)可利用第一焊料材料部分940而結合至重分佈結構920,第一焊料材料部分940結合至重分佈側結合結構938的第一子集內的各自一個重分佈側結合結構938,且至晶粒側結合結構(晶粒側結合結構780、晶粒側結合結構880)的各自一者。重分佈側結合結構938的第二子集不結合至任何的半導體晶粒(半導體晶粒700、半導體晶粒800)。
重分佈側結合結構938的第一子集可結合至第一焊料材料部分940的第一子集,且重分佈側結合結構938的第二子集可結合至第一焊料材料部分940的第二子集。重分佈側結合結構938的第二子集在本文中稱作虛設重分布側結合結構938D。第一焊料材料部分940的第二子集在本文中稱做虛設焊料材料部分940D。重分佈側結合結構938的第二子集(包括虛設重分布側結合結構938D)不具有至複數個半導體晶粒(半導體晶粒700、半導體晶粒800)的任何晶粒側結合結構(晶粒側結合結構780、晶粒側結合結構880)的任何結合。換句話說,重分佈側結合結構938的第二子集(包括虛設重分布側結合結構938D)不結合至複數個半導體晶粒(半導體晶粒700、半導體晶粒800)的任何晶粒側結合結構(晶粒側結合結構780、晶粒側結合結構880)。
重分佈側結合結構938的第一子集內的每一重分佈側結合結構938在平面視角中(例如:上視圖),可具有與複數個半導體晶粒(半導體晶粒700、半導體晶粒800)各自一者的區域(areal)重疊,且在平面視角中,可完全地位於複數個半導體晶粒(半導體晶粒700、半導體晶粒800)各自一者的面積內。每一虛設重分布側結合結構938D在平面視角中,不與複數個半導體晶粒(半導體晶粒700、半導體晶粒800)有任何區域重疊,且在平面視角中,可完全地位於複數個半導體晶粒(半導體晶粒700、半導體晶粒800)內一對相鄰的半導體晶粒(半導體晶粒700、半導體晶粒800)的面積之間。
第一焊料材料部分940的第一子集內的每一第一焊料材料部分940在平面視角中,可具有與複數個半導體晶粒(半導體晶粒700、半導體晶粒800)各自一者的區域(areal)重疊,且在平面視角中,可完全地位於複數個半導體晶粒(半導體晶粒700、半導體晶粒800)各自一者的面積內。每一虛設焊料材料部分940D在平面視角中,不與複數個半導體晶粒(半導體晶粒700、半導體晶粒800)有任何區域重疊,且在平面視角中,可完全地位於複數個半導體晶粒(半導體晶粒700、半導體晶粒800)內一對相鄰的半導體晶粒(半導體晶粒700、半導體晶粒800)的面積之間。
一般而言,第一焊料材料部分940(例如:第一焊料材料部分940的第一子集)可形成在重分佈側結合結構938的第一子集上,且附加的第一焊料材料部分940(例如:虛設焊料材料部分940D)可形成在重分佈側結合結構938的第二子集上(即,在虛設重分布側結合結構938D上)。附加的第一焊料材料部分(例如:虛設焊料材料部分940D)不結合至任何的晶粒側結合結構(晶粒側結合結構780、晶粒側結合結構880)。附加的第一焊料材料部分(例如:虛設焊料材料部分940D)不具有與晶粒側結合結構(晶粒側結合結構780、晶粒側結合結構880)的任何結合。
在一實施例中,虛設焊料材料部分940D可位於選自重分佈側結合結構938的第二子集的各自一個虛設重分布側結合結構938D上,且不接觸任何半導體晶粒(半導體晶粒700、半導體晶粒800)。在一實施例中,虛設焊料材料部分940D包括至少一列虛設焊料材料部分940D,沿著平行於選自半導體晶粒(半導體晶粒700、半導體晶粒800)的一對相鄰的半導體晶粒(半導體晶粒700、半導體晶粒800)的一對側壁的方向排列,且設置於相鄰的半導體晶粒(半導體晶粒700、半導體晶粒800)之間。每一虛設焊料材料部分940D具有與結合至重分佈側結合結構938與晶粒側結合結構(晶粒側結合結構780、晶粒側結合結構880)的各自一對的多組第一焊料材料部分940相同的材料組成。
一般而言,虛設重分布側結合結構938D及虛設焊料材料部分940D在平面視角(例如:第3B圖的上視圖)中不與複數個半導體晶粒(半導體晶粒700、半導體晶粒800)在每一單位面積UA中具有任何區域重疊。在一實施例中,在平面視角中,一列虛設重分布側結合結構938D及一列虛設焊料材料部分940D可位於複數個半導體晶粒(半導體晶粒700、半導體晶粒800)內一對相鄰的半導體晶粒(半導體晶粒700、半導體晶粒800)的面積之間。虛設重分布側結合結構938D及虛設焊料材料部分940D的排列可依據每一單位面積UA內的複數個半導體晶粒(半導體晶粒700、半導體晶粒800)的排列而有所不同。
第4A圖至第4C圖繪示示例性結構的替代性配置,由第3A圖及第3B圖的示例性結構衍生,改變半導體晶粒(半導體晶粒700、半導體晶粒800)的排列及/或半導體晶粒(半導體晶粒700、半導體晶粒800)的總數量及/或半導體晶粒(半導體晶粒700、半導體晶粒800)的種類。第4A圖至第4C圖中示例性結構的替代性配置內的半導體晶粒(第一半導體晶粒701、第二半導體晶粒702、第三半導體晶粒703、第四半導體晶粒704)包括一第一半導體晶粒701、一第二半導體晶粒702、選擇性地一第三半導體晶粒703及/或一第四半導體晶粒704。每一半導體晶粒(第一半導體晶粒701、第二半導體晶粒702、第三半導體晶粒703、第四半導體晶粒704)可包括一單晶片系統晶粒700或一記憶體晶粒800。虛設重分布側結合結構938D及虛設焊料材料部分940D的圖案可包括第4A圖繪示的單列圖案、第4B圖繪示的多列圖案、及/或第4C圖繪示的交叉圖案。一般而言,在至少一個虛設重分布側結合結構938D及至少一個虛設焊料材料部分940D放置在半導體晶粒{(半導體晶粒700、半導體晶粒800)或(第一半導體晶粒701、第二半導體晶粒702、第三半導體晶粒703、第四半導體晶粒704)}的相鄰一對之間的前提下,任何圖案皆可用於虛設重分布側結合結構938D及虛設焊料材料部分940D的排列。
雖然第3A圖、第3B圖及第4A圖至第4C圖繪示虛設焊料材料部分940D及虛設重分布側結合結構938D具有各自矩形的水平剖面形狀的配置,一般而言,虛設焊料材料部分940D及虛設重分布側結合結構938D可具有任何具有封閉緣周的二維曲線形狀的水平剖面形狀。
參照第5A圖,示出虛設焊料材料部分940D(及重分佈側結合結構938)的替代性形狀,可包括等邊長的正多邊形。
參照第5B圖,示出虛設焊料材料部分940D(及重分佈側結合結構938)的附加替代性形狀,可包括不規則的多邊形。
但替代性地,虛設焊料材料部分940D(及重分佈側結合結構938)可具有圓形、橢圓形、卵形、或具有封閉緣周的曲線二維形狀的水平剖面形狀。
參照第6圖,繪示一高帶寬記憶體(HBM)晶粒810,可用作第3A圖、第3B圖、第4A圖、第4B圖及/或第4C圖中的半導體晶粒800。高帶寬記憶體晶粒810包括靜態隨機存取記憶體晶粒(靜態隨機存取記憶體晶粒811、靜態隨機存取記憶體晶粒812、靜態隨機存取記憶體晶粒813、靜態隨機存取記憶體晶粒814、靜態隨機存取記憶體晶粒815)的垂直堆疊,透過微凸塊820彼此互連,且被環氧樹脂模製材料封閉框體816橫向地環繞。靜態隨機存取記憶體晶粒(靜態隨機存取記憶體晶粒811、靜態隨機存取記憶體晶粒812、靜態隨機存取記憶體晶粒813、靜態隨機存取記憶體晶粒814、靜態隨機存取記憶體晶粒815)垂直地相鄰的一對之間的間隙可用高帶寬記憶體底部填充材料部分822填充,高帶寬記憶體底部填充材料部分822橫向地環繞各自一組微凸塊820。高帶寬記憶體晶粒810可包括記憶體晶粒金屬結合結構880的一陣列,配置以在單位面積UA中結合至重分佈側結合結構938的一陣列的一子集。高帶寬記憶體晶粒810可配置以提供以JEDEC標準定義的高帶寬,即,藉由JEDEC固態技術協會所定義的標準。
參照第7A圖及第7B圖,可將一第一底部填充材料施加在重分佈結構920與結合至重分佈結構920的一組半導體晶粒(半導體晶粒700、半導體晶粒800)之間的每一間隙中。第一底部填充材料可包括任何技術領域中已知的底部填充材料。第一底部填充材料部分950可形成在每一單位面積UA內,在重分佈結構920及上方的一組複數個半導體晶粒(半導體晶粒700、半導體晶粒800)之間。第一底部填充材料部分950可藉由繞著各自一個單位面積UA中第一焊料材料部分940的各自一陣列而注射第一底部填充材料來形成。可用任何已知的底部填充材料施加方法,舉例來說,毛細底部填充方法、模塑底部填充方法、或印刷底部填充方法。
在每一單位面積UA內,第一底部填充材料部分950橫向地環繞且接觸單位面積UA內的每一第一焊料材料部分940,包括第一焊料材料部分940可結合至各自一對重分佈側結合結構938及晶粒側結合結構(晶粒側結合結構780、晶粒側結合結構880)的第一子集,以及第一焊料材料部分940不結合至任何晶粒側結合結構(晶粒側結合結構780、晶粒側結合結構880)的第二子集(即,虛設焊料材料部分940D)。第一底部填充材料部分950可形成繞著且可接觸單位面積UA中的第一焊料材料部分940、重分佈側結合結構938及晶粒側結合結構(晶粒側結合結構780、晶粒側結合結構880)。在每一單位面積UA中,虛設重分布側結合結構938D(即,重分佈側結合結構938不結合(即,不具有任何結合)至複數個半導體晶粒(半導體晶粒700、半導體晶粒800)的任何晶粒側結合結構(晶粒側結合結構780、晶粒側結合結構880)的子集可被第一底部填充材料部分950橫向地環繞且可接觸第一底部填充材料部分950。
單位面積UA中的每一重分佈結構920可包括重分佈側結合結構938。包括各自一組晶粒側結合結構(晶粒側結合結構780、晶粒側結合結構880)的複數個半導體晶粒(半導體晶粒700、半導體晶粒800)可透過第一焊料材料部分940的各自一組(包括第一焊料材料部分940的第一子集)而附接至重分佈側結合結構938的各自一子集。在每一單位面積UA內,第一底部填充材料部分950橫向地環繞重分佈側結合結構938及複數個半導體晶粒(半導體晶粒700、半導體晶粒800)的晶粒側結合結構(晶粒側結合結構780、晶粒側結合結構880)。重分佈側結合結構938的一子集(即,虛設重分布側結合結構938D)不結合至複數個半導體晶粒(半導體晶粒700、半導體晶粒800)的任何晶粒側結合結構(晶粒側結合結構780、晶粒側結合結構880),且可被第一底部填充材料部分950橫向地環繞。
參照第8A圖及第8B圖,環氧樹脂模製化合物(EMC)可施加在半導體晶粒(半導體晶粒700、半導體晶粒800)的各自一組的比鄰組件與第一底部填充材料部分950之間的間隙。環氧樹脂模製化合物可包括含環氧樹脂的化合物,可被固化(即,硬化)以提供具有足夠硬度及機械強度的介電材料部分。環氧樹脂模製化合物可包括環氧樹脂、硬化劑、二氧化矽(作為填充材料)以及其他添加物。環氧樹脂模製化合物可以液體形式或固體形式提供,視黏度及可流動性而定。液體環氧樹脂模製化合物提供較佳的操作性(handling)、好的可流動性、較少空隙、較佳的填充度、以及較少的流痕。固體環氧樹脂模製化合物提供較少的硬化收縮、較佳的站立高度(stand-off)、以及較少的晶粒漂移。環氧樹脂模製化合物內較高的填充物含量(例如:重量的85%)可減少在模具中的時間,降低模具收縮,且減少模具翹曲。環氧樹脂模製化合物中均勻的填充物尺寸分布可減少流痕,且可增強可流動性。若黏著層包括熱性脫結材料,環氧樹脂模製化合物的硬化溫度可低於第一黏著層301的釋放(脫結)溫度。舉例來說,環氧樹脂模製化合物的硬化溫度可在125℃至150℃的範圍內。
環氧樹脂模製化合物可在硬化溫度被硬化,以形成環氧樹脂模製化合物基質910M,橫向地環繞且埋設一組半導體晶粒(半導體晶粒700、半導體晶粒800)及第一底部填充材料部分950的每一組件。環氧樹脂模製化合物基質910M可包括複數個環氧樹脂模製化合物(EMC)晶粒框體,橫向地毗連彼此。每一環氧樹脂模製化合物晶粒框體可為環氧樹脂模製化合物基質910M的一部分,位於各自的單位面積UA內。因此,每一環氧樹脂模製化合物晶粒框體可橫向地環繞且埋設各自一組半導體晶粒(半導體晶粒700、半導體晶粒800)及各自的第一底部填充材料部分950。
覆蓋在包括半導體晶粒(半導體晶粒700、半導體晶粒800)的頂部表面的水平平面上的環氧樹脂模製化合物基質910M的部分可藉由平坦化製程移除。舉例來說,覆蓋在水平平面上的環氧樹脂模製化合物基質910M的部分可利用化學機械平坦化移除。環氧樹脂模製化合物基質910M的剩餘部分、半導體晶粒(半導體晶粒700、半導體晶粒800)、第一底部填充材料部分950以及重分佈結構920的二維陣列的組合包括一重組晶圓900W。位於單位面積UA內的環氧樹脂模製化合物基質910M的每一部分組成一環氧樹脂模製化合物晶粒框體。
參照第9圖,第二黏著層401可施加至重組晶圓900W實體顯露的平面表面,即,環氧樹脂模製化合物基質910M、半導體晶粒(半導體晶粒700、半導體晶粒800)及第一底部填充材料部分950的實體顯露表面。在一實施例中,第二黏著層401可包括與第一黏著層301的材料相同或不同的材料。若第一黏著層301包括熱性分解黏著材料,則第二黏著層401包括在更高溫度分解的另一種熱性分解黏著材料,或可包括光熱轉換材料。
第二載體基板400可附接至第二黏著層401。第二載體基板400可附接至相對於第一載體基板300,重組晶圓900W的相對側。一般而言,第二載體基板400可包括任何可用於第一載體基板300的材料。第二載體基板400的厚度可在500微米至2000微米的範圍內,但亦可用更小或更大的厚度。
第一黏著層301可在脫結溫度下藉由紫外光照射或熱退火分解。在第一載體基板300包括光透材料且第一黏著層301包括光熱轉換層的實施例中,第一黏著層301可藉由透過透明載體基板的輻射紫外光分解。光熱轉換層可吸收紫外光照射且產生熱,將光熱轉換層的材料分解,且導致透明的第一載體基板300從重組晶圓900W脫離。在第一黏著層301包括熱性分解黏著材料的實施例中,可在脫結溫度下執行熱退火製程,以將第一載體基板300從重組晶圓900W脫離。
參照第10圖,可藉由沉積及圖案化至少一金屬材料的堆疊而形成扇出結合墊928及第二焊料材料部分290,至少一金屬材料的堆疊可作用為金屬凸塊及焊料材料層。用於扇出結合墊928的金屬填充材料可包括銅。其他適合的材料可在本揭露實施例的預期範疇內。扇出結合墊928的厚度可在5微米至100微米的範圍內,但亦可用更小或更大的厚度。扇出結合墊928及第二焊料材料部分290可具有矩形、圓邊矩形或圓形的水平剖面形狀。其他適合的形狀可在本揭露實施例的預期範疇內。在扇出結合墊928形成為可控塌陷晶片連接(controlled collapse chip connection,C4)墊的實施例中,扇出結合墊928的厚度可在5微米至50微米的範圍內,但亦可用更小或更大的厚度。在一些實施例中,扇出結合墊928可為或可包括凸塊下金屬(under bump metallurgy,UBM)結構。扇出結合墊928的配置不限於扇出結構。替代性地,扇出結合墊928可配置為微凸塊結合(即,C2結合),且可具有在30微米至100微米的範圍內的厚度,但亦可用更小或更大的厚度。在此種實施例中,扇出結合墊928可形成為微凸塊(例如:銅柱)的陣列,具有在10微米至25微米的範圍內的橫向尺寸,且具有在20微米至50微米的範圍內的節距。在一些實施例中,第二焊料材料部分290可微或可包括銅柱。
扇出結合墊928及第二焊料材料部分290可相對於重分布結構層,形成在環氧樹脂模製化合物基質910M及多組半導體晶粒(半導體晶粒700、半導體晶粒800)的二維陣列的相對側。重分布結構層包括重分佈結構920的三維陣列。每一重分佈結構920可位於各自的單位面積UA內。每一重分佈結構920可包括重分佈介電層922、埋設在重分佈介電層922中的重分佈布線互連件924、以及扇出結合墊928。扇出結合墊928可相對於重分佈介電層922,位於重分佈側結合結構938的相對側,且可電性連接至重分佈側結合結構938的各自一者。
參照第11圖,第二黏著層401可在脫結溫度下藉由紫外光照射或藉由熱退火分解。在第二載體基板400包括光透材料且第二黏著層401包括光熱轉換層的實施例中,第二黏著層401可藉由透過透明載體基板的輻射紫外光分解。在第二黏著層401包括熱性分解黏著材料的實施例中,可在脫結溫度下執行熱退火製程,以將第二載體基板400從重組晶圓900W脫離。
參照第12圖,包括扇出結合墊928的重組晶圓900W可藉由執行切割製程,沿著切割通道而被後續地切割。切割通道對應於相鄰一對單位面積UA之間的邊界。從重組晶圓900W切割出的每一切割單元包括一扇出封裝900。換句話說,多組半導體晶粒(半導體晶粒700、半導體晶粒800)的二維陣列、第一底部填充材料部分950的二維陣列、環氧樹脂模製化合物基質910M、以及重分佈結構920的二維陣列的組件的每一切割部分包括一扇出封裝900。環氧樹脂模製化合物基質910M的每一切割部分包括一模製化合物晶粒框體910。重分布結構層的每一切割部分(包括重分佈結構920的二維陣列)包括一重分佈結構920。
參照第13圖,繪示在第12圖的製程步驟中,藉由切割示例性結構而獲得的扇出封裝900。扇出封裝900包括重分佈結構920,包括重分佈側結合結構938、複數個半導體晶粒(半導體晶粒700、半導體晶粒800)以及第一底部填充材料部分950。半導體晶粒(半導體晶粒700、半導體晶粒800)包括各自一組晶粒側結合結構(晶粒側結合結構780、晶粒側結合結構880),且晶粒側結合結構(晶粒側結合結構780、晶粒側結合結構880)透過第一焊料材料部分940的各自一祖而附接至重分佈側結合結構938的各自一子集。第一底部填充材料部分950橫向地環繞重分佈側結合結構938及複數個半導體晶粒(半導體晶粒700、半導體晶粒800)的晶粒側結合結構(晶粒側結合結構780、晶粒側結合結構880)。其中重分佈側結合結構938的一子集在平面視角中(即,沿著垂直於重分佈結構920與第一底部填充材料部分950之間的接合面的一方向),位於選自複數個半導體晶粒(半導體晶粒700、半導體晶粒800)的相鄰一對半導體晶粒(半導體晶粒700、半導體晶粒800)之間。扇出封裝900可包括模製化合物晶粒框體910,橫向地環繞複數個半導體晶粒(半導體晶粒700、半導體晶粒800),且包括模製化合物材料。在一實施例中,模製化合物晶粒框體910可包括與重分佈結構920的側壁垂直地重合的側壁,即,與重分佈結構920的側壁位於相同的垂直平面中。一般而言,在每一扇出封裝900內形成第一底部填充材料部分950之後,模製化合物晶粒框體910可繞著複數個半導體晶粒(半導體晶粒700、半導體晶粒800)形成。模製化合物材料接觸重分佈結構920的平面表面的緣周部分。
參照第14圖,封裝基板200可透過第二焊料材料部分290結合至扇出封裝900。封裝基板200可為核狀(cored)封裝基板,包括一核心基板210,或可為無核的封裝基板,不包括封裝核心。替代性地,封裝基板200可包括一系統整合封裝基板(system-on-integrated package substrate,SoIS),包括重分布及/或介電界面層、至少一埋設的中介層(例如:矽中介層)。此種系統整合封裝基板可包括利用焊料材料部分、微凸塊、底部填充材料部分(例如:模製底部填充材料部分)及/或黏著膜而達成的層對層的互連。雖然本揭露實施例利用示例性基板封裝描述,應瞭解的是本揭露實施例的範疇不限於任何特定種類的基板封裝,且可包括系統整合封裝基板。核心基板210可包括玻璃環氧樹脂板,包括貫通板的孔洞的陣列。包括金屬材料的穿芯貫孔結構214的陣列可提供在貫通板的孔洞中。每一穿芯貫孔結構214可或可不包括其中的圓柱形中空。選擇性地,介電襯墊212可用以將穿芯貫孔結構214從核心基板210電性隔離。
封裝基板200可包括板側表面增層線路(surface laminar circuit,SLC)240以及晶片側表面增層線路(SLC)260。板側表面增層線路240可包括板側絕緣層242,埋設有板側布線互連件244。晶片側表面增層線路260可包括晶片側絕緣層262,埋設有晶片側布線互連件264。板側絕緣層242及晶片側絕緣層262可包括光敏性環氧樹脂材料,可被微影圖案化以及後續地硬化。板側布線互連件244及晶片側布線互連件264可包括銅,可藉由電鍍而沉積在板側絕緣層242或晶片側絕緣層262中的圖案內。
在一實施例中,封裝基板200包括晶片側表面增層線路260以及板側表面增層線路240,晶片側表面增層線路260包括連接至晶片側結合墊268的一陣列的晶片側布線互連件264,晶片側結合墊268結合至第二焊料材料部分290的陣列,板側表面增層線路240包括連接至板側結合墊248的一陣列的板側布線互連件244。板側結合墊248的陣列配置以容許透過焊料球結合。晶片側結合墊268的陣列配置以容許透過可控塌陷晶片連接焊料球結合。一般而言,可利用任何種類的封裝基板200。雖然利用一實施例來描述本揭露,其中封裝基板200包括一晶片側表面增層線路260以及一板側表面增層線路240,本文明確地預期多種實施例,其中省略晶片側表面增層線路260及板側表面增層線路240其中一者,或是以結合結構的陣列(例如:微凸塊)來取代。在一說明範例中,晶片側表面增層線路260可以微凸塊的一陣列或任何其他結合結構的陣列取代。
附接至扇出封裝900之扇出結合墊928的第二焊料材料部分290可設置在封裝基板200的晶片側結合墊268的陣列上。可執行迴焊製程以迴焊第二焊料材料部分290,藉此導致扇出封裝900與封裝基板200之間的結合。在一實施例中,第二焊料材料部分290可包括可控塌陷晶片連接焊料球,且扇出封裝900可利用可控塌陷晶片連接焊料球的一陣列而附接至封裝基板200。
參照第15圖,藉由施加及塑形第二底部填充材料,可繞著第二焊料材料部分290形成第二底部填充材料部分292。在迴焊第二焊料材料部分290之後,藉由繞著第二焊料材料部分290的陣列注射第二底部填充材料,可形成第二底部填充材料部分292。可利用任何已知的底部填充材料施加方法,舉例來說,毛細底部填充方法、模塑底部填充方法、或印刷底部填充方法。
第二底部填充材料部分292可接觸每一第二焊料材料部分290(可為可控塌陷晶片連接焊料球或C2焊料蓋件),且可接觸扇出封裝900的垂直側壁。第二底部填充材料部分292形成在重分佈結構920與封裝基板200之間。第二底部填充材料部分292橫向地環繞且接觸第二焊料材料部分290的陣列以及扇出封裝900。
選擇性地,穩定結構294(例如:蓋件結構或環結構)可附接至扇出封裝900與封裝基板200的組件,以減少後續製程步驟期間及/或組件使用期間組件的變形。
參照第16圖,可提供包括一印刷電路板基板110以及數個印刷電路板結合墊180的印刷電路板(printed circuit board,PCB)100。印刷電路板100在印刷電路板基板110的至少一側上包括一印刷電路(圖未示)。可形成焊料接點190的一陣列以將板側結合墊248的陣列結合至印刷電路板結合墊180的陣列。焊料接點190可藉由將焊料球的一陣列設置在板側結合墊248的陣列與印刷電路板結合墊180的陣列之間,並迴焊焊料球的陣列而形成。藉由施加及塑形底部填充材料,可繞著焊料接點190形成底部填充材料部分192。封裝基板200透過焊料接點190的陣列附接至印刷電路板100。
參照第17圖,根據本揭露的一實施例,繪示用於形成示例性結構的步驟的流程圖。
參照步驟1710以及第1圖、第2A圖及第2B圖,可提一重分佈結構920,包括其上的重分佈側結合結構938。
參照步驟1720以及第3A圖至第6圖,可提供複數個半導體晶粒(半導體晶粒700、半導體晶粒800),包括各自一組晶粒側結合結構(晶粒側結合結構780、晶粒側結合結構880)。
參照步驟1730以及第3A圖至第6圖,利用第一焊料材料部分940,可將複數個半導體晶粒(半導體晶粒700、半導體晶粒800)結合至重分佈結構920,第一焊料材料部分940結合至重分佈側結合結構938的第一子集內各自一個重分佈側結合結構938以及各自一個晶粒側結合結構(晶粒側結合結構780、晶粒側結合結構880)。重分佈側結合結構938的第二子集(例如:虛設重分布側結合結構938D)未結合至任何半導體晶粒(半導體晶粒700、半導體晶粒800)。
參照步驟1740以及第7A圖及第7B圖,繞著第一焊料材料部分940、重分佈側結合結構938以及晶粒側結合結構(晶粒側結合結構780、晶粒側結合結構880),可形成一第一底部填充材料部分950。
參照所有圖式且根據本揭露的各種實施例,提供一種扇出封裝,包括一重分佈結構920、複數個半導體晶粒(半導體晶粒700、半導體晶粒800)、以及一底部填充材料部分(例如:第一底部填充材料部分950)。重分佈結構920在一側上包括複數個第一金屬結合結構(例如:重分佈側結合結構938)。半導體晶粒(半導體晶粒700、半導體晶粒800)包括透過凸塊部分(例如:第一焊料材料部分940)附接至第一金屬結合結構938的複數個第二金屬結合結構(例如:晶粒側結合結構(晶粒側結合結構780、晶粒側結合結構880))。底部填充材料部分橫向地環繞第一金屬結合結構938以及複數個半導體晶粒(半導體晶粒700、半導體晶粒800)的晶粒側結合結構(晶粒側結合結構780、晶粒側結合結構880),其中第一金屬結合結構938的一子集包括至少一虛設金屬結合結構938D,虛設金屬結合結構938D被底部填充材料部分950環繞,且藉由底部填充材料部分950從半導體晶粒(半導體晶粒700、半導體晶粒800)及第二金屬結合結構(晶粒側結合結構780、晶粒側結合結構880)電性隔離。一般而言,第一金屬結合結構及第二金屬結合結構可包括任何種類的結合結構,例如:可控塌陷晶片連接結合墊或C2結合柱或任何其他種類的金屬結構,焊料材料可結合至此種結合結構。
在一實施例中,在平面視角中,至少一虛設金屬結合結構938D位於選自複數個半導體晶粒(半導體晶粒700、半導體晶粒800)的相鄰一對半導體晶粒(半導體晶粒700、半導體晶粒800)之間。在一實施例中,在平面視角中,至少一虛設金屬結合結構938D與複數個半導體晶粒(半導體晶粒700、半導體晶粒800)不具有任何區域重疊。
在一實施例中,扇出封裝包括至少一虛設凸塊部分(例如:至少一虛設焊料材料部分940D),位於各自一個至少一虛設金屬結合結構938D上且不接觸任何第二金屬結合結構(晶粒側結合結構780、晶粒側結合結構880)。在一實施例中,至少一虛設凸塊部分938D的所有表面與底部填充材料部分950或至少一虛設凸塊結合部分938D接觸。
在一實施例中,至少一虛設凸塊部分938D包括至少一列虛設凸塊部分938D,沿著平行於選自複數個半導體晶粒(半導體晶粒700、半導體晶粒800)的相鄰一對半導體晶粒(半導體晶粒700、半導體晶粒800)的一對側壁排列,且位於此對側壁之間。在一實施例中,每一至少一虛設凸塊部分938D具有與凸塊部分938相同的材料組成。
在一實施例中,扇出封裝900可包括模製化合物晶粒框體910,橫向地環繞複數個半導體晶粒(半導體晶粒700、半導體晶粒800),且包括模製化合物材料。在一實施例中,模製化合物晶粒框體910可包括與重分佈結構920的側壁垂直地重核的側壁。
在一實施例中,重分佈結構920可包括:重分佈布線互連件924以及扇出結合墊928。重分佈布線互連件924埋設在重分佈介電層922中且電性連接至各自一個重分佈側結合結構938。扇出結合墊928位於重分佈側結合結構938的相對側且電性連接至各自一個重分佈側結合結構938。
在一實施例中,複數個半導體晶粒(半導體晶粒700、半導體晶粒800)包括至少一個單晶片系統(SoC)晶粒700以及一記憶體晶粒800。記憶體晶粒800例如為高帶寬記憶體(HBM)晶粒810,包括靜態隨機存取記憶體(SRAM)晶粒(靜態隨機存取記憶體晶粒811、靜態隨機存取記憶體晶粒812、靜態隨機存取記憶體晶粒813、靜態隨機存取記憶體晶粒814、靜態隨機存取記憶體晶粒815)的垂直堆疊,透過微凸塊820彼此互連,且被環氧樹脂模製材料封閉框體816橫向地環繞。
根據本揭露實施例的一型態,可提供包括扇出封裝900的一結構,可包括:重分佈結構920、複數個半導體晶粒(半導體晶粒700、半導體晶粒800)以及底部填充材料部分950。重分佈結構920可包括重分佈側結合結構938。半導體晶粒(半導體晶粒700、半導體晶粒800)可包括各自一組晶粒側結合結構(晶粒側結合結構780、晶粒側結合結構880),透過各自一組焊料材料部分940附接至重分佈側結合結構938的各自一子集。底部填充材料部分950橫向地環繞重分佈側結合結構938以及複數個半導體晶粒(半導體晶粒700、半導體晶粒800)的晶粒側結合結構(晶粒側結合結構780、晶粒側結合結構880)。其中重分佈側結合結構938的一子集(例如:虛設重分布側結合結構938D)未結合至複數個半導體晶粒(半導體晶粒700、半導體晶粒800)的任何一晶粒側結合結構(晶粒側結合結構780、晶粒側結合結構880),且被第一底部填充材料部分950橫向地環繞。
在一實施例中,在平面視角中,重分佈側結合結構938的一子集(例如:虛設重分布側結合結構938D)位於選自複數個半導體晶粒(半導體晶粒700、半導體晶粒800)的相鄰一對半導體晶粒(半導體晶粒700、半導體晶粒800)之間。在一實施例中,在平面視角中,重分佈側結合結構938的一子集(例如:虛設重分布側結合結構938D)與複數個半導體晶粒(半導體晶粒700、半導體晶粒800)的任何一者不具有區域重疊。
在一實施例中,扇出封裝可包括虛設焊料材料部分940D,位於各自一個選自重分佈側結合結構938的子集的重分佈側結合結構938(例如:虛設重分布側結合結構938D)上。在一些實施例中,虛設焊料材料部分940D及虛設重分布側結合結構938D可不接觸及/或電性連接至複數個半導體晶粒(半導體晶粒700、半導體晶粒800)的任何一者。
在一實施例中,虛設焊料材料部分940D的所有表面可與第一底部填充材料部分950或重分佈側結合結構938的子集(例如:虛設重分布側結合結構938D)接觸。在一實施例中,虛設焊料材料部分940D可包括至少一列虛設焊料材料部分940D,沿著平行於選自複數個半導體晶粒(半導體晶粒700、半導體晶粒800)的相鄰一對半導體晶粒(半導體晶粒700、半導體晶粒800)的一對側壁排列,且位於此對側壁之間。在一實施例中,每一虛設焊料材料部分940D可具有與多組焊料材料部分940相同的材料組成。
根據本揭露實施例的一型態,提供一種晶片封裝結構,可包括:扇出封裝900、複數個半導體晶粒(半導體晶粒700、半導體晶粒800)、第一底部填充材料部分950以及封裝基板200。扇出封裝900包括重分佈結構920,重分佈結構920包括重分佈側結合結構938。半導體晶粒(半導體晶粒700、半導體晶粒800)可包括各自一組晶粒側結合結構(晶粒側結合結構780、晶粒側結合結構880),可透過各自一組第一焊料材料部分940附接至重分佈側結合結構938的各自一子集。第一底部填充材料部分950橫向地環繞重分佈側結合結構938以及複數個半導體晶粒(半導體晶粒700、半導體晶粒800)的晶粒側結合結構(晶粒側結合結構780、晶粒側結合結構880)。其中在平面視角中,重分佈側結合結構938的一子集(例如:虛設重分布側結合結構938D)可位於選自複數個半導體晶粒(半導體晶粒700、半導體晶粒800)的相鄰一對半導體晶粒(半導體晶粒700、半導體晶粒800)之間。封裝基板200經由第二焊料材料部分290的一陣列附接至扇出封裝900。
在一實施例中,晶片封裝結構可包括一模製化合物晶粒框體910,橫向地環繞複數個半導體晶粒(半導體晶粒700、半導體晶粒800),且可包括模製化合物材料,接觸重分佈結構920的平面表面的緣周部分。
在一實施例中,晶片封裝結構可包括一第二底部填充材料部分292,橫向地環繞第二焊料材料部分290的陣列及扇出封裝900。
在一實施例中,重分佈側結合結構938的子集(例如:虛設重分布側結合結構938D)未結合至複數個半導體晶粒(半導體晶粒700、半導體晶粒800)的任何一晶粒側結合結構(晶粒側結合結構780、晶粒側結合結構880),且可被第一底部填充材料部分950橫向地環繞且接觸。
本揭露實施例的各種結構及方法可用以提供一種晶片封裝結構,包括扇出封裝900,扇出封裝900包括虛設重分布側結合結構938D以及虛設焊料材料部分940D,修飾用於底部填充材料的導管的圖案,且增加對於底部填充材料的毛細力。本揭露實施例的各種方法及結構可用以減少或消除第一底部填充材料部分950中的空隙,且增加扇出封裝900的可靠性。
根據本揭露的一些實施例,一種扇出封裝包括:一重分布結構、複數個半導體晶粒以及一底部填充材料部分。重分布結構在一側上包括複數個第一金屬結合結構。複數個半導體晶粒包括透過複數個凸塊部分而附接至第一金屬結合結構的複數個第二金屬結合結構。底部填充材料部分橫向地環繞第一金屬結合結構及半導體晶粒的第二金屬結合結構。第一金屬結合結構的一子集包括至少一個虛設金屬結合結構,被底部填充材料部分環繞並藉由底部填充材料部分從半導體晶粒及第二金屬結合結構電性隔離。
在一些實施例中,在平面視角中,至少一個虛設金屬結構位於選自半導體晶粒的一對相鄰的半導體晶粒之間。在一些實施例中,在平面視角中,至少一個虛設金屬結構不具有與任何半導體晶粒的區域重疊。在一些實施例中,扇出封裝更包括至少一虛設凸塊部分,定位在至少一個虛設金屬結構的各自一者上,且不接觸任何第二金屬結合結構。在一些實施例中,至少一個虛設凸塊部分的所有表面與底部填充材料部分或與至少一個虛設金屬結合結構接觸。在一些實施例中,至少一個虛設凸塊部分包括至少一列虛設焊料材料部分,沿著平行於選自半導體晶粒的一對相鄰的半導體晶粒的一對側壁的方向排列,且位於此對側壁之間。在一些實施例中,至少一個虛設凸塊部分的每一者具有與凸塊部分相同的材料組成。在一些實施例中,扇出封裝更包括一模製化合物晶粒框體,橫向地環繞半導體晶粒,且包括一模製化合物材料。在一些實施例中,模製化合物晶粒框體包括複數個側壁,與重分布結構的複數個側壁垂直地重合。在一些實施例中,重分布結構包括:複數個重分布布線互連件以及複數個扇出金屬結合結構。複數個重分布布線互連件埋設在複數個重分布介電層中,且電性連接至複數個重分布側結合結構的各自一者。複數個扇出金屬結合結構位於重分布側結合結構的一相反側上,且電性連接至重分布側結合結構的各自一者。在一些實施例中,半導體晶粒包括:至少一單晶片系統晶粒以及一高帶寬記憶體晶粒。高帶寬記憶體晶粒包括複數個靜態隨機存取記憶體晶粒的一垂直堆疊,透過複數個微凸塊彼此互連,且被一環氧樹脂模製材料封閉框體橫向地環繞。
根據本揭露的另一些實施例,一種晶片封裝結構包括:一扇出封裝以及一封裝基板。扇出封裝包括一重分布結構、複數個半導體晶粒以及一第一底部填充材料部分,重分布結構包括複數個重分佈側結合結構,半導體晶粒包括複數個晶粒側結合結構的各自一組,晶粒側結合結構透過複數個第一焊料材料部分的各自一組而附接至重分布側結合結構的各自一子集,第一底部填充材料部分橫向地環繞重分布側結合結構及半導體晶粒的晶粒側結合結構,其中在平面視角中,重分布側結合結構的一子集位於選自半導體晶粒的一對相鄰的半導體晶粒之間。封裝基板經由複數個第二焊料材料部分的一陣列而附接至扇出封裝。
在一些實施例中,晶片封裝結構更包括一模製化合物晶粒框體,橫向地環繞半導體晶粒,且包括一模製化合物材料,接觸重分布結構的一平面表面的一周圍部分。在一些實施例中,晶片封裝結構更包括一第二底部填充材料部分,橫向地環繞第二焊料材料部分的陣列及扇出封裝。在一些實施例中,重分布側結合結構的子集不結合至半導體晶粒的晶粒側結合結構的任何一者,且被第一底部填充材料部分橫向地環繞並接觸第一底部填充材料部分。
根據本揭露的又另一些實施例,一種形成晶片封裝結構的方法包括:提供一重分佈結構,包括其上的複數個重分布側結合結構;提供複數個半導體晶粒,包括複數個晶粒側結合結構的各自一組;利用複數個第一焊料材料部分將半導體晶粒結合至重分佈結構,第一焊料材料部分結合至重分布側結合結構的一第一子集中的各自一個重分布側結合結構及至晶粒側結合結構的各自一者,其中重分布側結合結構的一第二子集不結合至半導體晶粒的任何一者;以及繞著第一焊料材料部分、重分布側結合結構及晶粒側結合結構形成一第一底部填充材料部分。
在一些實施例中,方法更包括:在重分布側結合結構的第一子集上形成第一焊料材料部分;以及在重分布側結合結構的第二子集上形成複數個附加的第一焊料材料部分,其中附加的第一焊料材料部分不結合至任何晶粒側結合結構。在一些實施例中,第一底部填充材料部分橫向地環繞且接觸附加的第一焊料材料部分的每一者。在一些實施例中,方法更包括在形成第一底部填充材料部分之後,繞著半導體晶粒形成一模製化合物晶粒框體。在一些實施例中,方法更包括:利用複數個第二焊料材料部分的一陣列,將重分佈結構附接至一封裝基板;以及繞著重分佈結構與封裝基板之間的第二焊料材料部分的陣列,形成一第二底部填充材料部分。
前述內文概述了許多實施例的特徵,使本技術領域中具有通常知識者可以從各個方面更佳地了解本揭露。本技術領域中具有通常知識者應可理解,且可輕易地以本揭露為基礎來設計或修飾其他製程及結構,並以此達到相同的目的及/或達到與在此介紹的實施例等相同之優點。本技術領域中具有通常知識者也應了解這些相等的結構並未背離本揭露的發明精神與範圍。在不背離本揭露的發明精神與範圍之前提下,可對本揭露進行各種改變、置換或修改。
100:印刷電路板
110:印刷電路板基板
180:印刷電路板結合墊
190:焊料接點
192:底部填充材料部分
200:封裝基板
210:核心基板
212:介電襯墊
214:穿芯貫孔結構
240:板側表面增層線路
242:板側絕緣層
244:板側布線互連件
248:板側結合墊
260:晶片側表面增層線路
262:晶片側絕緣層
264:晶片側布線互連件
268:晶片側結合墊
290:第二焊料材料部分
292:第二底部填充材料部分
294:穩定結構
300:第一載體基板
301:第一黏著層
400:第二載體基板
401:第二黏著層
700:半導體晶粒(單晶片系統晶粒)
701:第一半導體晶粒
702:第二半導體晶粒
703:第三半導體晶粒
704:第四半導體晶粒
780:晶粒側結合結構(第二金屬結合結構)
800:半導體晶粒(記憶體晶粒)
810:高帶寬記憶體晶粒
811:靜態隨機存取記憶體晶粒
812:靜態隨機存取記憶體晶粒
813:靜態隨機存取記憶體晶粒
814:靜態隨機存取記憶體晶粒
815:靜態隨機存取記憶體晶粒
816:環氧樹脂模製材料封閉框體
820:微凸塊
822:高帶寬記憶體底部填充材料部分
880:晶粒側結合結構(第二金屬結合結構)(記憶體晶粒金屬結合結構)
900:扇出封裝
900W:重組晶圓
910:模製化合物晶粒框體
910M:環氧樹脂模製化合物基質
920:重分佈結構
922:重分佈介電層
924:重分佈布線互連件
928:扇出結合墊
938:重分佈側結合結構(第一金屬結合結構)( 凸塊部分)
938D:虛設重分布側結合結構(虛設金屬結合結構)(虛設凸塊結合部分)(虛設凸塊部分)
940:第一焊料材料部分
940D:虛設焊料材料部分
950:第一底部填充材料部分
1710,1720,1730,1740:步驟
UA:單位面積
根據以下的詳細說明並配合所附圖式做完整揭露。應被強調的是,根據本產業的一般作業,圖示並未必按照比例繪製。事實上,可能任意的放大或縮小元件的尺寸,以做清楚的說明。
第1圖為根據本揭露之一實施例,示例性結構的一區域的垂直剖面圖,包括第一載體基板及重分佈結構。
第2A圖為根據本揭露之一實施例,在形成重分佈側結合結構及第一焊料材料部分之後,示例性結構的一區域的垂直剖面圖。
第2B圖為第2A圖的示例性結構的區域的上視圖。
第3A圖為根據本揭露之一實施例,在附接半導體晶粒之後,示例性結構的區域的垂直剖面圖。
第3B圖為第3A圖的示例性結構的區域的上視圖。
第4A圖為根據本揭露之一實施例,在附接半導體晶粒之後,示例性結構的第一替代性配置的區域的上視圖。
第4B圖為根據本揭露之一實施例,在附接半導體晶粒之後,示例性結構的第二替代性配置的區域的上視圖。
第4C圖為根據本揭露之一實施例,在附接半導體晶粒之後,示例性結構的第三替代性配置的區域的上視圖。
第5A圖繪示根據本揭露之一實施例,第一焊料材料部分的替代形狀的上視圖。
第5B圖繪示根據本揭露之一實施例,第一焊料材料部分的附加替代形狀的上視圖。
第6圖為高帶寬記憶體晶粒的放大垂直剖面圖。
第7A圖為根據本揭露之一實施例,在形成第一底部填充材料部分之後,示例性結構的區域的垂直剖面圖。
第7B圖為第7A圖的示例性結構的區域的上視圖。
第8A圖為根據本揭露之一實施例,在形成環氧樹脂模製化合物(epoxy molding compound,EMC)基質之後,示例性結構的區域的垂直剖面圖。
第8B圖為第8A圖的示例性結構的區域的上視圖。
第9圖為根據本揭露之一實施例,在附接第二載體基板並拆卸第一載體基板之後,示例性結構的區域的垂直剖面圖。
第10圖為根據本揭露之一實施例,在形成扇出結合墊之後,示例性結構的區域的垂直剖面圖。
第11圖為根據本揭露之一實施例,在拆卸第二載體基板之後,示例性結構的區域的垂直剖面圖。
第12圖為根據本揭露之一實施例,在切割重組晶圓及環氧樹脂模製化合物基質的期間,示例性結構的區域的垂直剖面圖。
第13圖為根據本揭露之一實施例,扇出封裝的垂直剖面圖。
第14圖為根據本揭露之一實施例,在將扇出封裝附接至封裝基板之後,示例性結構的垂直剖面圖。
第15圖為根據本揭露之一實施例,在形成第二底部填充材料部分之後,示例性結構的垂直剖面圖。
第16圖為根據本揭露之一實施例,在封裝基板附接至印刷電路板(PCB)之後,示例性結構的垂直剖面圖。
第17圖為根據本揭露之一實施例,繪示用於形成示例性結構的步驟的流程圖。
290:第二焊料材料部分
700:半導體晶粒(單晶片系統晶粒)
780:晶粒側結合結構(第二金屬結合結構)
800:半導體晶粒(記憶體晶粒)
810:高帶寬記憶體晶粒
811:靜態隨機存取記憶體晶粒
812:靜態隨機存取記憶體晶粒
813:靜態隨機存取記憶體晶粒
814:靜態隨機存取記憶體晶粒
815:靜態隨機存取記憶體晶粒
816:環氧樹脂模製材料封閉框體
820:微凸塊
822:高帶寬記憶體底部填充材料部分
880:晶粒側結合結構(第二金屬結合結構)(記憶體晶粒金屬結合結構)
900:扇出封裝
910:模製化合物晶粒框體
920:重分佈結構
922:重分佈介電層
924:重分佈布線互連件
928:扇出結合墊
938:重分佈側結合結構(第一金屬結合結構)(凸塊部分)
938D:虛設重分布側結合結構(虛設金屬結合結構)(虛設凸塊結合部分)(虛設凸塊部分)
940:第一焊料材料部分
940D:虛設焊料材料部分
950:第一底部填充材料部分
Claims (1)
- 一種扇出封裝,包括: 一重分布結構,在一側上包括複數個第一金屬結合結構; 複數個半導體晶粒,包括透過複數個凸塊部分而附接至該些第一金屬結合結構的複數個第二金屬結合結構;以及 一底部填充材料部分,橫向地環繞該些第一金屬結合結構及該些半導體晶粒的該些第二金屬結合結構; 其中該些第一金屬結合結構的一子集包括至少一個虛設金屬結合結構,被該底部填充材料部分環繞並藉由該底部填充材料部分從該些半導體晶粒及該些第二金屬結合結構電性隔離。
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US17/462,066 | 2021-08-31 | ||
US17/462,066 US11997842B2 (en) | 2021-08-31 | 2021-08-31 | Dummy metal bonding pads for underfill application in semiconductor die packaging and methods of forming the same |
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US8338945B2 (en) * | 2010-10-26 | 2012-12-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Molded chip interposer structure and methods |
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JP6724808B2 (ja) * | 2017-01-31 | 2020-07-15 | 株式会社デンソー | 電子装置 |
US10157888B1 (en) * | 2017-06-20 | 2018-12-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated fan-out packages and methods of forming the same |
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US10847485B2 (en) * | 2018-12-21 | 2020-11-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Chip package structure and method for forming the same |
US11728278B2 (en) * | 2019-03-25 | 2023-08-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Board substrates, three-dimensional integrated circuit structures and methods of forming the same |
US11309283B2 (en) * | 2019-12-31 | 2022-04-19 | Powertech Technology Inc. | Packaging structure and manufacturing method thereof |
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US20230067350A1 (en) | 2023-03-02 |
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