TW202310166A - 用於半導體晶粒總成之結合墊及相關聯之方法及系統 - Google Patents
用於半導體晶粒總成之結合墊及相關聯之方法及系統 Download PDFInfo
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Abstract
揭示用於半導體晶粒總成之結合墊及相關聯之方法及系統。在一個實施例中,一半導體晶粒總成包含一第一半導體晶粒,其包含在該第一半導體晶粒之一第一側上的一第一結合墊。該半導體晶粒總成進一步包含一第二半導體晶粒,其包含在該第二半導體晶粒之一第二側上的一第二結合墊。該第一結合墊在該第一與第二結合墊之間的一結合界面處與該第二結合墊對準且結合至該第二結合墊,且該第一及第二結合墊之至少一者包含一第一金屬及不同於該第一金屬之一第二金屬。此外,該第一金屬位於該結合界面處,且該第二金屬具有對應於該第一或第二結合墊之一第二厚度之至少四分之一的一第一厚度。
Description
本揭示大體上係關於半導體晶粒總成,且更特定言之,係關於用於半導體晶粒總成之結合墊及相關聯之方法及系統。
半導體封裝通常包含安裝在一基板上並裝納在一保護性遮蓋物(例如,一囊封材料)中之一半導體晶粒(例如,記憶體晶片、微處理器晶片、成像器晶片)。半導體晶粒可包含功能特徵,諸如記憶體單元、處理器電路或成像器裝置,以及電連接至功能特徵之結合墊。結合墊可電連接至基板之對應導電結構,該等導電結構可耦合至該保護性遮蓋物外部的端子,使得半導體晶粒可連接至更高層級之電路系統。
市場壓力不斷促使半導體製造商減小半導體封裝之大小以適應電子裝置之空間約束。在一些半導體封裝中,可使用直接晶片附接方法(例如,半導體晶粒與基板之間的覆晶結合)來減少半導體封裝之覆蓋區。此直接晶片附接方法包含將電耦合至半導體晶粒之多個導電支柱直接連接至基板之對應導電結構(例如,導電凸塊)。在此方面,可在個別導電支柱上方形成一焊接結構用於將導電支柱結合至對應導電結構,例如,形成包含導電支柱、焊接結構及導電凸塊之接頭結構。此外,可應用一囊封材料來保護半導體晶粒。
下文描述係關於用於半導體晶粒總成之結合墊及相關聯之系統及方法之若干實施例之特定細節。晶圓級封裝(WLP)可為半導體晶粒總成(半導體裝置總成)提供縮放形狀因數。WLP技術利用一界面晶圓,半導體晶粒或半導體晶粒之堆疊(例如,主動晶粒、已知良好晶粒、記憶體晶粒)附接至該界面晶圓。個別半導體晶粒(或半導體晶粒之堆疊)與界面晶圓之對應界面晶粒對準並且電連接至界面晶圓之對應界面晶粒。界面晶粒可包含類型與該半導體晶粒不同之半導體晶粒(例如,控制半導體晶粒之邏輯晶粒)或具有重分佈層(RDL)之中介層晶粒,該重分佈層(RDL)經組態以在半導體晶粒(或堆疊之半導體晶粒)與更高層級之電路系統(例如,邏輯晶粒及/或記憶體晶粒外部的一主機裝置)之間路由電信號。
在半導體晶粒(或半導體晶粒之堆疊)已附接至可指稱晶圓上之晶片(CoW)之界面晶圓之後,囊封材料(例如,模製化合物材料、環氧模製化合物(EMC))可安置在界面晶圓上方,使得半導體晶粒(或半導體晶粒之堆疊)浸入囊封材料中。隨後,在一高溫下固化囊封材料以硬化囊封材料以便於為半導體晶粒提供保護。可使用研磨程序步驟去除半導體晶粒(或半導體晶粒之堆疊)之上的多餘囊封材料。使用囊封材料為半導體晶粒提供保護之程序步驟可指稱一模製程序。在模製程序之後,接著可進行一或多個單切程序步驟以沿界面晶圓之劃線單切(例如,切斷、分離)個別半導體晶粒總成。
對於某些半導體晶粒總成,藉由在半導體晶粒與界面晶圓(或界面晶圓之界面晶粒)之間形成接頭結構將半導體晶粒附接至界面晶圓,例如,在半導體晶粒上形成導電支柱,在界面晶粒上形成導電凸塊,及使用焊料將導電支柱連接至導電凸塊。半導體晶粒與界面晶粒之間的一距離可指稱一結合線厚度(BLT),其與接頭結構之一總高度相關。類似地,可藉由在兩個或多個半導體晶粒(例如,記憶體晶粒)之間形成接頭結構來將其彼此連接以產生半導體晶粒之一堆疊。在一些情況下,半導體晶粒總成包含承載半導體晶粒之一堆疊(例如,4、8、12或甚至更多數量之半導體晶粒)之一界面晶粒。因此,BLT加起來限制可容納在半導體晶粒總成中之半導體晶粒之數量,同時滿足半導體晶粒總成之一高度規格。
可藉由利用直接結合方案(其亦可被指稱零BLT組態)消除半導體晶粒之間(或半導體晶粒與界面晶粒之間)之接頭結構。因此,直接結合方案可促進降低半導體晶粒總成之總體高度或增加半導體晶粒之一數量,同時滿足半導體晶粒總成之高度要求。通常,直接結合方案包含直接結合至對應之對應物之兩種或更多種不同材料(例如,導電材料及環繞導電材料之介電材料)。換言之,分別地,一第一半導體晶粒之導電材料結合至一第二半導體晶粒之對應導電材料,且第一半導體晶粒之介電材料結合至一第二半導體晶粒之對應介電材料。以此方式,直接結合方案可在第一與第二半導體晶粒之導電材料之間形成互連件(具有零BLT之導電路徑),而環繞介電材料為互連件提供電隔離及結構支撐。
因此,直接結合可指稱組合結合、混合結合或類似者。一般而言,直接結合程序包含兩個階段。首先,將兩個晶粒/晶圓(例如,一頂部晶粒/晶圓、一底部晶粒/晶圓)附接在一起,使得頂部及底部晶粒/晶圓之介電材料彼此結合。在一些實施例中,待結合之表面被活化(例如,使用一電漿處置程序)以促進表面之結合。此外,頂部及底部晶粒之結合墊(包含導電材料)面向彼此對準以在其之間形成導電路徑,如下文更詳細描述。此外,結合墊可相對於介電材料之表面(例如,一結合界面、一配合界面)凹陷,使得介電材料之結合可在不受突出結合墊干擾之情況下達成。
隨後,結合晶粒/晶圓在一高溫下退火(例如,結合後退火),使得頂部及底部晶粒之導電材料可在由凹陷與環繞結合墊之介電材料界定之一開放空間內朝向彼此膨脹(例如,由於導電材料與介電材料之間的熱膨脹係數(CTE)之不匹配)。當頂部與底部導電材料之表面接觸時,導電材料交接(例如,經由自一種導電材料至另一種導電材料之原子遷移(混雜、擴散)),以形成永久性結合,例如,冶金結合。一旦在導電墊之間形成結合,當結合之晶粒/晶圓達到半導體晶粒總成之環境溫度或操作溫度時,導電材料不分離(或切斷)。
直接結合方案為半導體裝置總成提供各種優勢。舉例而言,在直接結合方案中消除了與形成接頭結構相關聯之良率、可靠性及/或效能問題。此外,可使用用於製造半導體裝置之各種程序步驟(例如,用於形成銅互連件之程序步驟、化學機械拋光處理步驟、濕式/乾式蝕刻程序步驟)來產生結合墊,使得可縮放結合墊之間距以達成細間距半導體晶粒堆疊。此外,藉由在半導體裝置總成中容量增加數量之記憶體晶粒,例如,由於零BLT,可增加半導體裝置總成之儲存容量,同時維持相同封裝高度。
與直接結合方案相關聯之挑戰之一可能係與對經結合晶粒/晶圓(例如,使用介電層結合彼此附接之晶粒/晶圓)進行退火以在結合後退火期間在結合墊之間形成冶金結合相關聯之熱循環。在一些情況下,結合後退火溫度範圍約在大約350℃至450℃之間。在一些實施例中,鑑於在直接結合程序步驟期間使用之某些材料,例如,用於將晶圓(例如,包含記憶體晶粒之半導體晶圓、包含邏輯晶粒之界面晶圓)附接至載體基板之一黏合材料,降低結合後退火溫度可為有益的。另外,或替代地,可限制結合後退火溫度以避免對已完成其處理之半導體晶粒(例如,動態隨機存取記憶體(DRAM)產品)進行額外之熱循環。在一些情況下,額外熱循環可能會對半導體晶粒具有不期望之影響。
本技術經設計以促進直接結合方案之結合墊之間的結合。更具體言之,本技術可適合於在相對較低之溫度(例如大約200℃或更低)下進行結合後退火程序。舉例而言,結合墊可包含彼此不同之複合導電材料(除用作結合墊之一襯墊之一導電材料之外之兩種或更多種導電材料(例如,一複合金屬結構))。在此方面,在退火溫度(例如,結合後退火溫度)下展現相對更高擴散率之一導電材料可安置在結合墊之結合界面(配合界面)處。因此,至少由於更高擴散率,可增強結合墊之間的結合強度,例如,促進跨越結合界面之晶粒生長,改良跨越結合界面之導電材料之混雜,避免在結合界面處之微孔隙形成等。在一些實施例中,此等導電材料包含銅。在一些實施例中,銅主要具有(111)晶體取向,其亦可被指稱奈米孿晶(nanotwin)銅(例如,NT-Cu (111))。
此外,結合墊之遠離結合界面之剩餘部分可包含不同於奈米孿晶銅之導電材料,例如,不具有一特定主要晶體取向之銅或具有不同於(111)之一主要晶體取向之銅,諸如(100)或(110)晶體取向。NT-Cu (111)具有更高擴散率(例如,與具有其他晶體組態之銅相比,約為三(3)倍之擴散率),其促進在相對較低之結合後退火溫度(例如,大約200℃或更低)下結合墊之間的結合,例如藉由抑制銅至銅凹入孔隙形成。因而,在配合界面處包含NT-Cu (111)之結合墊可適合於使用相對較低結合後退火溫度之直接結合程序,例如,晶片至晶圓(C2W)直接結合方案、面至背(F2B)直接結合方案。
術語「半導體裝置或晶粒」通常係指包含一或多種半導體材料之一固態裝置。半導體裝置之實例包含邏輯裝置、記憶體裝置、微處理器或二極體等等。此等半導體裝置可包含積體電路或組件、資料儲存元件、處理組件及/或在半導體基板上製造之其他特徵。此外,術語「半導體裝置或晶粒」可指代一成品裝置或在變成一成品裝置之前之各種處理階段處之一總成或其他結構。取決於其使用背景,術語「基板」可指代晶圓級基板或一經單切晶粒級基板。此外,一基板可包含一半導體晶圓、一封裝支撐基板、一中介層、一半導體裝置或晶粒或類似者。一般技術者將認知,可在晶圓級或晶粒級處執行本文中所描述之方法之適合步驟。
此外,除非內容脈絡另有指示,否則可使用常規半導體製造技術來形成本文中所揭示之結構。舉例而言,可使用化學氣相沈積、物理氣相沈積、原子層沈積、旋轉塗佈、鍍敷及/或其他適合技術來沈積材料。類似地,可(例如)使用電漿蝕刻、濕式蝕刻、化學機械平坦化或其他適合技術來去除材料。一些技術可與光刻程序組合。熟習相關技術者亦將理解,技術可具有額外實施例,並且可在不具有本文參考圖2A至圖5描述之實施例之若干細節之情況下實踐該技術。
如本文中所使用,術語「垂直」、「橫向」、「向下」、「向上」、「上」及「下」可指代鑑於圖中所展示之取向之半導體晶粒總成中之特徵之相對方向或位置。舉例而言,「上」或「最上」可指代定位成比另一特徵更接近於一頁面之頂部之特徵。然而,此等術語應廣義地解釋為包含具有其他取向之半導體裝置。此外,說明書及發明申請專利範圍中之術語「前」、「後」、「頂部」、「底部」、「上方」、「下方」及類似者(若存在)用於描述目的並且不一定用於描述永久性相對位置。應理解,如此使用之術語在適當之情況下係可互換的,使得本文描述之本發明之實施例例如能夠在除本文所繪示或以其他方式描述之取向以外之其他取向上操作。除非另有繪示,否則諸如「第一」及「第二」之術語用於任意區分此等術語描述之元件。因此,此等術語不一定希望表示指示此等元件之時間優先化或其他優先化。如本文使用之術語「耦合」不希望限於一直接耦合或一機械耦合。
圖1係根據本技術之實施例之具有半導體晶粒110之堆疊之一界面基板105 (或一界面晶圓)之一圖。鑑於對準且附接至界面基板105之對應界面晶粒106之經單切個別半導體晶粒110 (或半導體晶粒110之堆疊),承載半導體晶粒110之堆疊之界面基板105可指稱一重構晶圓(或如上文描述之CoW)。儘管本技術在本文中用包含附接至界面晶粒(例如,界面晶粒106)之半導體晶粒之一堆疊(例如,半導體晶粒110之堆疊)半導體裝置總成描述,但應理解,本技術之原理不限於此。舉例而言,根據本技術之一半導體裝置總成可包含附接(或結合)至一界面晶粒之一單一半導體晶粒(例如,一記憶體晶粒)。
在一些實施例中,界面晶粒106係與類型與堆疊之半導體晶粒110 (例如,記憶體晶粒、DRAM產品)不同之半導體晶粒(例如,邏輯晶粒、控制器晶粒)。邏輯晶粒可經組態以與半導體晶粒110及與邏輯晶粒耦合之更高層級之電路系統(例如,半導體裝置總成外部的主機裝置)交換電信號。在一些實施例中,界面晶粒106係具有各種導電結構(例如,重分佈層、通路、互連件)之中介層晶粒,該導電結構經組態以在半導體晶粒110之堆疊與更高層級之電路系統,例如,透過中介層晶粒與半導體晶粒110之堆疊耦合之一中央處理單元(CPU)之間路由電信號。
半導體晶粒110之堆疊包含彼此上下堆疊之半導體晶粒110。堆疊之各半導體晶粒110具有面朝界面晶粒106之一前側,其可被指稱具有記憶體陣列、耦合至記憶體陣列之積體電路、耦合至積體電路之結合墊等之半導體晶粒之一主動側,以及與前側對置之一後側。如本文更詳細地描述,半導體晶粒110之後側可包含經構形以附接至(或結合至)另一個晶粒(或晶圓)之結合墊的結合墊。此外,半導體晶粒110可包含延伸穿過半導體晶粒110之穿基板通路(TSV),其經構形以將前側上的結合墊與後側上的結合墊耦合。堆疊之最上半導體晶粒110可指稱一頂部晶粒,並且位於頂部晶粒與界面晶粒106之間的一或多個半導體晶粒110可指稱核心晶粒。
類似地,邏輯晶粒106包含一前側(例如,具有各種積體電路、結合墊及/或耦合至積體電路之導電結構之邏輯晶粒之主動側等)及與前側對置之一後側。前側上的導電結構可包含重分佈層及通路,以及經構形以與更高層級之電路系統,例如一中央處理單元(CPU)耦合之導電支柱/墊及/或端子(例如,一球柵陣列(BGA)中之球)。邏輯晶粒106之後側可包含經構形以附接至(或結合至)另一晶粒(例如,半導體晶粒110)之結合墊的結合墊。此外,邏輯晶粒106可包含延伸穿過邏輯晶粒106之TSV,其等經構形以將前側上的結合墊與後側上的結合墊耦合。
在一些實施例中,在完成前側晶圓處理(例如,形成耦合至積體電路之結合墊)之後,使用一黏合材料將核心晶圓(包含核心晶粒之晶圓)臨時附接至載體晶圓(或基板),例如,核心晶圓之前側面向載體晶圓。隨後,可減薄核心晶圓以自後側曝露核心晶粒之TSV。在已被減薄之核心晶粒/晶圓之後側處形成各種結構以促進核心晶粒之堆疊,例如,沈積介電層以保護核心晶粒之後側,形成連接至TSV之曝露表面之結合墊等。在一些實施例中,黏合材料可約束沈積介電層(及/或對結合墊進行退火)之溫度。然後,核心晶粒被劃切並且與頂部晶粒一起堆疊在界面基板105上(例如,使用用於直接結合之程序步驟)以產生重構晶圓,如在圖1中所繪示。然而,堆疊之頂部晶粒可能比核心晶粒更厚,並且可能不具有後側導電結構(或TSV)。
用於製備半導體晶粒以將其彼此上下堆疊(例如,在晶圓之前側上形成耦合至積體電路之結合墊及/或導電結構,將晶圓臨時附接至一載體基板,自後側減薄晶圓,在後側上形成導電墊等)之程序步驟可應用於界面基板105,使得可在界面晶粒106之前側及後側上形成用於堆疊半導體晶粒之適當導電結構。因而,界面基板105可對應於已完成上文描述之程序步驟之界面晶圓,例如,已被減薄且包含用於在前側及後側上進行堆疊之適當導電結構。圖1亦描繪半導體晶粒110之堆疊之間的界面基板105之劃線115 (其可指稱劃切道、切割線或類似者)(例如,沿x方向之水平劃線115a及沿y方向之垂直劃線115b)。在一些實施例中,在完成CoW之模製程序之後,沿劃線單切個別半導體晶粒總成。
圖2A至圖2C繪示根據本技術之實施例之用於核心半導體晶粒(或包含核心半導體晶粒之核心晶圓)程序之階段。圖2A繪示在完成前側處理後形成各種結構之後之一核心半導體晶粒(例如,一核心晶圓之一核心DRAM晶粒)之一部分之一橫截面圖。舉例而言,圖2A繪示具有一前側211及與前側211對置之一後側212之一半導體晶粒210 (其可為半導體晶粒110之一實例或包含半導體晶粒110之態樣)。半導體晶粒210之前側211包含積體電路215 (例如,一記憶體陣列、可操作地耦合至記憶體陣列之周邊電路系統等)、耦合至積體電路215之一互連件層220 (例如,包含導電跡線及通路之一或多個介電層)及一穿基板通路225 (TSV)。互連件層220進一步耦合至一TSV墊226及一探針墊230。半導體晶粒210亦包含可被隔離(例如,與積體電路215電隔離)或連接至半導體晶粒210之一接地平面之一虛設墊227。在一些實施例中,墊226、227及230包含Al (或AlCu合金)。
在已經在互連件層220上形成墊226、227及230後,可形成一介電層235 (例如,在約375℃下沈積之氧化矽(SiOx))。取決於墊226、227及230提供之寬高比,一或多個氣隙245可存在於介電層235中。此後,可在介電層235上形成一介電層240 (例如,在約350℃下沈積之矽碳氮化物(SiCN))。隨後,在介電層235及240中形成結合墊245及250。個別結合墊245及250包含一導電襯墊246 (例如,TaN)及一金屬247 (例如,銅)。金屬247可包含具有不同材料性質之兩種或更多種金屬(除導電襯墊246之外),如參考圖6A及圖6B更詳細描述。
結合墊245透過TSV墊226及互連件層220耦合至TSV 225,而結合墊250未連接至半導體晶粒210之任何電主動及/或功能組件。因而,結合墊250可指稱一虛設結合墊,而結合墊245可指稱一主動結合墊。結合墊250 (或貫穿半導體晶粒210分佈之複數個結合墊250)可提供結合墊245所需之程序均勻性以滿足,例如,禁止結合墊245之表面在介電層240之表面之上突出,金屬(例如銅)在介電層240之表面之下之凹陷(凹入及/或侵蝕)在一可接受範圍內,例如,在化學機械拋光(CMP)程序步驟之後。對結合墊245及250之此要求促進前側211與其他半導體晶粒(或邏輯晶粒)之正確結合。
圖2B繪示TSV 225已自後側212曝露之後之半導體晶粒210之一橫截面圖。在此方面,半導體晶粒210已使用一黏合材料260臨時附接至一載體基板265,其中半導體晶粒210之前側211面向載體基板265。隨後,已執行一背面研磨處理(或一CMP程序)以自後側212曝露TSV 225。在一些實施例中,TSV 225之一部分可自後側212突出,並且可形成一介電層270 (例如,在約180℃下沈積之氮化矽(SiN))以覆蓋半導體晶粒210之後側。此後,可去除(例如,拋光) TSV 225之上的介電層270之一部分以曝露TSV 225,如圖2B中描繪。
圖2C繪示已在完成後側處理後形成各種結構之後之半導體晶粒210之一橫截面圖。舉例而言,圖2C繪示一介電層275 (例如,在約180℃下沈積之SiOx)、一介電層280 (例如,在約180℃下沈積之SiN或SiCN)及在介電層275及280中形成之結合墊285及290。類似於結合墊245及250,結合墊290可指稱一虛設結合墊,而結合墊285可指稱一主動結合墊。結合墊285透過延伸穿過半導體晶粒210之TSV 225耦合至結合墊245。在一些實施例中,結合墊285及290具有與結合墊245及250相同之結構構形。舉例而言,個別結合墊285及290包含一導電襯墊246 (例如,TaN)及一金屬(例如,銅),其包含具有不同材料性質之兩種或更多種金屬(除導電襯墊246之外),如參考圖6A及圖6B更詳細描述。
應注意,鑑於黏合材料260,可約束(限制)在後側212上執行各種程序步驟之溫度。舉例而言,形成介電層270、275及280之溫度小於形成介電層235及240之溫度。在如在圖2C中所展示般完成後側處理之後,半導體晶粒210可被單切並自載體基板265脫離(例如,藉由去除黏合材料260),使得半導體晶粒210可附接至界面晶粒106 (及/或彼此上下堆疊以形成半導體晶粒210之一堆疊)以形成參考圖1之CoW。
圖3繪示在完成前側及後側處理後形成各種結構之後之一界面晶圓(例如,界面基板105)之一界面晶粒310 (其可為界面晶粒106之實例或包含界面晶粒106之態樣)之一部分之一橫截面圖。因而,界面晶粒310可被視為與圖2C中所繪示之半導體晶粒210處於同一階段。舉例而言,界面晶粒310包含一前側311及與前側311對置之一後側312。界面晶粒310之前側311包含各種積體電路315 (例如,邏輯電路系統)、耦合至積體電路315之一互連件層320 (例如,包含導電跡線及通路之一或多個介電層)及一TSV 325。互連件層320進一步耦合至一TSV墊326及一探針墊330。在一些實施例中,TSV墊326、一虛設墊327及探針墊330包含Al (或AlCu合金)。TSV墊326可進一步耦合至一導電墊394,導電墊394耦合至一銅墊395。在一些實施例中,在銅墊395上形成一焊料凸塊396。在一些實施例中,導電墊394包含鋁,而焊料凸塊396包含SnAg合金。
界面晶粒310之前側311可使用一黏合材料360臨時附接至一載體基板365,使得可在界面晶粒310之後側312上執行參考圖2B及圖2C描述之後側處理。因而,界面晶粒310已自後側減薄(例如,使用背面研磨程序)以曝露TSV 325。隨後,在後側上形成介電層370 (例如,在約180℃下沈積之SiN)、375 (例如,在約180℃下沈積之氧化矽)及380 (例如,在約180℃下沈積之SiCN或SiN)。在介電層380及375中形成一結合墊385 (主動結合墊)及一結合墊390 (虛設結合墊)。在一些實施例中,結合墊385及390具有與結合墊245及250相同之結構構形。舉例而言,個別結合墊385及390包含一導電襯墊(例如,導電襯墊246)及一金屬(例如,銅),其包含具有不同材料性質之兩種或更多種金屬(除導電襯墊246之外),如參考圖6A及圖6B更詳細描述。
圖4A及圖4B繪示根據本技術之實施例之用於形成半導體晶粒總成之一程序之階段。圖4A繪示一半導體晶粒(例如,圖2C中描繪之半導體晶粒210)附接至一界面晶圓之一界面晶粒(例如,圖3中描繪之界面晶粒310),該界面晶圓透過黏合材料360附接至載體基板365。在此方面,半導體晶粒210之前側211及界面晶粒310之後側可用一電漿程序來處置以促進半導體晶粒210之介電層240 (例如,在約350℃下沈積之SiCN)與界面晶粒310之介電層380 (例如,在約180℃下沈積之SiCN或SiN)之間在一結合界面450處之結合。應注意,由於金屬之表面之凹陷,結合墊之表面(例如,結合墊245及結合墊385之金屬表面)在此階段可能不會完全連結在一起(例如,交接)。舉例而言,圖4A繪示由凹陷形成之一間隙460。
圖4B繪示在一熱退火步驟之後(例如,在大約200℃或更低溫度下持續大約2小時左右)附接至界面晶粒310之半導體晶粒210。在熱退火步驟期間,結合墊245及結合墊385之金屬(例如,銅)在由凹槽及環繞結合墊245及385之介電層240及380界定之一開放空間內朝向彼此膨脹(例如,由於金屬與介電材料之間的CTE之不匹配)。當頂部及底部金屬之表面接觸時,金屬交接(例如,經由自一種金屬至另一種金屬之原子遷移(或混雜)以形成永久性結合,例如,冶金結合。因此,結合墊245及385之金屬(例如,銅)形成連續之金屬結構(例如,不具有跨越結合界面450之間隙,例如,在熱退火步驟之後)。舉例而言,圖4B繪示在熱退火步驟期間去除間隙460。
圖5係根據本技術之實施例之一半導體晶粒總成501之一圖。半導體晶粒總成501包含在一結合界面450a處直接結合至半導體晶粒之一堆疊之一界面晶粒(例如,界面晶粒310)。半導體晶粒之堆疊包含核心半導體晶粒210a及210b (例如,半導體晶粒210)及一頂部半導體晶粒505,其等之各者在一結合界面450b及450c處直接彼此結合。
頂部半導體晶粒505包含半導體晶粒210之態樣。舉例而言,頂部半導體晶粒505包含積體電路215及耦合至積體電路215及TSV 225之互連件層220。互連件層220進一步耦合至TSV墊226及探針墊230。此外,頂部半導體晶粒505包含形成在介電層235及240中之結合墊245及250。在一些實施例中,對於頂部半導體晶粒505省略TSV 225。在一些實施例中,頂部半導體晶粒505比核心半導體晶粒210a及210b更厚,此係因為頂部半導體晶粒505可能不需要自後側減薄。
如在圖5中描繪,半導體晶粒總成501使用黏合材料360臨時附接至載體基板365。在一些實施例中,可實行模製程序步驟以為半導體晶粒總成501提供保護。隨後,個別半導體晶粒總成501可被單切並自載體基板365脫離。儘管半導體晶粒總成501繪示具有結合至界面晶粒310之三(3)個半導體晶粒(即,核心半導體晶粒210a及210b以及頂部半導體晶粒505)之半導體晶粒之堆疊,但本技術不限於此。舉例而言,半導體晶粒之堆疊可包含8、12、16、32或甚至更多數量之半導體晶粒(例如,記憶體晶粒)。
圖6A繪示根據本技術之實施例之形成結合墊之程序步驟。圖6A包含繪示用於形成個別結合墊(例如,結合墊245、285及385)之若干階段之細節之圖610至635。應理解,儘管圖6A中描繪之各種結構與繪示用於在一半導體晶粒之一後側上形成結合墊(例如,結合墊285及385)之程序步驟相關,但程序步驟適用於在一半導體晶粒(例如,結合墊245)之一前側上形成結合墊。舉例而言,圖635中描繪之結合墊685可分別對應於半導體晶粒210及310之結合墊285及/或385,而相同程序步驟可用於形成半導體晶粒210之結合墊245。
圖610描繪在一介電材料650中形成之一開口670及在開口670之側壁及底部表面上以及介電材料650之表面上形成之一導電襯墊671 (例如,參考圖2A描述之TaN襯墊246)。開口670可具有一圓形、一橢圓形或一矩形等之一覆蓋區。開口670之底部表面曝露一導電結構660,其一部分包含在介電材料650中。以此方式,導電襯墊671與導電結構660接觸。圖610亦繪示一基板665,其可為半導體晶粒210 (或界面晶粒310)之基板(例如,一矽基板)之一實例或包含其態樣。
介電材料650可為一複合介電層。在圖610中所繪示之實施例中,介電材料650包含三(3)層介電層651、652及653,其可為參考圖2C描述之介電層270、275及280 (或參考圖3描述之介電層370、375及380)之實例或包含其態樣。在其他實施例中,例如,當在一半導體晶粒之一前側上形成結合墊(例如,結合墊245)時,介電材料650可包含參考圖2A描述之介電層235及240。此外,在圖610中所繪示之實施例中,導電結構660可為TSV 225 (或TSV 325)之一實例或包含其態樣。在其他實施例中,例如,當在一半導體晶粒之一前側形成結合墊(例如,結合墊245)時,導電結構660可為如參考圖2A描述之TSV墊226之一實例或包含其態樣。
圖615描繪在開口670中且在導電襯墊671上方形成之一第一金屬675。在一些實施例中,第一金屬675包含銅,可使用一鍍液(例如,使用電鍍程序步驟)將銅鍍敷在導電襯墊671上。圖620描繪導電襯墊671之上的第一金屬675 (例如,第一金屬675之多餘部分)已被去除。在一些實施例中,CMP程序步驟用於去除第一金屬675之多餘部分並停止在導電襯墊671上。圖625描繪開口670中之第一金屬675之一部分已被去除。在一些實施例中,選擇性去除第一金屬675之濕式及/或電漿蝕刻程序步驟可用於部分去除開口670中之第一金屬675。
在一些實施例中,在開口670中選擇性形成第一金屬675之自底向上沈積程序步驟可用於用第一金屬675部分填充開口670,而非使用參考圖615 (例如,鍍銅敷步驟)、620 (例如,CMP程序步驟)及625 (例如,濕式/電漿蝕刻程序步驟)描述之程序步驟。在此方面,自底向上沈積程序步驟可在對應於開口670之底部表面之導電襯墊671之一第一部分上選擇性地形成第一金屬675 (例如銅),而不在對應於開口670之側壁表面之導電襯墊671之一第二部分上(或在介電材料650之表面之上的導電襯墊671上)形成第一金屬675。
圖625描繪部分填充開口670之第一金屬675,其中第一金屬675具有在開口670之底部表面之上並與之平行之一第一頂部表面。在一些實施例中,第一頂部表面對應於開口670之深度之至少四分之一(在圖625中表示為「D」),例如,三分之一、一半、三分之二或類似者,使得開口670之剩餘部分可填充有一第二金屬680,如參考圖630及635描述。在此方面,開口670之深度大約對應於在開口670中形成之結合墊(例如,結合墊685)之一厚度。
圖630描繪形成在開口670中(與第一金屬675接觸)及導電襯墊671上的一第二金屬680。在一些實施例中,第二金屬680包含銅,其可使用一鍍液來鍍敷(例如,使用電鍍程序步驟)。在一些實施例中,對應於第二金屬680之銅可具有與對應於第一金屬675之銅不同之性質(例如,不同晶體取向),如下文更詳細描述。
圖635描繪導電襯墊671之上的第二金屬680 (例如,第二金屬680之多餘部分)已被去除。此外,去除介電層653之表面上的導電襯墊671。在一些實施例中,CMP程序步驟可用於在停止在介電層653上之前去除第二金屬680之多餘部分及導電襯墊671。如在圖635中描繪,第二金屬680之頂部表面通常可與介電材料650之表面齊平。舉例而言,第二金屬680不在介電材料650 (例如,介電層653)之頂部表面之上突出。在圖635中所繪示之實施例中,作為CMP程序之結果,第二金屬680可相對於介電材料650之頂部表面凹陷(在圖635中表示為「R」)。應理解,描繪結合墊685之圖635不係按比例繪製的,例如,結合墊685之一寬度範圍可自0.2微米至10微米(µm)變化,而凹陷(R)之範圍可小於5奈米(nm)。
在一些實施例中,填充開口670之銅包含多個晶粒,該晶粒各自具有彼此不同之大小及材料性質。取決於形成銅之程序條件(例如,電鍍溶液、溫度、銅在其上形成之襯墊層、形成銅之後之退火條件),銅晶粒可包含某些晶體取向之一分佈,例如,(100)、(110)、(111)或類似者。舉例而言,對應於第二金屬680之銅之銅晶粒之一半以上可具有(111)晶體取向-即,銅主要或大體上具有(111)晶體取向。具有(111)晶體取向之銅可被指稱奈米孿晶(例如,NT-銅(111)),其可在直接結合程序(包含相對較低之結合後退火溫度(例如,大約200℃或更低))期間促進銅之結合(交接)。舉例而言,奈米孿晶可促進跨越結合界面之晶粒生長,跨越結合界面之銅原子之混雜,在結合界面處減少微孔隙形成等。在一些情況下,奈米孿晶可包含經組態以促進奈米孿晶形成之一晶種層,例如一強(111)取向晶種層,該晶種層之90%以上之表面處於(111)晶體取向中。
與對應於第二金屬680之銅相反,對應於第一金屬675之銅可具有不同於(111)取向之一主要晶體取向,諸如(100)或(110)取向,例如,一半以上之其銅晶粒具有不同於(111)取向之一晶體取向。在一些情況下,對應於第一金屬675之銅可不具有特定主要(或主)晶體取向,例如,第一金屬675之銅晶粒具有各種晶體取向,使得無法判定一主要或主晶體取向。儘管銅之主要(或主)晶體取向之前述實例提供為銅晶粒之一半以上具有某些晶體取向,但本技術不限於此。舉例而言,可基於具有一特定晶體取向之銅晶粒之60%、70%、80%或甚至更大部分來判定銅之主要(或主)晶體取向。
圖6B係根據本技術之實施例彼此結合之結合墊之一圖。圖6B繪示(一底部半導體晶粒之)結合墊685與(一頂部半導體晶粒之)另一結合墊690接觸(直接結合),其可為參考圖2A描述之結合墊245之一實例或包含其態樣。結合墊690可能已藉由參考圖610至635描述之程序步驟形成。舉例而言,結合墊690包含第一金屬675及第二金屬680。此外,結合墊690耦合至TSV墊226,如參考圖2A描述。
跨越結合界面450,來自結合墊685及結合墊690之第二金屬680形成第二金屬680 (例如,第二金屬680之連續片,主要具有(111)晶體取向之銅)之一單一塊,其在導電結構660 (或TSV 225、325)與TSV墊226之間提供一導電路徑,以及在結合墊685與690之間提供一機械連接。此外,直接結合至介電層240之介電層653 (或280)在頂部與底部晶粒之間提供額外結合強度。
儘管圖6B描繪包含第一金屬675及第二金屬680 (例如,一複合金屬結構)之結合墊685及690兩者,但本技術不限於此。舉例而言,在一些實施例中,結合墊685或690中之一者僅包含第一金屬675 (而另一結合墊包含複合金屬結構)。在此等實施例中,第一金屬675及第二金屬680在結合界面450處彼此結合以在導電結構660 (或TSV 225、325)與TSV墊226之間提供導電路徑。在一些實施例中,結合墊685或690中之一者僅包含第二金屬680 (而另一結合墊包含複合金屬結構)。在一些實施例中,結合墊685及690兩者僅包含第二金屬680 (結合墊685及結合墊690均不包含複合金屬結構)。
圖6B進一步繪示兩個介電層在結合界面450處彼此結合,例如,介電層653 (或280)結合至介電層240。如本文描述,介電層653 (或280)可在與介電層240 (例如,在一半導體晶粒之一前側上形成各種結構之程序步驟期間沈積)相比相對較低之程序溫度下沈積(例如,在一半導體晶粒之一後側上形成各種結構之程序步驟期間沈積)。在一些實施例中,在沈積介電層653 (或280)時存在之黏合材料260 (或360)限制介電層653 (或280)之程序溫度,如參考圖2C描述。在此方面,介電層653 (或280)與240之間的唯一差異可為沈積溫度,例如,約180℃對約350℃。在一些實施例中,介電層653 (或280)及240可具有相同材料組成,例如,SiCN。在一些實施例中,介電層653 (或280)及240可具有不同材料組成,例如,SiCN對SiN。
參考圖5描述之半導體晶粒總成501可併入無數更大及/或更複雜之系統之任一者,其一代表性實例為圖7中示意性展示之系統770。系統770可包含半導體晶粒總成501、一電源772、一驅動器774、一處理器776及/或其他子系統或組件778。半導體晶粒總成501可包含通常類似於具有上文描述之結合墊(例如,結合墊685及690之特徵)的特徵。換言之,半導體晶粒總成501包含彼此結合之結合墊,其中結合墊之至少一者包含一第一金屬及不同於第一金屬之一第二金屬。此外,第一金屬位於結合界面處,並且第二金屬具有對應於第一或第二結合墊之第二厚度之至少四分之一的一第一厚度。鑑於由於零BLT組態而可容納在封裝中之記憶體晶粒(例如,DRAM晶粒)之增加之數量,半導體晶粒總成501可在給定封裝高度下包含一增加的記憶體(或儲存)容量。
所得系統770可執行各種各樣之功能之任一者,例如記憶體儲存、資料處理及/或其他適合功能。因此,代表性系統770可包含但不限於手持裝置(例如,行動電話、平板電腦、數位閱讀器及數位音頻播放器)、電腦及器械。系統770之組件可被容置在一單一單元中或分佈在多個互連單元上方(例如,透過一通信網路)。系統770之組件亦可包含遠端裝置及各種各樣之電腦可讀媒體之任一者。
圖8係根據本技術之實施例之形成結合墊之方法之一流程圖800。流程圖800可包含如參考圖6A描述之方法之態樣。
該方法包含在一介電材料中形成一開口使得開口之一底部表面曝露包含在介電材料中之一導電結構(方塊810)。該方法進一步包含用大體上具有一第一晶體取向之第一銅來部分地填充開口,其中第一銅連接至導電結構並且包含在開口之底部表面之上且與之平行之一第一頂部表面(方塊815)。該方法進一步包含用大體上具有不同於第一晶體取向之一第二晶體取向來填充開口,其中第二銅與第一銅之第一頂部表面接觸並且包含通常與介電材料之一表面齊平之一第二頂部表面(方塊820)。
在一些實施例中,第二晶體取向對應於(111)取向。在一些實施例中,該方法進一步包含在用第一銅來部分地填充開口之前,在介電材料之表面處、在開口之側壁表面處以及在開口之底部表面處形成一導電襯墊,其中第一銅透過導電襯墊連接至導電結構。在一些實例中,用第一銅來部分地填充開口包含在對應於開口之底部表面之導電襯墊之一第一部分上形成第一銅,而不在對應於開口之側壁面之導電襯墊之一第二部分上形成第一銅。
在一些實施例中,用第一銅來部分地填充開口包含:在導電襯墊上形成第一銅使得第一銅填充開口;去除對應於介電材料之表面之平面之上的第一銅之一第一部分;及自開口部分去除第一銅之一第二部分。在一些實例中,用第二銅填充開口包含:在第一銅之第一頂部表面上方及在介電材料之表面上方形成第二銅使得第二銅填充開口;及去除在對應於介電材料之表面之一平面之上的第二銅之一部分。
應注意,上文所描述之方法描述可能之實施方案,且操作及步驟可經重新配置或以其他方式修改且其他實施方案係可行的。此外,可組合來自方法中之兩者或兩者以上之實施例。此外,本文已為了闡釋而描述技術之特定實施例,但可在不背離本揭示之情況下作出各種修改。
本文中所論述之裝置(包含一半導體裝置)可形成於一半導體基板或晶粒(諸如矽、鍺、矽鍺合金、砷化鎵、氮化鎵等)上。在一些情況下,基板係一半導體晶圓。在其他情況中,基板可為一絕緣體上矽(SOI)基板,諸如玻璃上矽(SOG)或藍寶石上矽(SOS),或另一基板上之半導體材料之磊晶層。可藉由使用各種化學物種(包含但不限於:磷、硼或砷)之摻雜來控制基板或基板子區域之導電性。摻雜可在基板之初始形成或生長期間藉由離子植入或藉由任何其他摻雜方法而執行。
如本文中使用,包含發明申請專利範圍中,如在一項目清單(例如,前面標有諸如「之至少一者」或「之一或多者」之片語之一項目清單)中使用之「或」指示一包含性清單使得(例如)A、B或C之至少一者之一清單意謂A或B或C或AB或AC或BC或ABC (即,A及B及C)。此外,如本文中使用,片語「基於」不應理解為對一組封閉條件之一引用。舉例而言,描述為「基於條件A」之一例示性步驟可基於一條件A及一條件B兩者而不脫離本揭示之範疇。換言之,如本文中使用,片語「基於」應以與片語「至少部分基於」之相同方式理解。
可從上文瞭解,本文已出於闡釋目的而描述本發明之特定實施例,但可在不背離本發明之範疇之情況下作出各種修改。實情係,在前述描述中,討論眾多特定細節以提供本技術之實施例之一透徹及可行描述。然而,熟習相關技術者將認知,可在無一或多個特定細節之情況下實踐本揭示。在其他例子中,未展示或未詳細描述通常與記憶體系統及裝置相關聯之熟知結構或操作以免使本技術之其他態樣不清楚。一般而言,應瞭解,除本文中所揭示之特定實施例之外,各種其他裝置、系統及方法亦可在本技術之範疇內。
105:界面基板
106:界面晶粒
110:半導體晶粒
115a:水平劃線
115b:垂直劃線
210:半導體晶粒
210a:核心半導體晶粒
210b:核心半導體晶粒
211:前側
212:後側
215:積體電路
220:互連件層
225:穿基板通路
226:TSV墊
227:虛設墊
230:探針墊
235:介電層
240:介電層
245:結合墊
246:導電襯墊
247:金屬
250:結合墊
260:黏合材料
265:載體基板
270:介電層
275:介電層
280:介電層
285:結合墊
290:結合墊
310:界面晶粒
311:前側
312:後側
315:積體電路
320:互連件層
325:TSV
326:TSV墊
327:虛設墊
330:探針墊
360:黏合材料
365:載體基板
370:介電層
375:介電層
380:介電層
385:結合墊
390:結合墊
394:導電墊
395:銅墊
396:焊料凸塊
450:結合界面
450a:結合界面
450b:結合界面
450c:結合界面
460:間隙
501:半導體晶粒總成
505:頂部半導體晶粒
610:圖
615:圖
620:圖
625:圖
630:圖
635:圖
650:介電材料
651:介電層
652:介電層
653:介電層
660:導電結構
665:基板
670:開口
671:導電襯墊
675:第一金屬
680:第二金屬
685:結合墊
690:結合墊
770:系統
772:電源
774:驅動器
776:處理器
778:其他子系統或組件
810:方塊
815:方塊
820:方塊
參考以下圖式可更佳地理解本技術之諸多態樣。圖中之組件不一定按比例繪製。而係,重點放在清楚地繪示本技術之原理。
圖1係根據本技術之實施例之具有半導體晶粒之堆疊之一界面晶圓之一圖。
圖2A至圖2C繪示根據本技術之實施例之用於核心半導體晶粒之一程序之階段。
圖3係繪示根據本技術之實施例之一界面晶圓之一部分之一圖。
圖4A及圖4B繪示根據本技術之實施例之用於形成半導體晶粒總成之一程序之階段。
圖5係根據本技術之實施例之一半導體晶粒總成之一圖。
圖6A繪示根據本技術之實施例之形成結合墊之程序步驟。
圖6B係根據本技術之實施例彼此結合之結合墊之一圖。
圖7係示意性地繪示包含根據本技術之實施例組態之一半導體晶粒總成之一系統之一方塊圖。
圖8係根據本技術之實施例之形成結合墊之一方法之一流程圖。
210:半導體晶粒
240:介電層
245:結合墊
310:界面晶粒
360:黏合材料
365:載體基板
380:介電層
385:結合墊
450:結合界面
Claims (20)
- 一種半導體晶粒總成,其包括: 一第一半導體晶粒,其包含在該第一半導體晶粒之一第一側上的一第一結合墊;及 一第二半導體晶粒,其包含在該第二半導體晶粒之一第二側上的一第二結合墊;其中: 該第一結合墊在該第一結合墊與該第二結合墊之間的一結合界面處與該第二結合墊對準且結合至該第二結合墊;且 該第一及第二結合墊之至少一者包含主要具有一第一晶體取向之一第一銅層及主要具有不同於該第一晶體取向之一第二晶體取向之一第二銅層,該第一銅層位於該結合界面處。
- 如請求項1之半導體晶粒總成,其中該第一晶體取向對應於(111)取向。
- 如請求項1之半導體晶粒總成,其中該第二銅層具有對應於該第一或第二結合墊之一第二厚度之至少四分之一的一第一厚度。
- 如請求項1之半導體晶粒總成,其中: 該第一半導體晶粒之該第一側包含圍繞該第一結合墊之一第一介電材料,該第一介電材料在一第一溫度下形成; 該第二半導體晶粒之該第二側包含圍繞該第二結合墊之一第二介電材料,該第二介電材料在高於該第一溫度之一第二溫度下形成;且 該第一及第二介電材料在該結合界面處結合。
- 如請求項4之半導體晶粒總成,其中該第一及第二介電材料對應於矽碳氮化物。
- 如請求項1之半導體晶粒總成,其中該第一結合墊連接至延伸穿過該第一半導體晶粒並且經構形以將該第一結合墊耦合至該第一半導體晶粒之一第三側上的一導電結構之一穿基板通路(TSV),該第三側與該第一側對置。
- 如請求項6之半導體晶粒總成,其中該第一及/或第二半導體晶粒透過該導電結構與該半導體總成外部的一裝置交換電信號。
- 如請求項1之半導體晶粒總成,其中該第二結合墊連接至延伸穿過該第二半導體晶粒並且經構形以將該第二結合墊耦合至該第二半導體晶粒之一第四側上的一第三結合墊之一穿基板通路(TSV),該第四側與該第二側對置。
- 如請求項8之半導體晶粒總成,其中: 該第二半導體晶粒之該第四側包含圍繞該第三結合墊之一第一介電材料,該第一介電材料在一第一溫度下形成;且 該第二半導體晶粒之該第二側包含圍繞該第二結合墊之一第二介電材料,該第二介電材料在高於該第一溫度之一第二溫度下形成。
- 如請求項8之半導體晶粒總成,其中: 該第三結合墊經構形以在該第二結合界面處與該半導體總成之一第三半導體晶粒之一第四結合墊結合;及 該第三及第四結合墊之至少一者包含主要具有該第一晶體取向之一第三銅層及主要具有該第二晶體取向之一第四銅層,該第三銅層位於該第二結合界面處。
- 如請求項1之半導體晶粒總成,其中: 該第一半導體晶粒對應於一邏輯晶粒或一中介層晶粒;且 該第二半導體晶粒對應於一記憶體晶粒。
- 一種方法,其包括: 在一介電材料中形成一開口使得該開口之一底部表面曝露包含在該介電材料中之一導電結構; 用大體上具有一第一晶體取向之第一銅來部分地填充該開口,其中該第一銅連接至該導電結構並且包含在該開口之該底部表面之上且與之平行之一第一頂部表面;及 用大體上具有不同於該第一晶體取向之一第二晶體取向來填充該開口,其中該第二銅與該第一銅之該第一頂部表面接觸並且包含通常與該介電材料之一表面齊平之一第二頂部表面。
- 如請求項12之方法,其中該第二晶體取向對應於(111)取向。
- 如請求項12之方法,其進一步包括: 在用該第一銅來部分地填充該開口之前,在該介電材料之該表面處、在該開口之一側壁表面處以及在該開口之該底部表面處形成一導電襯墊,其中該第一銅透過該導電襯墊連接至該導電結構。
- 如請求項14之方法,其中用該第一銅來部分地填充該開口包含: 在對應於該開口之該底部表面之該導電襯墊之一第一部分上形成該第一銅,而不在對應於該開口之該側壁面之該導電襯墊之一第二部分上形成該第一銅。
- 如請求項14之方法,其中用該第一銅來部分地填充該開口包含: 在該導電襯墊上形成該第一銅使得該第一銅填充該開口; 去除對應於該介電材料之該表面之一平面之上的該第一銅之一第一部分;及 自該開口部分去除該第一銅之一第二部分。
- 如請求項12之方法,其中用該第二銅填充該開口包含: 在該第一銅之該第一頂部表面上方及在該介電材料之該表面上方形成該第二銅使得該第二銅填充該開口;及 去除在對應於該介電材料之該表面之一平面之上的該第二銅之一部分。
- 一種半導體晶粒總成,其包括: 一邏輯晶粒,其包含一第一側及與該第一側對置之一第二側,其中: 該第一側包含積體電路系統及與其耦合之導電結構;且 該第二側包含第一結合墊,其可操作地透過延伸穿過該邏輯晶粒之穿基板通路(TSV)與該導電結構耦合;及 一記憶體晶粒,其在該邏輯晶粒之該第二側處結合,該記憶體晶粒包含具有一記憶體陣列之一前側及與該記憶體陣列可操作地耦合之第二結合墊,其中: 個別第二結合墊在該記憶體晶粒與該邏輯晶粒之間的一結合界面處與對應第一結合墊對準且結合至該對應第一結合墊;且 該第一、第二或第一及第二結合墊兩者皆包含主要具有一第一晶體取向之一第一銅層及主要具有不同於該第一晶體取向之一第二晶體取向之一第二銅層,該第一銅層位於該結合界面處。
- 如請求項18之半導體晶粒總成,其中: 該記憶體晶粒包括安置在該記憶體晶粒之與該前側對置之一後側上的第三結合墊,該第三結合墊透過延伸穿過該記憶體晶粒之穿基板通路(TSV)耦合至該第二結合墊, 該第三結合墊用在一第一溫度下形成之一第一介電材料環繞;及 該第二結合墊用在高於該第一溫度之一第二溫度下形成之一第二介電材料環繞。
- 如請求項19之半導體晶粒總成,其中該記憶體晶粒係一第一記憶體晶粒,該半導體總成進一步包括: 一第二記憶體晶粒,其包含在該第二記憶體晶粒之一前側處之第四結合墊,該第二記憶體晶粒具有與該第四結合墊可操作地耦合之一第二記憶體陣列,其中: 個別第三結合墊在該第一與第二記憶體晶粒之間的一第二結合界面處與對應第四結合墊對準且結合至該對應第四結合墊,且 該第三、第四或第三及第四結合墊兩者皆包含主要具有該第一晶體取向之一第三銅層及主要具有該第二晶體取向之一第四銅層,該第三銅層位於該第二結合界面處。
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