TW202245057A - Method for improving semiconductor bonding quality - Google Patents

Abstract

The invention provides a method for improving semiconductor bonding quality, which comprises the following steps: providing a first substrate, carrying out multiple alternating deposition steps and multiple cycles of plasma steps, each deposition step deposits a dielectric layer, each plasma step carries out a plasma impact on the surface of the deposited dielectric layer to form a dangling bond-rich surface on the surface of the dielectric layer, and carrying out a planarization step to remove part of the dielectric layer and expose a dangling bond-rich surface.

Description

Methods for Improving the Quality of Semiconductor Bonding

The invention relates to the field of semiconductor manufacturing process, in particular to a method for improving bonding quality.

In the semiconductor manufacturing process, in order to save the area used by the wafer, a multi-layer stacked electronic component structure is often formed in the vertical direction in a stacked manner, which can effectively reduce the total area and facilitate the miniaturization of the wafer.

In addition, the required electronic components can also be formed on different wafers, and then the different wafers can be bonded together to achieve the same effect of stacking. Therefore, the quality of the bonding between the wafers will affect the yield of the final semiconductor device. Improving the bonding quality between wafers is also one of the development goals in this field.

The present invention provides a method for improving the quality of semiconductor bonding, comprising providing a first substrate, performing a plurality of alternating deposition steps and a plurality of cycles of plasma steps, wherein each deposition step deposits a dielectric layer, and each plasma step performing a plasma impact on the surface of the deposited dielectric layer to form a dangling bond-rich surface on the surface of the dielectric layer, and performing a planarization step to remove part of the dielectric layer and expose a rich Surface with dangling bonds.

The present invention is characterized in that before the bonding layer of the semiconductor wafer is bonded with another bonding layer, the flatter the surface of the bonding layer and the more danglings the surface contains, the more favorable it is to improve the bond strength. suitable quality. However, reducing the surface roughness using a planarization step also reduces the number of dangling bonds on the surface. Therefore, in the method proposed by the present invention, dielectric layer deposition and plasma impact are sequentially performed in an alternating manner, thereby forming alternately stacked dielectric layers and dangling bond-rich layers. In this way, after the subsequent planarization step, it is easy to park the surface in the dangling bond-rich layer, so the number of dangling bonds on the surface is large, which is beneficial to the subsequent bonding quality.

In order to enable those who are familiar with the general skills in the technical field of the present invention to further understand the present invention, the preferred embodiments of the present invention are enumerated below, together with the accompanying drawings, the composition of the present invention and the desired effects are described in detail. .

For the convenience of description, the drawings of the present invention are only schematic diagrams for easier understanding of the present invention, and the detailed proportions thereof can be adjusted according to design requirements. As for the up-down relationship of relative elements in the figures described in the text, those skilled in the art should understand that they refer to the relative positions of objects, so they can be reversed to present the same components, which should all belong to this specification. The scope of disclosure is described here first.

Please refer to FIG. 1 , which is a partial cross-sectional view of a semiconductor structure before bonding according to a preferred embodiment of the present invention. As shown in FIG. 1 , a first dielectric layer 10 is provided, and a wire 12 is formed in the first dielectric layer 10 . The material of the first dielectric layer 10 is, for example, silicon oxide, which may be the topmost layer of a multi-layer stacked dielectric layer on a substrate (not shown in the figure), where a wiring layer is formed. It can be understood that there may be other dielectric layers or wires under the first dielectric layer 10 , which are not shown here for the sake of brevity. The wire 14 is, for example, copper or other metals with good electrical conductivity. Next, a second dielectric layer 14 , a third dielectric layer 16 and a fourth dielectric layer 18 are sequentially formed on the first dielectric layer 10 and the wire 12 . In this embodiment, the second dielectric layer 14 is, for example, silicon carbon nitride (SiCN), the third dielectric layer 16 is, for example, tetraethoxysilane (TEOS), and the fourth dielectric layer 18 is, for example, carbon nitride Silicon (SiCN), but not limited thereto.

Wherein, the fourth dielectric layer 18 is the topmost layer structure, and it is also the surface that is mainly bonded with other dielectric layers on the substrate. In the present invention, the fourth dielectric layer 18 can also be defined as the bonding layer 18. .

In the conventional technology, after the bonding layer 18 is formed by deposition etc., a plasma step is usually carried out on the surface of the bonding layer 18 to break the chemical bonds on the surface of the bonding layer 18 and form dangling-rich bonds. bond) surface, that is, to increase the number of dangling bonds on the surface of the bonding layer 18. When the number of dangling bonds is larger, more free bonds such as OH groups can be captured in the subsequent bonding steps, so the bonding quality will be more stable.

The applicant found that when the surface of the bonding layer 18 is flatter, the quality of the bonding is also better. However, when the flatness of the surface of the bonding layer 18 is increased (the roughness is reduced) by chemical mechanical polishing (CMP) or the like, a part of the surface of the bonding layer 18 will be removed. At the same time, the surface rich in dangling bonds formed after the plasma treatment in the above steps is also removed.

Therefore, the present invention provides a method for improving the bonding quality of semiconductors. The bonding layer produced by the method of the present invention has the characteristics of being flat and rich in dangling bonds, so the present invention has the advantage of improving the bonding quality.

FIG. 2 is a schematic cross-sectional view of a topmost bonding layer of the semiconductor structure in FIG. 1 . In an embodiment of the present invention, during the process of depositing the fourth dielectric layer (bonding layer) 18 , the deposition step and the plasma step are sequentially performed in a repeating and alternating manner. That is to say, the fourth dielectric layer 18 is deposited in multiple stages, and a plasma step is performed after depositing a certain thickness of the dielectric layer, and then the dielectric layer and the plasma step are continued to be deposited, and the above steps are repeated several times . The plasma step described here is similar to the plasma step described in the above paragraph, and has the function of breaking the chemical bonds on the surface of the material layer to form dangling bonds (that is, silicon bonds, (Si-)), so the surface A dangling bond rich surface 20 is formed. Therefore, when the above-mentioned repeated and alternately performing the deposition step and the plasma step are completed, a stacked structure in which the dielectric layer 19 interacts with the dangling bond-rich surface 20 will be formed, wherein the dielectric layer 19 and the dangling bond-rich surface 20 are formed. The bond surface 20 is made of the same material as the fourth dielectric layer 18 , but the dangling bond-rich surface 20 has more dangling bonds after plasma treatment. In addition, in this embodiment, a part of the surface of the dielectric layer may be damaged during the plasma step, so the surface rich in dangling bonds 20 may be a rough surface 22 (for the sake of simplicity in the drawing, only the top rich surface 22 is drawn. The dangling bond-containing surface 20 has a rough surface 22, and indeed every dangling bond-rich surface 20 may have a rough surface 22).

The execution time of the plasma steps described in this embodiment is not limited. According to the applicant's experimental results, the execution time of each plasma step is greater than 1 second.

Next, as shown in FIG. 3 , a planarization step P1 is performed, such as a chemical mechanical polishing (CMP) step, to remove a portion of the dielectric layer 19 and a portion of the dangling bond-rich surface 20 . The purpose of the planarization step is to increase the flatness of the surface of the bonding layer 18, that is, to reduce the roughness of the surface of the bonding layer 18. Therefore, after the planarization step P1 is executed, if it stops at the dangling bond-rich surface 20, the rough surface will 22 is removed to become a flat surface. It should be noted that, in this embodiment, since the above-mentioned process has already formed a plurality of dangling bond-rich surfaces 20 in the entire fourth dielectric layer (bonding layer 18) through multiple plasma steps, when the planarization After step P1 is completed, the probability of stopping the surface on the dangling bond-rich surface 20 becomes greater, that is to say, the probability of the dangling bond-rich surface 20 being exposed increases. In addition, in other embodiments of the present invention, the thickness range of the dielectric layer left after the planarization step P1 can also be predicted by observing the approximate thickness removed by the planarization step P1, and the deposition and plasma steps In doing so (FIG. 2), a more intensive plasma treatment step is performed in the vicinity of this range to further increase the probability of the dangling bond-rich surface 20 being exposed.

Subsequently, as shown in FIG. 4 , the bonding layer 18 is bonded face-to-face with another bonding layer 28 . Wherein, another bonding layer 28 may be the topmost layer of a multi-layer structure formed on another substrate, and may also include a dielectric layer 19 and a dangling bond-rich surface 20, and its manufacturing method and materials may be the same as those in the above paragraph ( The methods described in Fig. 1 to Fig. 3) are similar and will not be repeated here.

The aforementioned bonding method includes, for example, performing a surface plasma activation (SPA) step to increase the dangling bond content of the dangling bond-rich surface again. Then, the steps of passing water vapor (providing OH bonds), high-temperature dehydration (removing water vapor to leave Si-O bonds or Si-Si bonds), and face-to-face bonding may be performed in sequence. Since these technologies belong to the known technologies in the art, details are not repeated here.

Based on the above paragraphs and drawings, the present invention provides a method for improving the bonding quality of semiconductors, which includes providing a first substrate, performing a plurality of alternate deposition steps and a plurality of cycles of plasma steps, wherein each deposition step deposits a substrate electric layer, each plasma step performs a plasma impact on the surface of the deposited dielectric layer, and forms a dangling bond-rich surface on the surface of the dielectric layer, and performs a planarization step to remove part of the dielectric layer electrical layer, and expose a surface rich in dangling bonds.

In some embodiments, the execution time of each plasma step is greater than 1 second.

In some embodiments, the material of the dielectric layer is silicon carbonitride (SiCN).

In some embodiments, wherein the planarizing step comprises chemical mechanical polishing (CMP), and the planarizing step reduces the roughness of the exposed dangling bond-rich surface.

In some embodiments, the dangling bonds include silicon bonds (Si-).

In some embodiments, further comprising bonding the first substrate to a second substrate.

In some embodiments, the step of bonding the first substrate to a second substrate comprises performing a surface plasmon activation step on the dangling bond-rich surface of the first substrate, again increasing the dangling bond-rich surface. the number of dangling bonds contained in the surface, a surface plasmon activation step is performed on a dangling bond-rich surface of the second substrate, again increasing the number of dangling bonds contained in the dangling bond-rich surface, and the first The dangling bond-rich surfaces of the substrate and a second substrate are bonded in a face-to-face manner

In some embodiments, the first substrate includes alternately formed dielectric layers and dangling bond-rich surfaces.

The present invention is characterized in that before the bonding layer of the semiconductor wafer is bonded with another bonding layer, the flatter the surface of the bonding layer and the more danglings the surface contains, the more favorable it is to improve the bond strength. suitable quality. However, reducing surface roughness using a planarization step also reduces the number of dangling bonds on the surface. Therefore, in the method proposed by the present invention, dielectric layer deposition and plasma impact are sequentially performed in an alternating manner, thereby forming alternately stacked dielectric layers and dangling bond-rich layers. In this way, after the subsequent planarization step, it is easy to park the surface in the dangling bond-rich layer, so the number of dangling bonds on the surface is large, which is beneficial to the subsequent bonding quality. The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

10: The first dielectric layer 12: wire 14: Second dielectric layer 16: The third dielectric layer 18: The fourth dielectric layer (bonding layer) 19: Dielectric layer 20: dangling bond-rich surface 22: rough surface 28: Bonding layer P1: Planarization step

FIG. 1 is a schematic partial cross-sectional view of a semiconductor structure before bonding according to a preferred embodiment of the present invention. FIG. 2 is a schematic cross-sectional view of a topmost bonding layer of the semiconductor structure in FIG. 1 . FIG. 3 is a schematic cross-sectional view of the bonding layer after a planarization step. FIG. 4 is a schematic cross-sectional view of a bonding layer bonding with another bonding layer.

18: The fourth dielectric layer (bonding layer)

19: Dielectric layer

20: dangling bond-rich surface

P1: Planarization step

Claims (8)

A method for improving semiconductor bonding quality, comprising: providing a first base; performing a plurality of alternating deposition steps and a plurality of cycles of plasma steps, wherein each deposition step deposits a dielectric layer, each plasma step performs a plasma impact on the surface of the deposited dielectric layer, and A surface rich in dangling bonds is formed on the surface of the dielectric layer; A planarization step is performed to remove a portion of the dielectric layer and expose a dangling bond rich surface. The method described in item 1 of the patent claims, wherein the execution time of each plasma step is greater than 1 second. The method described in claim 1, wherein the material of the dielectric layer is silicon carbonitride (SiCN). The method of claim 1, wherein the planarizing step comprises chemical mechanical polishing (CMP), and the planarizing step reduces the roughness of the exposed dangling bond-rich surface. The method described in claim 1, wherein the dangling bonds include silicon bonds (Si-). The method described in claim 1, further comprising bonding the first substrate to a second substrate. The method described in item 6 of the scope of the patent application, wherein the step of bonding the first substrate to a second substrate comprises: performing a plasma step on the dangling bond-rich surface of the first substrate, again increasing the amount of dangling bonds contained in the dangling bond-rich surface; performing a plasma step on a dangling bond-rich surface of the second substrate, again increasing the amount of dangling bonds contained in the dangling bond-rich surface; and The dangling bond-rich surfaces of the first substrate and a second substrate are bonded face-to-face. The method according to claim 1, wherein the first substrate includes the dielectric layer and the dangling bond-rich surface alternately formed.

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