TW202239144A - Direct current offset protection circuit and method - Google Patents

Abstract

A direct current (DC) offset protection circuit includes: a DC offset detection circuit and a control circuit. The DC offset detection circuit is arranged to detect whether a DC component exists in pulse-width-modulation (PWM) signals and accordingly generate a DC offset detection result. The control circuit is arranged to control an audio system according to the DC offset detection result. The DC offset detection circuit comprises a PWM polarity judgment circuit, a cascaded integrator-comb (CIC) filter and a DC offset judgment circuit. The PWM polarity judgment circuit is arranged to judge a polarity of complementary PWM signals and accordingly generate a polarity indication value. The CIC filter is arranged to generate a filter output signal by averaging a plurality of polarity indication values. The DC offset judgment circuit is arranged to generate the DC offset detection result by comparing the filter output signal with a predetermined DC threshold.

Description

DC offset protection circuit and method

The present invention relates to an audio system, in particular to a DC offset protection circuit and method for detecting a DC component in an audio system and performing protection control.

In audio systems, the protection of circuits and components is a necessary design consideration, one of which is output DC offset protection. Generally, the DC offset voltage is defined as the DC voltage level at the input terminal or output terminal of the circuit when no voltage is applied to the input terminal of the circuit. A DC offset voltage at the output may be caused by component/component mismatch, component degradation over time, electrical overstress, or other factors. DC offset voltage will cause a large amount of DC current to flow through the speakers of the audio system, which may cause irreversible damage to the speakers. Also, the large DC current draw on the speaker could be a burn risk. For this reason, DC offset voltages can have a negative impact on audio systems and need to be appropriately reduced.

Based on the above reasons, one object of the present invention is to provide a DC offset protection circuit and method for an audio system. In various embodiments of the present invention, a DC offset detection mechanism is provided to detect DC components in PWM signals commonly used in class-D amplifier-based audio systems . The DC offset detection mechanism of the present invention mainly relies on cascaded integrator-comb (CIC) filters to average the samples of the PWM signal to detect DC in the PWM signal. Element.

An embodiment of the present invention provides a DC offset protection circuit for an audio system. The DC offset protection circuit includes: a DC offset detection circuit and a control circuit. The DC offset detection circuit is used to detect whether there is a DC component in a plurality of pulse width modulation signals, and accordingly generate a DC offset detection result. The control circuit is used for controlling at least a part of the audio system according to the DC offset detection result. The DC offset detecting circuit includes: a pulse width modulation polarity judging circuit, a cascaded integral comb filter and a DC offset judging circuit. The PWM polarity judging circuit is used for judging the polarity of the complementary PWM signal pair and generating a polarity indication value accordingly. The cascaded integral comb filter is used to generate a filter output signal by averaging a plurality of polarity indication values. The DC offset judging circuit is used for comparing the filter output signal with at least a DC offset critical value, and accordingly generates the DC offset detection result.

An embodiment of the present invention provides a DC offset protection method for an audio system. The method includes: judging the polarity of the complementary pulse width modulation signal pair, and generating a polarity indication value accordingly; using a cascaded integral comb filter to average a plurality of polarity indication values to generate a filter output signal; The filter output signal is compared with at least one DC offset threshold to generate a DC offset detection result; and at least a part of the audio system is controlled according to the DC offset detection result.

In the following text, numerous specific details are described to provide the reader with a thorough understanding of the embodiments of the present invention. However, one skilled in the art will understand how to practice the invention without one or more of the specific details, or with other methods or elements or materials, or the like. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring core concepts of the invention.

Reference in the specification to "an embodiment" means that a particular feature, structure, or characteristic described in the embodiment may be included in at least one embodiment of the present invention. Therefore, appearances of "in one embodiment" in various places in this specification do not necessarily mean the same embodiment. Furthermore, the particular features, structures, or characteristics described above may be combined in any suitable form in one or more embodiments.

Please refer to FIG. 1 , which shows a DC offset protection circuit for an audio system in an embodiment of the present invention. As shown in the figure, the audio system 10 includes (but not limited to): an audio signal processing circuit 15 , a power stage 20 , a plurality of speakers 25 , and a DC offset protection circuit 30 . The DC offset protection circuit 30 includes a DC offset detection circuit 100 and a control circuit 200 . The DC offset detection circuit 100 is configured to detect whether there is a DC component in the audio system 10 . The control circuit 200 is configured to control at least a part of the audio system 10 according to the detection result of the DC offset detection circuit 100 .

In one embodiment, the audio signal processing circuit 15 may include (not shown) a sampling rate conversion unit, an equalizer, a volume control unit, a dynamic range control unit, a limiter unit, and a PWM pulse generator, etc., so that the input The digital audio signal performs a series of audio signal processing, and accordingly drives the speaker 25 in a switching manner (ie, through a pulse-width modulation (PWM) signal). The audio system 10 may include N audio channels. The audio signal processing circuit 15 outputs 2N PWM signals corresponding to N audio channels to drive N speakers. In general, a pair of stereo speakers 25 will be driven by four PWM signals PWML+, PWML-, PWMR+ and PWMR-. Among them, the four PWM signals include two pairs of complementary signals, a pair of complementary PWM signals PWML+ and PWML- are used to drive the speaker 25 on the left channel, and another pair of complementary PWM signals PWMR+ and PWMR- are used to drive the speaker 25 on the right channel. The speaker 25 is driven on the channel. The power stage 20 further outputs a PWM signal. The power stage 20 may include a plurality of power gates controlled by PWM signals, and correspondingly provide PWM to drive the speaker 25 . Please note that the number of audio channels, speakers and PWM signals in the audio system 10 mentioned herein is not a substantial limitation on the scope of the invention.

The DC offset detection circuit 100 is coupled to the power stage 20 and detects whether there is a DC component in any PWM signal output by the power stage 20 . Based on the detection of the DC component, the DC offset detection circuit 100 will generate a detection signal DC_DET to notify the control circuit 200 . According to the detection signal DC_DET, the control circuit 200 can control the power stage 25 to stop providing the PMW signal to the speaker 25 (once a DC component is detected). According to various embodiments of the present invention, the power stage 25 will stop providing PWM signals to all speakers 25 in the audio system 10 even if only one channel contains a DC component. In yet another embodiment, the power stage 25 will stop supplying the PWM signal to the specific speaker 25 associated with the channel containing the DC component. In addition, according to various embodiments of the present invention, when a DC component is detected, the control circuit 200 can further shut down other parts of the audio system 10 .

FIG. 2 illustrates a DC offset detection circuit 100 in an embodiment of the present invention. As shown in the figure, the DC offset detection circuit 100 includes a PWM polarity determination circuit 110 , a cascaded integrator-comb (CIC) filter 120 and a DC offset determination circuit 130 . The PWM polarity determination circuit 110 is used to detect the polarity of the PWM signal output by the power stage 20, thereby generating a plurality of polarity indication values PI, wherein the polarity indication value PI is used to indicate a pair of complementary PWM signals PWMR+ and PWMR- in the PWM signal. (or yes, PWML+ and PWML-) polarity. In one embodiment, the PWM polarity determination circuit 110 generates the polarity indication value PI according to the relationship between the sampling samples of the positive PWM signal (PWMR+) and the sampling samples of the negative PWM signal (PWMR-). For example, the positive PWM signal PWMR+ and the negative PWM signal PWMR- will be sampled at specific clock edges of a reference clock (not shown). Therefore, the PWM polarity determination circuit 110 generates the polarity indication value PI according to the real-time sampling samples of the positive PWM signal PWMR+ and the negative PWM signal PWMR−. Depending on the relationship between them (ie, the sampling sample of the positive PWM signal PWMR+ is greater than, equal to or smaller than the sampling sample of the negative PWM signal PWMR−), the polarity indicator value PI will be different.

In one embodiment, the polarity indication value may be represented by a floating point number with a sign. In addition, the number of bits of the sampling samples of the complementary PWM signals PWMR+ and PWMR- is less than the number of bits of the polarity indication value. For example, the sampling samples of the positive PWM signal PWMR+ or the negative PWM signal PWMR- may be 2-bit data, and the polarity indication value PI may be 3-bit data.

The polarity indicator value PI will be output to the CIC filter 120 every time the complementary PWM signals PWMR+ and PWMR− are sampled. The CIC filter 120 is configured to average a plurality of polarity indication values PI over a period of time to generate a filter output signal F_OUT. FIG. 3 shows a schematic diagram of the structure of a CIC filter used in the DC offset detection circuit 100 in an embodiment of the present invention. As shown in the figure, the CIC filter 120 includes a first adding circuit 121 , a first register circuit 122 , a second register circuit 123 , a switch circuit 124 , a second adding circuit 125 and a third register circuit 126 .

The first summing circuit 121 is coupled to the PWM polarity judging circuit 110, and is configured to add the polarity indication value PI to the first register output RO1 from the first register circuit 122, thereby generating a first Sum the result SUM1. The first register circuit 122 is coupled to the first summing circuit 121 and is configured to store the first summing result SUM1 and provide the first register output RO1 accordingly. The polarity indicator value PI will be accumulated in the first register circuit 122 within a certain time interval. The second register circuit 123 is coupled to the first register circuit 122 and configured to store the first register output RO1 and provide the second register output RO2 accordingly. The switch circuit 124 is coupled between the first register circuit 122 and the second register circuit 123, and is configured to turn on the first register circuit 122 and the second register circuit after a predetermined time expires. The signal path between the memory circuit 123. For example, after the first summing circuit 121 has added the polarity indication value PI to the first register output RO1 for ²²² times, the switch circuit 124 will turn on the signal path. The second summing circuit 125 is coupled to the switch circuit 124 and the second register circuit 123, and is configured to subtract the second register output RO1 from the first register output RO1 when the switch circuit 124 turns on the signal path. output RO2 to provide the second summing result SUM2. The third temporary register circuit 126 is coupled to the second summation circuit 125 and the DC offset judgment circuit 130, and is configured to store the second summation result SUM2, and provide a third temporary register output accordingly, so as to As a filter output signal F_OUT. In short, the CIC filter 120 is configured to perform a moving average calculation on the polarity indicator value PI over a period of time, and the filter output signal F_OUT is the result of this calculation.

The DC offset determination circuit 130 is configured to compare the filter output signal F_OUT with at least one of a positive DC offset threshold PTH and a negative DC offset threshold NTH to generate a DC offset detection result DC_DET. Wherein, the DC offset detection result DC_DET indicates whether there is a positive DC component or a negative DC component in the PWM signal output by the power stage 20 . Referring to FIG. 4A and FIG. 4B , these figures show the waveforms of the detection result DC_DET, the filter output signal F_OUT, the positive DC offset threshold PTH and the negative DC offset threshold NTH. As shown in the figure, when the filter output signal F_OUT exceeds the positive DC offset threshold PTH, or the filter output signal F_OUT exceeds the negative DC offset threshold NTH, the DC offset detection result DC_DET will be pulled up. In one embodiment, the positive DC offset threshold PTH and the negative DC offset threshold NTH can be determined by the rated power of the speaker 25 .

FIG. 5 shows a flow chart of a DC offset protection method according to an embodiment of the present invention, and the process includes the following steps:

Step 410: Determine the polarity of the PWM signal, and generate a polarity indication value accordingly;

Step 420: Using a CIC filter to average the plurality of polarity indication values to generate a filter output signal;

Step 430: Comparing the filter output signal with at least a DC offset threshold to generate a DC offset detection signal; and

Step 440: Control at least a part of an audio system according to the DC offset detection signal.

Since the principle and specific operation of the DC offset protection circuit 30 have been explained in detail above, for the sake of brevity, further descriptions on the principle and specific operation of steps 410-440 are omitted here. It should be noted that, in addition to steps 410-440, the DC offset protection method of the present invention may have more additional steps to realize DC offset detection and protection.

In summary, the present invention provides a DC offset protection circuit and method. The DC offset detection mechanism of the present invention can be used to detect the DC component in the PWM signal used by the audio system with the class D amplifier as the core structure. Moreover, the average calculation is performed on the sampling samples of the PWM signal through the CIC filter, so as to detect the DC component in the PWM signal, so as to prevent the potential DC current from damaging the speaker or the components in the audio system.

Embodiments of the invention can be implemented using devices, methods or computer program products. Therefore, the embodiment of the present invention can take the following forms: a complete hardware architecture, a complete software architecture (including firmware, resident software, microcode, etc.), or an architecture that combines software and hardware at the same time. These architectures can be found in this The manual is described in terms of "module" or "system". Furthermore, the embodiments of the present invention can use software or firmware stored in a memory to implement the embodiments of the present invention through an appropriate instruction execution system, and any of the following technologies or related technologies can also be applied Combined to complete: an individual arithmetic logic with logic gates that can perform logic functions according to data signals, an application specific integrated circuit (ASIC) with suitable combinational logic gates, a programmable gate array (programmable gate) array, PGA) or a field programmable gate array (field programmable gate array, FPGA), etc.

The processes and blocks in the flowcharts in the specification show the architecture, functions and operations that can be realized by the systems, methods and computer software products based on various embodiments of the present invention. In this regard, each block in the flowchart or functional block diagram may represent a module, section, or portion of program code, which includes one or more executable instructions for implementing the specified logical function. In addition, each block in the functional block diagram and/or flowchart, as well as the combination of blocks, can basically be realized by a dedicated hardware system for performing specified functions or actions, or a combination of dedicated hardware and computer program instructions. . These computer program instructions can also be stored in a computer-readable medium, which can make a computer or other programmable data processing device work in a specific way, so that the instructions stored in the computer-readable medium can realize the flow chart and/or the functional block The function/action specified by the block in the figure. The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

10: Audio system 15: Audio signal processing circuit 20: power level 30: DC offset protection circuit 100: DC offset detection circuit 110: PWM polarity judgment circuit 120: CIC filter 122, 123, 126: register circuit 130: DC offset judgment circuit 200: control circuit

FIG. 1 is a schematic diagram of a structure of a DC offset protection circuit used in an audio system according to an embodiment of the present invention. FIG. 2 is a schematic structural diagram of a DC offset detection circuit in a DC offset protection circuit according to an embodiment of the present invention. FIG. 3 is a schematic diagram of the architecture of cascaded integrating comb filters used in the DC offset detection circuit according to an embodiment of the present invention. 4A and 4B are waveform diagrams illustrating combinations of DC offset detection results, filter output signals, positive DC offset thresholds, and negative DC offset thresholds. FIG. 5 is a flowchart of a DC offset protection method according to an embodiment of the present invention.

100: DC offset detection circuit

110: PWM polarity judgment circuit

120: cascaded integral comb filter filter

130: DC offset judgment circuit

Claims (10)

A DC offset protection circuit for an audio system, comprising: A DC offset detection circuit for detecting DC components in a plurality of pulse-width modulation (PWM) signals, including: A PWM polarity judging circuit, used to judge the polarity of the complementary PWM signal pair, and generate a polarity indication value accordingly; a cascaded integrator-comb (CIC) filter, coupled to the PWM polarity judging circuit, for generating a filter output signal by averaging a plurality of polarity indication values; and a DC offset judging circuit, coupled to the CIC filter, for comparing the output signal of the filter with at least a DC offset threshold, thereby generating a DC offset detection result; and A control circuit, coupled to the DC offset judging circuit, is used for controlling at least a part of the audio system according to the DC offset detection result. The DC offset protection circuit as described in Claim 1, wherein the PWM polarity judgment circuit generates a The polarity indicates the value. The DC offset protection circuit as claimed in claim 1, wherein the number of bits of the sampling sample of the complementary PWM signal pair is lower than the number of bits of the polarity indication value, and the polarity indication value is a floating point with a sign number. The DC offset protection circuit as claimed in item 1, wherein the CIC filter includes: a first summing circuit, coupled to the PWM polarity judging circuit, for adding the polarity indication value and a first register output to generate a first summing result; a first register circuit, coupled to the first summing circuit, for storing the first summing result and providing the first register output accordingly; a second register circuit coupled to the first register circuit for storing the first register output and providing a second register output accordingly; a switch circuit, coupled between the first register circuit and the second register circuit, for turning on the first register circuit and the second register circuit after a predetermined time expires a signal path between circuits; a second summing circuit, coupled to the switch circuit and the second register circuit, for subtracting the second register from the output of the first register when the switch circuit turns on the signal path device output to provide a second summation result; and A third register circuit, coupled to the second summing circuit and the DC offset judgment circuit, for storing the second summing result, thereby providing a third register output as the filter output signal. The DC offset protection circuit as described in claim 1, wherein the DC offset judgment circuit is used to compare the output signal of the filter with at least one of a positive DC offset threshold and a negative DC offset threshold comparing to generate the DC offset detection result, wherein the DC offset detection result indicates whether there is a positive DC component or a negative DC component in the PWM signal. A DC offset protection method for an audio system, comprising judging the polarity of a complementary pulse-width modulation (PWM) signal pair, and generating a polarity indication value accordingly; using a cascaded integrator-comb (CIC) filter to average a plurality of polarity indication values to generate a filter output signal; comparing the filter output signal with at least one DC offset threshold to generate a DC offset detection result; and Controlling at least a part of the audio system according to the DC offset detection result. The DC offset protection method as described in claim item 6, wherein the step of generating the polarity indication value includes: The polarity indication value is generated according to a relationship between a sampling sample of a positive PWM signal and a sampling sample of a negative PWM signal in the pair of complementary PWM signals. The DC offset protection method as claimed in claim 6, wherein the number of bits of the sampling sample of the complementary PWM signal pair is lower than the number of bits of the polarity indication value, and the polarity indication value is a floating point with a sign number. The DC offset protection method as described in claim 6, wherein the step of using the CIC filter to average the plurality of polarity indication values to generate the filter output signal includes: adding the polarity indication value and a first temporary register output by using a first summing circuit to generate a first summing result; storing the first summation result with a first register circuit, and providing the first register output accordingly; subtracting a second register output from the first register output after expiration of a predetermined time using a second summing circuit to provide a second summing result; and using a second register circuit to store the first register output after expiration of a predetermined time and provide the second register output accordingly; and A third register circuit is used to store the second summation result, and accordingly a third register output is provided as the filter output signal. The DC offset protection method as described in claim 6, wherein the step of comparing the filter output signal with the at least one DC offset threshold to generate the DC offset detection result includes: comparing the filter output signal with at least one of a positive DC offset threshold and a negative DC offset threshold to generate the DC offset detection result, wherein the DC offset detection result indicates Whether there is a positive DC component or a negative DC component in the PWM signal.

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