CN115243157A

CN115243157A - DC offset protection circuit and method

Info

Publication number: CN115243157A
Application number: CN202110440618.XA
Authority: CN
Inventors: 邱信源; 杨翔宇
Original assignee: Elite Semiconductor Memory Technology Inc
Current assignee: Elite Semiconductor Memory Technology Inc
Priority date: 2021-04-23
Filing date: 2021-04-23
Publication date: 2022-10-25

Abstract

A dc offset protection circuit for an audio system, comprising: a DC offset detection circuit for detecting whether a plurality of pulse-width modulation (PWM) signals have DC components to generate a DC offset detection result; and a control circuit for controlling at least a portion of the audio system based on the DC offset detection result. The DC offset detection circuit comprises: a PWM polarity judgment circuit, a cascade integrator-comb filter and a DC offset judgment circuit. The PWM polarity judging circuit judges the polarity of the complementary PWM signal pair to generate a polarity indicating value. The cascaded integrator-comb filter averages the polarity indication values to produce a filter output signal. The DC offset judgment circuit compares the output signal of the filter with at least one DC offset critical value to generate the DC offset detection result.

Description

DC offset protection circuit and method

Technical Field

The present invention relates to an audio system, and more particularly, to a dc offset protection circuit and method for detecting a dc component and performing protection control in an audio system.

Background

In an audio system, protection of circuits and components is a necessary design consideration, one of which is output dc offset protection. In general, a dc offset voltage is defined as the dc voltage level at the input or output of a circuit when no voltage is applied to the input of the circuit. Dc offset voltage at the output may be caused by device/device mismatch, time-induced device degradation, electrical overstress (electrical stress), or other factors. The dc offset voltage will cause a large amount of dc current to flow through the speakers of the audio system, possibly causing irreversible damage to the speakers. In addition, large dc current drains on the speaker may risk burning. In view of this, the dc offset voltage may adversely affect the audio system, and therefore needs to be reduced appropriately.

Disclosure of Invention

For the above reasons, it is an object of the present invention to provide a dc offset protection circuit and method for an audio system. In various embodiments of the present invention, a dc offset detection mechanism is provided to detect dc components in pulse width modulated signals that are typically used in class D amplifier based audio systems. The DC offset detection mechanism of the invention mainly depends on a cascaded integrator-comb (CIC) filter to carry out average calculation on the sampling of the pulse width modulation signal, thereby detecting the DC component in the pulse width modulation signal.

An embodiment of the present invention provides a dc offset protection circuit for an audio system, the dc offset protection circuit comprising: a DC offset detection circuit and a control circuit. The DC offset detection circuit is used for detecting whether DC components exist in a plurality of pulse width modulation signals or not and generating a DC offset detection result according to the DC components. The control circuit is configured to control at least a portion of the audio system based on the DC offset detection result. The DC offset detection circuit comprises: a pulse width modulation polarity judgment circuit, a cascade integrator-comb filter and a DC offset judgment circuit. The pulse width modulation polarity judging circuit is used for judging the polarity of the complementary pulse width modulation signal pair and generating a polarity indicating value according to the polarity indicating value. The cascaded integrator-comb filter is configured to generate a filter output signal by averaging a plurality of polarity indication values. The DC offset judgment circuit is used for comparing the output signal of the filter with at least one DC offset critical value, and accordingly generating the DC offset detection result.

An embodiment of the present invention provides a dc offset protection method for an audio system. The method comprises the following steps: judging the polarity of the complementary pulse width modulation signal pair, and generating a polarity indication value according to the polarity indication value; averaging a plurality of polarity indication values by a cascade integrator comb filter to generate a filter output signal; comparing the output signal of the filter with at least one DC offset threshold value to generate a DC offset detection result; and controlling at least a portion of the audio system based on the DC offset detection result.

Drawings

Fig. 1 is a schematic diagram illustrating an architecture of a dc offset protection circuit for an audio system according to an embodiment of the present invention.

Fig. 2 is a schematic diagram illustrating a dc offset detection circuit in a dc offset protection circuit according to an embodiment of the invention.

FIG. 3 is a schematic diagram of a cascaded integrator-comb filter used in a DC offset detection circuit according to an embodiment of the present invention.

Fig. 4A and 4B are waveform diagrams illustrating a combination of the dc offset detection result, the filter output signal, the positive dc offset threshold and the negative dc offset threshold.

FIG. 5 is a flow chart of a DC offset protection method according to an embodiment of the invention.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a thorough understanding of embodiments of the invention to the reader. However, those skilled in the art will understand how to implement the invention without one or more of the specific details, or with other methods or components or materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the invention.

Reference in the specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the invention. Thus, the appearances of the phrase "in one embodiment" appearing in various places throughout the specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics described above may be combined in any suitable manner in one or more embodiments.

Referring to fig. 1, a dc offset protection circuit for an audio system according to an embodiment of the present invention is shown. As shown, audio system 10 includes (but is not limited to): audio signal processing circuit 15, power stage 20, a plurality of speakers 25, and dc offset protection circuit 30. The dc offset protection circuit 30 includes a dc offset detection circuit 100 and a control circuit 200. The dc offset detection circuit 100 is arranged to detect the presence of a dc component in the audio system 10. The control circuit 200 is arranged to control at least a part of the audio system 10 in dependence of the detection result of the dc offset detection circuit 100.

In one embodiment, the audio signal processing circuit 15 may include (not shown) a sampling rate conversion unit, an equalizer, a volume control unit, a dynamic range control unit, a clipping unit, a PWM pulse generator, and the like, so as to perform a series of audio signal processing on the input digital audio signal and accordingly drive the speaker 25 in a switching manner (i.e., by a pulse-width modulation (PWM) signal). Audio system 10 may contain N audio channels. The audio signal processing circuit 15 outputs 2N PWM signals corresponding to N audio channels, thereby driving N speakers. In a general case, a pair of stereo speakers 25 will be driven by four PWM signals PWML +, PWML-, PWMR + and PWMR-. Of these, two pairs of complementary PWM signals are included in the four PWM signals, one pair of complementary PWM signals PWML + and PWML-for driving the speaker 25 on the left channel, and the other pair of complementary PWM signals PWMR + and PWMR-for driving the speaker 25 on the right channel. The power stage 20 further outputs a PWM signal. Power stage 20 may include a plurality of power switches (power gates) controlled by PWM signals and accordingly provide PWM to drive speaker 25. Note that the number of channels, speakers, and PWM signals within audio system 10 as found herein is not a substantial limitation of the scope of the invention.

The dc offset detection circuit 100 is coupled to the power stage 20 and detects whether a dc component exists in any PWM signal outputted from the power stage 20. Based on the detection of the DC component, the DC offset detection circuit 100 will generate a detection signal DC _ DET to notify the control circuit 200. In response to the detection signal DC _ DET, the control circuit 200 may control the power stage 25 to stop providing the PMW signal to the speaker 25 (upon detection of the direct current component). According to various embodiments of the present invention, power stage 25 will stop providing PWM signals to all speakers 25 in audio system 10 even if only one channel contains a dc component. In yet another embodiment, the power stage 25 will stop providing PWM signals to the particular speaker 25 associated with the channel containing the dc component. In addition, control circuit 200 may further shut down other portions of audio system 10 when a dc component is detected, in accordance with various embodiments of the present invention.

Fig. 2 shows a dc offset detection circuit 100 according to an embodiment of the invention. As shown, the dc offset detection circuit 100 includes a PWM polarity determination circuit 110, a cascaded integrator-comb (CIC) filter 120, and a dc offset determination circuit 130. The PWM polarity determining circuit 110 is configured to detect the polarity of the PWM signal output by the power stage 20, so as to generate a plurality of polarity indication values PI, where the polarity indication values PI are used to indicate the polarities of a pair of complementary PWM signals PWMR + and PWMR- (or PWML + and PWML-) in the PWM signal. In one embodiment, the PWM polarity determination circuit 110 generates the polarity indication value PI according to a relationship between the sampled samples of the positive PMW signal (PWMR +) and the sampled samples of the negative PWM signal (PWMR-). For example, the positive PMW signal PWMR + and the negative PWM signal PWMR-will be sampled at a particular frequency edge of a reference frequency (not shown). Therefore, the PWM polarity determination circuit 110 generates the polarity indication value PI from the real-time sample of the positive PMW signal PWMR + and the negative PWM signal PWMR-. Depending on the relationship between them (i.e., the sampled samples of the positive PMW signal PWMR + are greater than, equal to, or less than the sampled samples of the negative PWM signal PWMR-), the polarity indication values PI will be different.

In one embodiment, the polarity indication value may be represented by a signed floating point number. In addition, the number of bits of the sampled samples of the complementary PWM signals PWMR + and PWMR-is less than the number of bits of the polarity indication value. For example, the sample of the positive PWM signal PWMR + or the negative PWM signal PWMR-may be 2-bit data, and the polarity indication value PI may be 3-bit data.

The polarity indication value PI is output to the CIC filter 120 every time the complementary PWM signals PWMR + and PWMR-are sampled. The CIC filter 120 is arranged to average a plurality of polarity indication values PI over a period of time to generate a filter output signal F _ OUT. Fig. 3 shows an architecture diagram of the dc offset detection circuit 100 using a CIC filter according to an embodiment of the present invention. As shown, the CIC filter 120 includes a first adding circuit 121, a first buffer circuit 122, a second buffer circuit 123, a switch circuit 124, a second adding circuit 125, and a third buffer circuit 126.

The first summing circuit 121 is coupled to the PWM polarity determining circuit 110 and configured to SUM the polarity indication value PI with the first buffer output ROl from the first buffer circuit 122, thereby generating a first summing result SUM1. The first register circuit 122 is coupled to the first summing circuit 121 and is configured to store the first summing result SUM1 and accordingly provide a first register output RO1. The polarity indication value PI is accumulated in the first buffer circuit 122 for a certain time interval. The second register circuit 123 is coupled to the first register circuit 122 and is configured to store the first register output RO1 and to provide the second register output RO2 accordingly. The switch circuit 124 is coupled between the first buffer circuit 122 and the second buffer circuit 123, and is configured to conduct a signal path between the first buffer circuit 122 and the second buffer circuit 123 after a predetermined time expires. For example, after the first summing circuit 121 has added the polarity indication value PI to the first buffer output RO1 for 222 times, the switch circuit 124 will turn on the signal path. The second summing circuit 125 is coupled to the switch circuit 124 and the second register circuit 123, and is configured to subtract the first register output RO1 from the second register output RO2 to provide a second summing result SUM2 when the switch circuit 124 turns on the signal path. The third buffer circuit 126 is coupled to the second summing circuit 125 and the dc offset determination circuit 130, and is configured to store the second summing result SUM2 and accordingly provide a third buffer output as the filter output signal F _ OUT. In short, the CIC filter 120 is arranged to perform a moving average calculation on the polarity indication PI over a period of time, and the filter output signal F _ OUT is the result of this calculation.

The DC offset decision circuit 130 is configured to compare the filter output signal F _ OUT with at least one of a positive DC offset threshold PTH and a negative DC offset threshold NTH to generate a DC offset detection result DC _ DET. Here, the DC offset detection result DC _ DET indicates whether a positive DC component or a negative DC component exists in the PWM signal output from the power stage 20. Referring to fig. 4A and 4B, waveforms of the detection result DC _ DET, the filter output signal F _ OUT, the positive DC offset threshold PTH and the negative DC offset threshold NTH are shown. As shown, when the filter output signal F _ OUT exceeds the positive DC offset threshold PTH, or the filter output signal F _ OUT exceeds the negative DC offset threshold NTH, the DC offset detection result DC _ DET will be pulled up. In one embodiment, positive dc offset threshold PTH and negative dc offset threshold NTH may be determined by the power rating of speaker 25.

Fig. 5 is a flow chart of the dc offset protection method according to the embodiment of the invention, the flow chart includes the following steps:

step 410: judging the polarity of the pulse width modulation signal and generating a polarity indication value according to the polarity of the pulse width modulation signal;

step 420: averaging a plurality of polarity indication values by using a CIC filter to generate a filter output signal;

step 430: comparing the output signal of the filter with at least one DC offset critical value to generate a DC offset detection signal; and

step 440: controlling at least a portion of an audio system according to the DC offset detection signal.

Since the principles and specific operations of dc offset protection circuit 30 have been explained in detail above, further explanation regarding the principles and specific operations of steps 410-440 is omitted here for the sake of brevity. It is noted that the dc offset protection method of the present invention may have more additional steps besides steps 410 to 440 to implement dc offset detection and protection.

To summarize, the present invention provides a dc offset protection circuit and method. The DC offset detection mechanism of the present invention can be used to detect the DC component in the PWM signal used in the audio system with class D amplifier as the core structure. And, an averaging calculation is performed on the sampled samples of the PWM signal by the CIC filter to detect a dc component in the PWM signal to prevent potential dc current from damaging components within the speaker or audio system.

Embodiments of the invention may be implemented using an apparatus, a method or a computer program product. Thus, embodiments of the invention may take the form of: an entirely hardware architecture, an entirely software architecture (including firmware, resident software, micro-program code, etc.) or an architecture combining software and hardware, which may be described herein in the context of a "module" or "system. Furthermore, in addition to implementing embodiments of the present invention using software or firmware stored in a memory by a suitable instruction execution system, any one or combination of the following techniques may be implemented: an individual arithmetic logic unit having logic gates for performing logic functions according to data signals, an Application Specific Integrated Circuit (ASIC) having appropriate combinational logic gates, a Programmable Gate Array (PGA) or a Field Programmable Gate Array (FPGA), etc.

The flowcharts and blocks in the flowcharts within this specification illustrate the architecture, functionality, and operation of what may be implemented by systems, methods and computer software products according to various embodiments of the present invention. In this regard, each block in the flowchart or functional block diagrams may represent a module, segment, or portion of program code, which comprises one or more executable instructions for implementing the specified logical function(s). In addition, each block of the functional block diagrams and/or flowchart illustrations, and combinations of blocks, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer program instructions. These computer program instructions may also be stored in a computer-readable medium that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable medium implement the function/act specified in the flowchart and/or block diagram block or blocks.

The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in accordance with the claims of the present invention should be covered by the present invention.

[ notation ] to show

10. Audio system

15. Audio signal processing circuit

20. Power stage

30. DC offset protection circuit

100. DC offset detection circuit

110 PWM polarity judging circuit

120 CIC filter

122. 123, 126 buffer circuit

130. DC offset judgment circuit

200. A control circuit.

Claims

1. A dc offset protection circuit for an audio system, comprising:

a dc offset detection circuit for detecting dc components in a plurality of Pulse Width Modulated (PWM) signals, comprising:

a PWM polarity judging circuit for judging the polarity of the complementary PWM signal pair and generating a polarity indication value according to the polarity indication value;

a cascaded integrator-comb (CIC) filter coupled to the PWM polarity decision circuit for generating a filter output signal by averaging a plurality of polarity indication values; and

a DC offset judgment circuit, coupled to the CIC filter, for comparing the output signal of the filter with at least one DC offset threshold value, thereby generating a DC offset detection result; and

a control circuit, coupled to the dc offset determining circuit, for controlling at least a portion of the audio system according to the dc offset detection result.

2. The dc offset protection circuit of claim 1, wherein the PWM polarity determination circuit generates the polarity indication value according to a relationship between a sampled sample of a positive PWM signal and a sampled sample of a negative PWM signal of the complementary PWM signal pair.

3. The dc offset protection circuit of claim 1, wherein the complementary PWM signal pair has sampled samples with a lower number of bits than the polarity indication value, and the polarity indication value is a signed floating point number.

4. The dc offset protection circuit of claim 1, wherein the CIC filter comprises:

a first summing circuit coupled to the PWM polarity determining circuit for summing the polarity indication value and a first buffer output to generate a first summing result;

a first register circuit, coupled to the first summing circuit, for storing the first summing result and providing the first register output accordingly;

a second register circuit, coupled to the first register circuit, for storing the first register output and providing a second register output accordingly;

a switch circuit, coupled between the first register circuit and the second register circuit, for conducting a signal path between the first register circuit and the second register circuit after a predetermined time expires;

a second summing circuit, coupled to the switch circuit and the second buffer circuit, for subtracting the second buffer output from the first buffer output to provide a second summing result when the switch circuit turns on the signal path; and

a third register circuit, coupled to the second summing circuit and the dc offset determining circuit, for storing the second summing result and providing a third register output as the filter output signal accordingly.

5. The dc-offset protection circuit of claim 1, wherein the dc-offset decision circuit is configured to compare the filter output signal with at least one of a positive dc-offset threshold and a negative dc-offset threshold to generate the dc-offset detection result, wherein the dc-offset detection result indicates whether a positive dc component or a negative dc component exists in the PWM signal.

6. A DC offset protection method for an audio system includes

Judging the polarity of the complementary Pulse Width Modulation (PWM) signal pair, and generating a polarity indication value according to the polarity indication value;

averaging a plurality of polarity indication values using a cascaded integrator-comb (CIC) filter to generate a filter output signal;

comparing the output signal of the filter with at least one DC offset threshold value to generate a DC offset detection result; and

controlling at least a portion of the audio system based on the DC offset detection result.

7. The method of claim 6, wherein the step of generating the polarity indication value comprises:

the polarity indication value is generated based on a relationship between a sampled sample of a positive PWM signal and a sampled sample of a negative PWM signal of the complementary PWM signal pair.

8. The method of claim 6, wherein the complementary PWM signal pair has sampled samples with a lower number of bits than the polarity indication value, and the polarity indication value is a signed floating point number.

9. The method of claim 6, wherein the step of averaging the plurality of polarity indication values by the CIC filter to generate the filter output signal comprises:

using a first summation circuit to sum the polarity indication value and a first buffer output to generate a first summation result;

storing the first summation result with a first register circuit and providing the first register output accordingly;

subtracting a second buffer output from the first buffer output after a predetermined time expires using a second summing circuit to provide a second summing result; and

utilizing a second register circuit to store the first register output after expiration of a predetermined time and to provide the second register output accordingly; and

a third register circuit is used to store the second summation result and accordingly provide a third register output as the filter output signal.

10. The method of claim 6, wherein comparing the filter output signal with the at least one DC offset threshold to generate the DC offset detection result comprises:

the filter output signal is compared with at least one of a positive dc offset threshold and a negative dc offset threshold to generate the dc offset detection result, wherein the dc offset detection result indicates whether a positive dc component or a negative dc component exists in the PWM signal.