JP2010284018A - Motor driving apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To certainly correct a variation while leaving the possibility of the detection of a phase current, based on a current detection in a DC bus in a three-phase motor as it is. <P>SOLUTION: According to a motor driving apparatus, modulation output values are corrected particularly on the basis of specified output limit conditions regarding two phases excepting a zero phase, and output as correction output values, and the variation errors of the modulation output values and the correction output values are integrated. According to the motor driving apparatus, the correction of the variation is solved by including a correction means correcting the variation errors integrated regarding the correction output values and a current detecting means detecting a current value flowing through the DC bus for a bridge circuit within a range satisfying the output limit conditions after the next PWM period. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention detects a current in a DC bus of a bridge circuit in a motor drive device that applies a pulse width modulation (PWM) voltage to a coil terminal of a motor in order to rotationally drive a multiphase motor. Thus, the present invention relates to a motor drive device that detects a phase current flowing through a coil of a motor.

  In the field of home appliances, OA equipment, or vehicle electric motors, non-commutator motors that perform commutation by an electric circuit using a switching element such as brushless motors and induction motors are widely used. Research and development of drive methods is actively conducted. One of such research and development is vector control. Here, in the case of vector control of a multi-phase motor, it is necessary to detect the phase current value flowing through the coils of all phases of the motor. For example, in the Y-connected three-phase motor, information on the phase current values of all phases is obtained. In order to obtain it, it is necessary to detect phase current values of at least two phases of the U phase, the V phase, and the W phase. It is necessary to provide two systems of current detection means for this detection, which causes an increase in cost.

  In order to solve this problem, a technique called a one-shunt resistance current detection method has been proposed in which current detection means is provided on a DC bus of a bridge circuit, and current for two phases is detected from the current of the DC bus. For example, Patent Document 1 describes that in order to drive a three-phase motor, a current detection shunt resistor is connected to a bus of an inverter unit composed of six switching elements to detect a current of each phase. ing.

As described in Patent Document 1, the phase current of the phase in which the switching element of the upper arm is ON flows to the DC bus without flowing back through the motor coil and the bridge circuit. In other words, the current value of the DC bus is the sum of the phase currents of the phases in which the upper switching elements are ON, except when all the switching elements of the three-phase upper arm are simultaneously turned ON. By sampling the output of the current detection means at an appropriate timing based on ON / OFF of the switching element of the bridge circuit, a two-phase phase current value can be detected.
However, in this method, when the duty value of the PWM signal for driving ON / OFF of the switching element of each phase is large to some extent, and when the difference in the duty value of the PWM signal between the phases is large, the two-phase current is generated without any problem. Although it can be detected, when the duty value of the PWM signal is small and when the duty value of the PWM signal between the phases is close, current detection for two phases cannot be performed. The lower limit value of the duty value of the PWM signal that enables this current detection and the lower limit value of the difference in duty value of the PWM signal between phases are determined by the circuit bandwidth of the current detection means and the degree of convergence of the ringing of the signal.

  Therefore, in Patent Document 2, when an output command value at which current for two phases cannot be detected is input in one shunt resistance current detection, an interval in which current detection is possible by correcting by increasing or decreasing the PWM signal. In addition, a method has been proposed in which the current can be detected and the output is deducted to zero by correcting the length of the PWM signal in the next PWM cycle by the amount increased or decreased by the correction. .

As described above, in the prior art, in order to detect the current of the DC bus, the length of the PWM pulse of a certain PWM cycle is corrected for increase / decrease, and the increase / decrease is corrected for the PWM pulse of the next PWM cycle. However, there is a possibility that the increase / decrease cannot be corrected with respect to the PWM pulse of the next PWM cycle. For example, when correction is performed to increase the length of the PWM pulse in a certain PWM cycle, the PWM pulse based on the command value input in the next PWM cycle is too short and becomes zero when the increase correction is reduced. Is the case. At this time, since the switching element of the upper arm is not turned ON in the PWM cycle to be corrected, the phase current does not flow to the DC bus. That is, there is a problem that correction of the increase / decrease may not be possible while detecting the phase current based on the current detection in the DC bus.
Therefore, it is an object of the present invention to reliably correct the increase / decrease while enabling detection of the phase current based on the current detection in the DC bus in the three-phase motor.

  This problem is a circuit in which a pair of an upper arm and a lower arm are connected in three phases, in which a switching element and a diode are connected in parallel, in the motor drive device according to the present invention. At least with respect to a bridge circuit that is connected to a coil terminal of a three-phase motor and applies a pulse-width modulated voltage to the coil terminal, and an output command value indicating a voltage to be applied to the coil terminal of each phase of the three-phase motor. Modulation means for two-phase modulation of the output command value of three phases and outputting as a modulation output value so that one phase is always a zero phase that is zero output, and modulation output values for two phases excluding the zero phase are predetermined. Is corrected based on the output limit condition, output as a corrected output value, and the increase / decrease error of the modulation output value and the corrected output value is integrated. Accumulated In the bridge circuit in accordance with a predetermined switching element drive logic from the correction means for correcting the reduction error, the PWM means for generating the PWM signal by pulse width modulating the correction output value of each phase, and the PWM signal of each phase This is solved by providing a gate signal generating means for generating a gate signal for the switching element of each phase and a current detecting means for detecting a current value flowing through the DC bus of the bridge circuit.

The correcting means includes an integrator that integrates the increase / decrease error for the two phases excluding the zero phase. When the zero phase shifts to a different phase in the next PWM cycle, the phase that becomes a non-zero phase from the next PWM cycle. The accumulator that accumulates the increase / decrease error of the phase that becomes the zero phase is loaded by inverting the sign of the accumulator value that accumulates the increase / decrease error of the phase that becomes the new zero phase. It is preferable to subtract the value of the integrator of the phase that becomes a new zero phase from the value.
Moreover, it is preferable that the current detection means detect a potential difference between both ends of the shunt resistor inserted in series with the DC bus.

Further, it is preferable that the current detection means execute current detection sampling at a timing when a predetermined interval has elapsed from the rising edge of the PWM signal of each phase.
Further, the PWM means compares the corrected output value of each phase, and when there is a set of phases in which the magnitude of the difference between the phases is smaller than the output difference threshold, the PWM signal of one of these phases is It is preferable that the output is delayed by a minimum value between the edges of the PWM signal.

The gate signal generating means generates a gate signal of the switching element of the upper arm, which is a signal delayed by a predetermined value with respect to the PWM signal of each phase, inverts the PWM signal of each phase, and It is preferable to generate a gate signal for the lower arm, which is a signal obtained by delaying the rise or fall of the signal by twice the predetermined value.
Further, as a predetermined output restriction condition, if the intermediate value of the modulation output value of each phase is less than the output restriction value, the correction means corrects the intermediate value to the output restriction value and outputs it as a corrected output value. Is more than the output limit value, it is preferable to output the intermediate value as it is as the corrected output value.

  According to the present invention, even if the length of the PWM pulse is corrected in a certain PWM cycle and the increase / decrease by the correction is integrated and the increase / decrease in the length of the PWM pulse cannot be corrected in the next PWM cycle, Since correction is performed in the following PWM cycles, phase current can be detected by detecting the current of the DC bus in all PWM cycles, and a voltage can be applied to the coil terminal with high accuracy in response to the output command value. it can.

Also, even if there is an increase / decrease to be corrected in the PWM pulse in the output of a certain phase, even if it changes to the zero phase of zero output, wait until the phase becomes non-zero again. Instead, by shifting the increase / decrease error to another phase, the error can be corrected quickly while maintaining the two-phase modulation.
Further, by using a shunt resistor, a three-phase coil current can be detected with an inexpensive configuration without using expensive components such as a current detection IC.

In addition, the current detection means executes current detection sampling at a timing when a predetermined interval has elapsed from the rising edge of the PWM signal of each phase, so that the waveform of the DC bus or the current detection means when the switching element is switched ON / OFF The influence of ringing or rise delay can be avoided, and current detection can be performed with high accuracy.
Further, the PWM means compares the corrected output value of each phase, and when there is a set of phases in which the magnitude of the difference between the phases is smaller than the output difference threshold, the PWM signal of one of these phases is Since the output is delayed by the minimum value between the edges of the PWM signal, the minimum value of the length between the rising edges of the PWM signal, which is necessary for detecting the three-phase current by detecting the current of the DC bus, is always secured. Therefore, it is possible to detect the phase current by detecting the current of the DC bus for any input of the output command value.

In addition, the gates for the upper arm and the lower arm so that the gate signal generating means has a predetermined short-circuit prevention section (dead time) provided for the purpose of preventing a short circuit between the switching elements of the upper arm and the lower arm. By generating the signal, the short circuit is surely prevented.
In addition, the correction means reliably corrects the intermediate value of the modulation output value of each phase so that the length of the section in which the switching element of the upper arm for any two phases is ON is not less than a predetermined minimum value. Current detection is guaranteed.

It is a figure which shows the structure of the motor drive device which applies the voltage by which the pulse width modulation was applied to the coil terminal of the motor according to this invention, and drives a motor. It is a figure which shows the structure of the upper arm in a bridge circuit. It is a figure which shows the example of a waveform of the output command value according to this invention. It is a figure which shows the modulation output value with respect to the example of a waveform of FIG. It is a flowchart which shows operation | movement of a correction | amendment means. It is a figure which shows the output restriction | limiting of a correction | amendment means. It is a figure which shows operation | movement of a PWM means and a gate signal production | generation means. It is a figure which shows the circuit of an electric current detection means. It is a figure which shows the example of a waveform of the gate signal of the switching element of an upper arm, and a DC bus current. It is a figure which shows the timing which an electric current detection means samples a filter output value. It is a flowchart which shows operation | movement of a PWM means. It is a figure which shows the delay of the PWM signal of a U phase.

Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.
FIG. 1 shows a schematic configuration of a motor driving apparatus that drives a motor by applying a pulse width modulated (hereinafter referred to as “PWM” as appropriate) voltage to a coil terminal of the motor in the present embodiment. The three-phase motor 1 has a phase difference of 120 degrees from each other and has Y-connected three-phase coils, and the non-connected ends of the coils are U-phase, V-phase, and W-phase switching elements. Is connected to a bridge circuit 2 constituted by The bridge circuit 2 includes a DC power supply (not shown), a modulation means 7 for modulating output command values (Vu, Vv, Vw) representing voltages to be applied to the respective coil terminals of the three-phase motor 1, and a modulation output value ( Correction means 6 for correcting the value of Vum, Vvm, Vwm) based on a predetermined output restriction condition, the corrected output value (Vur, Vvr, Vwr) and the carrier wave Vc are compared and pulse width modulated, and the PWM signal (Uon, Von, Won) generating PWM means 3, switching element short-circuit prevention interval (dead time) is inserted, and gate signals (UH, VH, WH, (UL, VL, WL) are connected to the gate signal generating means 5 and the current detecting means 4 for detecting the current value ig of the DC bus.

  FIG. 2 shows details of the bridge circuit 2, and the U-phase series circuit includes a switching element 25 and a lower arm 22 configured similarly to the upper arm 21 in which a diode 26 is connected in parallel. Has been. The V-phase series circuit and the W-phase series circuit are configured in the same manner, and these three phases of U phase, V phase, and W phase are connected to each other. A DC voltage output from a DC power supply is applied to these series circuits. Each switching element is driven by a gate signal (UH, VH, WH, UL, VL, WL), applies a PWM voltage to the coil of the three-phase motor 1, supplies a driving current to the coil, and 3 The phase motor 1 is rotationally driven. At this time, phase currents flowing through the U-phase, V-phase, and W-phase coils are denoted by iu, iv, and iw, respectively. H represents the upstream side (high voltage side) of the current, and L represents the downstream side (low pressure side).

  First, the modulation means 7 will be described. The modulation means 7 has a zero phase in which at least one phase output is zero with respect to an output command value (Vu, Vv, Vw) representing a voltage to be applied to each coil terminal of the three-phase motor 1. Two-phase modulation is performed and output as modulation output values (Vum, Vvm, Vwm).

  Here, the two-phase modulation in the present embodiment will be described with reference to FIGS. Assume that the output command value is given as positive and negative as shown in FIG. 3, the horizontal axis indicates time, and the vertical axis indicates the output command value. At this time, the output command value of the phase having the smallest value among the output command values of the three phases is subtracted from the relevant phase and the other two phases. However, when there are a plurality of phases having the same output command value and the same value, any phase may be selected from them, and the phase in which only one phase is zero is selected. 3, the result of this modulation is the modulation output value (Vum, Vvm, Vwm) shown in FIG. 4. The modulation output value is a non-negative value, and at least one phase always has zero output. Become a phase.

  Further, for example, the processing of the two-phase modulation when the U-phase output command value Vu is the smallest among the three phases is expressed by Equation 1. At this time, using a known relationship in which the total of the three-phase phase currents (iu, iv, iw) shown in Equation 3 is zero, the coil terminal voltage and the phase current are expressed in each phase as shown in Equation 2. It can be seen that the total value multiplied is equal before and after the two-phase modulation. This shows that even if the two-phase modulation in the present embodiment is executed, the power is the same, and the behavior of the motor is not different from the case where it is not modulated.

  Next, the correction means 6 will be described. The correction means 6 corrects the modulation output values (Vum, Vvm, Vwm) based on a predetermined output restriction condition for two phases excluding one zero phase, and corrects the corrected output values (Vur, Vvr, Vwr). ) Is output. Further, the correction means 6 takes an increase / decrease error between the modulation output value and the correction output value, integrates the error by an integrator (not shown), and corrects the increase / decrease for the output value after the next PWM cycle. . Here, “accumulate the error and correct the increase / decrease with respect to the output value after the next PWM cycle” means that the increase / decrease of one error in a certain PWM cycle must be corrected in the next PWM cycle. In other words, if the modulation output value (Vum, Vvm, Vwm) in the next PWM cycle is smaller than the error to be corrected, the modulation output value becomes zero. In such a case, the error is accumulated, and when the modulation output value can be corrected so as not to become zero after the next PWM cycle, the increase / decrease of the error is intended to be corrected.

Here, the operation of the correction means 6 will be described in detail.
As an output value limiting condition in the present embodiment, the minimum value of output values in two phases excluding the zero phase is limited. This is because the length of the section in which the switching element of the upper arm for any two phases is turned on needs to be equal to or greater than a predetermined minimum value in order to enable current detection described later. Since the correction means 6 is before the voltage is PWM-modulated, the minimum value of the ON section length of the switching element described above is represented by a voltage value, and this output limit value is Vmin.

Next, details of the correction processing in the correction means 6 will be described with reference to FIG. FIG. 5 is a flowchart of the correction process, which is executed once every PWM cycle.
First, the zero phase is selected from the modulation output values (Vum, Vvm, Vwm). However, when there are a plurality of phases with zero modulation output values, any phase can be used, so only one of them is selected as the zero phase (S01).

For the two phases excluding the zero phase, the integrated value of the increase / decrease error of the modulation output value and the correction output value is added to the modulation output value.
For example, when the W phase is zero phase in the PWM cycle of the count value n−1 and the PWM cycle of the count value n, the process shown in Expression 4 is executed. In Expression 4, dVu and dVv are integrated values of the increase / decrease errors of each phase due to correction, and Vu1 and Vv1 are intermediate values in processing. n is a count value incremented every PWM cycle.

Equation 4 means that the error integrated value of the U and V phases that have not been corrected by a certain PWM cycle is corrected in the U and V phases after the next PWM cycle.
Here, the “U and V-phase error integrated values that have not been corrected by a certain PWM period” will be described. For example, when the U-phase corrected output value Vur is less than Vmin twice in two consecutive PWM cycles (hereinafter referred to as Vur0 and Vur1, respectively), the error “− ( Vmin−Vur0) ”occurs. Even if it is attempted to correct the error in the second PWM cycle, the error cannot be corrected in the second PWM cycle because Vur1 <Vmin. Further, an error “− (Vmin−Vur1)” occurs in the second PWM cycle. Therefore, in these two PWM periods, the uncorrected error is “− (Vmin−Vur0) − (Vmin−Vur1)”. This indicates that errors that could not be corrected are added one after another (integration).

  Next, “correction in U and V phases after the next PWM cycle” will be described. Looking only at Expression 4, it seems that all accumulated error accumulated values are corrected in the next PWM cycle (S02). As described later, in step S03, two non-zero phases are corrected. Since the output value minimum value limiting process is performed, it is not always possible to correct all the following errors in the next PWM cycle as in the above example. Therefore, in the PWM cycle in which the error after the next PWM cycle can be corrected, the error accumulated so far is corrected.

Further, when the zero phase changes as an exceptional process, for example, when the U phase is the zero phase in the previous PWM cycle and the W phase changes from the PWM cycle to the zero phase, as shown in Expression 5 Further, the intermediate value Vu1 (n) is obtained by subtracting the integrated value dVw (n-1) of the W phase, which has changed from the PWM cycle to the zero phase, from the U phase modulation output value Vum (n), which has been zero phase until then. To do. In other words, the value of the integrator that integrated the increase / decrease error of the phase that becomes the new zero phase is inverted to the integrator that integrates the increase / decrease error of the phase that becomes the non-zero phase from the next PWM cycle ("- dVw (n-1) "). Here, immediately before the next PWM period, the value of the U-phase integrator that is the zero phase is zero, so “−dVw (n−1)” becomes the value of the integrator as it is (loaded). On the other hand, with respect to the V phase that has not changed in the non-zero phase, the integrated value dVv (n-1) is added to the modulation output value Vvm (n), and the integrated value dVw (n-1) is subtracted to obtain the intermediate value Vv1. (N). In other words, the value of the accumulator of the phase that newly becomes the zero phase is subtracted from the value of the accumulator of the phase that continuously becomes the non-zero phase (“dVv (n−1) −dVw (n−1)”). ). Here, since the value of the V-phase integrator is “dVv (n−1)”, “dVw (n−1)” is subtracted from “dVv (n−1)”.
This process is a process of shifting the uncorrected error integrated value to the other phase (U phase and V phase) because the W phase has become the zero phase. You can see that it has moved. The same applies to the case where the other phase is the zero phase, just by switching the phases (S02).

  Equation 5 shows that when the zero phase is changed from the U phase to the W phase, it is desired to correct the uncorrected error integrated value in the V and W phases in a certain PWM cycle in the V and W phases in the next PWM cycle. Since the W phase is a zero phase and cannot be corrected in the next PWM cycle, this means that the error integrated value is corrected in the U and V phases which are non-zero phases instead of the W phase.

  In this way, in the output of a certain phase (V phase and W phase) in a certain PWM cycle, although the increase / decrease error of the output value to be corrected remains, the W phase becomes zero phase in the next PWM cycle. Even if it has changed, the accumulated value of the increase / decrease error is transferred to the other phases (U phase and V phase), so that the other phase (U phase and The increase / decrease error is shifted to (V phase), and the error can be corrected quickly while maintaining the two-phase modulation.

  Next, the minimum value limiting process of the output value is performed for the two non-zero phases. For example, when the U phase is a non-zero phase, as shown in FIG. 6, if the intermediate value Vu1 is less than the output limit value Vmin, the output value is corrected to Vmin and output as a corrected output value Vur, and the intermediate value Vu1 Is output as the corrected output value Vur as it is. The above correction process is also performed for another non-zero phase. The correction process is not performed for the zero phase (S03).

Next, for the two non-zero phases, the error accumulation by the correction in step S03 is performed by an integrator (not shown). The processing when the W phase is the zero phase is shown in Equation 6. For example, in the case of the U phase, the error output value dVu (n) is obtained by subtracting the correction output value Vur (n) from the intermediate value Vu1 (n). The same applies to the case where the other phase is the zero phase, just by switching the phases (S04).
Finally, the PWM cycle count n is incremented (S05).

The detailed operation of the correction means 6 in the present embodiment is as described above. In steps S02 and S03, the output value is corrected and the increase / decrease error is corrected under the output restriction condition, and the uncorrected increase / decrease error is integrated in step S04. To do.
In this way, the correction output value obtained by correcting the modulation output value based on the predetermined output restriction condition by the correction means 6 and correcting the increase / decrease error accumulated for the correction output value within the range satisfying the output restriction condition is corrected. The corrected output value Vur that has been corrected is output.

Next, the PWM means 3 and the gate signal generation means 5 will be described.
The PWM means 3 compares the corrected output value (Vur, Vvr, Vwr) with the carrier wave Vc and performs pulse width modulation to generate a PWM signal (Uon, Von, Won).
The gate signal generation means 5 inserts a short-circuit prevention section (dead time) of the switching element into the PWM signal (Uon, Von, Won) based on a predetermined logic, and switches the switching element of the upper arm 21 of each phase. Gate signals (UH, VH, WH) and the gate signals (UL, VL, WL) of the switching elements of the lower arm 22 are generated.

Here, detailed operations of the PWM unit 3 and the gate signal generation unit 5 will be described with reference to FIG. 7 by taking only the U phase as an example.
First, the operation of the PWM means 3 will be described. The carrier wave Vc shown in the first stage of FIG. 7 is a triangular wave having a predetermined PWM cycle, and has an amplitude from the ground GND to the power supply voltage Vcc. The PWM means 3 compares the corrected output value Vur taking a non-negative value with the carrier wave Vc, and generates the PWM signal Uon shown in the second stage of FIG.

  Next, the operation of the gate signal generating means 5 will be described. As shown in the third and fourth stages of FIG. 7, the gate signal generating means 5 generates a gate signal UH of the switching element of the upper arm 21, which is a signal delayed by a predetermined value td with respect to the PWM signal Uon. Further, the PWM signal Uon is inverted to generate the gate signal UL of the lower arm 22 which is a signal obtained by delaying the rising edge (falling portion in Uon) by twice the predetermined value td. The predetermined value td is a short-circuit prevention section (dead time) provided for the purpose of preventing a short circuit between the switching elements of the upper arm and the lower arm. The operations in the other V and W phases are the same.

  Next, the current detection means 4 will be described. The current detection means 4 is a means for detecting the current value ig of the DC bus connecting the bridge circuit 2 and the ground GND. In this embodiment, as shown in FIG. 8, a shunt resistor 41 is inserted in series with the DC bus. Then, the potential difference between both ends is amplified and level-shifted by using the operational amplifier 42 and output as a filter output idet, and sampling means for detecting the current value of the DC bus by sampling the filter output idet (see FIG. (Not shown).

  Here, the relationship between the DC bus current ig and the phase currents iu, iv, iw will be described. FIG. 9 shows the relationship between the gate signal (UH, VH, WH) of the switching element of the upper arm 21 and the DC bus current ig. At this time, the W phase is a zero phase, the U-phase current iu flows in the DC bus current ig in the section (a), and the DC bus current ig in the section (b) is equal to the U-phase current iu and V This is a current obtained by adding the phase current iv of the phase. That is, the phase current of the phase where the switching element of the upper arm is ON flows to the DC bus.

  Next, detection of a three-phase phase current by detection of the DC bus current ig will be described. For example, in the case of FIG. 9, the U-phase current iu is detected by detecting the DC bus current ig in the section (a). Further, by detecting the DC bus current ig in the section (b), the sum of the U-phase phase current iu and the V-phase phase current iv is detected, and by subtracting the detected iu from the detected value, V-phase current iv is detected. Furthermore, since the three-phase motor 1 has the relationship of Expression 3, the remaining value of the W-phase current iw can also be detected. In this way, a three-phase phase current can be detected. The same applies to the case where the other phase is the zero phase, and the same processing is performed by estimating the current flowing through the DC bus from the logic of the gate signals (UH, VH, WH).

  Next, based on the above, the operation of the sampling means (not shown) will be described. As shown in FIG. 10, the sampling means has passed a predetermined interval ts from the rising edge generated twice in one PWM cycle of the gate signal (UH, VH, WH) of the switching element of the upper arm. The filter output idet is sampled at a point. Based on the above principle, the sampled value and the phase from the logic of the gate signal (UH, Vh, WH) indicating the phase in which the switching element of the upper arm is ON are shown. The current value is calculated and output as three-phase phase current data (diu, div, diw).

  Here, the predetermined section ts is a section provided to avoid the influence of the delay in the rise of the waveform of the filter output idet and the ringing when the switching element is switched ON / OFF. The output limit value Vmin needs to be set to a value that is equal to or greater than ts after pulse width modulation.

As described above, according to the present embodiment, correction for limiting the minimum output value in the output value correction is performed, so that even when a phase with a small output value exists, phase current can be detected by detecting the current of the DC bus, Furthermore, since the increase / decrease error due to the output value correction is integrated and corrected as necessary under the output restriction condition, the voltage can be applied to the coil terminal with high accuracy with respect to the output command value.
In addition, even if the output value to be corrected remains unchanged in the output of a certain phase, even if the output value has changed to the zero phase, the integrated value of the increase / decrease error is transferred to the other phase. Without waiting for a non-zero phase again, the increase / decrease error can be shifted to the other phase, and the error can be corrected quickly while maintaining the two-phase modulation. In addition, since current detection is performed using one shunt resistor and an operational amplifier, a three-phase coil current can be detected with an inexpensive configuration without using expensive components such as a current detection IC.
Furthermore, by adjusting the sampling timing of the current detection, it is possible to avoid the influence of the waveform rising delay and ringing in the current detection means, and to accurately detect the current.

Next, a second embodiment of the present invention will be described.
First, similarly to the first embodiment, the output command value (Vu, Vv, Vw) is modulated by the modulation means 7 to output the modulated output value (Vum, Vvm, Vwm), and then the modulated output value ( Vum, Vvm, Vwm) are corrected by the correcting means 6 and corrected output values (Vur, Vvr, Vwr) are output.
The PWM means 3 compares the corrected output value (Vur, Vvr, Vwr) with the carrier wave Vc and performs pulse width modulation to generate a PWM signal (Uon, Von, Won). However, in this embodiment, when the difference between the correction output values between the two non-zero phases is smaller than a predetermined value, the PWM signal of the phase with the smaller correction output value is delayed and output.

Hereinafter, the operation of the PWM means 3 of the present embodiment will be described in detail with reference to FIG. 11 showing an operation flowchart of the PWM means 3, taking the case where the W phase is a zero phase as an example.
First, the correction output value of each phase is pulse width modulated (S11).
Next, it is determined whether or not the difference between the two non-zero phase corrected output values is less than an output difference threshold Vth described later. For example, when the W phase is the zero phase, the authenticity of the expression shown in Expression 7 is determined (S12).

If step S12 is No (false), the process ends.
If step S12 is Yes (true), it is determined which of the non-zero phase correction output values is larger. For example, when the W phase is the zero phase, as shown in FIG. 11, the authenticity is determined for “Vvr is Vur or higher?” (S13).

  If Step S13 is Yes (true), as shown in FIG. 12, the rising edge of the U-phase PWM signal Uon is delayed by a predetermined value th described later with respect to the rising edge of the V-phase PWM signal Von. The output is delayed as described above (S14).

  The predetermined value th indicates the minimum value (hereinafter referred to as the minimum value between edges) that the length between the PWM signal rising edges in the two non-zero phases should be ensured. This is the length of the section necessary for accurate current detection while avoiding the effects of rising delay and ringing.

  The relationship between the output difference threshold Vth and the edge-to-edge minimum value th is shown in Equation 8 using the PWM cycle tpwm. This indicates that half of the value obtained by subjecting the output difference threshold Vth to pulse width modulation is the minimum value th between edges. Further, the minimum value th between edges is set to be larger than the value ts for setting the current detection sampling timing in the DC bus.

  Further, the delay amount in step S14 is shown in Equation 9. If the U-phase PWM signal Uon is delayed by the amount shown in Equation 9, the interval between the rising edges of the two non-zero phases becomes the lowest value th between edges.

On the other hand, when step S13 is No (false), the output is delayed with respect to the rising edge of the U-phase PWM signal Uon so that the rising edge of the V-phase PWM signal Von is delayed by the inter-edge minimum value th. This process is the same as step S14 except that the phase is changed (S15).
After steps S14 and S15 are completed, the processing in the PWM means 3 is terminated.

  Next, as in the first embodiment, the gate signal generation means 5 generates a gate signal (UH, VH, WH, UL, VL, WL) from the PWM signal (Uon, Von, Won) and detects the current. The means 4 detects the current value ig and the three-phase phase current of the DC bus connecting the bridge circuit 2 and the ground GND. Here, the sampling means is also similar in that a predetermined interval ts has elapsed from the rising edge generated twice in one PWM cycle of the gate signal (UH, VH, WH) of the switching element of the upper arm. The filter output idet is sampled. Based on the above principle, the sampled value and the logic of the gate signal (UH, Vh, WH) indicating the phase in which the switching element of the upper arm is turned on are calculated. Value is calculated and output as three-phase phase current data (diu, div, diw).

  As described above, according to the present embodiment, the non-zero phase correction output values are compared, and when the difference between the phases is smaller than the predetermined value, the PWM signal is configured to be output with a time difference. It is possible to always ensure the minimum value of the length between the rising edges of the PWM signal, which is necessary for stable current detection while avoiding the influence of the waveform rising delay and ringing in the detecting means 4. The phase current can be detected by detecting the current of the DC bus even when the output command value is input.

DESCRIPTION OF SYMBOLS 1 3 phase motor 2 Bridge circuit 21 Upper arm 22 Lower arm 25 Switching element 26 Diode 3 PWM means 4 Current detection means 41 Shunt resistor 42 Operational amplifier 5 Gate signal generation means 6 Correction means 7 Modulation means Vu, Vv, Vw Output command value (U phase, V phase, W phase)
Vum, Vvm, Vwm Modulation output value (U phase, V phase, W phase)
Vum, Vvm, Vwm Correction output value (U phase, V phase, W phase)
Uon, Von, Won PWM signal (U phase, V phase, W phase)
UH, VH, WH Switching element drive signal (U-phase, V-phase, W-phase upper arm)
UL, VL, WL Switching element drive signal (U-phase, V-phase, W-phase lower arm)
iu, iv, iw phase current (U phase, V phase, W phase)
idet filter output diu, div, diw Phase current data (U phase, V phase, W phase)
Vc carrier wave td Short-circuit prevention interval Dead (dead time) length tpwm PWM cycle length ts Current sample timing value th Minimum value between edges Vth Output difference threshold Vcc Power supply voltage GND Ground

Japanese Patent No. 2712470 Japanese Patent No. 3931079

Claims (7)

A circuit in which a switching element and a diode are connected in parallel, and a pair of an upper arm and a lower arm is connected in three phases, and the three-phase pair is connected to a coil terminal of a three-phase motor, and a pulse A bridge circuit for applying a width-modulated voltage to the coil terminals;
Two-phase modulation of the three-phase output command value so that at least one phase is a zero phase that is always zero output with respect to the output command value indicating the voltage to be applied to the coil terminals of each phase of the three-phase motor Modulation means for outputting as a modulation output value;
For the two phases other than the zero phase, the modulation output value is corrected based on a predetermined output restriction condition, output as a correction output value, and the increase / decrease error of the modulation output value and the correction output value is integrated, Correction means for correcting an increase / decrease error accumulated for the corrected output value within a range satisfying the output restriction condition after the PWM period;
PWM means for generating a PWM signal by pulse width modulating the corrected output value of each phase;
A gate signal generating means for generating a gate signal for each phase switching element in the bridge circuit according to a predetermined switching element drive logic from each phase PWM signal;
A motor drive device comprising: current detection means for detecting a current value flowing through a DC bus of the bridge circuit.   The correction means includes an integrator that integrates an increase / decrease error for two phases excluding the zero phase, and when the zero phase shifts to a different phase in the next PWM cycle, the phase that becomes a non-zero phase from the next PWM cycle The accumulator integrating the increase / decrease error of the phase that becomes a new zero phase is loaded by inverting the sign of the value of the accumulator that newly adds the increase / decrease error of the phase that becomes the zero phase, 2. The motor drive device according to claim 1, wherein a value of the integrator of a phase that becomes a new zero phase is subtracted from the value of.   The motor driving device according to claim 1, wherein the current detection unit detects a potential difference between both ends of a shunt resistor inserted in series with the DC bus.   4. The motor drive according to claim 1, wherein the current detection unit performs current detection sampling at a timing when a predetermined interval has elapsed from a rising edge of a PWM signal of each phase. apparatus.   The PWM means compares the corrected output value of each phase, and when there is a set of phases in which the magnitude of the difference between the phases is smaller than the output difference threshold, the PWM signal of one of these phases is changed to the other 5. The motor drive device according to claim 1, wherein the motor drive device outputs the signal delayed by a minimum value between edges with respect to the PWM signal. 6.   The gate signal generating means generates a gate signal of the switching element of the upper arm, which is a signal delayed by a predetermined value with respect to the PWM signal of each phase, inverts the PWM signal of each phase, and outputs the PWM signal 6. The motor drive device according to claim 1, wherein a gate signal of the lower arm, which is a signal obtained by delaying the rising or falling of the signal by two times a predetermined value, is generated.   If the intermediate value of the modulation output value of each phase is less than the output limit value as the predetermined output limit condition, the correction unit corrects the intermediate value to an output limit value and outputs the corrected output value as the intermediate value. The motor drive device according to any one of claims 1 to 6, wherein if the value is equal to or greater than an output limit value, the intermediate value is directly output as a corrected output value.

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