TW202234716A - Single photon avalanche diode and single photon avalanche diode array - Google Patents

Single photon avalanche diode and single photon avalanche diode array Download PDF

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TW202234716A
TW202234716A TW110141238A TW110141238A TW202234716A TW 202234716 A TW202234716 A TW 202234716A TW 110141238 A TW110141238 A TW 110141238A TW 110141238 A TW110141238 A TW 110141238A TW 202234716 A TW202234716 A TW 202234716A
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well layer
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TWI774602B (en
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吳勁昌
謝晉安
陳經緯
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神盾股份有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/1443—Devices controlled by radiation with at least one potential jump or surface barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/1446—Devices controlled by radiation in a repetitive configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors
    • H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
    • H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier
    • H01L31/107—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier working in avalanche mode, e.g. avalanche photodiode
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract

A single photon avalanche diode including a n-type semiconductor buried layer, an active region, and a n-type stacked layer is provided. The active region includes a first p-type semiconductor well layer, a first n-type semiconductor well layer, a second p-type semiconductor well layer, two anodes, and a p-type epitaxial layer. The first p-type semiconductor well layer is disposed on the n-type semiconductor buried layer. The first n-type semiconductor well layer is disposed on the first p-type semiconductor well layer. The second p-type semiconductor well layer is disposed on the first n-type semiconductor well layer. The two anodes are disposed on the second p-type semiconductor well layer at two opposite sides. The p-type epitaxial layer connects the first p-type semiconductor well layer and the second p-type semiconductor well layer. The n-type stacked layer is disposed beside the active region and on the n-type semiconductor buried layer. A single photon avalanche diode array is also provided.

Description

單光子崩潰二極體及單光子崩潰二極體陣列Single-photon collapsed diodes and single-photon collapsed diode arrays

本發明是有關於一種光二極體（photodiode）及光二極體陣列，且特別是有關於一種單光子崩潰二極體（single photon avalanche diode, SPAD）及單光子崩潰二極體陣列。The present invention relates to a photodiode and a photodiode array, and more particularly, to a single photon avalanche diode (SPAD) and a single photon avalanche diode array.

單光子崩潰二極體在受光照射後，使得電子與電洞分離而形成光電流。當與電洞分離的電子進入PN接面處之電場加速區（即雪崩區（avalanche region））時，電子被電場大幅地加速而撞擊其他原子，使其他原子游離出更多的電子，而形成崩潰電流（avalanche current）。崩潰電流的電流值遠大於原始的光電流，進而能夠有效提升感應靈敏度。When the single-photon collapsed diode is illuminated by light, the electrons and holes are separated to form a photocurrent. When the electrons separated from the holes enter the electric field acceleration region (ie, avalanche region) at the PN junction, the electrons are greatly accelerated by the electric field and hit other atoms, causing other atoms to dissociate more electrons to form collapse current (avalanche current). The current value of the collapse current is much larger than the original photocurrent, which can effectively improve the sensing sensitivity.

單光子崩潰二極體可應用於飛時測距裝置（time-of-flight ranging device, ToF ranging device）或光達（LiDAR），可藉由感測光的飛行時間來計算出物體的距離。然而，在單光子崩潰二極體中，在雪崩區以外的中性區（neutral region）的載子所受到的電場較為微弱，使得載子漂移（drift）至雪崩區的時間會有所延遲，導致時序顫動（timing jitter），這會對測量光的飛行時間的準確度造成影響。Single-photon collapsing diodes can be applied to time-of-flight ranging device (ToF ranging device) or LiDAR, which can calculate the distance of an object by sensing the flight time of light. However, in the single-photon collapsing diode, the electric field experienced by the carriers in the neutral region outside the avalanche region is relatively weak, so that the time of carrier drift to the avalanche region will be delayed. Causes timing jitter, which affects the accuracy of measuring the time of flight of light.

另一方面，當隨著光電技術的不斷演進，產品朝小型化發展，單光子崩潰二極體也被做得更小。在此情況下，光電子更容易往雪崩區以外的位置漂移，而導致光子偵測機率（photon detection probability, PDP）的損失。On the other hand, with the continuous evolution of optoelectronic technology and the development of products towards miniaturization, single-photon collapse diodes are also made smaller. In this case, the photoelectrons are more likely to drift outside the avalanche region, resulting in a loss of photon detection probability (PDP).

本發明提供一種單光子崩潰二極體及單光子崩潰二極體陣列，其可有效抑制時序顫動，且可有效降低光子偵測機率的損失。The present invention provides a single-photon collapsed diode and a single-photon collapsed diode array, which can effectively suppress timing jitter and can effectively reduce the loss of photon detection probability.

本發明的一實施例提出一種單光子崩潰二極體，包括一N型半導體埋層、一主動區及一N型堆疊層。主動區包括一第一P型半導體井層、一第一N型半導體井層、一第二P型半導體井層、二陽極及一P型磊晶層。第一P型半導體井層配置於N型半導體埋層上，第一N型半導體井層配置於第一P型半導體井層上。第二P型半導體井層配置於第一N型半導體井層上，此二陽極配置於第二P型半導體井層上。P型磊晶層連接第一P型半導體井層及第二P型半導體井層。N型堆疊層配置於主動區旁，且配置於N型半導體埋層上。An embodiment of the present invention provides a single-photon collapsed diode, which includes an N-type semiconductor buried layer, an active region, and an N-type stacked layer. The active region includes a first P-type semiconductor well layer, a first N-type semiconductor well layer, a second P-type semiconductor well layer, two anodes and a P-type epitaxial layer. The first P-type semiconductor well layer is arranged on the N-type semiconductor buried layer, and the first N-type semiconductor well layer is arranged on the first P-type semiconductor well layer. The second P-type semiconductor well layer is arranged on the first N-type semiconductor well layer, and the two anodes are arranged on the second P-type semiconductor well layer. The P-type epitaxial layer connects the first P-type semiconductor well layer and the second P-type semiconductor well layer. The N-type stack layer is disposed beside the active region and is disposed on the N-type semiconductor buried layer.

本發明的一實施例提出一種單光子崩潰二極體陣列，包括多個排成二維陣列的上述單光子崩潰二極體，其中每一單光子崩潰二極體的二陽極排列於一參考直線上，且相鄰的任二個單光子崩潰二極體的二個參考直線彼此不平行。An embodiment of the present invention provides a single-photon collapsed diode array, comprising a plurality of the single-photon collapsed diodes arranged in a two-dimensional array, wherein the two anodes of each single-photon collapsed diode are arranged on a reference line , and the two reference lines of any two adjacent single-photon collapsed diodes are not parallel to each other.

在本發明的實施例的單光子崩潰二極體及單光子崩潰二極體陣列中，由於利用N型半導體埋層、第一P型半導體井層、第一N型半導體井層及第二P型半導體井層來形成三個PN接面（p-n junction），也就是形成三個雪崩區，以增加光電子落於雪崩區的機會，因此能有效抑制時序顫動的問題，並可有效降低光子偵測機率的損失。此外，本發明的實施例的單光子崩潰二極體及單光子崩潰二極體陣列皆採用兩個陽極，可以使第一P型半導體井層的電壓準位比較平均。In the single-photon collapsed diode and the single-photon collapsed diode array according to the embodiments of the present invention, since the N-type semiconductor buried layer, the first P-type semiconductor well layer, the first N-type semiconductor well layer and the second P-type semiconductor well layer are used A type semiconductor well layer is used to form three PN junctions (p-n junctions), that is, three avalanche regions are formed to increase the chance of photoelectrons falling in the avalanche regions, so it can effectively suppress the problem of timing jitter and effectively reduce photon detection. loss of chance. In addition, the single-photon collapsed diode and the single-photon collapsed diode array of the embodiments of the present invention both use two anodes, which can make the voltage level of the first P-type semiconductor well layer relatively average.

另外，在本發明的實施例的單光子崩潰二極體陣列中，每一單光子崩潰二極體包括二陽極且其排列於一參考直線上，且相鄰的任二個單光子崩潰二極體的二個參考直線彼此不平行。也就是說，相鄰的單光子崩潰二極體的二個陽極是採用錯開設置的方式，而相鄰的單光子崩潰二極體中連接陽極的線路長度因而可以相同，能有效避免不同的單光子崩潰二極體有不同的電阻電容延遲。In addition, in the single-photon collapsed diode array of the embodiment of the present invention, each single-photon collapsed diode includes two anodes arranged on a reference line, and any two adjacent single-photon collapsed diodes The two reference lines of the volume are not parallel to each other. That is to say, the two anodes of the adjacent single-photon collapsed diodes are arranged in a staggered manner, and the lengths of the lines connecting the anodes in the adjacent single-photon collapsed diodes can be the same, which can effectively avoid different single-photon collapsed diodes. Photon collapse diodes have different resistance-capacitance delays.

請參照圖1至圖3，本實施例的單光子崩潰二極體陣列100包括多個排成二維陣列的單光子崩潰二極體200，每一單光子崩潰二極體200包括一N型半導體埋層（n-type semiconductor buried layer）210、一主動區300及一N型堆疊層400。主動區300包括一第一P型半導體井層（first p-type semiconductor well layer）310、一第一N型半導體井層320、一第二P型半導體井層330、二陽極340及一P型磊晶層350。Referring to FIGS. 1 to 3 , the single-photon collapsed diode array 100 of this embodiment includes a plurality of single-photon collapsed diodes 200 arranged in a two-dimensional array, and each single-photon collapsed diode 200 includes an N-type An n-type semiconductor buried layer 210 , an active region 300 and an N-type stacked layer 400 . The active region 300 includes a first p-type semiconductor well layer 310 , a first N-type semiconductor well layer 320 , a second P-type semiconductor well layer 330 , two anodes 340 and a P-type semiconductor well layer 310 Epitaxial layer 350 .

第一P型半導體井層310配置於N型半導體埋層210上，第一N型半導體井層320配置於第一P型半導體井層310上。第二P型半導體井層330配置於第一N型半導體井層320上，此二陽極340配置於第二P型半導體井層330上，例如是分別配置於第二P型半導體井層330上的相對兩側。P型磊晶層350連接第一P型半導體井層310及第二P型半導體井層330。N型堆疊層400配置於主動區300旁，且配置於N型半導體埋層210上。在本實施例中，單光子崩潰二極體200更包括一基板220，而N型半導體埋層210配置於基板220上，其中基板220例如為P型半導體基板。The first P-type semiconductor well layer 310 is disposed on the N-type semiconductor buried layer 210 , and the first N-type semiconductor well layer 320 is disposed on the first P-type semiconductor well layer 310 . The second P-type semiconductor well layer 330 is disposed on the first N-type semiconductor well layer 320 , and the two anodes 340 are disposed on the second P-type semiconductor well layer 330 , for example, respectively disposed on the second P-type semiconductor well layer 330 opposite sides. The P-type epitaxial layer 350 is connected to the first P-type semiconductor well layer 310 and the second P-type semiconductor well layer 330 . The N-type stack layer 400 is disposed beside the active region 300 and is disposed on the N-type semiconductor buried layer 210 . In this embodiment, the single-photon collapsed diode 200 further includes a substrate 220, and the N-type semiconductor buried layer 210 is disposed on the substrate 220, wherein the substrate 220 is, for example, a P-type semiconductor substrate.

在本實施例中，第一P型半導體井層310與N型半導體埋層210之間形成一第一PN接面J1，第一P型半導體井層310與第一N型半導體井層320之間形成一第二PN接面J2，第一N型半導體井層320與第二P型半導體井層330之間形成一第三PN接面J3，且第一、第二、第三PN接面J1、J2及J3形成三個雪崩區R1、R2、R3，即電場加速區。如圖3所繪示，在雪崩區R1、R2、R3中有較強的電場，能夠大幅加速光電子，以使光電子撞擊其他原子，使其他原子游離出更多的電子，而形成崩潰電流。In this embodiment, a first PN junction J1 is formed between the first P-type semiconductor well layer 310 and the N-type semiconductor buried layer 210 . A second PN junction J2 is formed therebetween, a third PN junction J3 is formed between the first N-type semiconductor well layer 320 and the second P-type semiconductor well layer 330, and the first, second and third PN junctions J1, J2 and J3 form three avalanche regions R1, R2, R3, namely electric field acceleration regions. As shown in Figure 3, there is a strong electric field in the avalanche regions R1, R2, R3, which can greatly accelerate the photoelectrons, so that the photoelectrons hit other atoms, so that other atoms dissociate more electrons and form a collapse current.

在本實施例的單光子崩潰二極體200及單光子崩潰二極體陣列100中，由於利用N型半導體埋層210、第一P型半導體井層310、第一N型半導體井層320及第二P型半導體井層330來形成第一、第二及第三PN接面J1、J2及J3，也就是形成三個雪崩區R1、R2及R3，以增加光電子落於雪崩區R1、R2、R3的機會，因此能有效抑制時序顫動的問題，並可有效降低光子偵測機率的損失。此外，本實施例的單光子崩潰二極體200及單光子崩潰二極體陣列100皆採用兩個陽極340，可以使第一P型半導體井層310的電壓準位比較平均。In the single-photon collapsed diode 200 and the single-photon collapsed diode array 100 of the present embodiment, the N-type semiconductor buried layer 210 , the first P-type semiconductor well layer 310 , the first N-type semiconductor well layer 320 and the The second P-type semiconductor well layer 330 is used to form the first, second and third PN junctions J1, J2 and J3, that is, to form three avalanche regions R1, R2 and R3 to increase the photoelectrons falling on the avalanche regions R1, R2 , R3, so it can effectively suppress the problem of timing jitter, and can effectively reduce the loss of photon detection probability. In addition, the single-photon collapsed diode 200 and the single-photon collapsed diode array 100 of the present embodiment both use two anodes 340 , which can make the voltage level of the first P-type semiconductor well layer 310 relatively average.

具體而言，當來自外界的光子50照射於曝光區Z1時（如圖2與圖3所繪示），會在曝光區Z1中產生光電子。在本實施例中，曝光區Z1為兩個陽極340之間的收光區域，在平行於第二P型半導體井層330的方向上（即圖2與圖3中的水平方向上），曝光區Z1的範圍小於主動區300的範圍。此外，曝光區Z1涵蓋雪崩區R1、R2及R3。相對於習知單光子崩潰二極體採用單一一個雪崩區，本實施例的單光子崩潰二極體200採用三個雪崩區R1、R2、R3，大幅提升了光電子落入雪崩區R1、R2、R3的機會，因此減少了光電子在雪崩區R1、R2、R3外受到較微弱的電場作用而導致時間延遲的問題，也可有效減少光電子橫向地往N型堆疊層400漂移的機會。故能有效抑制時序顫動的問題，並可有效降低光子偵測機率的損失。此外，即使單光子崩潰二極體200的尺寸越做越小，數量提升及涵蓋範圍比例變大的雪崩區R1、R2、R3可有效減少光電子橫向地往N型堆疊層400漂移或往其他位置漂移的機會，因此即便尺寸縮小仍可有效降低光子偵測機率的損失。Specifically, when the photons 50 from the outside irradiate the exposure zone Z1 (as shown in FIGS. 2 and 3 ), photoelectrons are generated in the exposure zone Z1 . In this embodiment, the exposure area Z1 is the light-receiving area between the two anodes 340 , and is exposed in a direction parallel to the second P-type semiconductor well layer 330 (ie, in the horizontal direction in FIGS. 2 and 3 ). The range of the zone Z1 is smaller than the range of the active zone 300 . In addition, the exposure zone Z1 covers the avalanche zones R1, R2 and R3. Compared with the conventional single-photon collapsed diode which adopts a single avalanche region, the single-photon collapsed diode 200 of this embodiment adopts three avalanche regions R1, R2, and R3, which greatly improves the photoelectrons falling into the avalanche regions R1, R2, and R3. Therefore, the problem of time delay caused by the weak electric field outside the avalanche regions R1, R2, and R3 is reduced, and the chance of the photoelectrons drifting laterally to the N-type stack layer 400 can also be effectively reduced. Therefore, the problem of timing jitter can be effectively suppressed, and the loss of photon detection probability can be effectively reduced. In addition, even if the size of the single-photon collapse diode 200 is getting smaller and smaller, the avalanche regions R1 , R2 , and R3 with an increased number and a larger coverage ratio can effectively reduce the lateral drift of photoelectrons to the N-type stack layer 400 or to other positions. Therefore, even the size reduction can effectively reduce the loss of photon detection probability.

此外，在本實施例的單光子崩潰二極體200及單光子崩潰二極體陣列100中，此二陽極340配置於第二P型半導體井層330上的相對兩側，且P型磊晶層350連接第一P型半導體井層310及第二P型半導體井層330，而在本實施例中此二陽極340更可以配置於P型磊晶層350上。因此，此二陽極340可透過P型磊晶層350而達到與第一P型半導體井層310良好的電性連接，而配置於相對兩側340的二陽極340更可使第一P型半導體井層310處的電場較為均勻，進而幫助崩潰電流的有效形成。In addition, in the single-photon collapsed diode 200 and the single-photon collapsed diode array 100 of this embodiment, the two anodes 340 are disposed on opposite sides of the second P-type semiconductor well layer 330, and the P-type epitaxial The layer 350 is connected to the first P-type semiconductor well layer 310 and the second P-type semiconductor well layer 330 , and in this embodiment, the two anodes 340 can be further disposed on the P-type epitaxial layer 350 . Therefore, the two anodes 340 can achieve good electrical connection with the first P-type semiconductor well layer 310 through the P-type epitaxial layer 350 , and the two anodes 340 disposed on opposite sides 340 can further enable the first P-type semiconductor well The electric field at the well layer 310 is relatively uniform, thereby facilitating the effective formation of the collapse current.

在本實施例中，P型磊晶層350沿著第一N型半導體井層320的側邊從第一P型半導體井層310延伸至第二P型半導體井層330。在圖2中，P型磊晶層350是沿著第一N型半導體井層320的相對兩側邊從第一P型半導體井層310延伸至第二P型半導體井層330。In this embodiment, the P-type epitaxial layer 350 extends from the first P-type semiconductor well layer 310 to the second P-type semiconductor well layer 330 along the side of the first N-type semiconductor well layer 320 . In FIG. 2 , the P-type epitaxial layer 350 extends from the first P-type semiconductor well layer 310 to the second P-type semiconductor well layer 330 along opposite sides of the first N-type semiconductor well layer 320 .

在本實施例中，主動區300更包括二P型重摻雜層360，分別連接二陽極340與第二P型半導體井層330，且在本實施例中亦可分別連接二陽極340與P型磊晶層350。此二P型重摻雜層360可提升此二陽極340與第一P型半導體井層310及第二P型半導體井層330的導電效果。在本實施例中，P型重摻雜層360的P型摻雜濃度大於第一P型半導體井層310的P型摻雜濃度，且大於第二P型半導體井層330的P型摻雜濃度。In this embodiment, the active region 300 further includes two P-type heavily doped layers 360, which are respectively connected to the two anodes 340 and the second P-type semiconductor well layer 330, and in this embodiment, the two anodes 340 and the P-type semiconductor well layer 330 are respectively connected. type epitaxial layer 350 . The two P-type heavily doped layers 360 can enhance the conductive effect of the two anodes 340 and the first P-type semiconductor well layer 310 and the second P-type semiconductor well layer 330 . In this embodiment, the P-type doping concentration of the P-type heavily doped layer 360 is greater than the P-type doping concentration of the first P-type semiconductor well layer 310 and greater than the P-type doping concentration of the second P-type semiconductor well layer 330 concentration.

在本實施例中，N型堆疊層400環繞主動區300。具體而言，在本實施例中，N型堆疊層400包括一第二N型半導體井層410及一陰極420。第二N型半導體井層410配置於N型半導體埋層上210，而陰極420配置於第二N型半導體井層410上。在本實施例中，N型堆疊層400更包括一高電壓N型半導體井層（high voltage n-type semiconductor well layer）430及一N型重摻雜層440。高電壓N型半導體井層430配置於N型半導體埋層210與第二N型半導體井層410之間，N型重摻雜層440配置於第二N型半導體井層410與陰極420之間。N型重摻雜層440可增進陰極420與第二N型半導體井層410之間的電性連接。在本實施例中，N型重摻雜層440的N型摻雜濃度大於第二N型半導體井層410的N型摻雜濃度。In this embodiment, the N-type stack layer 400 surrounds the active region 300 . Specifically, in this embodiment, the N-type stack layer 400 includes a second N-type semiconductor well layer 410 and a cathode 420 . The second N-type semiconductor well layer 410 is disposed on the N-type semiconductor buried layer 210 , and the cathode 420 is disposed on the second N-type semiconductor well layer 410 . In this embodiment, the N-type stacked layer 400 further includes a high voltage n-type semiconductor well layer 430 and an N-type heavily doped layer 440 . The high-voltage N-type semiconductor well layer 430 is disposed between the N-type semiconductor buried layer 210 and the second N-type semiconductor well layer 410 , and the N-type heavily doped layer 440 is disposed between the second N-type semiconductor well layer 410 and the cathode 420 . The N-type heavily doped layer 440 can improve the electrical connection between the cathode 420 and the second N-type semiconductor well layer 410 . In this embodiment, the N-type doping concentration of the N-type heavily doped layer 440 is greater than the N-type doping concentration of the second N-type semiconductor well layer 410 .

在本實施例中，第一P型半導體井層310的P型摻雜濃度是落在10 17cm -3至5×10 18cm -3的範圍內，第一N型半導體井層320的N型摻雜濃度是落在10 17cm -3至5×10 18cm -3的範圍內，且第二P型半導體井層330的P型摻雜濃度是落在10 17cm -3至5×10 18cm -3的範圍內。在本實施例中，P型磊晶層350的P型摻雜濃度小於第一P型半導體井層310的P型摻雜濃度，且小於第二P型半導體井層330的P型摻雜濃度。此外，在本實施例中，第一P型半導體井層310與第二P型半導體井層330之間的間距是落在1微米至2微米的範圍內。 In this embodiment, the P-type doping concentration of the first P-type semiconductor well layer 310 is in the range of 10 17 cm -3 to 5×10 18 cm -3 , the N of the first N-type semiconductor well layer 320 The P-type doping concentration is in the range of 10 17 cm -3 to 5×10 18 cm -3 , and the P-type doping concentration of the second P-type semiconductor well layer 330 is in the range of 10 17 cm -3 to 5× 10 18 cm -3 range. In the present embodiment, the P-type doping concentration of the P-type epitaxial layer 350 is smaller than the P-type doping concentration of the first P-type semiconductor well layer 310 and smaller than the P-type doping concentration of the second P-type semiconductor well layer 330 . In addition, in this embodiment, the distance between the first P-type semiconductor well layer 310 and the second P-type semiconductor well layer 330 is in the range of 1 μm to 2 μm.

在本實施例中，如圖1所示，每一單光子崩潰二極體200的二陽極340排列於一參考直線L1上，且相鄰的任二個單光子崩潰二極體200的二個參考直線L1彼此不平行。在本實施例中，相鄰的任二個單光子崩潰二極體200的二個參考直線L1彼此垂直。也就是說，相鄰的單光子崩潰二極體200的二個陽極340是採用錯開設置的方式，而在平行於單光子崩潰二極體陣列100的一中心線F1的方向上排列的相鄰的單光子崩潰二極體200中連接陽極的陽極線路110長度因而可以相同，能有效避免不同的單光子崩潰二極體200有不同的電阻電容延遲。In this embodiment, as shown in FIG. 1 , the two anodes 340 of each single-photon collapsed diode 200 are arranged on a reference line L1 , and any two adjacent single-photon collapsed diodes 200 have two anodes 340 . The reference lines L1 are not parallel to each other. In this embodiment, the two reference straight lines L1 of any two adjacent single-photon collapsed diodes 200 are perpendicular to each other. That is to say, the two anodes 340 of the adjacent single-photon collapsed diodes 200 are arranged in a staggered manner, and the adjacent anodes 340 arranged in a direction parallel to a center line F1 of the single-photon collapsed diode array 100 Therefore, the length of the anode line 110 connected to the anode in the single-photon collapsed diode 200 can be the same, which can effectively prevent different single-photon collapsed diodes 200 from having different resistance-capacitance delays.

在本實施例中，單光子崩潰二極體陣列100，更包括多個陽極線路110，每一陽極線路110具有二分支線路112，分別連接至一個單光子崩潰二極體200的二個陽極340。In this embodiment, the single-photon collapsed diode array 100 further includes a plurality of anode lines 110 , each anode line 110 has two branch lines 112 , which are respectively connected to the two anodes 340 of one single-photon collapsed diode 200 . .

在本實施例中，在以單光子崩潰二極體陣列100的中心線F1為對稱軸的任兩鏡像對稱位置上的二個單光子崩潰二極體200（例如單光子崩潰二極體200a與200b）上的陽極線路110的線路走向不同，但線路長度相等。如此可以使單光子崩潰二極體陣列100有較為對稱的感測效果。此外，在本實施例中，在平行於單光子崩潰二極體陣列100的中心線F1的方向上排列的相鄰二個單光子崩潰二極體200（例如單光子崩潰二極體200c與200d）上的陽極線路110的長度相等。In this embodiment, the two single-photon collapsed diodes 200 (for example, the single-photon collapsed diode 200a and the single-photon collapsed diode 200a and The lines of the anode lines 110 on 200b) have different line directions, but the line lengths are the same. In this way, the single-photon collapsed diode array 100 can have a relatively symmetrical sensing effect. In addition, in this embodiment, two adjacent single-photon collapsed diodes 200 (for example, the single-photon collapsed diodes 200 c and 200 d ) are arranged in a direction parallel to the center line F1 of the single-photon collapsed diode array 100 . ) on the anode lines 110 of equal length.

在本實施例中，N型半導體埋層210的材料例如為摻雜有磷(P)、砷(As)、銻(Sb)或其組合的矽。第一P型半導體井層310的材料例如為摻雜有硼(B)、銦(In)或其組合的矽。第一N型半導體井層320的材料例如為摻雜有磷(P)、砷(As)、銻(Sb)或其組合的矽。第二P型半導體井層330的材料例如為摻雜有硼(B)、銦(In)或其組合的矽。陽極340的材料例如為銅(Cu)、鎢(W)、鋁(Al)或其組合。P型磊晶層350的材料可為具有P型摻雜的矽，例如為摻雜有硼(B)、銦(In)或其組合的矽。P型重摻雜層360的材料例如為摻雜有硼(B)、銦(In)或其組合的矽。第二N型半導體井層410的材料例如為摻雜有磷(P)、砷(As)或其組合的矽。陰極420的材料例如為銅(Cu)、鎢(W)、鋁(Al)或其組合。高電壓N型半導體井層430的材料例如為摻雜有磷(P)、砷(As)或其組合的矽。N型重摻雜層440的材料例如為摻雜有磷(P)、砷(As)或其組合的矽。陽極線路110的材料例如為銅(Cu)、鎢(W)、鋁(Al)或其組合。基板220的材料例如為矽(Si)。然而，本發明並不以上述材料為限。In this embodiment, the material of the N-type semiconductor buried layer 210 is, for example, silicon doped with phosphorus (P), arsenic (As), antimony (Sb) or a combination thereof. The material of the first P-type semiconductor well layer 310 is, for example, silicon doped with boron (B), indium (In) or a combination thereof. The material of the first N-type semiconductor well layer 320 is, for example, silicon doped with phosphorus (P), arsenic (As), antimony (Sb) or a combination thereof. The material of the second P-type semiconductor well layer 330 is, for example, silicon doped with boron (B), indium (In) or a combination thereof. The material of the anode 340 is, for example, copper (Cu), tungsten (W), aluminum (Al) or a combination thereof. The material of the P-type epitaxial layer 350 may be silicon with P-type doping, such as silicon doped with boron (B), indium (In) or a combination thereof. The material of the P-type heavily doped layer 360 is, for example, silicon doped with boron (B), indium (In) or a combination thereof. The material of the second N-type semiconductor well layer 410 is, for example, silicon doped with phosphorus (P), arsenic (As) or a combination thereof. The material of the cathode 420 is, for example, copper (Cu), tungsten (W), aluminum (Al) or a combination thereof. The material of the high-voltage N-type semiconductor well layer 430 is, for example, silicon doped with phosphorus (P), arsenic (As) or a combination thereof. The material of the N-type heavily doped layer 440 is, for example, silicon doped with phosphorus (P), arsenic (As) or a combination thereof. The material of the anode line 110 is, for example, copper (Cu), tungsten (W), aluminum (Al) or a combination thereof. The material of the substrate 220 is, for example, silicon (Si). However, the present invention is not limited to the above-mentioned materials.

綜上所述，在本發明的實施例的單光子崩潰二極體及單光子崩潰二極體陣列中，由於利用N型半導體埋層、第一P型半導體井層、第一N型半導體井層及第二P型半導體井層來形成三個PN接面（p-n junction），也就是形成三個雪崩區，以增加光電子落於雪崩區的機會，因此能有效抑制時序顫動的問題，並可有效降低光子偵測機率的損失。此外，本發明的實施例的單光子崩潰二極體及單光子崩潰二極體陣列採用兩個陽極，可以使第一P型半導體井層的電壓準位比較平均。To sum up, in the single-photon collapsed diode and single-photon collapsed diode array according to the embodiments of the present invention, since the N-type semiconductor buried layer, the first P-type semiconductor well layer, and the first N-type semiconductor well are used layer and the second P-type semiconductor well layer to form three PN junctions (p-n junction), that is, to form three avalanche regions to increase the chance of photoelectrons falling in the avalanche regions, so it can effectively suppress the problem of timing jitter, and can Effectively reduce the loss of photon detection probability. In addition, the single-photon collapsed diode and the single-photon collapsed diode array of the embodiments of the present invention employ two anodes, which can make the voltage level of the first P-type semiconductor well layer relatively average.

另外，在本發明的實施例的單光子崩潰二極體陣列中，每一單光子崩潰二極體包括二陽極且其排列於一參考直線上，且相鄰的任二個單光子崩潰二極體的二個參考直線彼此不平行。也就是說，相鄰的單光子崩潰二極體的二個陽極是採用錯開設置的方式，而相鄰的單光子崩潰二極體中連接陽極的線路長度因而可以相同，能有效避免不同的單光子崩潰二極體有不同的電阻電容延遲。In addition, in the single-photon collapsed diode array of the embodiment of the present invention, each single-photon collapsed diode includes two anodes arranged on a reference line, and any two adjacent single-photon collapsed diodes The two reference lines of the volume are not parallel to each other. That is to say, the two anodes of the adjacent single-photon collapsed diodes are arranged in a staggered manner, and the lengths of the lines connecting the anodes in the adjacent single-photon collapsed diodes can be the same, which can effectively avoid different single-photon collapsed diodes. Photon collapse diodes have different resistance-capacitance delays.

50:光子 100:單光子崩潰二極體陣列 110:陽極線路 112:分支線路 200、200a、200b:單光子崩潰二極體 210:N型半導體埋層 220:基板 300:主動區 310:第一P型半導體井層 320:第一N型半導體井層 330:第二P型半導體井層 340:陽極 350:P型磊晶層 360:P型重摻雜層 400:N型堆疊層 410:第二N型半導體井層 420:陰極 430:高電壓N型半導體井層 440:N型重摻雜層 F1:中心線 J1:第一PN接面 J2:第二PN接面 J3:第三PN接面 D1:間距 L1:參考直線 R1、R2、R3:雪崩區 Z1:曝光區 50: Photon 100: Single-Photon Collapsed Diode Arrays 110: Anode line 112: Branch Line 200, 200a, 200b: Single-Photon Collapse Diodes 210: N-type semiconductor buried layer 220: Substrate 300: Active Zone 310: the first P-type semiconductor well layer 320: the first N-type semiconductor well layer 330: the second P-type semiconductor well layer 340: Anode 350: P-type epitaxial layer 360: P-type heavily doped layer 400:N-type stacked layers 410: the second N-type semiconductor well layer 420: Cathode 430: High Voltage N-Type Semiconductor Well Layer 440: N-type heavily doped layer F1: Centerline J1: The first PN junction J2: Second PN junction J3: The third PN junction D1: Spacing L1: reference line R1, R2, R3: Avalanche area Z1: Exposure Zone

圖1為本發明的一實施例的單光子崩潰二極體陣列的上視示意圖。 圖2為圖1的單光子崩潰二極體陣列沿著I-I線的剖面示意圖。 圖3為圖2中的單光子崩潰二極體的深度與電場分布的對照圖。 FIG. 1 is a schematic top view of a single-photon collapsed diode array according to an embodiment of the present invention. FIG. 2 is a schematic cross-sectional view of the single-photon collapsed diode array of FIG. 1 along the line I-I. FIG. 3 is a comparison diagram of the depth and electric field distribution of the single-photon collapsed diode in FIG. 2 .

50:光子 50: Photon

200:單光子崩潰二極體 200: Single Photon Collapse Diode

210:N型半導體埋層 210: N-type semiconductor buried layer

220:基板 220: Substrate

300:主動區 300: Active Zone

310:第一P型半導體井層 310: the first P-type semiconductor well layer

320:第一N型半導體井層 320: the first N-type semiconductor well layer

330:第二P型半導體井層 330: the second P-type semiconductor well layer

340:陽極 340: Anode

350:P型磊晶層 350: P-type epitaxial layer

360:P型重摻雜層 360: P-type heavily doped layer

400:N型堆疊層 400:N-type stacked layers

410:第二N型半導體井層 410: the second N-type semiconductor well layer

420:陰極 420: Cathode

430:高電壓N型半導體井層 430: High Voltage N-Type Semiconductor Well Layer

440:N型重摻雜層 440: N-type heavily doped layer

D1:間距 D1: Spacing

J1:第一PN接面 J1: The first PN junction

J2:第二PN接面 J2: Second PN junction

J3:第三PN接面 J3: The third PN junction

R1、R2、R3:雪崩區 R1, R2, R3: Avalanche area

Z1:曝光區 Z1: Exposure Zone

Claims (18)

一種單光子崩潰二極體，包括： 一N型半導體埋層； 一主動區，包括： 一第一P型半導體井層，配置於該N型半導體埋層上； 一第一N型半導體井層，配置於該第一P型半導體井層上； 一第二P型半導體井層，配置於該第一N型半導體井層上； 二陽極，配置於該第二P型半導體井層上；以及 一P型磊晶層，連接該第一P型半導體井層及該第二P型半導體井層；以及 一N型堆疊層，配置於該主動區旁，且配置於該N型半導體埋層上。 A single-photon collapse diode comprising: An N-type semiconductor buried layer; an active zone, including: a first P-type semiconductor well layer disposed on the N-type semiconductor buried layer; a first N-type semiconductor well layer, disposed on the first P-type semiconductor well layer; a second P-type semiconductor well layer disposed on the first N-type semiconductor well layer; two anodes, disposed on the second P-type semiconductor well layer; and a P-type epitaxial layer connecting the first P-type semiconductor well layer and the second P-type semiconductor well layer; and An N-type stacked layer is disposed beside the active region and on the N-type semiconductor buried layer. 如請求項1所述的單光子崩潰二極體，其中該第一P型半導體井層與該N型半導體埋層之間形成一第一PN接面，該第一P型半導體井層與該第一N型半導體井層之間形成一第二PN接面，該第一N型半導體井層與該第二P型半導體井層之間形成一第三PN接面，且該第一、第二、第三PN接面形成三個雪崩區。The single-photon collapsed diode as claimed in claim 1, wherein a first PN junction is formed between the first P-type semiconductor well layer and the N-type semiconductor buried layer, and the first P-type semiconductor well layer and the A second PN junction is formed between the first N-type semiconductor well layers, a third PN junction is formed between the first N-type semiconductor well layer and the second P-type semiconductor well layer, and the first and second Second, the third PN junction forms three avalanche regions. 如請求項2所述的單光子崩潰二極體，其中該單光子崩潰二極體在該二陽極之間的收光區域為一曝光區，該曝光區涵蓋該三個雪崩區。The single-photon collapsed diode according to claim 2, wherein a light-receiving area of the single-photon collapsed diode between the two anodes is an exposure area, and the exposure area covers the three avalanche areas. 如請求項3所述的單光子崩潰二極體，其中在平行於該第二P型半導體井層的方向上，該曝光區的範圍小於該主動區的範圍。The single-photon collapsed diode of claim 3, wherein in a direction parallel to the second P-type semiconductor well layer, the range of the exposure region is smaller than the range of the active region. 如請求項1所述的單光子崩潰二極體，其中該P型磊晶層沿著該第一N型半導體井層的側邊從該第一P型半導體井層延伸至該第二P型半導體井層。The single-photon collapsed diode of claim 1, wherein the P-type epitaxial layer extends from the first P-type semiconductor well layer to the second P-type along a side of the first N-type semiconductor well layer semiconductor well layer. 如請求項5所述的單光子崩潰二極體，其中該P型磊晶層沿著該第一N型半導體井層的相對兩側邊從該第一P型半導體井層延伸至該第二P型半導體井層。The single-photon collapsed diode of claim 5, wherein the P-type epitaxial layer extends from the first P-type semiconductor well layer to the second along opposite sides of the first N-type semiconductor well layer P-type semiconductor well layer. 如請求項1所述的單光子崩潰二極體，其中該N型堆疊層環繞該主動區。The single-photon collapsed diode of claim 1, wherein the N-type stack surrounds the active region. 如請求項1所述的單光子崩潰二極體，其中該主動區更包括二P型重摻雜層，分別連接該二陽極與該第二P型半導體井層。The single-photon collapsed diode as claimed in claim 1, wherein the active region further comprises two P-type heavily doped layers, respectively connecting the two anodes and the second P-type semiconductor well layer. 如請求項1所述的單光子崩潰二極體，其中該N型堆疊層包括： 一第二N型半導體井層，配置於該N型半導體埋層上；以及 一陰極，配置於該第二N型半導體井層上。 The single-photon collapsed diode of claim 1, wherein the N-type stack comprises: a second N-type semiconductor well layer disposed on the N-type semiconductor buried layer; and A cathode is disposed on the second N-type semiconductor well layer. 如請求項9所述的單光子崩潰二極體，其中該N型堆疊層更包括： 一高電壓N型半導體井層，配置於該N型半導體埋層與該第二N型半導體井層之間；以及 一N型重摻雜層，配置於該第二N型半導體井層與該陰極之間。 The single-photon collapsed diode as claimed in claim 9, wherein the N-type stacked layer further comprises: a high-voltage N-type semiconductor well layer disposed between the N-type semiconductor buried layer and the second N-type semiconductor well layer; and An N-type heavily doped layer is disposed between the second N-type semiconductor well layer and the cathode. 如請求項1所述的單光子崩潰二極體，其中該第一P型半導體井層的P型摻雜濃度是落在10 17cm -3至5×10 18cm -3的範圍內，該第一N型半導體井層的N型摻雜濃度是落在10 17cm -3至5×10 18cm -3的範圍內，且該第二P型半導體井層的P型摻雜濃度是落在10 17cm -3至5×10 18cm -3的範圍內。 The single-photon collapsed diode according to claim 1, wherein the P-type doping concentration of the first P-type semiconductor well layer is in the range of 10 17 cm -3 to 5×10 18 cm -3 , the The N-type doping concentration of the first N-type semiconductor well layer is in the range of 10 17 cm -3 to 5×10 18 cm -3 , and the P-type doping concentration of the second P-type semiconductor well layer is In the range of 10 17 cm -3 to 5×10 18 cm -3 . 如請求項1所述的單光子崩潰二極體，其中該第一P型半導體井層與該第二P型半導體井層之間的間距是落在1微米至2微米的範圍內。The single-photon collapsed diode of claim 1, wherein a distance between the first P-type semiconductor well layer and the second P-type semiconductor well layer falls within a range of 1 to 2 microns. 如請求項1所述的單光子崩潰二極體，其中該二陽極分別配置於該第二P型半導體井層上的相對兩側。The single-photon collapsed diode according to claim 1, wherein the two anodes are respectively disposed on opposite sides of the second P-type semiconductor well layer. 一種單光子崩潰二極體陣列，包括： 多個排成二維陣列的單光子崩潰二極體，每一單光子崩潰二極體包括： 一N型半導體埋層； 一主動區，包括： 一第一P型半導體井層，配置於該N型半導體埋層上； 一第一N型半導體井層，配置於該第一P型半導體井層上； 一第二P型半導體井層，配置於該第一N型半導體井層上； 二陽極，配置於該第二P型半導體井層上的相對兩側；以及 一P型磊晶層，連接該第一P型半導體井層及該第二P型半導體井層；以及 一N型堆疊層，配置於該主動區旁，且配置於該N型半導體埋層上， 其中，每一單光子崩潰二極體的該二陽極排列於一參考直線上，且相鄰的任二個單光子崩潰二極體的二個參考直線彼此不平行。 A single-photon collapsed diode array comprising: A plurality of single-photon collapsed diodes arranged in a two-dimensional array, each single-photon collapsed diode includes: An N-type semiconductor buried layer; an active zone, including: a first P-type semiconductor well layer disposed on the N-type semiconductor buried layer; a first N-type semiconductor well layer, disposed on the first P-type semiconductor well layer; a second P-type semiconductor well layer disposed on the first N-type semiconductor well layer; Two anodes, disposed on opposite sides of the second P-type semiconductor well layer; and a P-type epitaxial layer connecting the first P-type semiconductor well layer and the second P-type semiconductor well layer; and an N-type stack layer, disposed beside the active region, and disposed on the N-type semiconductor buried layer, Wherein, the two anodes of each single-photon collapsed diode are arranged on a reference line, and the two reference lines of any two adjacent single-photon collapsed diodes are not parallel to each other. 如請求項14所述的單光子崩潰二極體陣列，其中相鄰的任二個單光子崩潰二極體的該二個參考直線彼此垂直。The single-photon collapsed diode array according to claim 14, wherein the two reference straight lines of any two adjacent single-photon collapsed diodes are perpendicular to each other. 如請求項14所述的單光子崩潰二極體陣列，更包括多個陽極線路，每一陽極線路具有二分支線路，分別連接至一個單光子崩潰二極體的二個陽極。The single-photon collapsed diode array according to claim 14, further comprising a plurality of anode lines, each anode line has two branch lines, which are respectively connected to the two anodes of a single-photon collapsed diode. 如請求項16所述的單光子崩潰二極體陣列，其中在以該單光子崩潰二極體陣列的一中心線為對稱軸的任兩鏡像對稱位置上的二個單光子崩潰二極體上的陽極線路的線路走向不同，但線路長度相等。The single-photon collapsed diode array of claim 16, wherein on two single-photon collapsed diodes at any two mirror-symmetrical positions with a centerline of the single-photon collapsed diode array as the axis of symmetry The line direction of the anode line is different, but the line length is equal. 如請求項16所述的單光子崩潰二極體陣列，其中在平行於該單光子崩潰二極體陣列的一中心線的方向上排列的相鄰二個單光子崩潰二極體上的陽極線路的長度相等。The single-photon collapsed diode array of claim 16, wherein the anode lines on two adjacent single-photon collapsed diodes arranged in a direction parallel to a centerline of the single-photon collapsed diode array are equal in length.
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