TW202234637A - 半導體裝置 - Google Patents
半導體裝置 Download PDFInfo
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- TW202234637A TW202234637A TW110133734A TW110133734A TW202234637A TW 202234637 A TW202234637 A TW 202234637A TW 110133734 A TW110133734 A TW 110133734A TW 110133734 A TW110133734 A TW 110133734A TW 202234637 A TW202234637 A TW 202234637A
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- H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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Abstract
一或多個主動區結構各自在垂直方向中垂直地向外凸出基板,並在第一水平方向中水平延伸。源極/汲極構件在垂直方向中位於主動區結構上。源極/汲極接點在垂直方向中位於源極/汲極構件上。源極/汲極接點包括底部與頂部。保護襯墊層位於源極/汲極接點的頂部的側表面上,但不位於源極/汲極接點的底部的側表面上。
Description
本發明實施例一般關於半導體裝置,更特別關於場效電晶體如平面場效電晶體、三維鰭狀場效電晶體、或全繞式閘極裝置。
半導體積體電路產業已經歷指數成長。積體電路材料與設計的技術進展,使每一代的積體電路比前一代具有更小且更複雜的電路。在積體電路演進中,功能密度(比如單位晶片面積的內連線裝置數目)通常隨著幾何尺寸(比如採用的製作製程所能產生的最小構件或線路)縮小而增加。尺寸縮小的製程一般有利於增加產能並降低相關成本。尺寸縮小亦會增加處理與製造積體電路的複雜度。
舉例來說,隨著半導體裝置持續縮小,閘極接點與附近的源極/汲極接點之間可能更容易發生橋接(如電性短路)。不幸的是,避免這些橋接問題的習知方法可能會增加電阻及/或縮小源極/汲極磊晶著陸區。如此一來,會劣化裝置效能。
雖然製作半導體裝置的習知方法通常適用,但無法符合所有方面的需求。
本發明一實施例關於半導體裝置。半導體裝置包括一或多個主動區結構,各自在垂直方向中垂直地向外凸出基板,並在第一水平方向中水平延伸。半導體裝置包括源極/汲極構件,在垂直方向中位於主動區結構上。半導體裝置包括源極/汲極接點,在垂直方向中位於源極/汲極構件上。源極/汲極接點包括底部與頂部。半導體裝置包括保護襯墊層,位於源極/汲極接點的頂部的側表面上,但不位於源極/汲極接點的底部的側表面上。
本發明另一實施例關於半導體裝置。半導體裝置包括一或多個鰭狀結構,各自在垂直方向中垂直地凸出基板並在第一水平方向中水平延伸。半導體裝置包括磊晶源極/汲極,在垂直方向中位於鰭狀結構上。半導體裝置包括源極/汲極接點,在垂直方向中位於磊晶源極/汲極上。源極/汲極接點包括上側部分與下側部分。在垂直方向與垂直於第一水平方向的第二水平方向所定義的剖面中,下側部分具有斜向輪廓且最大寬度大於上側部分的最大寬度。
本發明又一實施例關於半導體裝置的形成方法。提供積體電路裝置,其包括主動區、源極/汲極構件形成於主動區上、閘極結構形成於主動區上並與源極/汲極構件相鄰、以及層間介電層形成於源極/汲極構件上。蝕刻開口於源極/汲極構件上。開口部分地延伸穿過層間介電層但不露出源極/汲極構件的上側表面。形成保護襯墊層於開口的側壁上。移除源極/汲極構件的上側表面上的層間介電層的保留部分,以露出源極/汲極構件的上側表面。形成源極/汲極接點於開口中。形成閘極接點於閘極結構上。
下述詳細描述可搭配圖式說明,以利理解本發明的各方面。值得注意的是,各種結構僅用於說明目的而未按比例繪製,如本業常態。實際上為了清楚說明,可任意增加或減少各種結構的尺寸。
下述內容提供的不同實施例或實例可實施本發明的不同結構。下述特定構件與排列的實施例係用以簡化本發明內容而非侷限本發明。舉例來說,形成第一構件於第二構件上的敘述包含兩者直接接觸的實施例,或兩者之間隔有其他額外構件而非直接接觸的實施例。此外,本發明之多個實例可重複採用相同標號以求簡潔,但多種實施例及/或設置中具有相同標號的元件並不必然具有相同的對應關係。
此外,本發明實施例之結構形成於另一結構上、連接至另一結構、及/或耦接至另一結構中,結構可直接接觸另一結構,或可形成額外結構於結構及另一結構之間(即結構未接觸另一結構)。此外,空間性的相對用語如「下方」、「其下」、「下側」、「上方」、「上側」、或類似用語可用於簡化說明某一元件與另一元件在圖示中的相對關係。空間性的相對用語可延伸至以其他方向使用之元件,而非侷限於圖示方向。此外,當數值或數值範圍的描述有「約」、「近似」、或類似用語時,除非特別說明否則其包含所述數值的+/-10%。舉例來說,用語「約5 nm」包含的尺寸範圍為4.5 nm至5.5 nm。
本發明一實施例關於形成獨特形狀的保護襯墊層於源極/汲極接點的側壁的一部分(非全部)上的新穎製作製程,以最小化電阻並避免電性橋接。具體而言,隨著半導體製作朝更小的技術節點進展,閘極接點位置稍微偏移即可能造成閘極接點與附近的源極/汲極接點之間的橋接(如電性短路)。為了避免閘極接點與源極/汲極接點橋接,可形成保護襯墊層於源極/汲極接點的側壁上。由於形成保護襯墊層,就算閘極接點的位置朝源極/汲極接點的方向偏移,最終位置偏移的閘極接點仍可避免直接物理接觸源極/汲極接點,因為保護襯墊層保留於閘極接點與源極/汲極接點之間,並避免閘極接點的導電材料直接接觸源極/汲極接點。因此保護襯墊層可避免閘極接點與源極/汲極接點之間的電性橋接。
然而若形成保護襯墊層,其將位於源極/汲極接點的所有側壁上,而缺點之一為減少源極/汲極磊晶著陸區。換言之,保護襯墊層的下表面將佔據磊晶形成的源極/汲極的上側表面,其將減少源極/汲極與源極/汲極接點(形成於源極/汲極上)之間的可用界面面積。減少源極/汲極表面接觸面積會增加源極/汲極接點相關的電阻,因為電阻與表面接觸面積成反比。源極/汲極接點電阻增加會造成更大的能耗及/或降低速度,這將劣化裝置效能而屬不想要的現象。
為了克服上述問題,本發明實施例採用新穎的製作製程以形成保護襯墊層於源極/汲極接點的側壁的上側部分上,而非源極/汲極接點的所有側壁上。由於保護襯墊層不在源極/汲極接點的側壁底部,磊晶源極/汲極構件的上側部分可100%用於源極/汲極接點的著陸。換言之,本發明實施例提供較大的界面面積於源極/汲極接點的下表面與磊晶源極/汲極構件的上表面之間。增加界面面積可減少源極/汲極接點電阻,進而改善裝置效能。與此同時,本發明實施例的保護襯墊層仍可有效阻擋閘極接點與源極/汲極接點的橋接。這是因為閘極接點的位置垂直高於源極/汲極接點,即源極/汲極接點的頂部或中間部分(仍被保護襯墊層所保護)比源極/汲極接點的底部(不含保護襯墊層)更易發生橋接(若發生的話)。本發明多種實施例將搭配圖2A至8A、2B至8B、2C至8C、及9至11詳述如下。
圖1A及1B係積體電路裝置90的一部份的三維透視圖與上視圖。積體電路裝置90可為處理積體電路時製作的中間裝置或其部分,其可包含靜態隨機存取記憶體及/或其他邏輯電路,被動構件如電阻、電容、或電感,以及主動構件如p型場效電晶體、n型場效電晶體、鰭狀場效電晶體、金氧半場效電晶體、互補式金氧半電晶體、雙極電晶體、高電壓電晶體、高頻電晶體、及/或其他記憶體單元。本發明實施例不限於任何特定數目的裝置或裝置區,或鍺任何特定的裝置設置,除非記載於請求項。舉例來說,雖然圖式中的積體電路裝置90為三維鰭狀場效電晶體裝置,本發明實施例的概念易可用於平面場效電晶體或全繞式閘極裝置。
如圖1A所示,積體電路裝置90包括基板110。基板110可包含半導體元素(單一元素)如矽、鍺、及/或其他合適材料;半導體化合物如碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、銻化銦、及/或其他合適材料;半導體合金如矽鍺、磷砷化鎵、砷化鋁銦、砷化鋁鎵、砷化鎵銦、磷化鎵銦、磷砷化鎵銦、及/或其他合適材料。基板110可為具有一致組成的單層材料。在其他實施例中,基板110可包含多個材料層,其可具有適用於製造積體電路裝置的類似或不同組成。在一例中,基板110可為絕緣層上矽基板,其具有半導體矽層形成於氧化矽層上。在另一例中,基板110可包含導電層、半導體層、介電層、其他層、或上述之組合。多種摻雜區如源極/汲極區可形成於基板110之中或之上。摻雜區可摻雜n型摻質如磷或砷及/或p型摻質如硼,端視設計需求而定。摻雜區可直接形成於基板110之上、p型井之中、n型井之中、雙井結構之中、或採用隆起結構。摻雜區的形成方法可為佈植摻質原子、原位摻雜的磊晶成長、及/或其他合適技術。
三維主動區形成於基板110上。主動區為伸長的鰭狀結構,其向上凸出基板110。如此一來,主動區之後可稱作鰭狀結構120。鰭狀結構120的製作方法可採用含光微影與蝕刻製程的合適製程。光微影製程可包含形成光阻層於基板110上、曝光光阻至一圖案、進行曝光後烘烤製成、並顯影光阻以形成含光阻的遮罩單元(未圖示)。接著採用遮罩單元以蝕刻凹陷至基板110中,並留下鰭狀結構120於基板110上。蝕刻製程可包含乾蝕刻、濕蝕刻、反應性離子蝕刻、及/或其他合適製程。在一些實施例中,鰭狀結構120的形成方法可為雙重圖案化或多重圖案化製程。一般而言,雙重圖案化或多重圖案化製程結合光微影與自對準製程,其產生的圖案間距小於採用單一的直接光微影製程所得的圖案間距。舉例來說,可形成層狀物於基板上,並採用光微影製程圖案化層狀物。採用自對準製程以沿著圖案化的層狀物側部形成間隔物。接著移除間隔物,而保留的間隔物或芯之後可用於圖案化鰭狀結構120。積體電路裝置90亦可包含源極/汲極構件122形成於鰭狀結構120上。源極/汲極構件122可包含磊晶層,其磊晶成長於鰭狀結構120上。
積體電路裝置90更包含隔離結構130形成於基板110上。隔離結構130電性分隔積體電路裝置90的多種構件。隔離結構130可包含氧化矽、氮化矽、氮氧化矽、氟矽酸鹽玻璃、低介電常數的介電材料、及/或其他合適材料。在一些實施例中,隔離結構130可包含淺溝槽隔離結構。在一實施例中,隔離結構130的形成方法可為在形成鰭狀結構120時,蝕刻溝槽於基板110中。接著可將上述隔離材料填入溝槽,再進行化學機械研磨製程。亦可實施其他隔離結構如場氧化物、局部氧化矽、及/或其他合適結構以作為隔離結構130。在其他實施例中,隔離結構130可包含多層結構,比如具有一或多個熱氧化物襯墊層。
積體電路裝置90亦包含閘極結構140形成於鰭狀結構120的通道區中的三側上並與其接合。閘極結構140可為虛置閘極結構(比如包含氧化物閘極介電層與多晶矽閘極),或高介電常數的閘極介電層與金屬閘極結構(其形成方法為取代虛置閘極結構)。雖然未圖示於此,閘極結構140可包含額外材料層如鰭狀結構120上的界面層、蓋層、其他合適層、或上述之組合。
如圖1B所示,多個鰭狀結構120的長度方向沿著X方向,而多個閘極結構140的長度方向沿著Y方向(一般垂直於鰭狀結構120)。在許多實施例中,積體電路裝置90包括額外結構如閘極間隔物(含氣體間隔物)沿著閘極結構140的側壁、硬遮罩層位於閘極結構140上、以及多種其他結構。
應理解的是,本發明的下述多種實施例可用於多通道裝置如全繞式閘極裝置。圖1C顯示全繞式閘極裝置150的三維透視圖。為了清楚說明與一致性,圖1C與圖1A及1B中的類似構件將以相同標號標示。舉例來說,主動區如鰭狀結構120在Z方向中垂直地向上凸出基板110。隔離結構130提供鰭狀結構120之間的電性隔離。閘極結構140位於鰭狀結構120與隔離結構130上。遮罩層155位於閘極結構140上,而閘極間隔物結構160 (其可包含氣體間隔物)位於閘極結構140的側壁上。蓋層165形成於鰭狀結構120上,以在形成隔離結構130時保護鰭狀結構120免於氧化。
多個奈米結構170位於每一鰭狀結構120上。奈米結構170可包含奈米片、奈米館、奈米線、或橫向延伸於X方向中的一些其他種類的奈米結構。閘極結構140之下的奈米結構170的部分可作為全繞式閘極裝置150的通道。介電內側間隔物175可位於奈米結構170之間。此外,雖然為了簡化圖式而未圖示,但閘極介電層以及閘極可包覆每一奈米結構170。在所述實施例中,閘極結構140之外的奈米結構170的部分可作為全繞式閘極裝置150的源極/汲極構件。然而在一些實施例中,連續的源極/汲極構件可磊晶成長於閘極結構140之外的鰭狀結構120的部分上。不論如何,導電源極/汲極接點180可形成於源極/汲極構件上,以提供電性連接至源極/汲極構件。層間介電層185形成於隔離結構130之上,以及閘極結構140與源極/汲極接點180周圍。
製作全繞式閘極裝置的其餘細節已揭露於2018/12/25獲證的美國專利US 10164012,其標題為Semiconductor Device and Manufacturing Method Thereof;2019/7/23獲證的美國專利US 10361278,其標題為Method of Manufacturing a Semiconductor Device and a Semiconductor Device;以及2018/2/6獲證的美國專利US 9887269,其標題為Multi-Gate Device and Method of Fabrication Thereof。雖然本發明實施例的內容關於鰭狀結構獲鰭狀場效電晶體裝置,此內容同樣可應用於全繞式閘極裝置。
圖2A至8A、2B至8B、及2C至8C係不同製作階段的積體電路裝置200的剖視圖或上視圖。具體而言,圖2A至8A對應沿著X方向的剖視圖,而圖2B至8B對應沿著Y方向的剖視圖。如此一來,圖2A至8A可視作X剖視圖,而圖2B至8B可視作Y剖視圖。圖2C至8C對應圖2A至8A與圖2B至8B,係不同製作階段的積體電路裝置200的上視圖。X剖面沿著圖2C至8C所示的剖線A-A’,而Y剖面沿著圖2C至8C所示的剖線B-B’。為了一致性與清楚說明,圖1A至1C中與圖2A至8A、圖2B至8B、與圖2C至8C類似的構件可用相同標號標示。
如圖2A至2C所示,積體電路裝置200包括圖1A至1C所示的基板110,比如矽基板。基板包括多個主動區結構。在所述實施例中,主動區結構包括圖1A及1B所示的鰭狀結構120。然而應理解在其他實施例中,主動區結構可包含圖1C所示的奈米結構。如圖2A及2C所示,鰭狀結構120各自橫向延伸於X方向中。如圖2B及2C所示,鰭狀結構120在Y方向中彼此隔有隔離結構130。源極/汲極構件122可形成於基板110之中或之上,其形成方法可採用磊晶成長製程。在一些實施例中,源極/汲極構件122成長於鰭狀結構120上,如圖2B及2C所示。在一些實施例中,可磊晶成長單一個源極/汲極構件122於多個鰭狀結構120的至少部分上側表面與側表面上。
層間介電層185 (亦圖示於圖1C)形成於基板110與鰭狀結構120上。層間介電層185的形成方法可為電漿輔助化學氣相沉積、可流動的化學氣相沉積、或其他合適方法。在一些實施例中,層間介電層185可包含氧化矽。在一些其他實施例中,層間介電層185可包含低介電常數的介電材料,其介電常數曉於氧化矽的介電常數(約3.9)。層間介電層185亦可視作第零層間介電層。
積體電路裝置200亦包含閘極結構140 (亦圖示於圖1A至1C)形成於基板110上。在一些實施例中,閘極結構140包括高介電常數的介電層與金屬閘極結構,其可各自包含高介電常數的閘極介電層與金屬閘極。閘極結構140的形成方法可採用閘極置換製程。具體而言,可先形成虛置閘極結構於基板110之上與源極/汲極構件122之間。虛置閘極結構可各自包含虛置閘極(如多晶矽閘極)與虛置閘極介電層(如氧化矽的閘極介電層)或高介電常數的閘極介電層(如介電常數大於氧化矽的介電常數的介電材料)。
在形成虛置閘極結構之後,可形成閘極間隔物結構160 (亦圖示於圖1C)於虛置閘極結構的側壁上。在一些實施例中,閘極間隔物結構160可各自包含多個閘極間隔物,比如閘極間隔物250與閘極間隔物260。閘極間隔物250直接位於虛置閘極結構的側壁上,且可包含低介電常數的介電材料(如介電常數小於約3.9的介電材料)。閘極間隔物260位於閘極間隔物250的側壁上,且可包含氮化矽材料。應理解可在形成閘極間隔物結構160之後,再形成層間介電層185。此外,一些實施例的閘極間隔物結構160可包含氣體間隔物。為了簡化圖式,氣體間隔物並未具體圖示於所述實施例中。
在閘極置換製程的一部分中,可採用一或多道蝕刻製程移除虛置閘極結構的虛置多晶矽閘極,以留下閘極間隔物結構160與層間介電層185所定義的開口(溝槽)。接著將閘極結構140的金屬閘極填入這些開口或溝槽。在一些實施例中,若虛置閘極結構包括虛置閘極介電層(如氧化矽的閘極介電層),則虛置閘極介電層亦可取代為高介電常數的閘極介電層以作為閘極結構140的一部分。高介電常數的閘極介電層的例子可包含氧化鉿、氧化鋯、氧化鋁、氧化鉿-氧化鋁合金、氧化鉿矽、氮氧化鉿矽、氧化鉿鉭、氧化鉿鈦、氧化鉿鋯、或上述之組合。金屬閘極形成於高介電常數的閘極介電層上,且可包含一或多個功函數金屬層與一或多個填充金屬層。功函數金屬層可設置以調整個別電晶體的功函數。功函數金屬層的材料例子可包含氮化鈦、鈦鋁、氮化鉭、碳化鈦、碳化鉭、碳化鎢、氮化鈦鋁、鋯鋁、鎢鋁、鉭鋁、鉿鋁、或上述之組合。填充金屬層可作為閘極的主要導電部分。
如圖2A所示,積體電路裝置200可更包含金屬層280形成於每一閘極結構140上,並形成遮罩層290於每一金屬層280上。在一些實施例中,金屬層280與遮罩層290的形成方法可各自為一或多道沉積製程,比如原子層沉積、物理氣相沉積、化學氣相沉積、或上述之組合。金屬層280可包含釕、鈷、銅、鋁、或另一合適的純金屬。金屬層280亦可視作閘極結構140的部分。
在一些實施例中,遮罩層290可包含氮化矽。在其他實施例中,遮罩層290可包含金屬氧化物如氧化鉭、氧化鋁、或氧化鋯。遮罩層290所用的其他合適材料可包括氮氧化矽、具有氮成分的氧化物、氮化氧化物、金屬氧化物介電層、具有鉿成分的氧化物、具有鉭成分的氧化鎢、具有鈦成分的氧化鎢、具有鋯成分的氧化物、具有鋁成分的氧化物、具有鑭成分的氧化物、高介電常數的介電材料、或上述之組合。可以理解的是,亦可進行平坦化製程如化學機械研磨製程,以平坦化遮罩層290的上側表面與層間介電層185的上側表面。在一些實施例中,高介電常數的介電層與金屬閘極結構140可包含額外層,比如界面層、蓋層、擴散/阻障層、或其他可行層。為了簡化圖式,此處不圖示這些額外層。
亦需注意的是在此製作階段中,不可由圖2C的上視圖直接看到鰭狀結構120與源極/汲極構件122,因為被形成其上的其他構件(如層間介電層185或閘極結構)擋住。然而為了方便理解本發明實施例,在圖2C的上視圖中以虛線表示鰭狀結構120及/或源極/汲極構件122的輪廓。
如圖3A至3C所示,對積體電路裝置200進行微影製程300。微影製程300的一部分為形成圖案化的光阻層310於層間介電層185上,比如採用一或多道光阻塗佈製程、曝光、烘烤、顯影、與沖洗製程(不必依此順序進行)。微影製程300亦包含蝕刻製程如濕蝕刻或乾蝕刻製程,其可採用圖案化的光阻層310作為遮罩層。蝕刻製程可蝕刻多個開口320至層間介電層185中。如圖3A所示,每一開口320對準個別的源極/汲極構件122。開口320亦可視作源極/汲極接點開口,因為其在之後的製程終將填入導電材料以形成源極/汲極接點於其中。
進行蝕刻製程而不完全移除層間介電層185,因此不露出源極/汲極構件122。然而蝕刻製程使每一開口320的深度330 (見圖3A)足以使層間介電層185的保留部分(位於源極/汲極構件122上)的上側表面340在Z方向中的垂直位置,至少高於金屬層280的上側表面。如下詳述,將導電材料填入開口320以形成源極/汲極接點,而閘極接點將形成於金屬層280上。為了避免源極/汲極接點與閘極接點之間的電性短路(如橋接),可形成保護襯墊層於閘極間隔物260的側壁上,以提供電性隔離於源極/汲極接點與閘極接點之間。開口320的深度330可使保護襯墊層長到足以避免源極/汲極接點與閘極接點之間的電性橋接,但不會長到佔據源極/汲極接點(之後形成)與源極/汲極構件122之間的界面面積。在此方式中,可依需求減少源極/汲極接點的電阻。
如圖4A至4C所示,對積體電路裝置進行多個沉積與蝕刻循環400。在多個沉積與蝕刻循環400的每一循環中,可進行沉積製程以沉積介電材料420,接著以蝕刻製程蝕刻沉積的介電材料420。在一些實施例中,沉積製程可包含原子層沉積製程,其可設置為準確並精確控制沉積的介電材料420在X方向中的厚度。在一些實施例中,沉積的介電材料420與閘極間隔物260可具有相同的材料組成。舉例來說,一些實施例中沉積製程所沉積的介電材料420與閘極間隔物260包含氮化矽。然而應理解在其他實施例中,沉積的介電材料420與閘極間隔物260可具有不同的材料組成。
沉積與蝕刻循環400的蝕刻製程可包含乾蝕刻製程或濕蝕刻製程。設置蝕刻製程的參數,使沉積的介電材料420與層間介電層185之間具有蝕刻選擇性,以蝕刻介電材料420而實質上不移除層間介電層185。舉例來說,可設置蝕刻製程,使介電材料420的蝕刻速率至少比層間介電層185的蝕刻速率大三倍。
進行沉積與蝕刻循環400,可由沉積與蝕刻的介電材料420之保留部分形成保護襯墊層如介電材料420。由於沉積與蝕刻的多個循環,最終的保護襯墊層如介電材料420各自具有上寬下窄的剖面輪廓於X方向與Z方向所定義的剖面中(如圖4A所示)以及Y方向與Z方向所定義的剖面中(如圖4B所示)。換言之,每一保護襯墊層如介電材料420的寬度(在X方向或Y方向中量測)與保護襯墊層如介電材料420的深度成一函數:隨著保護襯墊層如介電材料420的深度增加(比如更靠近基板110),其寬度減少。在層間介電層185的上表面(如開口320的下表面)或其附近處,每一保護襯墊層如介電材料420的寬度可近似0。如此一來,保護襯墊層如介電材料420不會非必要地縮小原本應為源極/汲極接點的體積,因為源極/汲極接點將在之後的製程形成於開口320中。
如圖5A至5C所示,對積體電路裝置200進行蝕刻製程450以移除層間介電層185的部分,直到露出源極/汲極構件122。在一些實施例中,蝕刻製程450包括濕蝕刻製程。蝕刻製程450在保護襯墊層如介電材料420與層間介電層185之間具有蝕刻選擇性。舉例來說,蝕刻製程450可設置為對層間介電層185的蝕刻速率,實質上大於對保護襯墊層如介電材料420的蝕刻速率。在此方式中,可蝕刻移除層間介電層185而實質上不移除保護襯墊層如介電材料420。然而如圖5A及5B所示,蝕刻製程450可能部分地蝕刻源極/汲極構件122。亦可在蝕刻製程450之前或之後移除光阻層310,且移除方法可為光阻剝除或灰化製程。
如圖6A至6C所示,對積體電路裝置200進行蝕刻製程500,以進一步蝕刻層間介電層185。在一些實施例中,蝕刻製程500為濕蝕刻製程,其設置為在層間介電層185與保護襯墊層如介電材料420之間具有蝕刻選擇性。舉例來說,蝕刻製程500設置為蝕刻移除層間介電層185 (比如含氧化矽)的蝕刻速率,實質上大於蝕刻保護襯墊層如介電材料420 (比如含氮化矽)的蝕刻速率。蝕刻製程500完全移除圖6A的X-Z剖面圖中覆蓋源極/汲極構件122的層間介電層185的保留部分,而保護襯墊層如介電材料420實質上完整。如此一來,移除層間介電層185將完全露出每一源極/汲極構件122的上側表面470。與此同時,保護襯墊層如介電材料420可保護層間介電層185的部分(保護襯墊層如介電材料420位於其上的部分)免於蝕刻。這會造成每一開口320的底部320A在Y方向中橫向擴張。如圖6B所示,底部320A在Y方向中比其餘的開口320向外凸出,而底部320A的側壁各自具有斜向輪廓。此輪廓為本發明實施例的獨特結構,因為習知的製作製程所形成的保護襯墊層如介電材料420不會只位於開口320中的層間介電層185的側壁之上側部分上。如此一來,習知積體電路裝置將缺乏開口320的底部320A橫向凸出的部分。
如圖7A至7C所示,對積體電路裝置200進行源極/汲極接點形成製程550,以形成源極/汲極接點570於開口320之中以及源極/汲極構件122之上。源極/汲極接點形成製程550可包含沉積製程,以沉積導電材料於源極/汲極構件122上並填入開口320。在一些實施例中,沉積製程可包含化學氣相沉積、物理氣相沉積、原子層沉積、或上述之組合,且沉積的導電材料可包含鈷。在其他實施例中,可沉積不同種類的金屬材料至開口320中,比如鋁、銅、鎢、釕、或上述之合金。在沉積製程之後,源極/汲極接點形成製程550亦可包含平坦化製程如化學機械研磨製程,以平坦化沉積的導電材料的上側表面與層間介電層185的上側表面。開口320中的最終結構為源極/汲極接點。
可以理解的是一些實施例可先形成金屬矽化物(如鈦矽化物)於每一源極/汲極構件的上側表面上,以增加導電性(或降低電阻)。舉例來說,可沉積少量的金屬如鈦於源極/汲極構件122的上側表面上,接著可在高溫下進行退火製程使金屬材料與源極/汲極構件中的矽材反應,以形成金屬矽化物的薄層於源極/汲極構件122的上側表面。接著可進行源極/汲極接點形成製程550的沉積製程(其沉積金屬如鈷),使沉積的導電材料(如鈷)形成於金屬矽化物上。為了簡化圖式,金屬矽化物未具體圖示於此。儘管如此,應理解金屬矽化物可視作源極/汲極接點570的一部分。
如上所述,由於本發明實施例進行的新穎製作製程流程(如形成保護襯墊層於開口320的部分側壁上),源極/汲極接點570可具有多種獨特的物理特性,其可使本發明實施例所製作的積體電路裝置易於辨識,比如可採用多種逆向工程技術(如穿透式電子顯微鏡或掃描式電子顯微鏡)辨識。
獨特的物理特性之一為每一源極/汲極構件122的上側表面470的實質上主要部分,可直接物理接觸形成其上的源極/汲極接點570 (其可包含金屬矽化物)。在一些實施例中,每一源極/汲極構件122的上側表面470可100%的直接物理接觸形成其上的源極/汲極接點570。這是可能的,因為在垂直延伸開口320以完全穿過層間介電層185而露出源極/汲極構件122的上側表面470之前,即形成保護襯墊層如介電材料420。如此一來,保護襯墊層如介電材料420的最底部端或最底部表面在Z方向中實質上垂直地高於源極/汲極構件122的上側表面470,因此保護襯墊層如介電材料420不太可能直接物理接觸源極/汲極構件122的上側表面470。綜上所述,源極/汲極構件122的上側表面470可100%作為源極/汲極接點570所用的著陸區,而非被保護襯墊層如介電材料420佔據而不必要地犧牲上側表面470的一部分。在此方式中,源極/汲極接點570所用的著陸面積增加可降低其電阻,進而改善裝置效能。
源極/汲極接點570的另一獨特特性為其底部的橫向凸出或擴張。具體而言,如圖7B所示的Y剖線的剖視圖,源極/汲極接點570可視作具有底部570A (直接物理接觸源極/汲極構件122的上側表面470的部分)與頂部570B (在Z方向中位於底部570A上)。頂部570B的側壁為平直或線性,且其寬度(在Y方向中測量的橫向尺寸)隨著不同深度的變化不明顯(小於約30%)。與此相較,源極/汲極接點570的底部在Y方向中比頂部570B向外凸出。舉例來說,底部570A的側表面580在Y方向中向外凸出頂部570B的側表面590的底端。在一些實施例中,底部570A的側表面580的最外側點在Y方向中,比頂部570B的側表面590的最外側點更外側。換言之,底部570A在Y方向中的最大寬度超過頂部570B的最大寬度。此外在圖7B的Y剖視圖中,側表面580具有斜向輪廓(比如在Y方向中向外傾斜)。在所示實施例中,底部570A的側表面580亦可為弧形或圓潤化,而頂部570B的側表面590可比側表面580更線性或筆直。類似地,由於保護襯墊層如介電材料420的底端未接觸源極/汲極接點570的底部570A,保護襯墊層如介電材料420不會減少源極/汲極接點570與源極/汲極構件122之間的界面面積。
如圖8A至8C所示,形成介電層600於層間介電層185與源極/汲極接點570之平坦化的上側表面上。在一些實施例中,介電層600包括氮化矽。接著可形成層間介電層610於介電層600上。在一些實施例中,層間介電層610包括氧化矽,或包括與層間介電層185類似的材料組成。層間介電層610亦可視作第一層間介電層。之後可形成多個閘極接點650與源極/汲極通孔660,其形成方法可包括圖案化製程以蝕刻閘極接點開口於閘極結構140上,並蝕刻源極/汲極通孔開口於源極/汲極接點570上。閘極接點開口垂直延伸穿過閘極結構140上的層間介電層610、介電層600、與遮罩層290的部分。源極/汲極通孔開口垂直延伸穿過源極/汲極接點570上的層間介電層610與介電層600的部分。接著將一或多種導電材料(如鈷、鎢、釕、銅、鋁、或上述之組合)填入閘極接點開口與源極/汲極通孔開口,以形成閘極接點650於閘極接點開口中,並形成源極/汲極通孔660於源極/汲極通孔開口中。閘極接點650提供電性連接至閘極結構140,而源極/汲極通孔660經由源極/汲極接點570提供電性連接至源極/汲極構件122。
如上所述,隨著半導體裝置的製作方法進展至較小的技術節點,多種積體電路構件的位置偏移可能造成電性橋接的風險。舉例來說,若不形成保護襯墊層如介電材料420,在蝕刻閘極接點開口時,只要閘極接點開口的位置朝附近的源極/汲極接點570稍微橫向偏移,就會非刻意地露出附近的源極/汲極接點570的一部分。當此狀況發生時,將導電材料填入閘極接點開口所形成的閘極接點650可能物理接觸源極/汲極接點570,造成閘極接點650與源極/汲極接點570之間產生不想要的電性短路。由於在閘極接點開口的蝕刻製程時,保護襯墊層的蝕刻速率遠小於遮罩層290的蝕刻速率,因此此處存在的保護襯墊層如介電材料420在蝕刻閘極接點開口時,可避免閘極接點開口露出源極/汲極接點570。換言之,即使閘極接點開口的位置在X方向中橫向偏移,仍可蝕刻閘極接點開口至穿過遮罩層290而不損傷保護襯墊層如介電材料420處,特別是因為保護襯墊層如介電材料420在X方向中的深度比閘極接點開口的深度深。如此一來,保護襯墊層如介電材料420可充分避免閘極接點650與源極/汲極接點570之間的電性橋接。
值得注意的是在圖8C的上視圖中,以虛線表示閘極結構140的輪廓,因為在此製作階段的上視圖無法直接看到閘極結構140。
積體電路裝置200可實施於多種積體電路應用中,包括記憶體裝置如靜態隨機存取記憶體裝置。在此考量中,圖9係單埠的靜態隨機存取記憶體單元800 (如一位元的靜態隨機存取記憶體單元)的電路圖。單埠的靜態隨機存取記憶體單元800包括上拉電晶體PU1及PU2、下拉電晶體PD1及PD2、與穿閘電晶體PG1及PG2。如電路圖所示,上拉電晶體PU1及PU2為p型電晶體,而穿閘電晶體PG1及PG2與下拉電晶體PD1及PD2為n型電晶體。在本發明多種實施例中,穿閘電晶體PG1及PG2與下拉電晶體PD1及PD2的間隔物,比上拉電晶體PU1及PU2的間隔物薄。由於所述實施例中的靜態隨機存取記憶體單元800包括六個電晶體,其亦可視作6T靜態隨機存取記憶體單元。
上拉電晶體PU1與下拉電晶體PD1的汲極耦接在一起,而上拉電晶體PU2與下拉電晶體PD2的汲極耦接在一起。上拉電晶體PU1與下拉電晶體PD1以及上拉電晶體PU2與下拉電晶體PD2交叉耦合,以形成第一資料閂鎖。上拉電晶體PU2與下拉電晶體PD2的閘極耦接在一起並耦接至上拉電晶體PU1與下拉電晶體PD1的汲極以形成第一儲存節點SN1,而上拉電晶體PU1與下拉電晶體PD1的閘極耦接在一起並耦接至上拉電晶體PU2與下拉電晶體PD2的汲極以形成互補第一儲存節點SNB1。上拉電晶體PU1及PU2的源極耦接至電源電壓Vcc (亦可視作Vdd),而下拉電晶體PD1及PD2的源極耦接至電壓Vss (在一些實施例中,其可為電性接地)。
第一資料閂鎖的第一儲存節點SN1經由穿閘電晶體PG1耦接至位元線BL,而互補第一儲存節點SNB1經由穿閘電晶體PG2耦接至互補位元線BLB。第一儲存節點SN1與互補第一儲存節點SNB1為互補節點,其通常為相反的邏輯等級(邏輯高或邏輯低)。穿閘電晶體PG1及PG2的閘極耦接至字元線WL。可採用平面電晶體裝置、鰭狀場效電晶體裝置、及/或全繞式閘極裝置,實施靜態隨機存取記憶體裝置如靜態隨機存取記憶體單元800。
圖10係本發明實施例中的積體電路製作系統900。製作系統900包括多個實體902、904、906、908、910、912、914、916、,,,、至N,其可經由通訊網路918相連。網路918可為單一網路或多種不同網路,比如網內網路或網際網路,其可包括有線或無線通訊通道。
在一些實施例中,實體902指的是製造協作所用的服務系統,實體904指的是使用者如監控感興趣的產品之產品工程師,實體906指的是控制製程與相關配方或者調整條件與設定製程工具的製程工程師,實體908指的是測試與測量積體電路所用的計量工具,實體910指的是半導體製程工具如極紫外線工具(用於進行光微影製程以定義靜態隨機存取記憶體裝置的閘極間隔物),實體912指的是與製程工具如實體910相關的虛擬計量模組,實體914指的是與處理工具如實體910以及額外的其他處理工具相關的進階處理控制模組,而實體916指的是與處理工具如實體910相關的取樣模組。
每一實體可與其他實體作用,以提供積體電路製作、製程控制、及/或計算能力至其他實體,或自其他實體接收這些能力。每一實體亦可包含一或多個計算機系統以進行計算並執行自動化。舉例來說,實體914的先進製程控制模組可包含多個計算機硬體,其具有軟體指令編碼於其中。計算機硬體可包含硬碟、隨身碟、光碟、隨機存取記憶體、顯示裝置如螢幕、輸入/輸出裝置如滑鼠與鍵盤。軟體指令可由任何合適的程式語言寫入,且可設計為執行特定工作。
積體電路製作系統900可整合製造積體電路(以及製造積體電路的先進製程控制)所用的實體。在一實施例中,先進製程控制包括依據計量結果,調整適用於相關晶圓的製程工具的製程條件、設定、及/或配方。
在另一實施例中,依據製程品質及/或產品品質確認的最佳採樣率,自處理過的晶圓子集測量計量結果。在又一實施例中,依據製程品質及/或產品品質的多種特性所確認的最佳採樣場及點,自處理的晶圓子集的選定場及點測量計量結果。
積體電路製作系統900提供的能力之一為實現諸如設計、工程、製程、計量、與高級製程控制的協作和資訊存取。積體電路製作系統900提供的另一能力為整合設備之間的系統,例如計量工具和製程工具之間的系統。這些整合有利於設施協調其活動。舉例來說,整合計量工具與製程工具可更有效地將製造資訊結合至製作製程或APC模組中,且可將計量工具在線上或現場測量的晶圓數據整合至相關的製程工具中。
圖11係本發明實施例中,製作半導體裝置的方法1000的流程圖。方法1000包括的步驟1010提供積體電路裝置,其包括主動區、源極/汲極構件形成於主動區上、閘極結構形成於主動區上並與源極/汲極構件相鄰、以及層間介電層形成於源極/汲極構件上。
方法1000包括的步驟1020蝕刻開口於源極/汲極構件上。開口部分地延伸穿過層間介電層,但不露出源極/汲極構件的上側表面。
方法1000包括的步驟1030形成保護襯墊層於開口側壁上。
方法1000包括的步驟1040移除源極/汲極構件的上側部分上的層間介電層的保留部分,以露出源極/汲極構件的上側表面。
方法1000包括的步驟1050形成源極/汲極接點於開口中。
方法1000包括的步驟1060形成閘極接點於閘極結構上。
在一些實施例中,步驟1020蝕刻開口,使其延伸的深度比閘極結構的上側表面更深。
在一些實施例中,步驟1030進行多個循環,其各自包含沉積介電材料的沉積製程與蝕刻沉積的介電材料的蝕刻製程。在一些實施例中,沉積製程沉積的介電材料可與層間介電層具有不同的材料組成。
在一些實施例中,步驟1040完全露出源極/汲極構件的上側表面。在一些實施例中,步驟1050形成源極/汲極接點於源極/汲極構件的所有上側表面上。
在一些實施例中,步驟1040的蝕刻製程在保護襯墊層與層間介電層之間具有蝕刻選擇性,以蝕刻層間介電層而實質上不影響保護襯墊層。
在一些實施例中,步驟1040進行第一蝕刻製程,可垂直延伸開口以穿過層間介電層,直到露出源極/汲極構件的上側表面,接著進行第二蝕刻製程以橫向擴展開口底部。
可以理解的是,方法1000在步驟1010至1060之前、之中、或之後可包含額外步驟。舉例來說,方法1000可包含步驟如形成虛置閘極結構、形成額外金屬層、封裝製程、測試製程、或類似步驟。為了簡化說明,在此不詳述這些額外步驟。
上述的進階微影製程、方法、與材料可用於許多應用,包括鰭狀場效電晶體。舉例來說,可圖案化鰭狀物以產生較緊密的空間於結構之間,而上述內容適用於此。此外,用於形成鰭狀場效電晶體的間隔物亦可視作芯,其可依據上述內容進行製程。亦應理解的是,本發明的上述多種實施例可用於多通道裝置如全繞式閘極裝置。本發明實施例的內容關於鰭狀結構或鰭狀場效電晶體裝置,但此內容同樣可用於全繞式閘極裝置。
總而言之,本發明實施例的保護襯墊層形成於源極/汲極接點的側表面之上側部分上,但不形成於源極/汲極接點的側表面的下側部分上。進行蝕刻製程以蝕刻源極/汲極接點開口,其部分延伸穿過層間介電層,其中源極/汲極接點開口對準但不露出其下方的源極/汲極構件。保護襯墊層形成於源極/汲極接點開口的側表面上。源極/汲極接點開口之後可向下垂直延伸以露出源極/汲極構件,接著形成導電材料以填入源極/汲極接點開口而形成源極/汲極接點。
本發明實施例可比習知裝置提供更多優點。然而應理解此處未說明所有優點、不同實施例可提供不同優點、且任何實施例不必具有特定優點。優點之一為電阻可降低。舉例來說,形成保護襯墊層與源極/汲極接點的製程順序,可確保源極/汲極接點可著陸於源極/汲極構件的所有上側表面上,而保護襯墊層不會佔據源極/汲極接點的著陸區的一部分。源極/汲極接點與源極/汲極構件之間的界面面積越大,則與源極/汲極接點相關的電阻越小,因為電阻與界面面積成反比。另一優點為保護襯墊層可避免或緩解源極/汲極接點與附近的閘極接點之間不想要的橋接。具體而言,隨著半導體結構尺寸隨著每一技術世代持續縮小,構件的位置偏移如閘極相對於源極/汲極接點的位置偏移,可能造成這些構件之間不想要的橋接或短路。此處的保護襯墊層可避免閘極接點開口突出而造成閘極接點與源極/汲極接點之間直接物理接觸的路徑。換言之,在蝕刻閘極接點開口時,就算閘極接點開口的位置朝著源極/汲極接點的方向橫向偏移,保護襯墊層的存在可阻止閘極接點開口的蝕刻製程到達源極/汲極接點。如此一來,可避免填入閘極接點開口的導電材料(形成閘極接點)到達源極/汲極接點。如此一來,保護襯墊層可減少閘極接點與源極/汲極接點之間的電性橋接風險。其他優點可包含與現存的製作製程(如鰭狀場效電晶體與全繞式閘極製程)相容,以簡化製作並降低實施成本。
本發明一實施例關於半導體裝置。半導體裝置包括一或多個主動區結構,各自在垂直方向中垂直地向外凸出基板,並在第一水平方向中水平延伸。半導體裝置包括源極/汲極構件,在垂直方向中位於主動區結構上。半導體裝置包括源極/汲極接點,在垂直方向中位於源極/汲極構件上。源極/汲極接點包括底部與頂部。半導體裝置包括保護襯墊層,位於源極/汲極接點的頂部的側表面上,但不位於源極/汲極接點的底部的側表面上。
在一些實施例中,半導體裝置更包括閘極結構,在第一水平方向中與源極/汲極接點相鄰;以及閘極接點,在垂直方向中位於閘極結構上,其中保護襯墊層在第一水平方向中分開閘極接點與源極/汲極接點。
在一些實施例中,保護襯墊層在垂直方向中的深度增加時,保護襯墊層在第一水平方向與不同於第一水平方向的第二水平方向中的寬度均減少。
在一些實施例中,保護襯墊層在垂直方向中的深度大於閘極接點的深度。
在一些實施例中,源極/汲極接點的底部在不同於第一水平方向的第二水平方向中,相對於頂部向外凸出。
在一些實施例中,源極/汲極構件的所有上側表面直接物理接觸源極/汲極接點。
在一些實施例中,源極/汲極接點的底部側表面,在垂直方向與不同於第一水平方向的第二水平方向所定義的剖視圖中具有斜向輪廓。
在一些實施例中,源極/汲極接點的底部側表面,在垂直方向與不同於第一水平方向的第二水平方向所定義的剖視圖中為弧形。
在一些實施例中,半導體裝置更包括層間介電層位於主動區結構上,其中保護襯墊層與層間介電層位於主動區結構上,其中保護襯墊層與層間介電層包括不同種類的介電材料。
在一些實施例中,主動區結構各自包含半導體鰭狀結構。
本發明另一實施例關於半導體裝置。半導體裝置包括一或多個鰭狀結構,各自在垂直方向中垂直地凸出基板並在第一水平方向中水平延伸。半導體裝置包括磊晶源極/汲極,在垂直方向中位於鰭狀結構上。半導體裝置包括源極/汲極接點,在垂直方向中位於磊晶源極/汲極上。源極/汲極接點包括上側部分與下側部分。在垂直方向與垂直於第一水平方向的第二水平方向所定義的剖面中,下側部分具有斜向輪廓且最大寬度大於上側部分的最大寬度。
在一些實施例中,半導體裝置更包括:閘極結構,在垂直方向中位於基板上並在第一水平方向中與源極/汲極接點相鄰;閘極接點,在垂直方向中位於閘極結構上;以及保護襯墊層,在第一水平方向中位於閘極接點與源極/汲極接點之間,其中保護襯墊層位於源極/汲極接點的上側部分的側表面上,且不位於源極/汲極接點的下側部分的側表面上。
在一些實施例中,保護襯墊層的寬度隨著深度變化。
本發明又一實施例關於半導體裝置的形成方法。提供積體電路裝置,其包括主動區、源極/汲極構件形成於主動區上、閘極結構形成於主動區上並與源極/汲極構件相鄰、以及層間介電層形成於源極/汲極構件上。蝕刻開口於源極/汲極構件上。開口部分地延伸穿過層間介電層但不露出源極/汲極構件的上側表面。形成保護襯墊層於開口的側壁上。移除源極/汲極構件的上側表面上的層間介電層的保留部分,以露出源極/汲極構件的上側表面。形成源極/汲極接點於開口中。形成閘極接點於閘極結構上。
在一些實施例中,露出步驟包括完全露出源極/汲極構件的上側表面;以及形成源極/汲極接點的步驟包括形成源極/汲極接點於源極/汲極構件的所有上側表面上。
在一些實施例中,形成保護襯墊層的步驟包括進行多個循環,其各自包含沉積製程以沉積介電材料,以及蝕刻製程以蝕刻沉積的介電材料。
在一些實施例中,沉積製程所沉積的介電材料與層間介電層的材料組成不同。
在一些實施例中,露出源極/汲極構件的上側表面的步驟為蝕刻製程,其在保護襯墊層與層間介電層之間具有蝕刻選擇性,以蝕刻層間介電層而實質上不影響保護襯墊層。
在一些實施例中,蝕刻開口的步驟包括使開口深度比閘極結構的上側表面深。
在一些實施例中,露出源極/汲極構件的上側表面的步驟包括:進行第一蝕刻製程以垂直延伸開口穿過層間介電層,直到露出源極/汲極構件的上側表面;以及進行第二蝕刻製程,以橫向擴展開口的底部。
上述實施例之特徵有利於本技術領域中具有通常知識者理解本發明。本技術領域中具有通常知識者應理解可採用本發明作基礎,設計並變化其他製程與結構以完成上述實施例之相同目的及/或相同優點。本技術領域中具有通常知識者亦應理解,這些等效置換並未脫離本發明精神與範疇,並可在未脫離本發明之精神與範疇的前提下進行改變、替換、或更動。
A-A’,B-B’:剖線
BL:位元線
BLB:互補位元線
N,902,904,906,908,910,912,914,916:實體
PD1,PD2:下拉電晶體
PG1,PG2:穿閘電晶體
PU1,PU2:上拉電晶體
SNB1:互補第一儲存節點
SN1:第一儲存節點
Vcc:電源電壓
Vss:電壓
WL:字元線
90,200:積體電路裝置
110:基板
120:鰭狀結構
122:源極/汲極構件
130:隔離結構
140:閘極結構
150:全繞式閘極裝置
155,290:遮罩層
160:閘極間隔物結構
165:蓋層
170:奈米結購
175:介電內側間隔物
180,570:源極/汲極接點
185,610:層間介電層
250,260:閘極間隔物
280:金屬層
300:微影製程
310:光阻層
320:開口
320A,570A:底部
330:深度
340,470:上側表面
400:沉積與蝕刻循環
420:介電材料
450,500:蝕刻製程
550: 源極/汲極接點形成製程
570B:頂部
580,590:側表面
600:介電層
650:閘極接點
660:源極/汲極通孔
800:靜態隨機存取記憶體單元
900:製作系統
918:網路
1000:方法
1010,1020,1030,1040,1050,1060:步驟
圖1A係本發明多種實施例中,鰭狀場效電晶體形式的積體電路裝置的透視圖。
圖1B係本發明多種實施例中,鰭狀場效電晶體形式的積體電路裝置的平面上視圖。
圖1C係本發明多種實施例中,全繞式閘極裝置形式的積體電路裝置的透視圖。
圖2A至8A係本發明多種實施例中,積體電路裝置在多種製作階段的X剖面的剖視圖。
圖2B至8B係本發明多種實施例中,積體電路裝置在多種製作階段的Y剖面的剖視圖。
圖2C至8C係本發明多種實施例中,積體電路裝置在多種製作階段的平面上視圖。
圖9係本發明多種實施例中,靜態隨機存取記憶體單元的電路圖。
圖10係本發明多種實施例中,製造系統的方塊圖。
圖11係本發明多種實施例中,製作半導體裝置的方法之流程圖。
B-B’:剖線
110:基板
120:鰭狀結構
122:源極/汲極構件
185,610:層間介電層
200:積體電路裝置
420:介電材料
470:上側表面
570:源極/汲極接點
570A:底部
570B:頂部
580,590:側表面
600:介電層
660:源極/汲極通孔
Claims (1)
- 一種半導體裝置,包括: 一或多個主動區結構,各自在垂直方向中垂直地向外凸出一基板,並在一第一水平方向中水平延伸; 一源極/汲極構件,在該垂直方向中位於該或該些主動區結構上; 一源極/汲極接點,在該垂直方向中位於該源極/汲極構件上,其中該源極/汲極接點包括一底部與一頂部;以及 一保護襯墊層,位於該源極/汲極接點的該頂部的側表面上,但不位於該源極/汲極接點的該底部的側表面上。
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US17/186,480 US11626495B2 (en) | 2021-02-26 | 2021-02-26 | Protective liner for source/drain contact to prevent electrical bridging while minimizing resistance |
US17/186,480 | 2021-02-26 |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI827501B (zh) * | 2022-10-06 | 2023-12-21 | 台灣積體電路製造股份有限公司 | 半導體結構及其製造方法 |
Family Cites Families (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6509267B1 (en) | 2001-06-20 | 2003-01-21 | Advanced Micro Devices, Inc. | Method of forming low resistance barrier on low k interconnect with electrolessly plated copper seed layer |
US8324660B2 (en) | 2005-05-17 | 2012-12-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication |
JP2009231497A (ja) | 2008-03-21 | 2009-10-08 | Toshiba Corp | 半導体装置及び半導体装置の製造方法 |
US9245805B2 (en) | 2009-09-24 | 2016-01-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Germanium FinFETs with metal gates and stressors |
US8836035B2 (en) | 2010-03-10 | 2014-09-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and apparatus for reducing gate resistance |
US8962400B2 (en) | 2011-07-07 | 2015-02-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | In-situ doping of arsenic for source and drain epitaxy |
US8841701B2 (en) | 2011-08-30 | 2014-09-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET device having a channel defined in a diamond-like shape semiconductor structure |
US8815712B2 (en) | 2011-12-28 | 2014-08-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for epitaxial re-growth of semiconductor region |
US9236267B2 (en) | 2012-02-09 | 2016-01-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cut-mask patterning process for fin-like field effect transistor (FinFET) device |
US8847293B2 (en) | 2012-03-02 | 2014-09-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Gate structure for semiconductor device |
US8836016B2 (en) | 2012-03-08 | 2014-09-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structures and methods with high mobility and high energy bandgap materials |
US9171929B2 (en) | 2012-04-25 | 2015-10-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained structure of semiconductor device and method of making the strained structure |
US9059292B2 (en) * | 2012-08-02 | 2015-06-16 | International Business Machines Corporation | Source and drain doping profile control employing carbon-doped semiconductor material |
US8928090B2 (en) * | 2012-10-31 | 2015-01-06 | International Business Machines Corporation | Self-aligned contact structure for replacement metal gate |
US9093530B2 (en) | 2012-12-28 | 2015-07-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin structure of FinFET |
US8853025B2 (en) | 2013-02-08 | 2014-10-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET/tri-gate channel doping for multiple threshold voltage tuning |
US9093514B2 (en) | 2013-03-06 | 2015-07-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Strained and uniform doping technique for FINFETs |
US9214555B2 (en) | 2013-03-12 | 2015-12-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Barrier layer for FinFET channels |
US8963258B2 (en) | 2013-03-13 | 2015-02-24 | Taiwan Semiconductor Manufacturing Company | FinFET with bottom SiGe layer in source/drain |
US8796666B1 (en) | 2013-04-26 | 2014-08-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | MOS devices with strain buffer layer and methods of forming the same |
US9136106B2 (en) | 2013-12-19 | 2015-09-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for integrated circuit patterning |
US9548303B2 (en) | 2014-03-13 | 2017-01-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET devices with unique fin shape and the fabrication thereof |
US9620601B2 (en) | 2014-07-01 | 2017-04-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Contact structures and methods of forming the same |
US9520482B1 (en) | 2015-11-13 | 2016-12-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of cutting metal gate |
US10153203B2 (en) | 2016-11-29 | 2018-12-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods for forming metal layers in openings and apparatus for forming same |
US10083863B1 (en) | 2017-05-30 | 2018-09-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Contact structure for semiconductor device |
US10164048B1 (en) | 2017-11-29 | 2018-12-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming source/drain contacts |
US10651292B2 (en) | 2018-02-19 | 2020-05-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Dual metal via for contact resistance reduction |
US10937876B2 (en) | 2018-10-26 | 2021-03-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Source/drain feature to contact interfaces |
KR20220028703A (ko) * | 2020-08-31 | 2022-03-08 | 삼성전자주식회사 | 반도체 장치 |
KR20220053879A (ko) * | 2020-10-23 | 2022-05-02 | 삼성전자주식회사 | 반도체 장치 |
-
2021
- 2021-02-26 US US17/186,480 patent/US11626495B2/en active Active
- 2021-09-10 TW TW110133734A patent/TW202234637A/zh unknown
-
2022
- 2022-01-20 CN CN202210066604.0A patent/CN114792657A/zh active Pending
-
2023
- 2023-04-10 US US18/297,892 patent/US20230246083A1/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI827501B (zh) * | 2022-10-06 | 2023-12-21 | 台灣積體電路製造股份有限公司 | 半導體結構及其製造方法 |
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