TW202232679A - 封裝、封裝元件及其製作方法 - Google Patents
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- TW202232679A TW202232679A TW110127040A TW110127040A TW202232679A TW 202232679 A TW202232679 A TW 202232679A TW 110127040 A TW110127040 A TW 110127040A TW 110127040 A TW110127040 A TW 110127040A TW 202232679 A TW202232679 A TW 202232679A
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Abstract
實施例包含封裝以及用於形成封裝的方法,所述封裝包含具有由介電材料製成的基底的中介物。中介物亦可包含在基底上方的重佈線結構,所述重佈線結構包含在包含多次橫向交疊圖案化曝露的圖案化製程中拼接在一起的金屬化圖案。
Description
半導體行業歸因於各種電子組件(例如電晶體、二極體、電阻器、電容器等)的積集度的持續改良而已經歷快速發展。主要地,積集度的此改良源自於最小特徵尺寸的迭代減小,此允許將更多組件整合至給定區域中。
隨著對於縮小的電子元件的需求增長,已出現對於更小且更創造性的半導體晶粒的封裝技術的需求。此等封裝系統的實例為疊層封裝(Package-on-Package;PoP)技術。在PoP元件中,頂部半導體封裝堆疊於底部半導體封裝的頂部上,以提供高積集度及高組件密度。另一實例為基底上晶圓上晶片(Chip-On-Wafer-On-Substrate;CoWoS)結構。在一些實施例中,為形成CoWoS結構,將多個半導體晶片附接至晶圓,並且緊接著執行切割製程以將晶圓分離成多個中介物,其中中介物中的每一者具有與其附接的一或多個半導體晶片。附接有半導體晶片的中介物被稱作晶圓上晶片(Chip-On-Wafer;CoW)結構。接著將CoW結構附接至基底(例如,印刷電路板)以形成CoWoS結構。此等及其他進階封裝技術使得能夠生產具有增強的功能性及小的佔據面積的半導體元件。
以下揭露內容提供用於實施本發明實施例的不同特徵的許多不同實施例或實例。下文描述組件及佈置的特定實例以簡化本揭露當然,此等僅為實例且並不意欲為限制性的。舉例而言,在以下描述中,第一特徵在第二特徵上方或上的形成可包含第一特徵及第二特徵直接接觸地形成的實施例,且亦可包含額外特徵可形成於第一特徵與第二特徵之間使得第一特徵與第二特徵可不直接接觸的實施例。另外,本揭露可在各種實例中重複附圖標記及/或字母。此重複出於簡單及明晰的目的,且其本身並不指示所論述的各種實施例及/或配置之間的關係。
此外,為易於描述,可使用諸如「在...下面」、「在...下方」、「下部」、「在...上方」、「上部」以及類似者的空間相對術語,以描述如諸圖中所示出的一個部件或特徵相對於另一(些)部件或特徵的關係。除圖式中所描繪的定向之外,空間相對術語亦意欲涵蓋元件在使用或操作中的不同定向。裝置可以其他方式定向(旋轉90度或處於其他定向),且本文中所使用的空間相對描述詞同樣可相應地進行解釋。
根據一些實施例,形成小晶片中介物,其包含充當基底層的介電填充層,而非例如矽層或預先形成的基底核心層。利用介電填充層作為基底層為有成本效益的,且有利地提供相較使用矽基底層或類似者更低的應力集中。小晶片中介物附接有載板基底,所述載板基底可在將小晶片中介物放置於封裝元件中之後移除。小晶片中介物亦可併入重佈線結構,且在一些實施例中,重佈線結構可藉由拼接製程(stitching process)中的多個並排圖案化製程形成,所述拼接製程提供將若干圖案並排組合在重佈線結構的特定層的較大金屬化圖案中的能力。
圖1至圖21示出形成介電中介物的製程的中間步驟的橫截面視圖及俯視圖。介電中介物有利地不利用矽基底,且替代地使用介電基底。因此,介電中介物可以比矽類中介物更有成本效益的方式產生。此外,介電中介物可具有更合乎需要的應力集中效果,藉此減小所得封裝的應力。
在圖1中,提供載板基底110。在一些實施例中,在載板基底110上形成釋放層112(為簡單起見,在其他圖中省略)。其他實施例可省略釋放層112。載板基底110可為玻璃載板基底、陶瓷載板基底或其類似物。載板基底110可為矽類基底,諸如矽塊體。將在後續步驟中諸如藉由分解釋放層112或研磨掉載板基底110來移除載板基底110。載板基底110可為晶圓(諸如圖1中所示出),以使得可同時在載板基底110上形成多個中介物。應理解,儘管圖1中示出對應於中介物區域100A、中介物區域100B以及中介物區域100C的三個位點,但可同時在載板基底110上方使用任何數目的位點。
釋放層112(若使用)可由聚合物類材料形成,所述釋放層112可連同載板基底110一起自將在後續步驟中形成的上覆結構移除。在一些實施例中,釋放層112為在加熱時損失其黏著特性的環氧類熱釋放材料,諸如光-熱轉換(light-to-heat-conversion;LTHC)釋放塗層。在其他實施例中,釋放層112可為在曝露於UV光時損失其黏著特性的紫外線(ultra-violet;UV)膠。釋放層112可以液體形式分配且經固化,可為層壓至載板基底110上的層壓膜,或可為類似物。釋放層112的頂部表面可經調平,且可具有高平坦度。
穿孔125形成於載板基底110上方且延伸遠離載板基底110。作為形成穿孔125的實例,晶種層(未示出)形成於載板基底110上方(例如,釋放層112上或載板基底110正上方)。在一些實施例中,晶種層為金屬層,其可為單層或包括由不同材料形成的多個子層的複合層。在一特定實施例中,晶種層包括鈦層及鈦層上方的銅層。可使用例如PVD或類似製程來形成晶種層。在晶種層上形成且圖案化光阻。光阻可藉由旋塗或類似製程形成,且可曝露於光以進行圖案化。光阻的圖案對應於導通孔。圖案化形成穿過光阻的開口以曝露出晶種層。在光阻的開口中及晶種層的曝露部分上形成導電材料。導電材料可藉由鍍覆,諸如電鍍或無電鍍覆或類似製程形成。導電材料可包括金屬,如銅、鈦、鎢、鋁或類似物。移除光阻及晶種層上未形成導電材料的部分。可藉由可接受的灰化或剝離製程,諸如使用氧電漿或類似製程來移除光阻。一旦移除光阻,則諸如藉由使用可接受的蝕刻製程(諸如藉由濕式蝕刻或乾式蝕刻)來移除晶種層的曝露部分。晶種層的剩餘部分及導電材料形成穿孔125。
在圖2中,在穿孔125上方及周圍形成介電填充物120。在一些實施例中,介電填充物120可包括如二氧化矽、氮化矽或類似物的非聚合物,諸如使用任何適合的製程沉積的另一氧化物或氮化物或另一絕緣材料。舉例而言,介電填充物120可藉由CVD、PECVD或ALD沉積製程、FCVD或旋塗玻璃製程形成。然而,可利用任何適合的材料及任何適合的沉積製程。介電填充物120可形成為具有例如約1微米與約30微米之間厚的厚度。在完成的小晶片中介物中,當移除載板基底110時,介電填充物120將為小晶片中介物中的最厚層。
在圖3中,對介電填充物120執行平坦化製程以曝露出穿孔125。穿孔125及介電填充物120的頂部表面在製程變化內的平坦化製程之後實質上共面。平坦化製程可為例如化學機械研磨(chemical-mechanical polish;CMP)、研磨(grinding)製程或類似製程。在一些實施例中,例如,若已曝露出穿孔125,則可省略平坦化。穿孔125可用於將訊號自介電填充物120的一側路由至介電填充物120的相對側。由於穿孔125穿過介電填充物120,因此其可被稱作介電穿孔或TDV。
仍參考圖3,在另一實施例中,可在形成穿孔125之前沉積介電填充物120。在此實施例中,一旦已放置介電填充物120,則微影遮罩及蝕刻製程可用於形成穿過介電填充物120的開口以曝露出下伏釋放層112或載板基底110。一旦已形成開口,則可用導電材料填充開口,在一些實施例中,所述導電材料包含襯裡層及/或障壁層。接著,可用導電材料填充開口的剩餘部分。導電材料可包含上文針對穿孔125所論述的彼等中的任一者。可藉由將銅電鍍至晶種層上,填充且過度填充開口來形成導電材料。一旦開口已經填充,即可經由諸如化學機械研磨(CMP)的平坦化製程來移除開口外部的多餘襯裡、障壁層、晶種層以及導電材料,但可使用任何適合的移除製程。在此類實施例中,穿孔125可具有頂部較底部更寬的錐形形狀(更接近於載板基底110)。
圖4示出根據一些實施例的圖3的結構的實例俯視圖。如圖4中所示出,介電填充物120亦示出為穿孔125的頂部。儘管穿孔125經示出為圓形的,但其亦可為其他形狀。舉例而言,其可為圓形、正方形、矩形、橢圓形、長橢圓形、具有圓形端部的矩形、類似形狀以及其組合。
圖5至圖21示出在穿孔125上方形成重佈線結構128(參見圖19)的製程的中間步驟的各種視圖。簡要地參考圖20,重佈線結構128包含介電層130及介電層140、視情況選用的金屬化圖案132、金屬化圖案138以及金屬化圖案148以及通孔136及通孔146。
在圖5中,可在介電填充物120上形成視情況選用的金屬化圖案132。作為形成金屬化圖案132的一實例,在介電填充物120上方形成晶種層。在一些實施例中,晶種層為金屬層,其可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中,晶種層包括鈦層及鈦層上方的銅層。可使用例如物理氣相沉積(physical vapor deposition;PVD)或類似製程來形成晶種層。接著在晶種層上形成且圖案化光阻(未示出)。光阻可藉由旋塗或類似製程形成,且可曝露於光以進行圖案化。光阻的圖案對應於金屬化圖案132。圖案化形成穿過光阻的開口以曝露出晶種層。在光阻的開口中及晶種層的曝露部分上形成導電材料。導電材料可藉由鍍覆,諸如電鍍或無電鍍覆或類似製程形成。導電材料可包括金屬,如銅、鈦、鎢、鋁或類似物。接著,移除光阻及晶種層上未形成導電材料的部分。可藉由可接受的灰化或剝離製程,諸如使用氧電漿或類似製程來移除光阻。一旦移除光阻,則諸如藉由使用可接受的蝕刻製程(諸如藉由濕式蝕刻或乾式蝕刻)來移除晶種層的曝露部分。晶種層的剩餘部分及導電材料形成金屬化圖案132。
可在介電填充物120上及視情況選用的金屬化圖案132上方形成介電層130。介電層130的底部表面可與介電填充物120的頂部表面、視情況選用的金屬化圖案132的上部表面以及穿孔125的上部表面接觸。在一些實施例中,介電層130由聚合物形成,聚合物可為可使用微影罩幕圖案化的感光性材料,諸如PBO、聚醯亞胺、BCB或類似物。在其他實施例中,介電層130由氮化物,諸如氮化矽;氧化物,諸如氧化矽、PSG、BSG、BPSG或類似物形成。介電層130可藉由旋塗、層壓、CVD、類似製程或其組合形成。
接著,將介電層130圖案化以形成曝露出視情況選用的金屬化圖案132的部分及/或穿孔125的通孔開口131。圖案化可藉由可接受的製程形成,諸如在介電層130為感光性材料時藉由將介電層130曝露於光或藉由使用例如非等向性蝕刻來進行蝕刻。若介電層130為感光性材料,則介電層130可在曝光之後顯影。
在圖6中,在形成通孔開口131之後,可將介電層130圖案化以在其中形成開口156(圖8),所述開口156中將形成金屬化圖案。在形成開口156的實例中,在介電層130上方以及通孔開口131中形成光罩150。光罩150在曝光製程162中曝露,所述曝光製程162使光穿過光罩幕160,諸如倍縮光罩(reticle)。在示出的實施例中,光罩150的曝露部分產生曝光區域152,經由光罩150的顯影製程移除所述曝光區域152。其他實施例可使用導致保持光罩的曝光區域152的負型光罩150。
在圖7中,在已經由中介物區域100A、中介物區域100B以及中介物區域100C中的每一者中的曝光製程162曝露出光罩150之後,對光罩150進行顯影且移除曝光區域152,從而在光罩150中留下開口154。開口154可曝露出開口131及下伏的視情況選用的金屬化圖案132及/或穿孔125。
在圖8中,光罩150用作蝕刻罩幕,且經由適合的蝕刻製程將開口154轉移至下伏介電層130以在介電層130中形成開口156。
在圖9中,藉由可接受的灰化或剝離製程,諸如藉由使用氧電漿或類似製程來移除光罩150。接著,將導電材料134沉積至開口156中以形成金屬化圖案138(圖10)。作為形成金屬化圖案138的實例,可在介電層130上方及開口156中以及開口131中形成視情況選用的障壁層。視情況選用的障壁層可包含鈦、氮化鈦、鉭、氮化鉭或類似物或其組合,且可使用任何適合的方法來形成,所述方法包含藉由PVD、CVD或類似製程。視情況選用的障壁層可對填塞開口131及開口156,且可覆蓋介電層130的上部表面。接著,可在介電層130上方及開口156中以及開口131中形成晶種層。在一些實施例中,晶種層為金屬層,其可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中,晶種層包括鈦層及鈦層上方的銅層。可使用例如物理氣相沉積(PVD)或類似製程來形成晶種層。接著,在開口131中及開口156中以及介電層130上方形成導電材料134。導電材料134可藉由任何適合的製程,諸如藉由PVD、CVD、鍍覆(諸如電鍍或無電鍍覆)或類似製程而形成。導電材料134可包括金屬,如銅、鈦、鎢、鋁或類似物。
在圖10中,將導電材料134平坦化以形成金屬化圖案138。在平坦化製程中,移除導電材料134的多餘材料,且導電材料的上部表面變得與介電層130的上部表面齊平。在介電層130分隔導電材料134的各部分時,導電圖案138顯現。平坦化製程可包含任何適合的製程,諸如化學機械研磨(CMP)、回蝕製程、類似製程或其組合。
圖11示出根據一些實施例的圖10的結構的俯視圖。圖11示出金屬化圖案138、通孔136以及介電層130。應理解,圖11僅出於說明的目的且並不意欲為限制性的。金屬化圖案138可主要水平地、豎直地或水平與豎直之間的混合(如所繪示)延伸。通孔136的尺寸可等同於、小於或大於金屬化圖案138的寬度w1。金屬化圖案138的寬度w1可在0.05微米與5微米之間。金屬化圖案138的間距p1可在0.1微米與10微米之間。在一些實施例中,寬度w1可與間距p1相同。
圖12至圖19示出跨多個封裝區域(諸如跨第一中介物區域100A、第二中介物區域100B以及第三中介物區域100C)使用拼接製程形成單個金屬化圖案。因此,超小晶片中介物100'可包含多個中介物區域。在此類實施例中,此等亦可被稱為圖案化區域或中介物/圖案化區域。將多個中介物區域或圖案化區域拼接在一起或合併以形成超小晶片中介物100'提供形成具有比可用於曝露出光罩的光罩幕更大的佔據面積的金屬化物的能力。舉例而言,多個光罩幕圖案可經拼接在一起以形成作為金屬化圖案的部分的導電線,所述金屬化圖案自第一中介物/圖案化區域100A延伸至第二中介物/圖案化區域100B。拼接製程提供金屬化圖案的形成,所述金屬化圖案大於用於形成其的光罩幕。光罩幕的尺寸是藉由曝光工具(例如,紫外光或極紫外光源)來判定。拼接製程將多個曝光合併成單個連續性圖案,而不必修改曝光工具來容納較大光罩幕。
在圖12中,在形成通孔開口131(參見圖5)之後,可將介電層130圖案化以在其中形成開口156(圖16),所述開口156將用於形成金屬化圖案。圖12至圖15示出拼接製程的實例使用。在介電層130上方以及通孔開口131中形成光罩150。光罩150在曝光製程162中曝露,所述曝光製程162使光穿過光罩幕160A,諸如倍縮光罩。在所示出實例中,光罩150的曝露部分產生曝光區域152A,隨後經由光罩150的顯影製程移除所述曝光區域152A。其他實施例可使用導致保持光罩150的曝光區域152A的負型光罩150。值得注意的是,光罩150僅曝露於第一中介物區域100A中。
在圖13中,光罩150在另一曝光製程162中曝露出,所述曝光製程162使光穿過光罩幕160B。光罩幕160B可為與光罩幕160A相同的光罩幕或可為不同光罩幕。在所示出實例中,光罩150的曝露部分產生雙重曝光區域152B及曝光區域152C,隨後經由光罩150的顯影製程移除所述雙重曝光區域152B及曝光區域152C。其他實施例可使用導致保持光罩150的雙重曝光區域152B及曝光區域152C的負型光罩150。雙重曝光區域152B已在曝光製程162中曝露兩次。其第一次經由光罩幕160A曝露且第二次經由光罩幕160B曝露。兩次曝光之間的交疊區域為雙重曝光區域152B。
在圖14中,光罩150在另一曝光製程162中曝露,所述曝光製程162使光穿過光罩幕160C。光罩幕160C可為與光罩幕160A及/或光罩幕160B相同的光罩幕或可為不同光罩幕。在所示出實例中,光罩150的曝露部分產生雙重曝光區域152D及曝光區域152E,隨後經由光罩150的顯影製程移除所述雙重曝光區域152D及曝光區域152E。其他實施例可使用導致保持光罩150的雙重曝光區域152D及曝光區域152E的負型光罩150。雙重曝光區域152D已在曝光製程162中曝光兩次。其第一次經由光罩幕160B曝光且第二次經由光罩幕160C曝光。兩次曝光之間的交疊區域為雙重曝光區域152D。
在圖15中,在已經由中介物區域100A、中介物區域100B以及中介物區域100C中的每一者中的曝光製程162曝露光罩150之後,對光罩150進行顯影且移除曝光區域152A、曝光區域152C以及曝光區域152E以及雙重曝光區域152B及雙重曝光區域152D,從而在光罩150中留下開口154。開口154可曝露出開口131及下伏的視情況選用的金屬化圖案132及/或穿孔125。
在圖16中,光罩150用作蝕刻罩幕,且經由適合的蝕刻製程將開口154轉移至下伏介電層130以在介電層130中形成開口156。
在圖17中,藉由可接受的灰化或剝離製程,諸如藉由使用氧電漿或類似製程來移除光罩150。接著,將導電材料沉積至開口156中以形成金屬化圖案138及交疊區域138o。此等可使用與上文關於圖9及圖10所論述的製程及材料類似的製程及材料來形成。值得注意地,金屬化圖案138的交疊區域138o可在封裝區域之間(例如,中介物區域100A與中介物區域100B之間)橋接以形成超小晶片中介物100'。
圖18示出根據一些實施例的圖17的結構的俯視圖。圖18示出金屬化圖案138、通孔136以及介電層130。圖18亦示出交疊區域138o。應理解,圖18僅出於說明的目的且並不意欲為限制性的。金屬化圖案138可主要水平地、豎直地或水平與豎直之間的混合(如所繪示)延伸。通孔136的尺寸可等同於、小於或大於金屬化圖案138的線的寬度w1。金屬化圖案138的寬度w1可在0.05微米與5微米之間。金屬化圖案138的間距p1可在0.05微米與5微米之間。在一些實施例中,寬度w1可與間距p1相同。交疊區域138o中的線的寬度w2的尺寸可與寬度w1相同或略微大於寬度w1。寬度w2可大於寬度w1。
圖19A至圖19D示出在使用拼接製程時圖17及圖18的交疊區域138o的不同實施例的俯視圖。圖19A至圖19D的實施例中的每一者可存在於單個金屬化圖案138中。在圖19A中,來自第一圖案化製程的金屬化圖案138a的線寬d1可具有來自第二圖案化製程的金屬化圖案138b的相同線寬d2。交疊區域138o可具有比線寬d2及/或線寬d1大約5%至50%的線寬d3。線寬d3的此增加可由雙重曝光光罩(例如,圖12的光罩150)的交疊區域引起,所述交疊區域用於圖案化下伏介電層130。與將通常藉由光罩幕曝露相比,雙重曝光可影響光罩的更大寬度。舉例而言,曝光區域中的光滲出可影響周圍區域。在其他實施例中,交疊區域138o可具有比線寬d2及/或線寬d1小約10%至30%的線寬d3。線寬d3的此減小可由雙重曝光交疊區域中的負型光罩引起。在負型光罩中,光罩中的保留區域經曝露,同時保護經移除區域。與將通常藉由光罩幕曝露相比,雙重曝光可影響光罩的更大部分。舉例而言,曝光區域中的光滲出可影響周圍區域,包含至交疊區域中。
在圖19B中,來自第一圖案化製程的金屬化圖案138a的線寬d1可具有來自第二圖案化製程的金屬化圖案138b的相同線寬d2。交疊區域138o可具有與線寬d1及/或線寬d2約相同寬度的線寬d3。儘管在圖19A中光罩的雙重曝光出引起擴寬,但在圖19B中,雙重曝光可不引起擴寬。舉例而言,可控制交疊區域的曝露強度以防止擴寬或所使用光罩幕可經調節以在交疊區域中具有較窄曝露以補償雙重曝光。
在圖19C中,來自第一圖案化製程的金屬化圖案138a的線寬d1可具有來自第二圖案化製程的金屬化圖案138b的相同線寬d2。交疊區域138o可具有線寬d3,其至多比線寬d2及/或線寬d3寬約100%。由距離d4表示的偏移展現至多約50%線寬d1及/或線寬d2(無論哪個較小)的輕微圖案未對準。當線寬d1等於線寬d2時,由距離d5表示的對應偏移等於距離d4。
在圖19D中,來自第一圖案化製程的金屬化圖案138a的線寬d1可小於來自第二圖案化製程的金屬化圖案138b的線寬d2。交疊區域138o可具有與線寬d1及/或線寬d2中的更寬者約相同的線寬d3。金屬化圖案138a與金屬化圖案138b之間產生偏移d4。亦可組合圖19C及圖19D的實施例。在此實施例中,圖19C中的對應寬度d5不等於寬度d4。
在圖20中,形成介電層130、通孔136以及金屬化圖案138的製程可視需要重複多次以包含重佈線結構128的額外層。舉例而言,如所示出,可使用與用於沉積介電層130的材料及製程類似的材料及製程來沉積介電層140。接著可使用與例如關於圖5至圖8或圖12至圖16針對介電層130所描述的製程及材料類似的製程及材料來圖案化介電層140。接著,可使用與上文關於通孔136及金屬化圖案138所論述的製程及材料類似的製程及材料來沉積通孔146及金屬化圖案148。
應理解,可使用其他適合的製程來形成重佈線結構128。舉例而言,上文所描述的製程符合雙鑲嵌製程,其中溝渠及通孔開口兩者形成於介電層130中,其中通孔開口在溝渠之下且連接至溝渠。接著將導電材料填充至溝渠及通孔開口中以分別形成金屬線(例如,金屬化圖案138)及通孔(例如,通孔136)。亦可使用單鑲嵌製程,其中首先在介電層(例如,介電層130)中形成溝渠,接著用導電材料填充溝渠。接著執行諸如CMP製程的平坦化製程,以移除高於介電層的頂部表面的導電材料的過量部分,從而在溝渠中留下金屬線。接著,以與金屬線的形成類似的方式單獨地形成通孔。另外其他適合的製程可用於形成重佈線結構128。所有此類製程可利用拼接製程(諸如上文關於圖12至圖16所描述)以圖案化大於用於光圖案化的光罩幕的區域。
仍參考圖20,絕緣層170可經沉積於重佈線結構128及經由絕緣層170形成的導電連接件172上方,以接觸重佈線結構128的頂部金屬特徵。絕緣層170可以是可使用微影罩幕圖案化的任何適合的絕緣材料,諸如PBO、聚醯亞胺、BCB或類似物。在其他實施例中,絕緣層170由氮化物,諸如氮化矽;氧化物,諸如氧化矽、PSG、BSG、BPSG或類似物形成。絕緣層170可藉由旋塗、層壓、CVD、類似物或其組合形成。接著,絕緣層170經圖案化以形成曝露出重佈線結構128的最上部金屬化圖案(例如,金屬化圖案148)的部分的開口。圖案化可藉由可接受的製程形成,諸如藉由在絕緣層170為感光性材料時使絕緣層170曝露於光或藉由使用例如非等向性蝕刻來進行蝕刻。若絕緣層170為感光性材料,則絕緣層170可在曝光之後顯影。
導電連接件172形成於絕緣層170的開口中。在一些實施例中,導電連接件172可包含視情況選用的凸塊下金屬(under bump metallurgies;UBM),所述凸塊下金屬延伸穿過絕緣層170以物理地且電性地耦接金屬化圖案148。UBM可由與金屬化圖案148相同的材料形成。導電連接件172可包含球柵陣列封裝(ball grid array;BGA)連接件、焊料球、金屬柱、受控塌陷晶片連接(controlled collapse chip connection;C4)凸塊、微型凸塊、無電鍍鎳無電鈀浸鍍金技術(electroless nickel-electroless palladium-immersion gold technique;ENEPIG)形成的凸塊或類似物。導電連接件172可包含導電材料,諸如焊料、銅、鋁、金、鎳、銀、鈀、錫、類似物或其組合。導電連接件172可藉由濺鍍、印刷、電鍍、無電鍍覆、CVD或類似製程形成。導電連接件172可無焊料且具有實質上豎直的側壁。在一些實施例中,導電連接件172包含金屬柱及形成於金屬柱的頂部上的金屬頂蓋層。金屬頂蓋層可包含鎳、錫、錫鉛、金、銀、鈀、銦、鎳鈀金、鎳金、類似物或其組合,且可由鍍覆製程形成。
圖21示出圖20的結構的俯視圖。導電連接件172經示出為設置於規則圖案中,然而,應理解導電連接件172可經無規地設置或設置於不同圖案中。圖20及圖21中所示出的所得結構可包含個別中介物區域100A、中介物區域100B、中介物區域100C等(諸如關於圖10所示出),及/或可包含由兩個或大於兩個圖案化區域(諸如關於圖17所示出)製成的超小晶片中介物100'。
在圖22中,圖20的結構可經單體化成小晶片,諸如小晶片中介物100,其可對應於中介物區域100A、中介物區域100B或中介物區域100C(等等)或超小晶片中介物100'(對應於一或多個拼接中介物/圖案區域100A、100B及/或100C(等等))。在一些實施例中,形成小晶片中介物100可包含使用單體化製程,包含沿切割道區域(例如,第一中介物區域100A與第二中介物區域100B之間)鋸割。鋸割將第一中介物區域100A自第二中介物區域100B單體化。在其他實施例中,鋸割可介於超小晶片中介物100'與鄰接超封裝100'之間,其由上文所描述的拼接製程產生。所得小晶片中介物100經提供作為實例,且可來自第一中介物區域100A,或可在上文所論述的超小晶片中介物100'中包含第一中介物/圖案區域100A、第二中介物/圖案區域100B以及第三中介物/圖案區域100C中的每一者。然而,應理解,所示出的超小晶片中介物100'僅為實例,且任何數目的中介物/圖案區域可在上文所描述的拼接製程中組合成超小晶片中介物100',彼此水平地及/或豎直地鄰接。
在圖23中,將小晶片中介物100安裝至載板基底202。小晶片中介物100各自對應於圖22的小晶片中介物100。儘管示出兩個小晶片中介物100,但可放置更少或更多額外小晶片中介物100。此外,小晶片中介物100可為相同或可為不同的。舉例而言,所示出的小晶片中介物100中的一者可對應於封裝區域100B,而所示出的小晶片中介物100中的另一者可對應於超小晶片中介物100'等。取放製程可用於拾取小晶片中介物100且將其定位於載板基底202上。可在載板基底202上形成釋放層,所述釋放層用作黏著劑但可易於在後續步驟中移除以移除載板基底202。載板基底202可為玻璃載板基底、陶瓷載板基底或類似物。載板基底202可為晶圓,使得多個封裝可同時形成於載板基底202上。
釋放層可由聚合物類材料形成,可將所述釋放層連同載板基底202一起自將在後續步驟中形成的上覆結構移除。在一些實施例中,釋放層為在加熱時損失其黏著特性的環氧類熱釋放材料,諸如光-熱轉換(LTHC)釋放塗層。在其他實施例中,釋放層可為在曝露於UV光時損失其黏著特性的紫外線(UV)膠。釋放層可以液體形式分配且經固化,可為層壓至載板基底上的層壓膜,或可為類似物。釋放層的頂部表面可經調平,且可具有高平坦度。
圖23中亦繪示視情況選用的穿孔210。穿孔210可在放置小晶片中介物100之前或之後形成。穿孔210形成於載板基底202上且在垂直於載板基底202的主表面的豎直方向上延伸遠離載板基底202。作為形成穿孔210的實例,可在載板基底202上方形成晶種層(未示出)。在一些實施例中,晶種層為金屬層,其可為單層或包括由不同材料形成的多個子層的複合層。在一特定實施例中,晶種層包括鈦層及鈦層上方的銅層。可使用例如PVD或類似製程來形成晶種層。接著在晶種層上形成且圖案化光阻。光阻可藉由旋塗或類似製程形成,且可曝露於光以進行圖案化。光阻的圖案對應於導通孔。圖案化形成穿過光阻的開口以曝露出晶種層。在光阻的開口中及晶種層的曝露部分上形成導電材料。導電材料可藉由鍍覆,諸如電鍍或無電鍍覆或類似製程形成。導電材料可包括金屬,如銅、鈦、鎢、鋁或類似物。移除光阻及晶種層上未形成導電材料的部分。可藉由可接受的灰化或剝離製程,諸如使用氧電漿或類似製程來移除光阻。一旦移除光阻,則諸如藉由使用可接受的蝕刻製程(諸如藉由濕式蝕刻或乾式蝕刻)來移除晶種層的曝露部分。晶種層的剩餘部分及導電材料形成穿孔210。
在圖24中,可在小晶片中介物100及穿孔210上方以及小晶片中介物100與穿孔210之間沉積包封體214。在形成之後,包封體214包封穿孔210及小晶片中介物100。包封體214可為模製化合物、環氧樹脂或類似物。包封體214可藉由壓縮模製、轉移模製或類似製程施加,且可形成於載板基底202上方以使得穿孔210及/或小晶片中介物100經掩埋或覆蓋。包封體214進一步形成於小晶片中介物100之間及小晶片中介物100與穿孔210之間的間隙區中。包封體214可以液體或半液體形式施加且接著隨後經固化。
在圖25中,對包封體214執行平坦化製程以曝露出穿孔210及導電連接件172。平坦化製程亦可移除穿孔210及導電連接件172的材料直至曝露出導電連接件172及穿孔210為止。穿孔210、導電連接件172以及包封體214的頂部表面在製程變化內的平坦化製程之後實質上共面。在一些實施例中,包封體214可繼續環繞導電連接件172,而在其他實施例中,導電連接件172可經調平以具有與絕緣層170的上部表面齊平的上部表面,絕緣層170中的一些亦可藉由平坦化製程移除。平坦化製程可為例如化學機械研磨(CMP)、研磨製程或類似製程。在一些實施例中,例如若已曝露出穿孔210及/或導電連接件172,則可省略平坦化。
在圖26中,在包封體214、穿孔210以及小晶片中介物100上方形成前側重佈線結構228。前側重佈線結構228包含介電層228-d及金屬化圖案228-m。可使用與上文所描述的重佈線結構128類似的製程及材料來形成前側重佈線結構228,包含使用視情況選用的拼接製程來執行拼接在一起的多個圖案化步驟,如上文所描述。
可在重佈線結構228上方沉積包封體230。在一些實施例中,諸如圖26中所示出,重佈線結構228可具有比載板基底202的橫向範圍更小的橫向範圍。在此類實施例中,包封體可在重佈線結構228的側壁上。在其他實施例中,重佈線結構228可延伸至載板基底202的橫向範圍。可使用與上文關於包封體214所論述的製程及材料類似的製程及材料來形成包封體230。包封體230的材料組成可與包封體214的材料組成相同或不同。在一些實施例中,包封體230可由介電材料,諸如氧化矽、氮化矽、氮氧化矽、碳氧化矽、類似物或其組合製成,且可藉由旋塗或類似製程沉積。在一些實施例中,可首先形成包封體230,接著可在包封體230中製得開口,重佈線結構228形成於開口中,且包封體230的額外層形成於重佈線結構228上方。
接著可在包封體230中形成開口以曝露出重佈線結構228的頂部金屬化圖案228-m。導電連接件235可形成於頂部金屬化圖案228-m上的開口中。可使用與上文關於導電連接件172所描述的製程及材料類似的製程及材料來形成導電連接件235,包含視情況選用的凸塊下金屬(UBM)。在導電連接件235不包含焊料凸塊的實施例中,亦可在導電連接件235上形成焊料凸塊237。焊料凸塊237可藉由任何適合的製程,諸如藉由焊料印刷或鍍覆,接著以回焊製程來形成。
在圖27中,可藉由焊料凸塊237將元件250安裝至導電連接件172。元件250可包含元件250A、元件250B以及元件250C。元件250可包含積體電路晶粒、積體電路上系統(system on integrated circuit;SOIC)元件、小晶片元件等等。舉例而言,元件250可包含邏輯元件(例如中央處理單元(central processing unit;CPU)、圖形處理單元(graphics processing unit;GPU)、系統晶片(system-on-a-chip;SoC)、應用程序處理器(application processor;AP)、微控制器等)、記憶體元件(例如動態隨機存取記憶體(dynamic random access memory;DRAM)晶粒、靜態隨機存取記憶體(static random access memory;SRAM)晶粒等)、功率管理元件(例如功率管理積體電路(power management integrated circuit;PMIC)晶粒)、射頻(radio frequency;RF)元件、感測器元件、微機電系統(micro-electro-mechanical-system)元件、訊號處理元件(例如數位訊號處理(digital signal processing;DSP)晶粒)、前端元件(例如類比前端(analog front-end;AFE)晶粒)、類似物或其組合。
元件250(例如,元件250A、元件250B以及元件250C)中的每一者可屬於相同類型或不同類型,例如,屬於上文所列的彼等類型的元件。元件250可包含前側連接件255。取放製程可用於拾取且定位元件250以將前側連接件255對準至導電連接件235,且接合製程可例如藉由回焊焊料凸塊237以將元件250物理地且電性地耦接至導電連接件235而發生。
在將元件250安裝至導電連接件235之後,可在元件250下方、元件250與重佈線結構228之間以及圍繞導電連接件235與前側連接件255之間的接合點沉積視情況選用的底部填充物260。在一些實施例中,底部填充物260可在所安裝元件250之間向上延伸,甚至延伸至所安裝元件250的上部表面。底部填充物260可減小應力且保護由焊料凸塊237的回焊產生的接合點。底部填充物可在附接元件250之後由毛細流動製程形成,或可在附接元件250之前由適合的沉積方法形成。
在沉積視情況選用的底部填充物之後,可在重佈線結構228上方以及元件250之間沉積包封體265。可使用與上文關於圖24所論述的用於沉積包封體214的製程及材料類似的製程及材料來沉積包封體265。具體而言,可將包封體265沉積至完全覆蓋元件250的厚度,此後可使用諸如CMP製程的平坦化製程來使包封體265的上部表面與元件250的上部表面齊平。在一些實施例中,可藉由平坦化製程來薄化元件250。在一些實施例中,可省略底部填充物260,且包封體265可充當底部填充物260及包封體265兩者。
在圖28中,載板基底202可藉由剝離製程移除且結構翻轉且附接至安裝平台204。安裝平台204可為類似於載板基底202、條帶、安裝框架或類似物的另一載板基底。在實例剝離製程中,剝離包含將諸如雷射光或UV光的光投影於釋放層上,使得釋放層在光的熱量下分解且可移除載板基底202。接著,翻轉結構且將其放置於載帶(未示出)上。若不使用釋放層,則結構可經翻轉且放置於安裝平台204上,且接著可藉由向上壓力或藉由在研磨製程中研磨載板基底202來機械地移除載板基底202。載板基底202的移除曝露出小晶片中介物100的載板基底110。
在圖29中,藉由移除小晶片中介物100的載板基底110來修改小晶片中介物100。可經由調平製程移除小晶片中介物100的載板基底110,所述調平製程移除載板基底110且使穿孔210的(現)上部表面與包封體214的上部表面及小晶片中介物100齊平。調平製程可包含平坦化製程,諸如研磨製程、CMP製程、蝕刻製程、類似製程或其組合。在一些實施例中,可在介電填充物120與載板基底110之間使用釋放層112。在此類實施例中,釋放層104可用於例如藉由執行包封體214及穿孔210的回蝕直至曝露出載板基底110來更輕易地釋放載板基底110。接著,可藉由將光(諸如雷射光或UV光)投影於釋放層112上,使得釋放層112在光的熱量下分解且可移除載板基底110來移除載板基底110。在以此方式移除載板基底110之後,CMP製程仍可用於使包封體214、穿孔210、介電填充物120以及穿孔125的上部表面齊平。在移除載板基底110之後,小晶片中介物100的最厚層為介電填充物120,其充當小晶片中介物100的基底。在一些實施例中,小晶片中介物100的一個主表面可包括介電填充物120且小晶片中介物100的另一主表面可包括重佈線結構128。
在圖30中,可在小晶片中介物100上方形成視情況選用的重佈線結構278。可使用與上文關於圖26的重佈線結構228所論述的製程及材料類似的製程及材料來形成重佈線結構278。可在重佈線結構278上方及/或周圍沉積包封體280。可使用與上文關於圖26的包封體230所論述的製程及材料類似的製程及材料來形成包封體280。接著可在包封體280中形成開口以曝露出重佈線結構278的頂部金屬化圖案。可在重佈線結構278的頂部金屬化圖案上的開口中形成導電連接件285。可使用與上文關於導電連接件172所描述的製程及材料類似的製程及材料來形成導電連接件285,包含視情況選用的凸塊下金屬(UBM)。在導電連接件285不包含焊料凸塊的實施例中,亦可在導電連接件285上形成焊料凸塊287。焊料凸塊287可藉由任何適合的製程,諸如藉由焊料印刷或鍍覆,接著以回焊製程來形成。
在圖31中,可移除安裝平台204且結構翻轉。完成的結構可為封裝元件300,包含多個元件250及一或多個小晶片中介物100,所述一或多個小晶片中介物有助於將訊號自元件250重新分佈至導電連接件285/自導電連接件285重新分佈至元件250。視情況選用的拼接製程可用於形成包含金屬化圖案的超封裝,所述金屬化圖案延伸超出用於光圖案化的光罩幕(例如,倍縮光罩)的橫向邊界。
圖32示出根據另一實施例的封裝元件300。在圖32中,省略穿孔210。在此類實施例中,可省略形成穿孔210的製程,且可形成橫向地環繞小晶片中介物100的包封體214(參見圖24)。
圖33示出根據另一實施例的封裝元件300。在圖33中,可省略小晶片中介物100內的穿孔125(參見圖2)。在此類實施例中,可省略形成穿孔125的製程(參見圖1及其隨附描述),且可在載板基底110上方沉積介電填充物120。
圖34示出根據另一實施例的封裝元件300。在圖34中,可省略重佈線結構278。在此類實施例中,可省略形成重佈線結構278(參見圖30及其隨附描述)的製程,且可在穿孔125、穿孔210、包封體214以及介電填充物120正上方形成包封體280。
圖31至圖34中所示出的封裝元件300中的每一者利用缺乏矽基底(諸如,載板基底110)的小晶片中介物100。替代地,中介物100的作用「基底」為亦可具有視情況選用的穿孔125的介電填充物120。由於小晶片中介物100不具有矽基底,因此小晶片中介物100的應力集中低於其他中介物技術。舉例而言,取決於厚度、結晶定向以及軸方向,矽基底的楊氏係數(Young's modulus)可在約130吉帕與180吉帕之間。相比之下,介電填充物120的楊氏係數可在約50吉帕與約100吉帕之間,諸如在約65吉帕與75吉帕之間。因此,小晶片中介物100展現明顯小於其他中介物技術的應力集中。減小的應力係數亦允許較大佔據面積中介物及上文所描述的拼接製程的成功使用。
圖35至圖45示出根據一些實施例的形成封裝元件的製程中的中間步驟。在所示出製程中,相同參考是指先前所描述的相同特徵。在圖35至圖45中,首先將元件250附接至載板且在後續製程期間附接小晶片中介物100。
在圖35中,提供載板基底302。將元件250(諸如元件250A及元件250B)附接至載板基底302。載板基底302可為與載板基底110類似的材料,且可使用與上文所論述的釋放層112類似的釋放層將元件250附接至載板基底302。
在圖36中,包封體265經沉積於元件250上方且橫向地環繞元件250。在一些實施例中,包封體265可覆蓋元件250的連接件255,諸如圖36中所示出。在一些實施例中,連接件255可不自元件250突出且包封體可設置於元件250的上部表面上,但不橫向地環繞連接件255。可使用與上文關於圖24所描述的包封體214類似的製程及材料來形成包封體265。
在圖37中,使用諸如CMP製程的平坦化製程來使包封體265及連接件255的上部表面齊平。在連接件255經嵌入於元件250中的實施例中,平坦化製程亦可使包封體265與元件250的其餘部分的上部表面齊平。此類實施例中的平坦化製程可使來自包封體265的連接件255曝露。
接著,在圖37中,在包封元件250上方形成重佈線結構228。重佈線結構228用於將訊號路由至元件250的連接件255且自元件250的連接件255路由訊號。重佈線結構228與上文所描述的重佈線結構228類似,且可使用相同製程及材料形成。在一些實施例中,包封體230橫向地包封重佈線結構228。在重佈線結構228上方形成導電連接件235及焊料凸塊237。可使用與上文所描述類似的製程及材料來形成導電連接件235及焊料凸塊237。亦在重佈線結構228上方形成穿孔210。可使用與上文所論述的穿孔210類似的製程及材料來形成穿孔210。然而,應注意,可在金屬化圖案228-m(或形成於金屬化圖案228-m上的凸塊下結構)上沉積穿孔210。舉例而言,穿孔210的沉積可藉由鍍覆製程,諸如藉由電鍍覆或無電鍍覆進行。
在圖38中,藉助於焊料凸塊237將小晶片中介物100附接至導電連接件235。小晶片中介物100可具有出於處置目的而與其附接的載板(諸如,如上文所描述的載板基底110)。應理解,儘管示出了小晶片中介物100中的一者,但可使用任何數目個此類小晶片中介物100。另外,小晶片中介物100可為如上文所論述的小晶片中介物100中的任一者,包含含有藉由拼接製程接合在一起的設置於其中的多個圖案化區域的超小晶片中介物100'。
在圖39中,底部填充物260可視情況藉由小晶片中介物100與重佈線結構228之間的毛細流動製程沉積或注入以環繞且支撐導電連接件235與導電連接件172之間的連接。包封體265沉積於穿孔210及小晶片中介物100上方且橫向地環繞穿孔210及小晶片中介物100。在省略底部填充物260的實施例中,包封體265亦可用作底部填充物。
在圖40中,可執行調平製程以使小晶片中介物100的介電填充物120的上部表面與包封體265及穿孔210齊平。亦藉由移除小晶片中介物的載板基底110來修改小晶片中介物100。舉例而言,可移除載板基底110作為調平製程的一部分或作為分離製程的一部分。調平製程可包含研磨、蝕刻、CMP製程、類似製程或其組合。在一些實施例中,可在介電填充物120與載板基底110之間使用釋放層112。在此類實施例中,釋放層104可用於例如藉由執行包封體214及穿孔210的回蝕直至曝露出載板基底110來更輕易地釋放載板基底110。接著,可藉由將光(諸如雷射光或UV光)投影於釋放層112上,使得釋放層112在光的熱量下分解且可移除載板基底110來移除載板基底110。在以此方式移除載板基底110之後,CMP製程仍可用於使包封體214、穿孔210、介電填充物120以及穿孔125的上部表面齊平。在移除載板基底110之後,小晶片中介物100的最厚層為介電填充物120,其充當小晶片中介物100的基底。在一些實施例中,小晶片中介物100的一個主表面可包括介電填充物120且小晶片中介物100的另一主表面可包括重佈線結構128。
在圖41中,可在小晶片中介物100上方形成視情況選用的重佈線結構278。可使用與上文關於圖26的重佈線結構228所論述的製程及材料類似的製程及材料來形成重佈線結構278。可在重佈線結構278上方及/或周圍沉積包封體280。可使用與上文關於圖26的包封體230所論述的製程及材料類似的製程及材料來形成包封體280。接著可在包封體280中形成開口以曝露出重佈線結構278的頂部金屬化圖案。可在重佈線結構278的頂部金屬化圖案上的開口中形成導電連接件285。可使用與上文關於導電連接件172所描述的製程及材料類似的製程及材料來形成導電連接件285,包含視情況選用的凸塊下金屬(UBM)。在導電連接件285不包含焊料凸塊的實施例中,亦可在導電連接件285上形成焊料凸塊287。焊料凸塊287可藉由任何適合的製程,諸如藉由焊料印刷或鍍覆,接著以回焊製程來形成。
在圖42中,可藉由剝離製程來移除載板基底302且結構翻轉。在實例剝離製程中,剝離包含將諸如雷射光或UV光的光投影於釋放層上,使得釋放層在光的熱量下分解且可移除載板基底302。若未使用釋放層,則結構可翻轉且接著載板基底302可藉由向上壓力或藉由在研磨製程中研磨載板基底302而機械地移除。
圖42中所示出的完成的結構可為封裝元件400,包含多個元件250及一或多個小晶片中介物100,所述一或多個小晶片中介物有助於將訊號自元件250重新分佈至導電連接件285/自導電連接件285重新分佈至元件250。視情況選用的拼接製程可用於形成超小晶片中介物100'作為小晶片中介物100,所述小晶片中介物100包含延伸超出用於光圖案化的光罩幕(例如,倍縮光罩)的橫向邊界的金屬化圖案。
圖43示出根據另一實施例的封裝元件400。在圖43中,省略穿孔210。在此等實施例中,可省略形成穿孔210的製程,且可形成橫向地環繞小晶片中介物100的包封體214(參見圖39)。
圖44示出根據另一實施例的封裝元件400。在圖44中,可省略小晶片中介物100內的穿孔125(參見圖2)。在此類實施例中,可省略形成穿孔125的製程(參見圖1及其隨附描述),且可在載板基底110上方沉積介電填充物120。
圖45示出根據另一實施例的封裝元件400。在圖45中,可省略重佈線結構278。在此類實施例中,可省略形成重佈線結構278(參見圖41及其隨附描述)的製程,且可在穿孔125、穿孔210、包封體214以及介電填充物120正上方形成包封體280。
圖35至圖45中所示出的封裝元件400中的每一者利用缺乏矽基底(諸如,載板基底110)的小晶片中介物100。替代地,中介物100的作用「基底」為亦可具有視情況選用的穿孔125的介電填充物120。由於小晶片中介物100不具有矽基底,因此小晶片中介物100的應力集中低於其他中介物技術。舉例而言,取決於厚度、結晶定向以及軸方向,矽基底的楊氏係數可在約130吉帕與180吉帕之間。相比之下,介電填充物120的楊氏係數可在約50吉帕與約100吉帕之間,諸如在約65吉帕與75吉帕之間。因此,小晶片中介物100展現明顯小於其他中介物技術的應力集中。減小的應力係數亦允許較大佔據面積中介物及上文所描述的拼接製程的成功使用。
關於封裝元件300及封裝元件400,亦可包含其他特徵及製程。舉例而言,可包含測試結構以輔助對封裝元件300及封裝元件400的驗證測試。測試結構可包含例如形成於重佈線層中或形成於基底上的測試襯墊,其允許測試封裝元件300及封裝元件400、使用探針及/或探針卡以及類似物。可對中間結構以及最終結構執行驗證測試。另外,本文中所揭露的結構及方法可結合併入有對良裸晶粒的中間驗證的測試方法而使用,以提高良率且降低成本。後續製程可將封裝元件300及/或封裝元件400安裝至元件基底。
圖46至圖52為經由封裝元件300及封裝元件400的小晶片中介物100層的水平橫截面視圖。圖46為沿圖31中的線A-A'(對於封裝元件300)截取的實例橫截面視圖,且圖47為沿圖42中的線B-B'(對於封裝元件400)截取的實例橫截面視圖。圖46至圖52中的每一者示出沿類似水平橫截面平面的類似結構中的小晶片中介物100的各種配置。應理解,橫截面視圖僅為實例,且其可以任何適合方式組合以達成特定佈局或配置。舉例而言,與所描繪的小晶片中介物相比,可併入更多或更少的小晶片中介物100。另外,超小晶片中介物100'可與其他小晶片中介物一起使用及組合,如圖46至圖52中所示出。
在圖46中,示出根據一些實施例的經由小晶片中介物100的水平橫截面視圖。如圖46中所提及,元件300/元件400可具有多個小晶片中介物100。在圖46的實例中,四個小晶片中介物100設置於包封體214的層中。可使用更多或更少的小晶片中介物100。由於小晶片中介物100包括介電填充物120而非矽基底層(例如,載板基底110),因此多個小晶片中介物100中的每一者的應力集中較小,從而由於減小彎曲及脫層風險而產生較大可靠性。小晶片中介物100可各自具有相同中介物設計、不同中介物設計或相同中介物設計及不同中介物設計的組合。小晶片中介物100亦可包含具有一個圖案化區域的中介物或具有多個圖案化區域(並排)的超小晶片中介物100'的混合。
在圖47中,示出根據一些實施例的經由小晶片中介物100的水平橫截面視圖。在圖47所示出的實施例中,包含超小晶片中介物100'作為小晶片中介物100。超小晶片中介物100'可具有多個圖案化區域,諸如圖案化區域100A及圖案化區域100B。元件300/元件400可具有多個小晶片中介物100,包含多個超小晶片中介物100'、小晶片中介物100或其組合。在圖47的實例中,一個超小晶片中介物100'設置於包封體214的層中。可使用更多或更少的小晶片中介物100。由於超小晶片中介物100'包括介電填充層120而非矽基底層(例如,載板基底110),因此超小晶片中介物100'中的每一者的應力集中較小,從而由於減小彎曲及脫層風險而產生較大可靠性。在使用多個小晶片中介物100(包含超小晶片中介物100')的情況下,小晶片中介物100可各自具有相同中介物設計、不同中介物設計或相同中介物設計與不同中介物設計的組合。
在圖48中,示出根據一些實施例的經由小晶片中介物100的水平橫截面視圖。在圖48中所示出的實施例中,包含小晶片中介物100及超小晶片中介物100'的混合。超小晶片中介物100'可具有多個圖案化區域,諸如圖案化區域100A及圖案化區域100B。在圖48的實例中,兩個超小晶片中介物100'設置於包封體214的層中,且兩個小晶片中介物100設置於包封體214的層中。可使用更多或更少的小晶片中介物100(及/或超小晶片中介物100')。由於小晶片中介物100及/或超小晶片中介物100'包括介電填充物120而非矽基底層(例如,載板基底110),因此小晶片中介物100及/或超小晶片中介物100'中的每一者的應力集中較小,從而由於減小彎曲及脫層風險而產生較大可靠性。多個小晶片中介物100及/或超小晶片中介物100'可各自分別具有相同中介物設計、不同中介物設計或相同中介物設計與不同中介物設計的組合。
在圖49中,示出根據一些實施例的經由小晶片中介物100的水平橫截面視圖。在圖49中所示出的實施例中,包含兩個超小晶片中介物100'。超小晶片中介物100'可具有多個圖案化區域,諸如圖案化區域100A、圖案化區域100B以及圖案化區域100C。元件300/元件400可具有多個小晶片中介物100,包含多個超小晶片中介物100'、小晶片中介物100或其組合。在圖49的實例中,兩個超小晶片中介物100'設置於包封體214的層中。可使用更多或更少的小晶片中介物100及/或超小晶片中介物100'。由於超小晶片中介物100'包括介電填充層120而非矽基底層(例如,載板基底110),因此超小晶片中介物100'中的每一者的應力集中較小,從而由於減小彎曲及脫層風險而產生較大可靠性。在使用多個小晶片中介物100及/或超小晶片中介物100'的情況下,小晶片中介物100可各自具有相同中介物設計、不同中介物設計或相同中介物設計與不同中介物設計的組合。
在圖50及圖51中,示出根據一些實施例的經由小晶片中介物100的水平橫截面視圖。在圖50及圖51中所示出的實施例中,包含超小晶片中介物100'作為小晶片中介物100。在圖50中,超小晶片中介物100'可具有多個圖案化區域,諸如圖案化區域100A、圖案化區域100B、圖案化區域100C、圖案化區域100D、圖案化區域100E以及圖案化區域100F。在圖51中,超小晶片中介物100'可具有多個圖案化區域,諸如圖案化區域100A、圖案化區域100B、圖案化區域100C、圖案化區域100D、圖案化區域100E、圖案化區域100F、圖案化區域100G以及圖案化區域100H。元件300/元件400可具有多個小晶片中介物100,包含多個超小晶片中介物100'、小晶片中介物100或其組合。在圖50及圖51中所示出的實例中,一個超小晶片中介物100'設置於包封體214的層中。可使用更多或更少的小晶片中介物100。由於超小晶片中介物100'包括介電填充物120而非矽基底層(例如,載板基底110),因此超小晶片中介物100'中的每一者的應力集中較小,從而由於減小彎曲及脫層風險而產生較大可靠性。在使用多個小晶片中介物100(包含超小晶片中介物100')的情況下,小晶片中介物100可各自具有相同中介物設計、不同中介物設計或相同中介物設計與不同中介物設計的組合。
圖46至圖51中所提供的實例意欲作為非限制性實例。其可經組合以形成使用小晶片中介物100及/或超小晶片中介物100'的不同配置及佈局。對於超小晶片中介物100',可將任何數目個圖案區域可拼接在一起。儘管超小晶片中介物100'經示出為矩形,但圖案區域可拼接在一起成其他形狀,諸如el形狀(el shape)、tee形狀(tee shape)、加號形狀、矩環形狀等等。
實施例有利地將一或多個小晶片中介物用於封裝元件中路由的訊號。小晶片中介物提供優於其他中介物技術的明顯優點。具體而言,小晶片中介物不具有矽基底部分。替代地,小晶片中介物的作用「基底」為形成於稍後經移除的載板基底上方的介電填充材料。重佈線結構可形成於介電填充「基底」的任一側上以提供訊號路由能力,且設置於介電填充物中的穿孔可將訊號自中介物的一側傳輸至中介物的相對側。藉由移除中介物的矽基底部分且僅依賴於介電填充物作為「基底」,減小中介物的應力集中。因此,已完成封裝中的彎曲減少且環繞小晶片中介物的包封體的脫層可能性降低。實施例進一步提供關於小晶片中介物的圖案化的優點。當在介電填充物上方形成重佈線結構時,可將重佈線結構的金屬化圖案的兩個或大於兩個鄰接區域拼接在一起以提供具有較給定光罩幕尺寸通常可能的佔據面積更大佔據面積的金屬化圖案。
一個實施例為一種方法,包含將第一中介物附接至封裝結構,第一中介物包含形成於載板基底上的介電填充物。所述方法亦包含將第一中介物橫向地包封於第一包封體中。所述方法亦包含將第一元件附接至封裝結構。所述方法亦包含將第一元件橫向地包封於第二包封體中。所述方法亦包含移除第一包封體的部分且移除第一中介物的載板基底以曝露出介電填充物。所述方法亦包含在封裝結構上形成外部連接件,外部連接件中的一或多者藉助於第一中介物電性耦接至第一元件。在一實施例中,形成延伸穿過第一中介物的介電填充物的穿孔。在一實施例中,形成延伸穿過第一包封體的穿孔。在一實施例中,在第一中介物上方形成重佈線結構,重佈線結構比第一中介物更寬,重佈線結構插入於第一中介物與外部連接件之間。在一實施例中,使第一可光圖案化材料的第一部分曝露於第一光罩幕圖案,使第一可光圖案化材料的第二部分曝露於第二光罩幕圖案,其中第一部分與第二部分交疊,第一部分及第二部分一起形成第一圖案;且基於第一圖案形成金屬化圖案。在一實施例中,第一部分與第二部分的交疊區域中的金屬化圖案具有比第一部分或第二部分中的金屬化圖案更寬的線寬。在一實施例中,將第二中介物附接至封裝結構,第二中介物鄰近第一中介物,第二中介物包含形成於第二載板基底上的第二介電填充物,且移除第二載板基底以曝露出第二介電填充物。在一實施例中,在將第一元件附接至封裝結構之後將第一中介物附接至封裝結構。
另一實施例為一種封裝,包含第一元件,第一元件由第一包封體橫向地包封。所述封裝亦包含第一中介物,第一中介物包含介電填充層,第一中介物不含矽層,第一中介物由第二包封體橫向地包封。所述封裝亦包含外部連接件,外部連接件中的一或多者藉助於第一中介物電性耦接至第一元件。在一實施例中,第一中介物的介電填充層包含設置於介電填充層中的一系列穿孔。在一實施例中,第一中介物包含第一重佈線結構及第二重佈線結構,第一重佈線結構及第二重佈線結構設置於介電填充層的相對側上。在一實施例中,封裝包含延伸穿過第二包封體的穿孔。在一實施例中,第一中介物包含重佈線結構,重佈線結構包含第一金屬化圖案,第一金屬化圖案包含交疊導體,交疊導體具有第一寬度,第一金屬化圖案的第一金屬線具有第二寬度,第一金屬線連續地延伸至交疊導體中,第一寬度大於第二寬度。在一實施例中,第一金屬化圖案的第二金屬線在與第一金屬線相對的交疊導體的一側處連續地延伸至交疊導體中,第一金屬線與第二金屬線偏移,第一金屬線平行於第二金屬線。
另一實施例為一種封裝元件,包含一或多個嵌入式元件。封裝元件亦包含第一包封體層,第一包封體層包封一或多個嵌入式元件。封裝元件亦包含一或多個小晶片中介物,一或多個小晶片中介物中的每一者具有基底,所述基底包含楊氏係數在50吉帕與100吉帕之間的第一材料。封裝元件亦包含第二包封體層,第二包封體層包封一或多個小晶片中介物。封裝元件亦包含設置於第一包封體層與第二包封體層之間的第一重佈線結構。封裝元件亦包含外部連接件,其中外部連接件中的一或多者電性耦接至一或多個嵌入式元件及一或多個小晶片中介物。在一實施例中,一或多個小晶片中介物各自包含介電填充層。在一實施例中,一或多個小晶片中介物中的至少一者的介電填充層包含穿過介電填充層的厚度的穿孔。在一實施例中,封裝元件更包含設置於外部連接件與一或多個小晶片中介物之間的第二重佈線結構,第二重佈線結構將一或多個小晶片中介物中的第一小晶片中介物與一或多個小晶片中介物中的第二小晶片中介物電性耦接。在一實施例中,封裝元件更包含延伸穿過第二包封體層的穿孔,所述穿孔將第一重佈線結構直接物理地且電性地耦接至第二重佈線結構。在一實施例中,一或多個小晶片中介物中的第一中介物包含拼接重佈線結構,所述拼接重佈線結構包含第一金屬化圖案,所述第一金屬化圖案具有第一部分、第二部分以及對應於第一部分與第二部分的交疊區域的交疊部分,其中第一部分中的第一金屬化圖案的第一金屬線寬小於交疊部分中的第一金屬化圖案的第二金屬線寬。
前文概述若干實施例的特徵,使得所屬領域中具通常知識者可更佳理解本揭露的態樣。所屬領域的技術人員應瞭解,其可容易地使用本揭露作為設計或修改用於進行本文中所引入的實施例的相同目的及/或達成相同優點的其他製程及結構的基礎。所屬領域中具通常知識者亦應認識到,此類等效構造並不脫離本揭露的精神及範疇,且其可在不脫離本揭露的精神及範疇的情況下在本文中作出各種改變、替代以及更改。
100:小晶片中介物
100':超小晶片中介物
100A、100B、100C:中介物區域
100D、100E、100F、100G、100H:圖案化區域
110、202、302:載板基底
112:釋放層
120:介電填充物
125、210:穿孔
128、278:重佈線結構
130、140:介電層
131:通孔開口
132、138、138a、138b、148:金屬化圖案
134:導電材料
136、146:通孔
138o:交疊區域
150:光罩
152、152A、152B、152C、152D、152E:曝光區域
154、156:開口
160、160A、160B、160C:光罩幕
162:曝光製程
170:絕緣層
172、235、285:導電連接件
204:安裝平台
214、230、265、280:包封體
228:前側重佈線結構
228-d:介電層
228-m:金屬化圖案
237、287:焊料凸塊
250、250A、250B、250C:元件
255:前側連接件
260:底部填充物
300、400:封裝元件
d1、d2、d3:線寬
d4、d5:距離
p1:間距
w1、w2:寬度
結合附圖閱讀以下詳細描述會最佳地理解本揭露的各態樣。應注意,根據業界中的標準慣例,各種特徵未按比例繪製。事實上,為論述清楚起見,可任意增大或減小各種特徵的尺寸。
圖1至圖22示出根據一些實施例的用於形成小晶片中介物的製程期間的中間步驟的橫截面視圖及俯視圖。
圖23至圖34示出根據一些實施例的利用小晶片中介物形成封裝元件的製程期間的中間步驟的橫截面視圖。
圖35至圖45示出根據一些實施例的利用小晶片中介物形成封裝元件的製程期間的中間步驟的橫截面視圖。
圖46至圖51示出根據各種實施例的關於利用一或多個小晶片中介物的各種配置的俯視圖。
100:小晶片中介物
210:穿孔
214、230、265、280:包封體
228:前側重佈線結構
235、285:導電連接件
237、287:焊料凸塊
250、250A、250B、250C:元件
255:前側連接件
260:底部填充物
278:重佈線結構
300:封裝元件
Claims (20)
- 一種方法,包括: 將第一中介物附接至封裝結構,所述第一中介物包括形成於載板基底上的介電填充物; 將所述第一中介物橫向地包封於第一包封體中; 將第一元件附接至所述封裝結構; 將所述第一元件橫向地包封於第二包封體中; 移除所述第一包封體的部分且移除所述第一中介物的所述載板基底以曝露出所述介電填充物;以及 在所述封裝結構上形成外部連接件,所述外部連接件中的一或多者藉助於所述第一中介物電性耦接至所述第一元件。
- 如請求項1所述的方法,更包括: 形成延伸穿過所述第一中介物的所述介電填充物的穿孔。
- 如請求項1所述的方法,更包括: 形成延伸穿過所述第一包封體的穿孔。
- 如請求項1所述的方法,更包括: 在所述第一中介物上方形成重佈線結構,所述重佈線結構比所述第一中介物更寬,所述重佈線結構插入於所述第一中介物與所述外部連接件之間。
- 如請求項1所述的方法,更包括: 使第一可光圖案化材料的第一部分曝露於第一光罩幕圖案; 使所述第一可光圖案化材料的第二部分曝露於第二光罩幕圖案,所述第一部分與所述第二部分交疊,所述第一部分及所述第二部分一起形成第一圖案;以及 基於所述第一圖案形成金屬化圖案。
- 如請求項5所述的方法,其中所述第一部分與所述第二部分的交疊區域中的所述金屬化圖案具有比所述第一部分或所述第二部分中的所述金屬化圖案更寬的線寬。
- 如請求項1所述的方法,更包括: 將第二中介物附接至所述封裝結構,所述第二中介物鄰接所述第一中介物,所述第二中介物包括形成於第二載板基底上的第二介電填充物;以及 移除所述第二載板基底以曝露出所述第二介電填充物。
- 如請求項1所述的方法,其中在將所述第一元件附接至所述封裝結構之後將所述第一中介物附接至所述封裝結構。
- 一種封裝,包括: 第一元件,所述第一元件由第一包封體橫向地包封; 第一中介物,所述第一中介物包括介電填充層,所述第一中介物不含矽層,所述第一中介物由第二包封體橫向地包封;以及 外部連接件,所述外部連接件中的一或多者藉助於所述第一中介物電性耦接至所述第一元件。
- 如請求項9所述的封裝,其中所述第一中介物的所述介電填充層包含設置於所述介電填充層中的一系列穿孔。
- 如請求項9所述的封裝,其中所述第一中介物包含第一重佈線結構及第二重佈線結構,所述第一重佈線結構及所述第二重佈線結構設置於所述介電填充層的相對側上。
- 如請求項9所述的封裝,更包括延伸穿過所述第二包封體的穿孔。
- 如請求項9所述的封裝,其中所述第一中介物包括重佈線結構,所述重佈線結構包括第一金屬化圖案,所述第一金屬化圖案包含交疊導體,所述交疊導體具有第一寬度,所述第一金屬化圖案的第一金屬線具有第二寬度,所述第一金屬線連續地延伸至所述交疊導體中,所述第一寬度大於所述第二寬度。
- 如請求項13所述的封裝,其中所述第一金屬化圖案的第二金屬線在所述交疊導體的與所述第一金屬線相對的一側處連續地延伸至所述交疊導體中,所述第一金屬線與所述第二金屬線偏移,所述第一金屬線平行於所述第二金屬線。
- 一種封裝元件,包括: 一或多個嵌入式元件; 第一包封體層,所述第一包封體層包封所述一或多個嵌入式元件; 一或多個小晶片中介物,所述一或多個小晶片中介物中的每一者具有基底,所述基底包括楊氏係數在50吉帕與100吉帕之間的第一材料; 第二包封體層,所述第二包封體層包封所述一或多個小晶片中介物; 第一重佈線結構,設置於所述第一包封體層與所述第二包封體層之間;以及 外部連接件,其中所述外部連接件中的一或多者電性耦接至所述一或多個嵌入式元件及所述一或多個小晶片中介物。
- 如請求項15所述的封裝元件,其中所述一或多個小晶片中介物各自包括介電填充層。
- 如請求項16所述的封裝元件,其中所述一或多個小晶片中介物中的至少一者的所述介電填充層包括穿過所述介電填充層的厚度的穿孔。
- 如請求項15所述的封裝元件,更包括設置於所述外部連接件與所述一或多個小晶片中介物之間的第二重佈線結構,所述第二重佈線結構將所述一或多個小晶片中介物中的第一小晶片中介物與所述一或多個小晶片中介物中的第二小晶片中介物電性耦接。
- 如請求項18所述的封裝元件,更包括延伸穿過所述第二包封體層的穿孔,所述穿孔將所述第一重佈線結構直接物理地且電性地耦接至所述第二重佈線結構。
- 如請求項15所述的封裝元件,其中所述一或多個小晶片中介物中的第一中介物包含拼接重佈線結構,所述拼接重佈線結構包括第一金屬化圖案,所述第一金屬化圖案具有第一部分、第二部分以及對應於所述第一部分與所述第二部分的交疊區域的交疊部分,其中所述第一部分中的所述第一金屬化圖案的第一金屬線寬小於所述交疊部分中的所述第一金屬化圖案的第二金屬線寬。
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