TW202225970A - Slot connectivity test device and test method thereof - Google Patents
Slot connectivity test device and test method thereof Download PDFInfo
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Abstract
Description
本發明涉及資訊安全的技術領域,特別是涉及一種插槽連通性測試裝置及其測試方法。The present invention relates to the technical field of information security, in particular to a socket connectivity testing device and a testing method thereof.
主機板廠商的主機板上會有很多外部設備互連匯流排插槽(PCIe Slot),對於新生產的主機板來說,外部設備互連匯流排插槽在焊接時候可能會有虛焊,需要進行物理連接的連通性測試,測試外部設備互連匯流排插槽網路的連通性,來保證主機板生產品質。There are many PCIe slots on the motherboard manufacturer's motherboard. For newly produced motherboards, the external device interconnect bus slot may be soldered when soldering. Carry out the connectivity test of the physical connection, and test the connectivity of the external device interconnection bus bar slot network to ensure the production quality of the motherboard.
目前,在進行主機板網路連通性測試時,需要為主機板添加一些複雜的專用測試設備,例如網卡,GPU卡等插在外部設備互連匯流排插槽中進行測試驗證,由於專用測試設備價格較高,導致測試成本高,而且使用專用測試設備整個測試過程較複雜,耗時較長,測試效率低。At present, when testing the network connectivity of the motherboard, it is necessary to add some complex special test equipment to the motherboard, such as network cards, GPU cards, etc., which are inserted into the external equipment interconnection busbar slots for test verification. Due to the special test equipment The high price leads to high testing costs, and the entire testing process using special testing equipment is more complicated, time-consuming, and testing efficiency is low.
鑒於以上所述現有技術的缺點,本發明的目的在於提供一種插槽連通性測試裝置及其測試方法,用於解決現有技術中測試主機板上用於外部設備互連的匯流排插槽的連通性時測試成本高、測試效率低的問題。In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a socket connectivity test device and a test method thereof, which are used to solve the problem of testing the connectivity of the bus bar sockets used for the interconnection of external devices on the motherboard in the prior art. The problem of high test cost and low test efficiency during sex.
為實現上述目的及其他相關目的,本發明提供一種插槽連通性測試裝置,所述插槽連通性測試裝置包括一電路板、一Retimer晶片、一連接端以及一回傳模組;所述連接端裝設於所述電路板一側,係用於插接待測主機板的插槽;所述Retimer晶片裝設於所述電路板上,所述Retimer晶片的信號發送端子與信號接收端子分別與所述連接端電連接,所述信號接收端子接收待測主機板發送的輸出信號,所述信號發送端子經由所述Retimer晶片和所述連接端向待測主機板發送測試信號;所述回傳模組用於將所述信號接收端子接收的所述輸出信號回傳到所述Retimer晶片的信號發送端子,以使得所述信號發送端子經由所述Retimer晶片和所述連接端向待測主機板發送測試信號。In order to achieve the above object and other related objects, the present invention provides a socket connectivity test device, the socket connectivity test device includes a circuit board, a Retimer chip, a connection end and a return module; the connection The terminal is installed on one side of the circuit board, and is used to insert the slot of the motherboard under test; the Retimer chip is installed on the circuit board, and the signal sending terminal and the signal receiving terminal of the Retimer chip are respectively connected with The connecting end is electrically connected, the signal receiving terminal receives the output signal sent by the motherboard to be tested, and the signal sending terminal sends a test signal to the motherboard to be tested via the Retimer chip and the connecting terminal; the return transmission The module is used to transmit the output signal received by the signal receiving terminal back to the signal transmitting terminal of the Retimer chip, so that the signal transmitting terminal can send the signal to the motherboard under test via the Retimer chip and the connecting terminal. Send a test signal.
於本發明一實施例中,所述連接端為金手指組件。In an embodiment of the present invention, the connecting end is a gold finger component.
於本發明一實施例中,所述金手指組件包含的金手指個數與所述待測主機板的插槽的端子個數匹配。In an embodiment of the present invention, the number of golden fingers included in the golden finger assembly matches the number of terminals of the socket of the motherboard to be tested.
於本發明一實施例中,所述回傳模組為裝設於所述電路板上,並分別與所述Retimer晶片的信號接收端子和所述信號發送端子相連的回傳電路。In an embodiment of the present invention, the return module is a return circuit mounted on the circuit board and connected to the signal receiving terminal and the signal transmitting terminal of the Retimer chip, respectively.
於本發明一實施例中,所述回傳模組包括與所述電路板相連的控制板和裝設於所述控制板上的分別與所述Retimer晶片的信號接收端子和所述信號發送端子相連的回傳電路。In an embodiment of the present invention, the return transmission module includes a control board connected to the circuit board, and a signal receiving terminal and the signal transmitting terminal respectively connected to the Retimer chip mounted on the control board. connected return circuit.
於本發明一實施例中,所述回傳電路包括一端與所述Retimer晶片的信號接收端子相連,另一端與所述Retimer晶片的信號發送端子相連的回傳電阻模組。In an embodiment of the present invention, the return circuit includes a return resistance module whose one end is connected to the signal receiving terminal of the Retimer chip and the other end is connected to the signal transmitting terminal of the Retimer chip.
於本發明一實施例中,所述回傳模組位於所述Retimer晶片內並通過所述Retimer晶片內的串列器/解串器將所述信號接收端子接收的所述輸出信號回傳到所述Retimer晶片的信號發送端子。In an embodiment of the present invention, the return module is located in the Retimer chip and transmits the output signal received by the signal receiving terminal back to the Retimer chip through a serializer/deserializer in the Retimer chip. The signal sending terminal of the Retimer chip.
為實現上述目的及其他相關目的,本發明還提供一種插槽連通性測試方法,所述插槽連通性測試方法應用於插槽連通性測試裝置;所述插槽連通性測試裝置包括一電路板、一Retimer晶片、一連接端以及一回傳模組,所述Retimer晶片具有信號接收端子和信號發送端子;所述插槽連通性測試方法包括以下步驟:在所述連接端插接待測主機板的插槽時,通過Retimer晶片的信號接收端子從待測主機板接收輸出信號;基於所述回傳模組將所述信號接收端子接收的所述輸出信號回傳到所述Retimer晶片的信號發送端子;所述信號發送端子經由所述Retimer晶片和所述連接端向待測主機板發送測試信號。In order to achieve the above object and other related objects, the present invention also provides a slot connectivity testing method, which is applied to a slot connectivity testing device; the slot connectivity testing device includes a circuit board , a Retimer chip, a connecting end and a return module, the Retimer chip has a signal receiving terminal and a signal transmitting terminal; the slot connectivity test method comprises the following steps: inserting the motherboard under test at the connecting end When the socket is installed, the output signal is received from the motherboard to be tested through the signal receiving terminal of the Retimer chip; based on the return module, the output signal received by the signal receiving terminal is sent back to the signal transmission of the Retimer chip terminal; the signal sending terminal sends a test signal to the motherboard to be tested via the Retimer chip and the connection terminal.
於本發明一實施例中,所述連接端為金手指組件。In an embodiment of the present invention, the connecting end is a gold finger component.
於本發明一實施例中,所述金手指組件包含的金手指個數與所述待測主機板的插槽的端子個數匹配。In an embodiment of the present invention, the number of golden fingers included in the golden finger assembly matches the number of terminals of the socket of the motherboard to be tested.
於本發明一實施例中,所述回傳模組為裝設於所述電路板上,並分別與所述Retimer晶片的信號接收端子和所述信號發送端子相連的回傳電路。In an embodiment of the present invention, the return module is a return circuit mounted on the circuit board and connected to the signal receiving terminal and the signal transmitting terminal of the Retimer chip, respectively.
於本發明一實施例中,所述回傳模組包括與所述電路板相連的控制板和裝設於所述控制板上的分別與所述Retimer晶片的信號接收端子和所述信號發送端子相連的回傳電路。In an embodiment of the present invention, the return transmission module includes a control board connected to the circuit board, and a signal receiving terminal and the signal transmitting terminal respectively connected to the Retimer chip mounted on the control board. connected return circuit.
於本發明一實施例中,所述回傳電路包括一端與所述Retimer晶片的信號接收端子相連,另一端與所述Retimer晶片的信號發送端子相連的回傳電阻模組。In an embodiment of the present invention, the return circuit includes a return resistance module whose one end is connected to the signal receiving terminal of the Retimer chip and the other end is connected to the signal transmitting terminal of the Retimer chip.
於本發明一實施例中,所述回傳模組位於所述Retimer晶片內並通過所述Retimer晶片內的串列器/解串器將所述信號接收端子接收的所述輸出信號回傳到所述Retimer晶片的信號發送端子。In an embodiment of the present invention, the return module is located in the Retimer chip and transmits the output signal received by the signal receiving terminal back to the Retimer chip through a serializer/deserializer in the Retimer chip. The signal sending terminal of the Retimer chip.
如上所示,本發明的一種插槽連通性測試裝置及其測試方法通過將成本低廉的Retimer晶片的信號接收端子接收的信號通過外部鏈路或晶片內部,回傳到Retimer晶片的信號發送端子,不需要專用的測試設備就能實現對主機板上插槽的連通性測試,大大降低了主機板的生產測試成本。As shown above, a socket connectivity testing device and testing method of the present invention transmits the signal received by the signal receiving terminal of the low-cost Retimer chip to the signal sending terminal of the Retimer chip through an external link or inside the chip, The connectivity test of the socket on the motherboard can be realized without special test equipment, which greatly reduces the production test cost of the motherboard.
以下通過特定的具體實例說明本發明的實施方式,本領域技術人員可由本說明書所揭露的內容輕易地瞭解本發明的其他優點與功效。本發明還可以通過另外不同的具體實施方式加以實施或應用,本說明書中的各項細節也可以基於不同觀點與應用,在沒有背離本發明的精神下進行各種修飾或改變。需說明的是,在不衝突的情況下,以下實施例及實施例中的特徵可以相互組合。The embodiments of the present invention are described below through specific specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments may be combined with each other under the condition of no conflict.
需要說明的是,以下實施例中所提供的圖示僅以示意方式說明本發明的基本構想,遂圖式中僅顯示與本發明中有關的組件而非按照實際實施時的元件數目、形狀及尺寸繪製,其實際實施時各元件的型態、數量及比例可為一種隨意的改變,且其元件佈局型態也可能更為複雜。It should be noted that the drawings provided in the following embodiments are only used to illustrate the basic concept of the present invention in a schematic way, so the drawings only show the components related to the present invention rather than the number, shape and number of components in actual implementation. For dimension drawing, the type, quantity and ratio of each element can be arbitrarily changed in actual implementation, and the layout of the element may also be more complicated.
本實施例的目的在於提供一種插槽連通性測試裝置100及其測試方法,用於解決現有技術中測試主機板上用於外部設備互連的匯流排插槽的連通性時測試成本高、測試效率低的問題。The purpose of this embodiment is to provide a socket
以下將詳細闡述本實施例的插槽連通性測試裝置100及其測試方法的原理及實施方式,使本領域技術人員不需要創造性勞動即可理解本發明的插槽連通性測試裝置100及其測試方法。The principle and implementation of the socket
實施例1Example 1
如圖1所示,本實施例提供一種插槽連通性測試裝置100,所述插槽連通性測試裝置100包括電路板110,Retimer晶片130,連接端120以及回傳模組140。As shown in FIG. 1 , the present embodiment provides a socket
於本實施例中,所述連接端120裝設於所述電路板110一側,用於插接待測主機板的插槽210。In this embodiment, the
具體地,於本實施例中,所述連接端120為金手指組件。Specifically, in this embodiment, the connecting
其中,所述金手指組件包含的金手指個數與所述待測主機板的插槽210的端子個數匹配,即根據所述待測主機板的插槽210的導電端子的數量確定所述插槽連通性測試裝置100中連接端120的金手指個數。The number of gold fingers included in the gold finger assembly matches the number of terminals of the
於本實施例中,所述待測主機板的插槽210優選但不限於PCIe插槽。In this embodiment, the
根據待測主機板的插槽210的輸出信號定義所述金手指組件的各個金手指。例如,所述待測主機板通過插槽輸出的輸出信號包括PCIe信號和時鐘重定信號以及I2C信號,對應的金手指組件定義對應的金手指從所述待測主機板的插槽210接收PCIe信號和時鐘重定信號以及I2C信號。Each gold finger of the gold finger assembly is defined according to the output signal of the
於本實施例中,所述Retimer晶片130裝設於所述電路板110上,所述Retimer晶片130的信號發送端子與信號接收端子分別與所述連接端120電連接,所述信號接收端子接收待測主機板發送的輸出信號,所述信號發送端子經由所述Retimer晶片和所述連接端向待測主機板發送測試信號。In this embodiment, the
其中,Retimer晶片130採用信號調理技術來提升信號完整性,增加高速信號的有效傳輸距離。Retimer晶片130採用業界主流封裝,其功耗、傳輸時延等關鍵性能指標領先其它測試晶片,並且Retimer晶片130支援SRIS(具有獨立擴展頻譜時鐘架構的分離式參考時鐘)和Retimer級聯等應用。所述Retimer晶片130可與PCIe插槽通信,例如,所述Retimer晶片130符合PCIe 4.0規範、PCIe 5.0規範、或符合未來PCIe標準規範。相比現有技術中的專用測試設備網卡,GPU卡等,所述Retimer晶片130具有價格低廉的優勢。所以通過本實施例的Retimer晶片130對待測主機板的插槽210進行連通性測試,可以大大降低主機板的生產測試成本。Among them, the Retimer
在所述金手指組件插接到待測主機板的插槽210中時,從所述待測主機板的插槽210接收PCIe 信號和時鐘重定信號以及I2C信號等輸出信號,然後傳入Retimer晶片130中。所述Retimer晶片130的信號接收端子接收待測主機板發送的輸出信號,並經所述回傳模組140之後,所述Retimer晶片130的信號發送端子向待測主機板發送測試信號。在所述待測主機板的中央處理器CPU)檢測到所述Retimer晶片130發送的測試信號時,即實現了測試主機板的插槽的連通性。When the golden finger assembly is inserted into the
於本實施例中,所述回傳模組140用於將所述信號接收端子接收的所述輸出信號回傳到所述Retimer晶片的信號發送端子,以使得所述信號發送端子經由Retimer晶片130和連接端120向待測主機板發送測試信號。In this embodiment, the
於本實施例中,優選地,所述回傳模組140通過外部鏈路環回所述Retimer晶片130的信號。In this embodiment, preferably, the
圖1顯示為回傳模組140通過外部鏈路環回所述Retimer晶片130的信號的一種結構示意圖。具體地,於本實施例中,如圖1所示,所述回傳模組140設置在所述電路板110外部,包括與所述電路板110相連的控制板141和裝設於所述控制板141上的分別與所述Retimer晶片130的信號接收端子和所述信號發送端子相連的回傳電路142。所述控制板141用於承載所述回傳電路142,控制實現所述回傳電路142與所述電路板110的信號連接。FIG. 1 is a schematic diagram of a structure of the
即所述回傳模組140通過位於所述Retimer晶片130的外部,獨立於所述Retimer晶片130的控制板141和回傳電路142將所述信號接收端子接收的所述輸出信號回傳到所述Retimer晶片的信號發送端子,以使得所述信號發送端子經由所述Retimer晶片和所述連接端向待測主機板發送測試信號。在所述待測主機板的中央處理器220(CPU)檢測到所述Retimer晶片130發送的測試信號時,即實現了測試主機板的插槽的連通性。That is, the
其中,於本實施例中,所述回傳電路例如包括回傳電阻模組,所述回傳電阻模組的一端與所述Retimer晶片130的信號接收端子相連,另一端與所述Retimer晶片130的信號發送端子相連。其中,所述回傳電阻模組包括一個或多個電阻。In this embodiment, the return circuit includes, for example, a return resistance module. One end of the return resistance module is connected to the signal receiving terminal of the
圖2顯示為回傳模組140通過外部鏈路環回所述Retimer晶片130的信號的另一種結構示意圖。如圖2所示,於本實施例中,所述回傳模組140裝設於所述電路板110上,所述回傳模組140包括裝設於所述電路板110上的回傳電路,所述回傳電路分別與所述Retimer晶片130的信號接收端子和所述信號發送端子相連,所述回傳電路通過所述電路板110實現與所述Retimer晶片130的信號連接。FIG. 2 is a schematic diagram showing another structure of the
其中,於本實施例中,所述回傳電路例如包括回傳電阻模組,所述回傳電阻模組的一端與所述Retimer晶片130的信號接收端子相連,另一端與所述Retimer晶片130的信號發送端子相連。其中,所述回傳電阻模組包括一個或多個電阻。In this embodiment, the return circuit includes, for example, a return resistance module. One end of the return resistance module is connected to the signal receiving terminal of the
即本實施例中,所述回傳模組140與所述Retimer晶片130集成於一個電路板110上,所述回傳模組140位於所述Retimer晶片130的外部,獨立於所述Retimer晶片130,所述回傳模組140將所述信號接收端子接收的所述輸出信號回傳到所述Retimer晶片的信號發送端子,以使得所述信號發送端子經由Retimer晶片130和連接端120向待測主機板發送測試信號。在所述待測主機板的中央處理器(CPU)檢測到所述Retimer晶片130發送的測試信號時,即實現了測試主機板的插槽的連通性。That is, in this embodiment, the
此外,所述回傳模組140也可以通過所述Retimer晶片130的內部鏈路環回所述Retimer晶片130的信號。In addition, the
圖3顯示為回傳模組140通過所述Retimer晶片130內部鏈路環回所述Retimer晶片130的信號的一種結構示意圖。如圖3所示,所述回傳模組140位於所述Retimer晶片130內並通過所述Retimer晶片130內的串列器/解串器SERDES(SERializer / DESerializer)將所述信號接收端子接收的所述輸出信號回傳到所述Retimer晶片的信號發送端子。FIG. 3 is a schematic diagram showing a structure of the
其中,SERDES在發送端多路低速並行信號被轉換成高速串列信號,經過傳輸媒體(光纜或銅線),最後在接收端將高速串列信號重新轉換成低速並行信號。Among them, the SERDES multi-channel low-speed parallel signals are converted into high-speed serial signals at the transmitting end, and then pass through the transmission medium (optical cable or copper wire), and finally the high-speed serial signals are re-converted into low-speed parallel signals at the receiving end.
所述Retimer晶片130內部具有串列器/解串器,本實施例的回傳模組140在Retimer晶片內部利用串列器/解串器可以將信號轉換的功能將所述Retimer晶片130信號接收端子接收的所述輸出信號經Retimer晶片內部的串列器/解串器處理後,回傳到所述Retimer晶片的信號發送端子,以使得所述信號發送端子經由連接端120向待測主機板發送測試信號。在所述待測主機板的中央處理器220(CPU)檢測到所述Retimer晶片130發送的測試信號時,即實現了測試主機板的插槽的連通性。The
為使本領域技術人員進一步理解本實施例的插槽連通性測試裝置100,以下對本實施例的插槽連通性測試裝置100的使用過程進行說明。In order for those skilled in the art to further understand the socket
如圖4所示,主機板200具有多個插槽:插槽1……插槽N;本實施例的插槽連通性測試裝置100每次測試一個插槽的連通性,若多個插槽同時測試,可以在每一個插槽中插接一個本實施例的插槽連通性測試裝置100。As shown in FIG. 4 , the motherboard 200 has multiple slots: slot 1...slot N; the slot
在插槽連通性測試裝置100的金手指組件插接到插槽中時,所述金手指組件從所述主機板200的插槽接收PCIe信號和時鐘重定信號以及I2C信號等輸出信號,然後傳入插槽連通性測試裝置100的Retimer晶片。所述Retimer晶片的信號接收端子接收主機板200發送的輸出信號,並經所述回傳模組之後,所述Retimer晶片的信號發送端子向主機板200發送測試信號。在所述主機板200的中央處理器220(CPU)檢測到所述Retimer晶片發送的測試信號時,即實現了測試主機板200的插槽的連通性。When the golden finger assembly of the slot
所以本實施例的插槽連通性測試裝置100利用成本低廉的Retimer晶片,將Retimer晶片的信號接收端子接收的信號通過外部鏈路或晶片內部,回傳到Retimer晶片的信號發送端子,實現對主機板200上插槽的連通性測試,有效降低了主機板200的生產測試成本。Therefore, the socket
實施例2Example 2
本實施例提供一種插槽連通性測試方法,所述插槽連通性測試方法應用於本申請的插槽連通性測試裝置;所述插槽連通性測試裝置包括電路板,Retimer晶片,連接端以及回傳模組,所述Retimer晶片具有信號接收端子和信號發送端子;如圖5所示,所述插槽連通性測試方法包括以下步驟:This embodiment provides a socket connectivity test method, which is applied to the socket connectivity test device of the present application; the socket connectivity test device includes a circuit board, a Retimer chip, a connection end and For the return module, the Retimer chip has a signal receiving terminal and a signal transmitting terminal; as shown in Figure 5, the slot connectivity test method includes the following steps:
步驟S100,在所述連接端插接待測主機板的插槽時,通過Retimer晶片的信號接收端子從待測主機板接收輸出信號;Step S100, when the connection end is inserted into the slot of the motherboard to be tested, receive an output signal from the motherboard to be tested through a signal receiving terminal of the Retimer chip;
步驟S200,基於所述回傳模組將所述信號接收端子接收的所述輸出信號回傳到所述Retimer晶片的信號發送端子;Step S200, based on the return module, return the output signal received by the signal receiving terminal to the signal sending terminal of the Retimer chip;
步驟S300,所述信號發送端子經由所述Retimer晶片和所述連接端向待測主機板發送測試信號。Step S300, the signal sending terminal sends a test signal to the motherboard to be tested via the Retimer chip and the connection terminal.
於本實施例中,所述連接端為金手指組件。In this embodiment, the connecting end is a gold finger assembly.
其中,所述金手指組件包含的金手指個數與所述待測主機板的插槽的端子個數匹配,即根據所述待測主機板的插槽的導電端子的數量確定所述插槽連通性測試裝置中連接端的金手指個數。The number of gold fingers included in the gold finger assembly matches the number of terminals in the slot of the motherboard to be tested, that is, the slot is determined according to the number of conductive terminals of the slot of the motherboard to be tested. The number of gold fingers on the connection end in the connectivity test device.
根據待測主機板的插槽的輸出信號定義所述金手指組件的各個金手指。例如,所述待測主機板通過插槽輸出的輸出信號包括PCIe信號和時鐘重定信號以及I2C信號,對應的金手指組件定義對應的金手指從所述待測主機板的插槽接收PCIe信號和時鐘重定信號以及I2C信號。Each gold finger of the gold finger assembly is defined according to the output signal of the slot of the motherboard to be tested. For example, the output signals output by the motherboard to be tested through the slot include PCIe signals, reclocking signals and I2C signals, and the corresponding golden finger component defines the corresponding golden finger to receive PCIe signals and Reclock signal and I2C signal.
於本實施例中,所述回傳模組為裝設於所述電路板上,並分別與所述Retimer晶片的信號接收端子和所述信號發送端子相連的回傳電路。In this embodiment, the return module is a return circuit mounted on the circuit board and connected to the signal receiving terminal and the signal transmitting terminal of the Retimer chip, respectively.
於本實施例中,所述回傳模組包括與所述電路板相連的控制板和裝設於所述控制板上的分別與所述Retimer晶片的信號接收端子和所述信號發送端子相連的回傳電路。In this embodiment, the return module includes a control board connected to the circuit board, and a control board mounted on the control board and connected to the signal receiving terminal and the signal transmitting terminal of the Retimer chip, respectively. return circuit.
於本實施例中,所述回傳電路包括一端與所述Retimer晶片的信號接收端子相連,另一端與所述Retimer晶片的信號發送端子相連的回傳電阻模組。In this embodiment, the return circuit includes a return resistance module whose one end is connected to the signal receiving terminal of the Retimer chip, and the other end is connected to the signal transmitting terminal of the Retimer chip.
於本實施例中,所述回傳模組位於所述Retimer晶片內並通過所述Retimer晶片內的串列器/解串器將所述信號接收端子接收的所述輸出信號回傳到所述Retimer晶片的信號發送端子。In this embodiment, the return module is located in the Retimer chip and transmits the output signal received by the signal receiving terminal back to the Retimer chip through a serializer/deserializer in the Retimer chip. The signal transmission terminal of the Retimer chip.
其中,本實施例中回傳模組的結構和功能與實施例1中回傳模組140的結構和功能相同,所述Retimer晶片的結構和功能與實施例1中Retimer晶片130的結構和功能相同,實施例間相同的部分不再贅述。The structure and function of the return module in this embodiment are the same as those of the
綜上所述,本發明的一種插槽連通性測試裝置及其測試方法通過將成本低廉的Retimer晶片的信號接收端子接收的信號通過外部鏈路或晶片內部,回傳到Retimer晶片的信號發送端子的方式,不需要專用的測試設備就能實現對主機板上插槽的連通性測試,大大降低了主機板的生產測試成本。所以,本發明有效克服了現有技術中的種種缺點而具高度產業利用價值。To sum up, a socket connectivity test device and a test method of the present invention transmits the signal received by the signal receiving terminal of the low-cost Retimer chip to the signal transmitting terminal of the Retimer chip through the external link or the inside of the chip. In this way, the connectivity test of the slot on the motherboard can be realized without special test equipment, which greatly reduces the production test cost of the motherboard. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.
上述實施例僅例示性說明本發明的原理及其功效,而非用於限制本發明。任何熟悉此技術的人士皆可在不違背本發明的精神及範疇下,對上述實施例進行修飾或改變。因此,舉凡所屬技術領域中具有通常知識者在未脫離本發明所揭示的精神與技術思想下所完成的一切等效修飾或改變,仍應由本發明的權利要求所涵蓋。The above-mentioned embodiments merely illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed in the present invention should still be covered by the claims of the present invention.
100:插槽連通性測試裝置 110:電路板 120:連接端 130:Retimer晶片 140:回傳模組 141:控制板 142:回傳電路 200:主機板 210:待測主機板的插槽 220:中央處理器 S100~S300:步驟 100: Slot Continuity Test Set 110: circuit board 120: Connection end 130:Retimer Chip 140: Return Module 141: Control panel 142: Return circuit 200: Motherboard 210: Slot of the motherboard to be tested 220: CPU S100~S300: Steps
圖1顯示為本發明的插槽連通性測試裝置通過外部鏈路進行回傳時的一種結構示意圖;1 shows a schematic structural diagram of the slot connectivity test device of the present invention when backhauling is performed through an external link;
圖2顯示為本發明的插槽連通性測試裝置通過外部鏈路進行回傳時的另一種結構示意圖;FIG. 2 shows another structural schematic diagram of the slot connectivity test device of the present invention when backhauling is performed through an external link;
圖3顯示為本發明的插槽連通性測試裝置通過內部鏈路進行回傳時的一種結構示意圖;3 is a schematic structural diagram of the slot connectivity test device of the present invention when backhauling is performed through an internal link;
圖4顯示為本發明的插槽連通性測試裝置應用於主機板的插槽測試時的應用示意圖;4 is a schematic diagram illustrating the application of the slot connectivity testing device of the present invention to slot testing of a motherboard;
圖5顯示為本發明的插槽連通性測試方法於一實施例中的流程圖。FIG. 5 is a flowchart of the method for testing socket connectivity according to an embodiment of the present invention.
100:插槽連通性測試裝置 100: Slot Continuity Test Set
110:電路板 110: circuit board
120:連接端 120: Connection end
130:Retimer晶片 130:Retimer Chip
140:回傳模組 140: Return Module
141:控制板 141: Control panel
142:回傳電路 142: Return circuit
210:待測主機板的插槽 210: Slot of the motherboard to be tested
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