TW202224207A - LED element and manufacturing method thereof being provided with a support substrate, an upper layer, a bonding layer, an upper layer, a first semiconductor layer, an active layer, and a second semiconductor layer - Google Patents

Abstract

The subject of the present invention is to improve the wafer shear strength after chip formation in an LED element formed by producing an epitaxial layer on a support substrate other than the growth substrate. The LED element of the solution is provided with a support substrate made of Si, an upper layer formed on the support substrate, a bonding layer made of a metal material, an upper layer formed on the bonding layer, a first semiconductor layer of n-type or p-type, an active layer formed above the first semiconductor layer, and a second semiconductor layer formed above the active layer and having a conductivity type different from that of the first semiconductor layer. The support substrate has the (001) plane as one main surface and is of a rectangular plate shape having a side substantially parallel to the (110) direction and a side substantially parallel to the (1-10) direction. The second semiconductor layer has the (001) plane as one main surface. The (100) direction or the (010) direction of the second semiconductor layer is substantially parallel to the (110) direction of the support substrate.

Description

LED element and its manufacturing method

The present invention relates to an LED element and a method for manufacturing the same.

In recent years, semiconductor light-emitting elements having an emission wavelength in the infrared region with a wavelength of 1000 nm or more have been widely used for crime prevention, surveillance cameras, gas detectors, medical sensors, and industrial equipment.

A semiconductor light-emitting element having a light emission wavelength of 1000 nm or more has been generally manufactured by the following procedure (refer to Patent Document 1 described later). That is, on the InP substrate as the growth substrate, the semiconductor layer of the first conductivity type, the active layer (also referred to as the "light emitting layer") and the second conductivity type are sequentially epitaxially grown lattice-matched to the InP substrate. the semiconductor layer. After that, electrodes for injecting electric current are formed on the semiconductor wafer, and the wafer is cut and manufactured.

Conventionally, as a semiconductor light-emitting element having an emission wavelength of 1000 nm or more, there has been a development of a semiconductor laser element in advance. On the other hand, with regard to LED components, development is slower than that of laser components because there are not many uses.

However, in recent years, due to the widespread use of applications, an improvement in light output has also been gradually demanded for infrared LED elements. The InP substrate is the same as the GaAs substrate used in the visible light region, and exhibits a high refractive index of 3 or more. Therefore, if the light is to be extracted through the InP substrate, total reflection occurs due to the difference in refractive index at the interface with air, and the light extraction efficiency is limited to be low. Furthermore, since the thermal resistance of the InP substrate is large, the light output tends to be saturated during high-current driving. Under such circumstances, the structure disclosed in Patent Document 1 is not suitable for realizing an LED element having a high light output.

As a method of obtaining a higher light output than the structure disclosed in Patent Literature 1, for example, the structure disclosed in Patent Literature 2 is considered. That is, it is estimated that the structure achieved by removing the growth substrate after bonding the growth substrate to form the epitaxial layer on a support substrate (such as a Si substrate highly doped with B or the like) exhibiting high heat dissipation conductivity is effective. [Prior Art Literature] [Patent Literature]

[Patent Document 1] Japanese Patent Application Laid-Open No. 4-282875 [Patent Document 2] Japanese Patent Laid-Open No. 2013-030606

[The problem to be solved by the invention]

After removing the growth substrate, dicing for wafer formation is performed. After that, the wafer was mounted on a dry body using Ag paste. Here, as a result of intensive research by the inventors of the present application, it has been confirmed that, depending on the diced wafer, the bonding force with the Ag paste is weakened and sufficient die shear strength cannot be secured. If the wafer shear strength is low, it may not be able to be stably fixed to the dry body, and may also be a cause of poor electrical contact, which is not preferable.

The present invention has been made in view of the related problems, and an object of the present invention is to improve the wafer shear strength after wafer formation in an LED element formed by forming an epitaxial layer on a support substrate other than the growth substrate. [means to solve the problem]

The LED element of the present invention is characterized by having: The support substrate is made of Si; The bonding layer is formed on the upper layer of the aforementioned support substrate and is made of metal material; The n-type or p-type first semiconductor layer is formed on the upper layer of the aforementioned bonding layer; an active layer formed on the upper layer of the first semiconductor layer; and The second semiconductor layer is formed on the upper layer of the above-mentioned active layer, and the conductivity type is different from that of the above-mentioned first semiconductor layer; The above-mentioned support substrate is a rectangular plate having a side substantially parallel to the [110] direction and a side substantially parallel to the [1-10] direction with the (001) plane as one main surface; The second semiconductor layer has the (001) plane as one main surface, and the [100] direction or the [010] direction of the second semiconductor layer is substantially parallel to the [110] direction of the support substrate.

In this specification and the drawings, (hkl) described using three integers h, k, and l represents a plane orientation. In addition, [hkl] represents the normal direction of the surface (hkl). Here, h, k, and l are the same or different integers, and are called Miller indices. The "-" shown before the Miller index is the one shown on the head of the original number, which is called "superscript line", and is described before the Miller index in this specification and the drawings for convenience of description.

In this specification, a certain direction d1 and other directions d2 are "substantially parallel" means that the straight line Ld1 parallel to the direction d1 is completely parallel to the straight line Ld2 parallel to the direction d2, that is, the two straight lines (Ld1 , the angle formed by Ld2) is 0°, which also means that the angle formed by these two straight lines is less than 2°. Furthermore, when the direction d1 and the direction d2 are "substantially parallel", the angle formed by the straight line Ld1 parallel to the direction d1 and the straight line Ld2 parallel to the direction d2 is preferably 1.5° or less, more preferably 1° or less.

In this specification, the description of "GaInAsP" represents a mixed crystal of Ga, In, As, and P, and the description of the composition ratio is merely omitted. The same applies to other descriptions such as "AlGaInAs".

In this specification, "peak wavelength" refers to the wavelength in the emission spectrum at which the light output is the highest.

According to the conventional method, regarding the reason why the phenomenon of insufficient wafer shear strength occurs when the LED element formed into a wafer by dicing after peeling the growth substrate is mounted on a dry body, etc. It is examined as follows.

When bonding a growth substrate (for example, an InP substrate) for forming an epitaxial layer and a Si substrate as a support substrate, from the viewpoints of stable bonding strength and securing electrical conductivity, generally, the two substrates are separately formed by forming a film with solder or the like. The bonding layers are bonded to each other in the state of bonding layers made of metal.

After the growth substrate and the support substrate are bonded together, the epitaxial layer is left and the growth substrate is removed. After that, the wafer is chipped by dicing. Here, the epitaxial layer is mechanically fragile due to its thin film thickness, and if the epitaxial layer is cut, the epitaxial layer may be peeled off from the epitaxial layer, which may cause fatal damage to the device. Therefore, generally, before the dicing process, the epitaxial layer formed at the dicing position is removed by etching or the like (Mesa etching).

The epitaxial layer grown on the main surface of the growth substrate made of the InP substrate is, due to its chemical properties, along the [110] direction and the [1-10] direction of the original InP substrate, in other words, along the epitaxial layer. When etching is performed in the [110] direction and the [1-10] direction of the crystal layer, a shape with high linearity is obtained. That is, after the plateau etching process, cutting lines along the [110] direction and the [1-10] direction are formed. Therefore, the cutting process is carried out along the cutting line.

Furthermore, even in the case of using a GaAs substrate as the growth substrate, if the epitaxial layer is similarly etched along the [110] direction and the [1-10] direction, a shape with high linearity can be obtained. Therefore, the cutting process is also performed along the [110] direction and the [1-10] direction at this time.

However, on the growth substrate and the support substrate, generally, an orientation plane for confirming the crystal orientation is formed (hereinafter, the situation is roughly described as "OF (orientation flat)"). Conventionally, when a growth substrate and a support substrate are bonded together, a process of aligning the directions using the OF is often performed. OF is a growth substrate and a support substrate with the (001) plane as one main surface, and OF is generally formed on the (110) plane. Therefore, if the OF of the growth substrate and the OF of the support substrate are in the same direction and then bonded together, It is bonded in a state that the [110] direction of the growth substrate and the [110] direction of the support substrate face almost the same direction.

Therefore, when dicing the thus bonded support substrate, the [110] direction and the [1-10] direction of the support substrate which are almost parallel to the [110] direction and the [1-10] direction of the previously formed epitaxial layer are cut. 10] direction for cutting.

However, the cutting process is performed by cutting the support substrate with a high-speed rotating blade (typically, a diamond blade). In this case, cracks inevitably occur on the back surface side of the support substrate. There are several reasons for the occurrence of cracks. For example, it is estimated that abrasive grains (typically, diamond fine powder) of the insert contact the support substrate at high speed, chips are drawn into the cutting interface, and the insert has Rotation shaking (eccentricity), cutting different materials together (such as Si substrate and dicing tape, etc.), etc.

As a support substrate, a single crystal substrate of Si is generally used from the viewpoint of obtaining high electrical conductivity and high thermal conductivity. The single crystal substrate has splitting properties, and it is easy to split in the direction along the plane where the atoms are aligned (that is, the predetermined crystal orientation).

The crystal structure of Si is a diamond structure. Comparing the (110) plane and the (100) plane, two planes orthogonal to the (001) plane, the (110) plane has higher splitting properties than the (100) plane. Furthermore, the (110) plane, (-1-10) plane, (1-10) plane and ( The -110) planes are equal when the symmetry of the crystal is considered, and can be collectively referred to as {110} planes. Similarly, the (100) plane, the (-100) plane, the (010) plane, and the (0-10) plane are equal when the symmetry of the crystal is considered, and can be collectively referred to as {100} planes. Using this generic term, in the support substrate made of Si, the cleavage property of the {110} plane is higher than that of the {100} plane.

That is, when the support substrate made of Si is cut along the [110] direction and the [1-10] direction close to the support substrate, the direction of the cut becomes almost parallel to {110}, which has high splitting properties. face direction. As a result, the {110} plane which becomes the cut surface tends to be a smooth surface with low fixing effect.

In this state, when a conductive adhesive such as Ag paste is used to mount on a dry body or the like, the force of the conductive adhesive to bond to the surface of the support substrate tends to decrease. As a result, it is presumed that sufficient wafer shear strength cannot be obtained.

On the other hand, according to the LED element of the present invention, the second semiconductor layer forming the epitaxial layer is in a state where the (001) plane is the main surface similarly to the support substrate, and the [100] direction or the [010] direction of the second semiconductor layer ] direction is substantially parallel to the [110] direction of the support substrate. That is, the [110] direction of the second semiconductor layer and the [110] direction of the support substrate are substantially inclined by only 45°. In addition, here, 45° is essentially within the range of 45°±2° in consideration of the error during manufacture.

That is, since the [100] direction or the [010] direction of the second semiconductor layer is substantially parallel to the [110] direction of the support substrate, the directions of the dicing lines are the [110] direction and the [1] direction of the second semiconductor layer. The -10] direction is substantially inclined by 45° with respect to the [110] direction and the [1-10] direction of the support substrate. That is, the support substrate made of Si was cut along a dicing line substantially inclined by 45° with respect to the [110] direction and the [1-10] direction of the support substrate.

In this case, cracks formed during dicing tend to propagate along the [110] direction and the [1-10] direction of the support substrate. In addition, the Si substrate also exhibits high splitting properties with respect to the {111} plane ((111) plane, (1-11) plane, (-1-11) plane, (-111) plane, so that cracking is easy. Push in a direction parallel to the face. However, both the {110} plane and the {111} plane are inclined at an angle of 40° to 50° with respect to the {100} plane. Therefore, cleavage in other directions occurs before the cracks propagate to the larger cleavage surface, and many uneven portions formed by cracks of moderate size are formed on the surface of the support substrate. As a result, the fixing effect with respect to the conductive adhesive is improved, and the wafer shear strength is improved.

Furthermore, from the aforementioned viewpoint, the growth substrate on which the epitaxial layer is grown is not limited to the case of InP, and an LED element having an epitaxial layer grown on a growth substrate having the same crystal structure as InP in the cleavage orientation is used. , the same effect can be achieved. As an example, as the growth substrate, GaAs and GaP can be used in addition to InP. That is, in the LED element of the present invention, the first semiconductor layer, the active layer, and the second semiconductor layer may be any materials that can be lattice-matched to the aforementioned growth substrate. Since the emission wavelength of the LED element depends on the band gap energy of the constituent material of the active layer, the LED element of the present invention is not limited to an infrared LED element, and can be applied to an LED element in a part of the visible range.

As an example, when the growth substrate is an InP substrate, any one of the first semiconductor layer, the active layer, and the second semiconductor layer may belong to the group consisting of InP, GaInAsP, AlGaInAs, AlInAs, and InGaAs one or two or more of them. Any of these materials is a material that can be lattice matched to an InP substrate. With this structure, an LED element that generates infrared light having a peak wavelength of 1000 nm or more and less than 2000 nm can be realized.

As another example, when the growth substrate is a GaAs substrate, any one of the first semiconductor layer, the active layer, and the second semiconductor layer may belong to the group consisting of GaAs, AlGaInAs, AlGaAs, GaAsP, and GaP one or two or more of them. Any of these materials is a material that can be lattice matched to a GaAs substrate. With this structure, an LED element that generates visible light or near-infrared light with a peak wavelength of 600 nm or more and less than 1000 nm can be realized.

Preferably, the angle formed between the [100] direction or the [010] direction of the second semiconductor layer and the [110] direction of the support substrate is 2° or less. Furthermore, the angle is more preferably 1.5° or less, and particularly preferably 1° or less. The smaller the angle is, the closer the angle between the cutting direction of the support substrate and the [110] direction and the [1-10] direction of the support substrate is to 45°, so that it becomes easier to form minute irregularities on the surface of the support substrate, and more Improves wafer shear strength.

The LED element may include: a first electrode formed on the main surface of the support substrate, on the main surface opposite to the side where the bonding layer is formed; and a second electrode formed on the upper layer of the second semiconductor layer .

The aforementioned LED components may also have: The reflective layer is formed at the position of the upper layer of the aforementioned bonding layer, and the position of the lower layer of the aforementioned first semiconductor layer is made of a material with a higher reflectivity to the light generated in the aforementioned active layer than the aforementioned bonding layer; a dielectric layer formed at a position above the reflective layer and at a position below the first semiconductor layer; and The contact electrode penetrates through the dielectric layer in a direction perpendicular to the main surface of the support substrate in a partial region of the dielectric layer, and electrically connects the reflection layer and the first semiconductor layer.

According to this structure, among the light rays emitted from the active layer, the light rays traveling on the side of the support substrate can be returned to the side of the second semiconductor layer corresponding to the light extraction surface, thereby improving the light extraction efficiency.

Furthermore, if the purpose is only to return the light traveling on the support substrate side to the light extraction surface side, a structure in which the reflective layer directly contacts the entire surface of the first semiconductor layer (more specifically, the contact layer) may be used. However, in order to reduce the contact resistance of the contact layer made of a semiconductor material and the reflective layer made of a metal material, it is necessary to perform heat treatment on both. By this heat treatment, when a contact layer made of a semiconductor material and a reflective layer made of a metal material are brought into contact with each other for heat treatment, the metal material constituting the reflective layer and the contact layer are alloyed, resulting in a decrease in reflectance. According to a related point of view, the reflective layer cannot directly contact the contact layer. Therefore, from the viewpoint of ensuring electrical connection between the reflective layer and the contact layer, as in the above-mentioned structure, a through hole is provided in order to electrically connect the first semiconductor layer and the reflective layer while forming the reflective layer in the lower layer of the dielectric layer. Contact electrodes within the dielectric layer.

Although the reflectivity of the contact electrode is lower than that of the reflection layer, it is composed of a material that is easily alloyed with the contact layer and can realize low contact resistance. As an example, AuZn, AuBe, Au/Zn/Au layer structure or the like can be used for the contact electrode. In addition, the dielectric layer is appropriately selected from a material that exhibits insulating properties, high thermal stability, and high transmittance of light emitted from the active layer. As an example, SiO ₂ , SiN, Al ₂ O ₃ or the like can be used for the dielectric layer. Thereby, the light emitted from the active layer and traveling toward the support substrate passes through the region in the dielectric where the contact electrode is not formed, and is then reflected by the reflective layer formed thereunder and guided to the light extraction surface.

From the viewpoint of improving the light extraction efficiency, in the direction parallel to the (001) plane which is the main surface of the support substrate (hereinafter simply referred to as the "plane direction"), it is preferable to reduce the area of the region where the contact electrodes are formed as much as possible. On the other hand, if the area is too small, the path of the current flowing in the semiconductor layer will be concentrated in a part, and the resistance will increase. From a related viewpoint, it is preferable that the contact electrodes are formed at discrete plural places in the plane direction.

Furthermore, the present invention is a method of manufacturing an LED element having the aforementioned structure, characterized by having: Process (a) of preparing a growth substrate with the (001) plane as one of the main surfaces; Step (b) of sequentially epitaxially growing the second semiconductor layer, the active layer and the first semiconductor layer on the (001) surface of the growth substrate to form the epitaxial layer; Process (c) of preparing the aforementioned support substrate with the (001) plane as one of the main surfaces; While keeping the [110] direction of the support substrate substantially parallel to the [100] direction or the [010] direction of the growth substrate, the epitaxial layer formed on the growth substrate faces the side of the support substrate side. In the state, the process (d) of laminating the support substrate and the growth substrate; After the aforementioned process (d), the process (e) of peeling off the aforementioned growth substrate; and In a state where the support substrate side is fixed, from the epitaxial layer on the opposite side to the support substrate, along a direction substantially parallel to the [100] direction of the second semiconductor layer, and to the second semiconductor layer Process (f) of dicing in a direction substantially parallel to the [010] direction of the semiconductor layer.

In this way, the cutting direction of the cutting process in step (f) can be substantially inclined by 45° with respect to the [110] direction and the [1-10] direction of the support substrate where cracks are likely to propagate, so that it is easy to form on the surface of the support substrate Tiny bumps. Thereby, when the conductive adhesive is used for bonding to the dry body after that, the fixing effect between the conductive adhesive and the support substrate is improved, and the wafer shear strength is further improved.

The manufacturing method of the said LED element may have the process (h) of attaching to the said dry body using a conductive adhesive with the said support substrate side facing the dry body after the said process (f).

The step (d) is to adhere the support substrate and the growth substrate while maintaining the orientation plane on which the support substrate is to be formed and the orientation plane or index plane formed on the growth substrate to be substantially inclined by 45°. You can also. Here, the term "substantially 45°" refers to the error during manufacture as described above, and may be within the range of 45°±2°.

Furthermore, the manufacturing method of the LED element may further include the step (g) of forming the bonding layer on the upper layer of the epitaxial layer and the upper layer of the support substrate before the step (d); The aforementioned project (d) has: Preparing works for pushing and positioning members (d1); Carrying out the process (d2) of adjusting the directions of the support substrate and the growth substrate so that the [110] direction of the support substrate and the [100] direction or the [010] direction of the growth substrate are substantially parallel to each other; In order to maintain the direction adjusted by the process (d2), the process (d3) of pressing the support substrate and the growth substrate toward the positioning member by the pressing member; and Step (d4) of laminating the support substrate and the growth substrate through the bonding layer is performed while pressing the overlapping support substrate and the growth substrate while performing the step (d3).

Since this method suppresses the degree of freedom with respect to the rotation direction in the state where the two substrates are overlapped and aligned, cutting can be performed while maintaining the direction adjusted in the process (d2). [Effect of invention]

According to the present invention, in the LED element formed by forming the epitaxial layer on the support substrate other than the growth substrate, the chip shear strength after wafering can be improved.

Embodiments of the LED element and its manufacturing method of the present invention will be described with reference to the drawings. In addition, the following drawings illustrate the disclosure, and the dimension ratios in the drawings are not necessarily consistent with the actual dimension ratios. In addition, there are cases where the dimension ratios do not match between the drawings.

In this specification, the expression "the layer B is formed on the upper layer of the layer A" naturally includes the situation where the layer B is directly formed on the surface of the layer A, and also includes the situation where the layer B is formed on the surface of the layer A with a thin film interposed therebetween. the intent of the situation. In addition, the term "thin film" here refers to a layer having a thickness of 10 nm or less, and may preferably refer to a layer having a thickness of 5 nm or less.

FIG. 1 is a cross-sectional view schematically showing the structure of the LED element of the present embodiment. The LED element 1 shown in FIG. 1 includes the epitaxial layer 20 formed on the upper layer of the support substrate 11 . The LED element 1 shown in FIG. 1 corresponds to a schematic cross-sectional view taken along the XY plane at a predetermined position. In the following description, the XYZ coordinate system attached to FIG. 1 is appropriately referred to.

In addition, in the following description, when expressing directions, positive and negative directions are distinguished, such as "+X direction" and "-X direction", which are described with positive and negative signs. In addition, when the direction is expressed without distinguishing between positive and negative directions, it is only described as "X direction". That is, in this specification, when describing only the "X direction", both "+X direction" and "-X direction" are included. The same applies to the Y direction and the Z direction.

The LED element 1 of the present embodiment generates infrared light L in the epitaxial layer 20 (more specifically, in the active layer 25 described later). More specifically, as shown in FIG. 1 , the infrared light L ( L1 , L2 ) is extracted in the +Y direction with reference to the active layer 25 . As an example, the infrared light L is light having a peak wavelength of 1000 nm or more and 2000 nm or less.

[Element structure] Hereinafter, the structure of the LED element 1 will be described in detail.

(Supporting Substrate 11 ) The supporting substrate 11 is made of Si, and is doped with a dopant at a high concentration so as to exhibit conductivity. As an example, a Si substrate having a resistivity of 10 mΩcm or less is doped with B (boron) at a dopant concentration of 1×10 ¹⁹ /cm ³ or more. As the dopant, other than B (boron), for example, P, As, Sb, or the like can be used. Conductivity is ensured by doping the dopant at a high concentration. In addition, by using the Si substrate, high heat dissipation can be ensured, and the manufacturing cost can be reduced.

The thickness (length in the Y direction) of the support substrate 11 is not particularly limited, but is, for example, 50 μm or more and 500 μm or less, preferably 100 μm or more and 300 μm or less.

One main surface of the support substrate 11 is a (001) surface.

(Joint layer 13) The LED element 1 shown in FIG. 1 includes the bonding layer 13 formed on the upper layer of the support substrate 11 . The bonding layer 13 is made of a low melting point solder material, for example, Au, Au-Zn, Au-Sn, Au-In, Au-Cu-Sn, Cu-Sn, Pd-Sn, Sn, or the like. As will be described later with reference to FIG. 8A , the bonding layer 13 is used for bonding the growth substrate 3 and the support substrate 11 on which the epitaxial layer 20 is formed on the upper surface. The thickness of the bonding layer 13 is not particularly limited, but is, for example, 0.5 μm or more and 5.0 μm or less, preferably 1.0 μm or more and 3.0 μm or less.

(Barrier layer 14, Barrier layer 16) The LED element 1 shown in FIG. 1 includes barrier layers (14, 16). The barrier layers (14, 16) are provided for the purpose of suppressing the diffusion of the solder material constituting the bonding layer 13, and the material is not limited as long as the relevant functions can be achieved. For example, it can be realized using a material including Ti, Pt, or the like. As an example, it is composed of a Ti/Pt/Au laminate.

The thickness of the barrier layers (14, 16) is not particularly limited, but is, for example, 0.05 μm or more and 3 μm or less, preferably 0.2 μm or more and 1 μm or less.

In addition, in the LED element 1 shown in FIG. 1, although the barrier layer (14, 16) is formed, in this invention, whether the barrier layer (14, 16) is provided may be arbitrary.

(reflective layer 15) The LED element 1 shown in FIG. 1 includes the reflective layer 15 formed on the upper layer of the bonding layer 13 . The reflection layer 15 functions to guide the infrared light L2 traveling toward the support substrate 11 side (−Y direction) among the infrared light L generated in the active layer 25 in the +Y direction. The reflective layer 15 is made of a conductive material and has a high reflectance to infrared light L. As shown in FIG. The reflectivity of the reflection layer 15 to the infrared light L is preferably 70% or more, more preferably 80% or more, and particularly preferably 90% or more.

In the case where the peak wavelength of the infrared light L is 1000 nm or more and 2000 nm or less, a metal material such as Ag, Ag alloy, Au, Al, and Cu can be used for the reflection layer 15 . The material constituting the reflective layer 15 is appropriately selected according to the wavelength of the light generated in the active layer 25 .

The thickness of the reflection layer 15 is not particularly limited, but is, for example, 0.1 μm or more and 2.0 μm or less, preferably 0.3 μm or more and 1.0 μm or less.

As shown in FIG. 1 , by forming the barrier layer 14 between the reflective layer 15 and the bonding layer 13 , the material constituting the bonding layer 13 is diffused on the side of the reflective layer 15 , and the decrease in reflectance of the reflective layer 15 can be suppressed.

Furthermore, from the viewpoint of improving the light extraction efficiency, as shown in FIG. 1 , it is preferable that the LED element 1 includes the reflective layer 15 . In the present invention, whether or not the LED element 1 includes the reflective layer 15 is optional.

(Dielectric layer 17) The LED element 1 shown in FIG. 1 includes the dielectric layer 17 formed on the upper layer of the reflective layer 15 . The dielectric layer 17 is made of a material that exhibits electrical insulating properties and has high transmittance to infrared light L. As shown in FIG. The transmittance of the dielectric layer 17 to the infrared light L is preferably 70% or more, more preferably 80% or more, and particularly preferably 90% or more.

In the case where the peak wavelength of the infrared light L is 1000 nm or more and 2000 nm or less, a material such as SiO ₂ , SiN, Al ₂ O ₃ or the like can be used for the dielectric layer 17 . The material constituting the dielectric layer 17 is appropriately selected according to the wavelength of the light generated in the active layer 25 .

(Epitaxial layer 20) The LED element 1 shown in FIG. 1 includes the epitaxial layer 20 formed on the upper layer of the dielectric layer 17 . The epitaxial layer 20 is composed of a laminate of a plurality of layers. Specifically, the epitaxial layer 20 includes a contact layer 21 , a first cladding layer 23 , an active layer 25 , and a second cladding layer 27 . Each of the semiconductor layers ( 21 , 23 , 25 , 27 ) constituting the epitaxial layer 20 is composed of a material that is lattice-matched to the growth substrate 3 to be described later and can be epitaxially grown.

<<Contact Layer 21, First Coating Layer 23>> In this embodiment, the contact layer 21 is formed of, for example, p-type GaInAsP. The thickness of the contact layer 21 is not limited, but is, for example, 10 nm or more and 1000 nm or less, preferably 50 nm or more and 500 nm or less. In addition, the p-type dopant concentration of the contact layer 21 is preferably 5×10 ¹⁷ /cm ³ or more and 3×10 ¹⁹ /cm ³ or less, more preferably 1×10 ¹⁸ /cm ³ or more and 2×10 ¹⁹ / cm ³ or less.

In this embodiment, the first cladding layer 23 is formed on the upper layer of the contact layer 21, and is formed of, for example, p-type InP. The thickness of the first coating layer 23 is not limited, but is, for example, 1000 nm or more and 10000 nm or less, preferably 2000 nm or more and 5000 nm or less. The p-type dopant concentration of the first cladding layer 23 is preferably 1×10 ¹⁷ /cm ³ or more and 3×10 ¹⁸ /cm ³ or less, more preferably 5×10 ¹⁷ /cm ³ or more and 3×10 ¹⁸ /cm ³ or less.

As the p-type dopant material contained in the contact layer 21 and the first cladding layer 23, Zn, Mg, Be, etc. can be used, Zn or Mg is preferable, and Zn is particularly preferable. In this embodiment, the contact layer 21 and the first cladding layer 23 correspond to the "first semiconductor layer".

"Active Layer 25" In the present embodiment, the active layer 25 is formed of a semiconductor layer formed on the upper layer of the first cladding layer 23 . The active layer 25 is appropriately selected from a material that can generate light of a target wavelength, is lattice-matched to the growth substrate 3 described later with reference to FIGS. 4A and 4B , and can be epitaxially grown.

For example, when the LED element 1 that emits infrared light L with a peak wavelength of not less than 1000 nm and not more than 2000 nm is not realized, the active layer 25 may be a single-layer structure of GaInAsP, AlGaInAs, or InGaAs; The quantum well layer formed of InGaAs and the MQW (Multiple Quantum Well) structure of the barrier layer formed of GaInAsP, AlGaInAs, InGaAs, or InP having a larger band gap energy than the quantum well layer may be used.

When the active layer 25 has a single-layer structure, the film thickness of the active layer 25 is 50 nm or more and 2000 nm or less, preferably 100 nm or more and 300 nm or less. When the active layer 25 has an MQW structure, a quantum well layer and a barrier layer having a film thickness of 5 nm or more and 20 nm or less are laminated in a range of 2 cycles or more and 50 cycles or less.

The active layer 25 may be doped n-type or p-type, or may be undoped. When doping n-type, Si can be used as a dopant, for example.

<<Second Coating Layer 27 >> In this embodiment, the second coating layer 27 is formed on the upper layer of the active layer 25, and is formed of, for example, n-type InP. The thickness of the second coating layer 27 is not limited, but is, for example, 100 nm or more and 10000 nm or less, preferably 500 nm or more and 5000 nm or less. The n-type dopant concentration of the second cladding layer 27 is preferably 1×10 ¹⁷ /cm ³ or more and 5×10 ¹⁸ /cm ³ or less, more preferably 5×10 ¹⁷ /cm ³ or more and 4×10 ¹⁸ / cm ³ or less. As the n-type impurity material to be doped into the second cladding layer 27, Sn, Si, S, Ge, Se, etc. can be used, and Si is particularly desirable. The second cladding layer 27 corresponds to the "second semiconductor layer".

The first cladding layer 23 and the second cladding layer 27 are materials that do not absorb infrared light L generated in the active layer 25, and are lattice-matched to the growth substrate 3 (see FIGS. 4A and 4B to be described later), and can be epitaxy. The material for the crystal growth is appropriately selected. When an InP substrate is used as the growth substrate 3 , materials such as GaInAsP and AlGaInAs can be used as the first cladding layer 23 and the second cladding layer 27 in addition to InP.

(contact electrode 31) The LED element 1 shown in FIG. 1 is provided with the contact electrode 31 which penetrates the dielectric material layer 17 in the Y direction among plural places in the dielectric material layer 17, and is formed. The contact electrode 31 connects the contact layer 21 formed on the +Y side of the dielectric layer 17 and the reflective layer 15 formed on the -Y side of the dielectric layer 17 . That is, the reflective layer 15 is electrically connected to the first cladding layer 23 (first semiconductor layer) through the contact electrode 31 .

The contact electrode 31 is made of a material that can make ohmic contact with the contact layer 21 . As an example, the contact electrode 31 is made of materials such as Au/Zn/Au, AuZn, AuBe, and the like, and a plurality of these materials may be provided. These materials are relatively low in reflectivity to infrared light L compared to the materials constituting the reflective layer 15 .

The pattern shape of the contact electrode 31 when viewed in the Y direction is arbitrary. However, from the viewpoint of wide-ranging current flow in the active layer 25 in a direction parallel to the main surface (XY plane, (001) plane) of the support substrate 11 (hereinafter referred to as "plane direction"), the contact electrode 31 is a It is preferable to arrange a plurality of them dispersed in the plane direction.

The total area of all the contact electrodes 31 when observed in the Y-square is relative to the area of the epitaxial layer 20 (such as the active layer 25 ) in the plane direction, preferably 30% or less, more preferably 20% or less, 15% or less Particularly ideal. When the total area of the contact electrode 31 becomes relatively large, the infrared light L2 traveling from the active layer 25 to the support substrate 11 side (-Y direction) is absorbed by the contact electrode 31, resulting in a decrease in extraction efficiency. On the other hand, if the total area of the contact electrodes 31 is too small, the resistance value increases and the forward voltage increases.

(first electrode 33) The LED element 1 shown in FIG. 1 includes the first electrode 33 formed on the surface of the support substrate 11 opposite to the epitaxial layer 20 (the −Y side). The first electrode 33 makes ohmic contact with the support substrate 11 . As an example, the first electrode 33 is made of materials such as AuGe/Ni/Au, Pt/Ti, Ge/Pt, and the like, and may be composed of a plurality of these materials. The first electrode 33 is formed at a predetermined position on the back surface side of the support substrate 11, and may not necessarily be formed on the entire back surface.

(Second electrode 32) The LED element 1 shown in FIG. 1 includes the second electrode 32 formed on the upper layer of the second coating layer 27 . The second electrode 32 is preferably formed to extend in a lattice shape in the upper layer of the second coating layer 27 when viewed in the Y direction. Thereby, the current flowing in the active layer 25 can be diffused in the surface direction, and light can be emitted in a wide range of the active layer 25 . However, in the present invention, the pattern shape of the second electrode 32 is arbitrary.

As an example, the second electrode 32 is composed of materials such as Au/Zn/Au, AuZn, AuBe, and the like, and may be composed of a plurality of these materials.

(sheet electrode 34) The LED element 1 shown in FIG. 1 includes the sheet electrode 34 formed on the upper surface of the second electrode 32 . In addition, in FIG. 1, although the sheet-like electrode 34 is formed in the whole upper surface of the 2nd electrode 32, it is shown in figure, but this is for convenience of illustration. Actually, the sheet electrode 34 may be formed on the surface of a part of the second electrode 32 extending in the surface direction. The sheet electrode 34 is formed of, for example, Ti/Au, Ti/Pt/Au, or the like.

This sheet-like electrode 34 is provided for the purpose of securing a region that contacts the bonding wire for power supply, but in the present invention, whether or not the sheet-like electrode 34 is provided is optional.

[direction] The LED element 1 shown in FIG. 1 has a structure in a state of being turned into a wafer. That is, as will be described later with reference to FIG. 10B , a structure in a state where the wafer including the support substrate 11 is diced.

FIG. 2 is a diagram showing a plan view when only the support substrate 11 is extracted from the LED element 1 shown in FIG. 1 and viewed from the +Y side, with the crystal orientation using the Miller index added. As described above, the support substrate 11 is a Si substrate whose one main surface is the (001) plane. Here, it is assumed that the epitaxial layer 20 is formed on the (001) plane of the support substrate 11 . That is, in FIG. 2, the top view of the state in which the (001) surface of the support substrate 11 faces the +Y side is shown.

As shown in FIG. 2 , the support substrate 11 has a rectangular plate shape having sides substantially parallel to the [110] direction and sides substantially parallel to the [1-10] direction. That is, among the four sides constituting the support substrate 11, the two sides facing one pair are at an angle within a range of 2° or less with respect to the [110] direction of the support substrate 11, and the two sides facing the other pair are The [1-10] direction of the support substrate 11 is an angle within a range of 2° or less.

3A is a diagram showing a plan view when only the second cladding layer 27 (second semiconductor layer) is extracted from the LED element 1 shown in FIG. 1 and viewed from the +Y side with the addition of the crystal orientation using the Miller index .

As described later with reference to FIG. 5A , the epitaxial layer 20 including the second cladding layer 27 is formed by epitaxial growth on the growth substrate 3 having the (001) plane as the main plane. That is, each semiconductor layer constituting the epitaxial layer 20 is grown while maintaining the crystal orientation of the growth substrate 3 . Then, as described later with reference to FIGS. 8A and 8B , the growth substrate 3 is removed after being attached to the support substrate 11 with the epitaxial layer 20 facing the support substrate 11 side. That is, the main surface of the epitaxial layer 20 is the same (001) surface as that of the growth substrate 3, and this surface faces the support substrate 11 side. Therefore, FIG. 3A shows a plan view of a state in which the (00-1) plane on the back side faces the +Y side with respect to the (001) plane of the second coating layer 27 . However, the epitaxial layer 20 may be formed on the (00-1) plane of the growth substrate 3 .

As shown in FIGS. 2 and 3A , in the LED element 1 of the present embodiment, the [100] direction of the second coating layer 27 is substantially parallel to the [110] direction of the support substrate 11 . That is, the angle formed by the [100] direction of the second coating layer 27 and the [110] direction of the support substrate 11 is within a range of 2° or less. In addition, the angle formed by the [100] direction of the second coating layer 27 and the [110] direction of the support substrate 11 can be measured using, for example, an X-ray diffraction method (XRD method).

When evaluating the angle between the directions, the positive and negative directions of the directions are irrelevant. That is, the [110] direction and the [-1-10] direction are regarded as the same direction, and similarly, the [1-10] direction and the [-110] direction are regarded as the same direction.

That is, as shown in FIGS. 2 and 3A , the [110] direction of the second coating layer 27 of the LED element 1 of the present embodiment is substantially inclined by 45° with respect to the [110] direction of the support substrate 11 . This means that the [110] direction of each semiconductor layer constituting the epitaxial layer 20 is substantially inclined by 45° with respect to the [110] direction of the support substrate 11 .

The direction of one side of each semiconductor layer constituting the epitaxial layer 20, that is, the [110] direction is substantially inclined by 45° with respect to the [110] direction of the support substrate 11, which means that in the dicing process for waferization, the direction along the direction from the support The [110] direction of the substrate is slanted by 45° for cutting. As a result, cracks formed by cutting tend to propagate in a direction different from that of the cut surface. However, since the direction of the fractured surface is substantially more inclined by 45° than the direction with high splitting properties, the splitting in other directions occurs before the cracking advances to the larger splitting surface, and most of the cracks are moderately large. The concavo-convex portion is formed on the surface of the support substrate.

Thereby, the fixing effect with respect to the conductive adhesive is improved, and the wafer shear strength is improved. The point where the wafer shear strength is improved by the structure of the present invention will be described later with reference to Examples.

Furthermore, from the viewpoint of making the cutting direction a direction ([110] direction) with high cleavage to the support substrate 11 that is substantially inclined by 45°, as shown in FIG. The [010] direction of the crystal layer 20) and the [110] direction of the support substrate 11 (see FIG. 2) may be arranged at an angle within a range of 2° or less.

[Manufacturing method] An example of the manufacturing method of the above-mentioned LED element 1 is demonstrated with reference to each figure of FIG. 4A - FIG. 11. FIG. 4A, 5A-5C, 6A, 7, 8A, 9A-9E, and 10A-11 are cross-sectional views of a process in the manufacturing process. Other drawings will be described later.

(step S1) As shown in FIG. 4A , the growth substrate 3 is prepared. In the present embodiment, an InP substrate having a (001) plane as one main surface is desirably used. FIG. 4B is a plan view in which the (001) plane of the growth substrate 3 is the upper surface. Here, as an example, an InP substrate provided with an orientation plane (OF) and an index plane (IF) is used as the growth substrate 3 . The OF system is formed on the (110) surface of the growth substrate 3 , and the IF system is formed on the (1-10) surface of the growth substrate 3 .

In addition, the growth substrate 3 is not limited to InP as long as it can grow the epitaxial layer 20 to be formed in the next process, and GaAs or GaP may be used.

This step S1 corresponds to the process (a).

(step S2) As shown in FIG. 5A , the growth substrate 3 is transferred into an MOCVD (Metal Organic Chemical Vapor Deposition) apparatus, and on the (001) surface of the growth substrate 3, a buffer layer 29, an etch stop layer (ES layer) 28, a second The cladding layer 27 , the active layer 25 , the first cladding layer 23 and the contact layer 21 are epitaxially grown in sequence to form the epitaxial layer 20 . In this step S2, according to the material and film thickness of the layer to be grown, the type and flow rate of the raw material gas, the processing time, the ambient temperature, and the like are appropriately adjusted.

As an example, the buffer layer 29 is formed by forming n-type InP containing Si as a dopant with a predetermined film thickness (for example, about 500 nm), and then, the film material is different from the buffer layer with a predetermined film thickness (for example, about 200 nm). 29 (here, the InGaAs layer) to form the ES layer 28 . After that, the second cladding layer 27 , the active layer 25 , the first cladding layer 23 , and the contact layer 21 are formed in this order while the growth conditions are set so as to achieve the above-mentioned film thickness and composition.

This step S2 corresponds to the process (b).

(Step S3 ) After the wafer on which the epitaxial layer 20 is formed is taken out from the MOCVD apparatus, a dielectric layer 17 made of, for example, SiO ₂ is formed by a plasma CVD method (see FIG. 5B ). Next, a photoresist mask patterned by photolithography is formed on the surface of the dielectric layer 17 . After removing the dielectric layer 17 formed in the opening of the photoresist by an etching method using a predetermined chemical such as buffered hydrofluoric acid, a contact made of Au/Zn/Au is formed by an EB evaporation device, for example. The material film of the electrode 31 .

Next, after removing the photoresist mask, the material film formed in the unneeded region (but except for the desired region to be formed by the alignment marks described later) is peeled off to form the contact electrode 31 . At this time, an alignment mark made of the same material as the contact electrode 31 is formed on a part of the epitaxial layer 20 with the OF formed on the growth substrate 3 as a reference. Ideally, the alignment marks are provided at two or three or more positions sufficiently spaced apart from the region where the LEDs are to be formed in the surface direction of the growth substrate 3 . After that, ohmic contact between the contact layer 21 and the contact electrode 31 is achieved by applying an alloying treatment (annealing treatment) by, for example, a heat treatment at 450° C. for 10 minutes.

(step S4) As shown in FIG. 5C , the reflective layer 15 , the barrier layer 14 , and the bonding layer 13 a are formed in this order. For example, the reflective layer 15 is formed by depositing Al/Au with a predetermined thickness by an EB evaporation device, and then the barrier layer 14 is formed by depositing Ti/Pt/Au with a predetermined thickness. Next, Ti/Au is deposited to a predetermined thickness to form the bonding layer 13a. The bonding layer 13a may be made of the same material as the bonding layer 13 described above.

(step S5) As shown in FIG. 6A, another support substrate 11 different from the growth substrate 3 is prepared. In the present embodiment, a conductive Si substrate in which B (boron) is doped at a high concentration with the (001) plane as one main surface is used. The resistivity of the support substrate 11 is preferably less than 100 mΩ·cm (=1 mΩ·m).

FIG. 6B is a plan view in which the (001) plane of the support substrate 11 is the upper surface. Here, as the support substrate 11, a Si substrate in which an orientation plane (OF) is formed on the (110) plane is used as an example.

This step S5 corresponds to the process (c).

(step S6) As shown in FIG. 7 , the barrier layer 16 and the bonding layer 13 b are formed on the main surface of the support substrate 11 . The barrier layer 16 and the bonding layer 13b are formed by the same method as the barrier layer 14 and the bonding layer 13a described above in step S4.

This step S6 corresponds to the process (g). In addition, whether to form the barrier layer 16 is arbitrary.

(step S7) Next, as shown in FIG. 8A , the long substrate 3 and the support substrate 11 are bonded together through the bonding layers 13 ( 13 a , 13 b ). Ideally, the surfaces of the bonding layers 13 ( 13 a , 13 b ) are superimposed and aligned.

In this superimposition and alignment process, the positional relationship between the growth substrate 3 and the support substrate 11 is adjusted so that the positional relationship does not deviate. 8B and 8C are diagrams schematically showing an example of a method for maintaining the aligned state, and FIG. 8C is a diagram when FIG. 8B is viewed from the direction d1. Pressing members (53, 54) made of leaf springs, etc., and positioning members (51, 52) made of pins, etc. are prepared (process (d1)).

The pressing member 53 and the positioning member 51 are used for positioning the support substrate 11 (here, the Si substrate), and the pressing member 54 and the positioning member 52 are used for the positioning of the growth substrate 3 (here, the InP substrate). That is, as shown in FIG. 8C , the positioning member 51 is constituted by a pin or the like protruding from the base 58 with a height less than the thickness of the support substrate 11 . In addition, although not shown, the pressing member 53 is comprised so that the side area of the support substrate 11 may be pressed, but the growth substrate 3 may not be pressed. Also, as shown in FIG. 8C , the positioning member 52 is constituted by a pin or the like that pushes only the side surface of the growth substrate 3 , and the pressing member 54 is configured to press the side surface area of the growth substrate 3 without pressing the support substrate 11 . constituted in such a way.

Then, the OF of the growth substrate 3 (InP) and the OF of the support substrate 11 (Si) are adjusted to be substantially inclined by 45° (process (d2)). In other words, it is adjusted so that the [110] direction of the support substrate 11 and the [100] direction of the growth substrate 3 are substantially parallel (see FIG. 8B ).

In this state, the support substrate 11 is pressed by the pressing member 53 toward the positioning member 51 side by the external force f53 , and the growth substrate 3 is pressed by the pressing member 54 toward the positioning member 52 side by the external force f54 . Thereby, the [100] direction of the growth substrate 3 and the [110] direction of the support substrate 11 are held substantially parallel to each other (process (d3)).

This pressing is performed to maintain the [100] direction of the growth substrate 3 and the [110] direction of the support substrate 11 substantially parallel, and the wafer bonding apparatus is used to pressurize and raise the temperature (step (d4)). As a result, the bonding layer 13a on the growth substrate 3 and the bonding layer 13b on the support substrate 11 are melted and integrated (bonding layer 13) to bond the two substrates. As a result, after the growth substrate 3 and the support substrate 11 are bonded together, the [100] direction of the growth substrate 3 and the [110] direction of the support substrate 11 also become substantially parallel. In other words, the [110] direction of the growth substrate 3 and the [110] direction of the support substrate 11 are substantially inclined by 45°.

This step S7 corresponds to the process (d).

(step S8) As shown in FIG. 9A , the growth substrate 3 is removed. As an example, the growth substrate 3 is removed by immersing the joined substrates in a hydrochloric acid-based etchant. At this time, since the ES layer 28 formed of a different material from the growth substrate 3 and the buffer layer 29 is insoluble in the hydrochloric acid-based etchant, the etching process is stopped when the ES layer 28 is exposed.

This step S8 corresponds to the process (e).

(step S9) As shown in FIG. 9B , the ES layer 28 is removed to expose the second coating layer 27 . For example, after washing with pure water as necessary, the ES layer 28 is removed by dipping in a predetermined chemical solution that is soluble in the ES layer 28 and insoluble in the second coating layer 27 . As an example, a mixed solution (SPM) of sulfuric acid and hydrogen peroxide water can be used.

(step S10) As shown in FIG. 9C , the second electrode 32 is formed on the surface of the exposed second coating layer 27 . More specifically, a photoresist mask patterned by photolithography is formed on the surface of the second coating layer 27 based on the alignment marks formed in step S3. Next, a material for forming the second electrode 32 (for example, Au/Ge/Au) is formed into a film by an EB vapor deposition apparatus, and then the second electrode 32 is formed by lift-off. After that, in order to realize the ohmic contact property of the second electrode 32 , an alloying treatment (annealing treatment) is applied by, for example, a heat treatment at 450° C. for 10 minutes.

Next, sheet electrodes 34 are formed at predetermined positions on the upper surface of the second electrodes 32 . At this time, like the second electrode 32, it can be realized by the film formation by the EB vapor deposition apparatus and the peeling process.

(step S11) As shown in FIG. 9D , plateau etching is performed on the epitaxial layer 20 . More specifically, a photoresist patterned by a photolithography method is formed on the basis of the calibration marks formed in step S3. Specifically, a photoresist having branched opening regions along the [110] direction and the [1-10] direction of the second cladding layer 27 is formed. Next, using the photoresist as a mask, etching is performed with a predetermined etchant to etch a predetermined portion of the epitaxial layer 20 to expose the dielectric layer 17 . After that, the photoresist is removed with a cleaning solution such as acetone.

Through this process, cutting lines along the [110] direction and the [1-10] direction are formed in the epitaxial layer 20 .

(step S12) As shown in FIG. 9E , after adjusting the thickness of the back surface side of the support substrate 11 , the first electrodes 33 are formed on the back surface side of the support substrate 11 . As a specific method of forming the first electrode 33 , as with the second electrode 32 , a material for forming the first electrode 33 (eg, Ti/Pt/Au) is formed by an EB vapor deposition apparatus, and then can be formed by lift-off.

In addition, the adjustment of the thickness of the back surface side of the support substrate 11 can be performed as needed, and it is not necessarily a necessary process. In addition, the degree of thickness is appropriately set according to the application and the like.

(step S13) Wafering is performed by dicing each of the support substrates 11 . This process will be described with reference to FIGS. 10A and 10B .

FIG. 10A is a diagram schematically showing a cross-section of the wafer at the time point when step S12 is completed. By performing the plateau etching process in step S11 , dicing lines 38 for distinguishing each element are formed on the epitaxial layer 20 , and each epitaxial layer 20 is respectively formed on the common support substrate 11 .

In this state, for example, using a diamond knife or the like, dicing is performed together with the support substrate 11 along the dicing line 38 formed in step S11 (see FIG. 10B ). More specifically, the blade 41 is inserted to perform dicing in a state where the back surface side (the first electrode 33 side) of the support substrate 11 is attached to the dicing tape 40 and fixed. At this time, the cutting thickness of the dicing tape 40 (cutting depth wd40 ) is appropriately set.

After cutting, the cutting chips are removed by appropriate cleaning and other processes.

At a time point before the start of step S13 , cutting lines 38 along the [110] direction and the [1-10] direction are formed on the epitaxial layer 20 . Then, in step S7, the support substrate 11 and the growth substrate 3 are bonded together so that the [100] direction of the growth substrate 3 and the [110] direction of the support substrate 11 are substantially parallel. That is, in a state where the [110] direction of the epitaxial layer 20 and the [110] direction of the support substrate 11 are substantially inclined by 45°, the process is carried out along the [110] direction and the [1-10] direction of the epitaxial layer 20 . cut.

Thereby, the support substrate 11 is also diced along the dicing lines 38 that are substantially inclined by 45° with respect to the [110] direction and the [1-10] direction with respect to the support substrate 11 . The dicing direction is substantially inclined by 45° with respect to the direction parallel to the highly cleavable {110} plane of the support substrate 11 , and the cleavage in other directions occurs before the cleavage generated during dicing is advanced to the larger cleavage plane. , many concavo-convex portions formed by cracks of moderate size are formed on the surface of the support substrate 11 .

This step S13 corresponds to the process (f).

(step S14) The wafered LED element 1 is mounted on a dry body 61 or the like using a conductive adhesive 62 such as Ag paste (see FIG. 11 ). As described above, the surface of the support substrate 11 is formed with minute concavo-convex portions, so that the Ag paste has a fixing effect and high wafer shear strength is ensured.

This step S14 corresponds to the process (h).

[verify] Hereinafter, an embodiment is used to verify the improvement of the chip shear strength according to the aforementioned LED element.

(Example 1) The LED element manufactured by the method of the above-mentioned steps S1-S13 was set as Example 1. Here, in step S7, the bonding is performed in a state adjusted and held so that the OF of the growth substrate 3 (InP) and the OF of the support substrate 11 (Si) are approximately 45°. At this time, the angle formed between the [110] direction of the growth substrate 3 and the [110] direction of the support substrate 11 was 45.3°. This angle is measured by a metal microscope equipped with a coordinate measurement function.

In addition, in step S13, the dicing pitch (that is, the corresponding wafer width) is set to 350 μm. The width of the notch (cutting groove) formed in the support substrate 11 after the completion of step S13 was 30 μm on average.

Furthermore, in step S11, the plateau etching is performed according to the alignment mark attached to the epitaxial layer 20 in step S3, so the direction of the plateau etching (direction of the cutting line) is the [110] direction and the [110] direction of the growth substrate 3. The deviation in the 1-10] direction is suppressed within a range of ±0.3°, and the [110] direction and the [1-10] direction of the growth substrate 3 can be regarded as the same direction.

(Example 2) The LED element manufactured by the method similar to Example 1 except having eased the precision of the alignment adjustment in step S7 was set as Example 2. At this time, the angle formed between the [110] direction of the growth substrate 3 and the [110] direction of the support substrate 11 was 43.3°.

(Comparative Example 1) Except in step S7, the jigs such as the positioning member 51 and the pressing member 52 are not used, and the bonding is performed only after the OF of the growth substrate 3 (InP) and the OF of the support substrate 11 (Si) are in the same direction. Other than that, the LED element manufactured by the same method as Example 1 was used as Comparative Example 1. At this time, the angle formed between the [110] direction of the growth substrate 3 and the [110] direction of the support substrate 11 was 4.0°.

12A to 12B are photographs of the back surface side of the support substrate 11 included in the LED elements of each of Example 1 and Comparative Example 1. FIG. Specifically, after attaching the sheet electrode 34 side of the LED element to a dicing tape different from the dicing tape 40 used in step S13, the dicing tape 40 is peeled off, and each LED is observed with a ranging microscope from the first electrode 33 side. photo of components.

In any of the photographs, the rectangular-shaped regions are wafer portions, and the margins correspond to the gaps between adjacent wafers after being diced. Compared with the photograph of FIG. 12B , the photograph of FIG. 12A confirms that many concavities and convexities of the folded shape are formed in the marginal region.

(test) The LED elements of Examples 1 to 2 and Comparative Example 1 manufactured through the processes up to step S13 were mounted on the iron body plated with Ag paste Ag in the same manner as in step S14 (see FIG. 11 ). With respect to the mounted LED elements (the number of samples was 48, respectively), a wafer shear test was performed by a method according to IEC60749-19. The results are disclosed in Table 1 below.

Compared with Example 1 and Example 2, it can be seen that the wafer shear strength of Comparative Example 1 is low. From this, according to the LED elements of Example 1 and Example 2, it can be seen that the bonding force to the conductive adhesive is improved by forming fine irregularities on the surface of the support substrate 11 after dicing, and the wafer shear strength is also improved.

Furthermore, for the sake of prudence, t(94)=-6.6, P=2×10 ^-9 after the t-test of the two-sided test was performed for each data of Example 1 and Comparative Example 1 at a significance level of 5%. Thereby, it can be judged that Example 1 and Comparative Example 1 have a superiority gap. In addition, after performing the t-test of the two-sided test with the significance level of 5% for each data of Example 2 and Comparative Example 1, t(94)=-3.6, P=4×10 ^-4 . Thereby, it can be judged that Example 2 is superior to Comparative Example 1.

[Other Embodiments] Hereinafter, other embodiments will be described.

<1> In the LED element 1 shown in FIG. 1 , a concavo-convex portion may be formed on the surface of the second coating layer 27 on the +Y side. The formation of the concavo-convex portion reduces the amount of infrared light L( L1 , L2 ) traveling in the +Y direction from the active layer 25 reflected on the surface of the second cladding layer 27 to the active layer 25 side, thereby improving light extraction efficiency.

The concave-convex portion is formed by applying wet etching to the surface of the second coating layer 27 in the region where the second electrode 32 is not formed, for example, after step S10.

<2> Each of the above-mentioned steps S1 to S14 may be appropriately changed in the order as long as it does not affect the manufacture of the LED element 1 .

<3> In the above-mentioned step S7, the positioning member 51 and the pressing member 52 are used, and the bonding is performed while maintaining the aligned state. However, the method of holding the state of the alignment is not limited to this method. As another method, any method may be used as long as the alignment can be performed with higher accuracy than the alignment by visual inspection. For example, a bonding aligner (Bond aligner) can be used to align the alignment plane and the alignment mark. method etc.

1: LED components 3: Growth substrate 11: Support substrate 13: Bonding layer 13a: Bonding layer 13b: Bonding layer 14: Barrier layer 15: Reflective layer 16: Barrier layer 17: Dielectric layer 20: Epitaxy layer 21: Contact layer 23: The first coating layer 25: Active layer 27: Second coating 28: ES layer 29: Buffer layer 31: Contact electrode 32: Second electrode 33: The first electrode 34: Sheet electrode 38: Cutting Line 40: Cutting Tape 41: Blade 51: Positioning components 52: Positioning components 53: Push member 54: Push member 58: Pedestal 61: dry body 62: Conductive Adhesive f53, f54: external force L, L1, L2: Infrared light wd40: cutting depth

1 is a cross-sectional view schematically showing the structure of one embodiment of the LED element of the present invention. [ Fig. 2] Fig. 2 is a diagram showing a plan view when only the support substrate 11 is extracted from Fig. 1 and viewed from the +Y side with the addition of the crystal orientation using the Miller index. 3A is a diagram showing a plan view when only the second coating layer 27 is extracted from FIG. 1 and viewed from the +Y side with the addition of the crystal orientation using the Miller index. 3B is another diagram showing a plan view when only the second coating layer 27 is extracted from FIG. 1 and viewed from the +Y side with the addition of the crystal orientation using the Miller index. 4A is a cross-sectional view for explaining a process of the manufacturing method of the LED element shown in FIG. 1 . [ FIG. 4B ] A plan view in which the (001) plane of the growth substrate 3 is the upper surface. 5A is a cross-sectional view for explaining a process of the manufacturing method of the LED element shown in FIG. 1 . 5B is a cross-sectional view for explaining a process of the manufacturing method of the LED element shown in FIG. 1 . 5C is a cross-sectional view for explaining a process of the manufacturing method of the LED element shown in FIG. 1 . 6A is a cross-sectional view for explaining a process of the manufacturing method of the LED element shown in FIG. 1 . [ FIG. 6B ] A plan view in which the (001) surface of the support substrate 11 is the upper surface. [ Fig. 7] Fig. 7 is a cross-sectional view for explaining a process of the manufacturing method of the LED element shown in Fig. 1 . 8A is a cross-sectional view for explaining a process of the manufacturing method of the LED element shown in FIG. 1 . 8B is a diagram schematically showing an example of a method for maintaining the state of alignment of the growth substrate 3 and the support substrate 11 . [ Fig. 8C ] A schematic diagram when the state shown in Fig. 8B is viewed from the direction d1. 9A is a cross-sectional view for explaining a process of the manufacturing method of the LED element shown in FIG. 1 . 9B is a cross-sectional view for explaining a process of the manufacturing method of the LED element shown in FIG. 1 . 9C is a cross-sectional view for explaining a process of the manufacturing method of the LED element shown in FIG. 1 . 9D is a cross-sectional view for explaining a process of the manufacturing method of the LED element shown in FIG. 1 . 9E is a cross-sectional view for explaining a process of the manufacturing method of the LED element shown in FIG. 1 . 10A is a cross-sectional view for explaining a process of the manufacturing method of the LED element shown in FIG. 1 . 10B is a cross-sectional view for explaining a process of the manufacturing method of the LED element shown in FIG. 1 . [ Fig. 11] Fig. 11 is a cross-sectional view for explaining a process of the manufacturing method of the LED element shown in Fig. 1 . 12A is a photograph of the back side of the support substrate 11 of the LED element of Example 1. [ FIG. 12B is a photograph of the back side of the support substrate 11 of the LED element of Comparative Example 1. [ FIG.

1: LED components

11: Support substrate

13: Bonding layer

14: Barrier layer

15: Reflective layer

16: Barrier layer

17: Dielectric layer

20: Epitaxy layer

21: Contact layer

23: The first coating layer

25: Active layer

27: Second coating

31: Contact electrode

32: Second electrode

33: The first electrode

34: Sheet electrode

L, L1, L2: Infrared light

Claims (12)

An LED element is characterized by having: The support substrate is made of Si; The bonding layer is formed on the upper layer of the aforementioned support substrate and is made of metal material; The n-type or p-type first semiconductor layer is formed on the upper layer of the aforementioned bonding layer; an active layer formed on the upper layer of the first semiconductor layer; and The second semiconductor layer is formed on the upper layer of the above-mentioned active layer, and the conductivity type is different from that of the above-mentioned first semiconductor layer; The above-mentioned support substrate is a rectangular plate having a side substantially parallel to the [110] direction and a side substantially parallel to the [1-10] direction with the (001) plane as one main surface; The second semiconductor layer has the (001) plane as one main surface, and the [100] direction or the [010] direction of the second semiconductor layer is substantially parallel to the [110] direction of the support substrate. The LED element according to claim 1, wherein, The angle formed between the [100] direction or the [010] direction of the second semiconductor layer and the [110] direction of the support substrate is 2° or less. The LED element according to claim 1 or 2, comprising: a first electrode, which is formed on the main surface of the support substrate, on the main surface on the opposite side to the side where the bonding layer is formed; and The second electrode is formed on the upper layer of the second semiconductor layer. The LED element according to claim 3, further comprising: The reflective layer is formed at the position of the upper layer of the aforementioned bonding layer, and the position of the lower layer of the aforementioned first semiconductor layer is made of a material with a higher reflectivity to the light generated in the aforementioned active layer than the aforementioned bonding layer; a dielectric layer formed at a position above the reflective layer and at a position below the first semiconductor layer; and The contact electrode penetrates through the dielectric layer in a direction perpendicular to the main surface of the support substrate in a partial region of the dielectric layer, and electrically connects the reflection layer and the first semiconductor layer. The LED element according to claim 1 or 2, wherein, Each of the first semiconductor layer, the active layer, and the second semiconductor layer is made of a material that can be lattice-matched to a growth substrate made of InP. The LED element according to claim 1 or 2, wherein, Each of the first semiconductor layer, the active layer, and the second semiconductor layer is composed of one or more of the group consisting of InP, GaInAsP, AlGaInAs, AlInAs, and InGaAs. The LED element according to claim 1 or 2, wherein, The above-mentioned active layer generates infrared light with a peak wavelength of 1000 nm or more and less than 2000 nm. A method for manufacturing an LED element, which is the method for manufacturing an LED element according to claim 1, characterized by comprising: Process (a) of preparing a growth substrate with the (001) plane as one of the main surfaces; Step (b) of sequentially epitaxially growing the second semiconductor layer, the active layer and the first semiconductor layer on the (001) surface of the growth substrate to form the epitaxial layer; Process (c) of preparing the aforementioned support substrate with the (001) plane as one of the main surfaces; While keeping the [110] direction of the support substrate substantially parallel to the [100] direction or the [010] direction of the growth substrate, the epitaxial layer formed on the growth substrate faces the side of the support substrate side. In the state, the process (d) of laminating the support substrate and the growth substrate; After the aforementioned process (d), the process (e) of peeling off the aforementioned growth substrate; and In a state where the support substrate side is fixed, from the epitaxial layer on the opposite side to the support substrate, along a direction substantially parallel to the [100] direction of the second semiconductor layer, and to the second semiconductor layer Process (f) of dicing in a direction substantially parallel to the [010] direction of the semiconductor layer. The method for manufacturing an LED element according to claim 8, comprising: After the above-mentioned process (f), the process (h) of the above-mentioned dry body is mounted using a conductive adhesive with the support substrate side facing the dry body. The manufacturing method of the LED element as described in claim 8 or 9, wherein, The step (d) is to adhere the support substrate and the growth while maintaining the orientation plane formed on the support substrate and the orientation plane or index plane formed on the growth substrate in a state of being substantially inclined by 45°. substrate. The method for manufacturing an LED element according to claim 8 or 9, comprising: Before the process (d), the process (g) of forming the bonding layer on the upper layer of the epitaxial layer and the upper layer of the support substrate; The aforementioned project (d) has: Preparing works for pushing and positioning members (d1); Carrying out the process (d2) of adjusting the directions of the support substrate and the growth substrate so that the [110] direction of the support substrate and the [100] direction or the [010] direction of the growth substrate are substantially parallel to each other; In order to maintain the direction adjusted by the process (d2), the process (d3) of pressing the support substrate and the growth substrate toward the positioning member by the pressing member; and Step (d4) of laminating the support substrate and the growth substrate through the bonding layer is performed while pressing the overlapping support substrate and the growth substrate while performing the step (d3). The manufacturing method of the LED element as described in claim 8 or 9, wherein, The aforementioned growth substrate is an InP substrate; Each of the first semiconductor layer, the active layer, and the second semiconductor layer is made of a material that can be lattice matched to the growth substrate made of InP.

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