JP2022087393A - Led element and method of manufacturing the same - Google Patents

Abstract

To improve a die shear strength after being cut into chips in an LED element formed with an epitaxial layer on a support substrate different from a growth substrate.SOLUTION: An LED element 1 comprises: a support substrate 11 made of Si; a bonding layer 13 formed on an upper layer of the support substrate and made of a metal material; an n-type or p-type first semiconductor layer formed on an upper layer of the bonding layer; an active layer 25 formed on an upper layer of the first semiconductor layer; and a second semiconductor layer formed on an upper layer of the active layer and having a different conductivity type from that of the first semiconductor layer. The support substrate has a (001) plane as one principal surface, and has a rectangular plate-like shape which has a side substantially parallel to a [110] direction and a side substantially parallel to a [1-10] direction. The second semiconductor layer has a (001) plane as one principal surface, and a [100] direction or a [010] direction of the second semiconductor layer is substantially parallel to the [110] direction of the support substrate.SELECTED DRAWING: Figure 1

Description

The present invention relates to an LED element and a method for manufacturing the same.

In recent years, semiconductor light emitting elements having an infrared wavelength of 1000 nm or more as a light emitting wavelength have been widely used in applications such as crime prevention / surveillance cameras, gas detectors, medical sensors, and industrial equipment.

A semiconductor light emitting device having a light emitting wavelength of 1000 nm or more has been generally manufactured by the following procedure (see Patent Document 1 below). That is, on the InP substrate as a growth substrate, a first conductive type semiconductor layer, an active layer (sometimes referred to as a "light emitting layer"), and a second conductive type semiconductor that are lattice-matched to the InP substrate. The layers are sequentially epitaxially grown. After that, an electrode for current injection is formed on the semiconductor wafer, and the electrode is cut into chips to manufacture the wafer.

Conventionally, as a semiconductor light emitting device having a light emitting wavelength of 1000 nm or more, the development of a semiconductor laser device has been advanced in advance. On the other hand, LED elements have not been developed as much as laser elements because they have not been used so much.

However, in recent years, with the spread of applications, it has become necessary to improve the optical output of infrared LED elements. The InP substrate has a high refractive index of 3 or more, similar to the GaAs substrate used in the visible light region. Therefore, when light is taken out through the InP substrate, total reflection occurs due to the difference in refractive index at the interface with air, and the light extraction efficiency is low and limited. Further, since the InP substrate has a large thermal resistance, the optical output tends to be saturated in a large current drive. Under these circumstances, the structure disclosed in Patent Document 1 is unsuitable for realizing an LED element that obtains a high light output.

As a method of obtaining a light output higher than that of the structure disclosed in Patent Document 1, for example, adoption of the structure disclosed in Patent Document 2 can be considered. That is, it is realized by attaching a growth substrate on which an epitaxial layer is formed to a conductive support substrate (such as a Si substrate in which B or the like is doped with a high concentration) showing high heat dissipation, and then removing the growth substrate. It is considered that the above-mentioned structure is effective.

Japanese Unexamined Patent Publication No. 4-282875 Japanese Unexamined Patent Publication No. 2013-030606

After the growth substrate is removed, dicing for chipping is performed. The chip is then mounted on the stem using Ag paste or the like. Here, as a result of diligent research by the present inventor, it was confirmed that the bonding force with the Ag paste is weakened depending on the diced chip, and sufficient die share strength cannot be secured. If the die share strength is low, it may not be stably fixed to the stem, which may cause electrical contact failure, which is not preferable.

In view of the above problems, an object of the present invention is to improve the die share strength after chipping in an LED element in which an epitaxial layer is formed on a support substrate different from the growth substrate.

The LED element according to the present invention is
A support board made of Si and
A bonding layer formed on the upper layer of the support substrate and made of a metal material,
An n-type or p-type first semiconductor layer formed on the upper layer of the bonding layer,
The active layer formed on the upper layer of the first semiconductor layer and
A second semiconductor layer formed on the upper layer of the active layer and having a different conductive type from the first semiconductor layer is provided.
The support substrate exhibits a rectangular plate shape having a (001) plane as one main surface and having sides substantially parallel to the [110] direction and sides substantially parallel to the [1-10] direction. ,
The second semiconductor layer has a (001) plane as one main surface, and the [100] direction or the [010] direction of the second semiconductor layer is substantially parallel to the [110] direction of the support substrate. It is characterized by being.

In the present specification and drawings, notation (hkl) using three integers h, k, l indicates a plane orientation. Further, [hkl] indicates the normal direction of the plane (hkl). Here, h, k and l are the same or different integers and are called the Miller index. The "-" that appears before the Miller index is originally represented above the number and is called a "bar", but for convenience of notation, it appears before the Miller index in the present specification and drawings. It is written in.

In the present specification, "substantially parallel" in one direction d1 and another direction d2 means that the straight line Ld1 parallel to the direction d1 and the straight line Ld2 parallel to the direction d2 are completely parallel, that is, Not only when the angle formed by these two straight lines (Ld1 and Ld2) is 0 °, it means that the angle formed by these two straight lines is 2 ° or less. When the direction d1 and the direction d2 are "substantially parallel", the angle formed by the straight line Ld1 parallel to the direction d1 and the straight line Ld2 parallel to the direction d2 is preferably 1.5 ° or less. , More preferably 1 ° or less.

In the present specification, the description "GaInAsP" means that it is a mixed crystal of Ga, In, As and P, and the description of the composition ratio is simply omitted. The same applies to other descriptions such as "AlGaInAs".

As used herein, the term "peak wavelength" refers to the wavelength with the highest light output in the emission spectrum.

The reason why the phenomenon that the die share strength is insufficient when the LED element chipped by dicing after the growth substrate and the support substrate are pasted together by the conventional method and then mounted on the stem etc. has occurred. The inventor considers as follows.

When bonding a growth substrate (for example, an InP substrate) on which an epitaxial layer is formed and a Si substrate as a support substrate, a metal such as solder is attached to both substrates from the viewpoint of ensuring stable bonding strength and conductivity. It is usual that these bonding layers are bonded to each other in a state where the bonding layers made of silicon are formed into a film.

After the growth substrate and the support substrate are bonded together, the growth substrate is removed leaving an epitaxial layer. After that, the wafer is made into chips by dicing. Here, since the epitaxial layer has a thin film thickness and is mechanically fragile, if the epitaxial layer is cut, fatal damage to the device such as film peeling from the epitaxial layer is caused. It can occur. Therefore, before the dicing step, it is usual to remove the epitaxial layer formed at the relevant portion of dicing by etching or the like in advance (mesa etching).

The epitaxial layer grown on the main surface of the growth substrate made of the InP substrate is, due to its chemical properties, along the [110] and [1-10] directions of the original InP substrate, in other words, the epitaxial layer. Etching along the [110] and [1-10] directions gives a highly linear shape. That is, after the mesa etching step, dicing lines along the [110] direction and the [1-10] direction are formed. Therefore, the dicing step is performed along this dicing line.

Even when a GaAs substrate is used as the growth substrate, if the epitaxial layer is similarly etched along the [110] direction and the [1-10] direction, a highly linear shape can be obtained. Therefore, in this case as well, the dicing step is executed along the [110] direction and the [1-10] direction.

By the way, in general, an orientation flat (hereinafter, may be abbreviated as "OF") for confirming the crystal orientation is formed on the growth substrate or the support substrate. Conventionally, when the growth substrate and the support substrate are bonded to each other, a step of aligning the orientation using this OF is often performed. As for the OF, since the OF is generally formed on the (110) plane on the growth substrate or the support substrate having the (001) plane as one main surface, the OF of the growth substrate and the OF of the support substrate are used. When they are bonded in the same direction, they are bonded in a state where the [110] direction of the growth substrate and the [110] direction of the support substrate are oriented in substantially the same direction.

Therefore, when dicing is performed on the support substrates bonded in this way, the support substrate [110] is substantially parallel to the [110] direction and the [1-10] direction of the previously formed epitaxial layer. ] Direction and the direction close to the [1-10] direction will be diced.

By the way, the dicing step is performed by cutting the support substrate with a blade (typically a diamond blade) that rotates at high speed. At this time, chipping inevitably occurs on the back surface side of the support substrate. There are several possible reasons for chipping. For example, the abrasive grains of the blade (typically fine powder of diamond) come into contact with the support substrate at high speed, cutting chips are caught in the cutting interface, and the blade The reason may be that there is rotational fluctuation (eccentricity), that different materials (for example, Si substrate and dicing tape, etc.) are cut together.

As the support substrate, a Si single crystal substrate is generally used from the viewpoint of obtaining high conductivity and high thermal conductivity. The single crystal substrate is cleavable and easily cleaves in a direction along a plane in which the atomic arrangement is aligned (that is, a predetermined crystal orientation).

The crystal structure of Si is a diamond structure, and when comparing the (110) plane and the (100) plane, which are two planes orthogonal to the (001) plane, the (110) plane has more cleavage than the (100) plane. high. The (110) plane, the (-1-10) plane, the (1-10) plane, and the (-110) plane are equivalent in view of the symmetry of the crystal, and can be collectively referred to as the {110} plane. .. Similarly, the (100) plane, the (-100) plane, the (010) plane, and the (0-10) plane are equivalent in view of the symmetry of the crystal, and can be collectively referred to as the {100} plane. Using this generic notation, in a support substrate made of Si, the {110} plane has higher cleavage than the {100} plane.

That is, when the support substrate made of Si is diced along the [110] direction and the direction close to the [1-10] direction of the support substrate, the dicing direction is almost the {110} surface having high cleavage. The directions are parallel. As a result, the {110} surface, which is the cut surface, tends to be a smooth surface with little anchoring effect.

When mounted on a stem or the like using a conductive adhesive such as Ag paste in such a state, the force with which the conductive adhesive binds to the surface of the support substrate tends to decrease. As a result, it is presumed that sufficient die-share strength was not obtained.

On the other hand, according to the LED element according to the present invention, the second semiconductor layer forming the epitaxial layer and the support substrate are in the same (001) plane as the main surface, and the second semiconductor layer [ The 100] direction or the [010] direction is configured to be substantially parallel to the [110] direction of the support substrate. That is, the [110] direction of the second semiconductor layer and the [110] direction of the support substrate are substantially tilted by 45 °. It should be noted that substantially 45 ° here may be within the range of 45 ° ± 2 ° in consideration of an error during manufacturing.

That is, since the [100] direction or the [010] direction of the second semiconductor layer is configured to be substantially parallel to the [110] direction of the support substrate, the second semiconductor is the direction of the dicing line. The [110] direction and [1-10] of the layer are substantially tilted by 45 ° with respect to the [110] direction and the [1-10] direction of the support substrate. That is, the support substrate made of Si is diced along the dicing line substantially inclined by 45 ° with respect to the [110] direction and the [1-10] direction of the support substrate.

At this time, the chipping formed during dicing tends to propagate along the [110] direction and the [1-10] direction of the support substrate. Further, in the Si substrate, the {111} plane ((111) plane, (1-11) plane, (-1-11) plane, (-111 plane)) also exhibits high cleavage. Cleavage tends to progress in the direction parallel to. However, both the {110} plane and the {111} plane are tilted at an angle of 40 ° to 50 ° with respect to the {100} plane. Therefore, before the chipping progresses to the large cleavage surface, cleavage occurs in another direction, and a large number of uneven portions made of chipping of an appropriate size are formed on the surface of the support substrate. As a result, the anchor effect on the conductive adhesive is enhanced, and the die shear strength is improved.

From the above viewpoint, it is not limited to the case where the growth substrate on which the epitaxial layer is grown is InP, but the LED element provided with the epitaxial layer grown on the growth substrate having the same crystal structure as InP in the opening direction. However, the same effect can be achieved. As an example, GaAs and GaP can be used as the growth substrate in addition to InP. That is, in the LED element according to the present invention, the first semiconductor layer, the active layer, and the second semiconductor layer may be any material capable of lattice matching with the above-mentioned growth substrate. Since the emission wavelength of the LED element depends on the band gap energy of the constituent material of the active layer, the LED element of the present invention is not limited to the infrared LED element, but may be an LED element in a part of the visible range. Can also be applied.

As an example, when the growth substrate is an InP substrate, the first semiconductor layer, the active layer, and the second semiconductor layer all belong to the group consisting of InP, GaInAsP, AlGaInAs, AlInAs, and InGaAs. Or it can be composed of two or more types. All of these materials are lattice-matchable materials with respect to the InP substrate. With this configuration, it is possible to realize an LED element that generates infrared light having a peak wavelength of 1000 nm or more and less than 2000 nm.

As another example, when the growth substrate is a GaAs substrate, the first semiconductor layer, the active layer, and the second semiconductor layer all belong to the group consisting of GaAs, AlGaInAs, AlGaAs, GaAsP, and GaP. It can be composed of one type or two or more types. All of these materials are lattice-matchable materials with respect to the GaAs substrate. With this configuration, it is possible to realize an LED element that produces visible light or near-infrared light having a peak wavelength of 600 nm or more and less than 1000 nm.

The angle between the [100] direction or the [010] direction of the second semiconductor layer and the [110] direction of the support substrate is preferably 2 ° or less. The angle is more preferably 1.5 ° or less, and particularly preferably 1 ° or less. The smaller this angle is, the closer the angle between the dicing direction of the support substrate and the [110] direction and the [1-10] direction of the support substrate is to 45 °, so that the surface of the support substrate has minute irregularities. It becomes easier to form and the die share strength is further increased.

The LED element is formed on a first electrode formed on a main surface of the main surface of the support substrate opposite to the side on which the bonding layer is formed, and an upper layer of the second semiconductor layer. It may be provided with a second electrode.

The LED element is
A reflective layer made of a material formed at the position of the upper layer of the bonding layer and the position of the lower layer of the first semiconductor layer and having a reflectance to light generated by the active layer higher than that of the bonding layer.
The dielectric layer formed at the position of the upper layer of the reflective layer and the position of the lower layer of the first semiconductor layer,
In a partial region of the dielectric layer, a contact electrode that penetrates the inside of the dielectric layer in a direction orthogonal to the main surface of the support substrate and electrically connects the reflection layer and the first semiconductor layer is provided. It doesn't matter if it is equipped.

According to this configuration, among the light emitted from the active layer, the light that has traveled to the support substrate side can be returned to the second semiconductor layer side corresponding to the light extraction surface, so that the light extraction efficiency is improved.

If the purpose is simply to return the light traveling on the support substrate side to the light extraction surface side, a structure in which the reflective layer is directly contacted with the entire surface of the first semiconductor layer (more specifically, the contact layer) may be adopted. It seems like that. However, in order to reduce the contact resistance between the contact layer made of a semiconductor material and the reflective layer made of a metal material, it is necessary to heat-treat both of them. When the contact layer made of a semiconductor material and the reflective layer made of a metal material are brought into contact with each other to perform the heat treatment by this heat treatment, the metal material constituting the reflective layer and the contact layer are alloyed and the reflectance is lowered. From this point of view, the reflective layer cannot be brought into direct contact with the contact layer. Therefore, from the viewpoint of ensuring the electrical connection between the reflective layer and the contact layer, the first semiconductor layer and the reflective layer are electrically formed while the reflective layer is formed under the dielectric layer as in the above structure. Contact electrodes are provided that penetrate through the dielectric layer for connection.

Although the contact electrode has a lower reflectance than the reflective layer, it is composed of a material that can be easily alloyed with the contact layer to achieve low contact resistance. As an example, AuZn, AuBe, Au / Zn / Au layer structure and the like can be used as the contact electrode. The dielectric layer is appropriately selected from materials that exhibit insulating properties, have high thermal stability, and have high transmittance for light emitted from the active layer. As an example, SiO ₂ , SiN, Al ₂ O ₃ and the like can be used as the dielectric layer. As a result, the light emitted from the active layer and traveling toward the support substrate passes through the region in the dielectric in which the contact electrode is not formed, and then is reflected by the reflective layer formed in the lower layer thereof to the light extraction surface. Be guided.

From the viewpoint of increasing the light extraction efficiency, the area of the region where the contact electrode is formed is made as small as possible in the direction parallel to the (001) plane which is the main plane of the support substrate (hereinafter, simply referred to as “plane direction”). Is preferable. On the other hand, if this area is made too small, the path of the current flowing in the semiconductor layer is concentrated in some places and the resistance becomes large. From this point of view, it is preferable that the contact electrodes are formed at a plurality of positions discrete with respect to the plane direction.

Further, the present invention is a method for manufacturing an LED element showing the above configuration.
(001) A step (a) of preparing a growth substrate having one surface as a main surface, and
The step (b) of forming the epitaxial layer by epitaxially growing the second semiconductor layer, the active layer, and the first semiconductor layer on the (001) plane of the growth substrate.
(001) The step (c) of preparing the support substrate having one surface as one main surface, and
While holding the [110] direction of the support substrate and the [100] direction or the [010] direction of the growth substrate substantially in parallel, the epitaxial layer formed on the growth substrate is placed on the support substrate side. The step (d) of bonding the support substrate and the growth substrate in a state of facing toward
The step (e) of peeling the growth substrate after the step (d),
With the support substrate side fixed, the direction substantially parallel to the [100] direction of the second semiconductor layer from the side of the epitaxial layer located on the side opposite to the support substrate, and the first. (2) It is characterized by having a step (f) of dicing along a direction substantially parallel to the [010] direction of the semiconductor layer.

As a result, the dicing direction in the dicing step of the step (f) can be substantially tilted by 45 ° with respect to the [110] direction and the [1-10] direction of the support substrate where chipping easily progresses, so that the support can be supported. It becomes easy to form minute irregularities on the surface of the substrate. As a result, when the stem or the like is subsequently joined to the stem or the like using a conductive adhesive, the anchoring effect between the conductive adhesive and the support substrate is enhanced, and the die shear strength is further enhanced.

The method for manufacturing the LED element may include, after the step (f), a step (h) of mounting the LED element on the stem using a conductive adhesive with the support substrate side facing the stem. ..

In the step (d), the support substrate and the support substrate are held while holding the orientation flat formed on the support substrate and the orientation flat or the index flat formed on the growth substrate in a substantially tilted state of 45 °. It may be bonded to the growth substrate. As described above, the term "substantially 45 °" here means that an error during manufacturing is taken into consideration, and may be within the range of 45 ° ± 2 °.

Further, the method for manufacturing the LED element includes a step (g) of forming the bonding layer on the upper layer of the epitaxial layer and the upper layer of the support substrate before the step (d).
The step (d) is
The step of preparing the pressing member and the positioning member (d1), and
A step of adjusting the orientations of the support substrate and the growth substrate so that the [110] direction of the support substrate and the [100] direction or the [010] direction of the growth substrate are substantially parallel to each other (d2). )When,
In order to maintain the orientation adjusted by the step (d2), the support substrate and the growth substrate are pressed against the positioning member by the pressing member (d3).
It has a step (d4) of bonding the support substrate and the growth substrate via the bonding layer by pressurizing the overlapped support substrate and the growth substrate while executing the step (d3). It doesn't matter if it is a thing.

By this method, the degree of freedom regarding the rotation direction in the state where both substrates are overlapped is suppressed, so that dicing can be performed while maintaining the orientation adjusted in the step (d2).

According to the present invention, in an LED element in which an epitaxial layer is formed on a support substrate different from the growth substrate, the die share strength after chipping can be improved.

It is sectional drawing which shows typically the structure of one Embodiment of the LED element of this invention. It is a figure which shows the plan view when only the support substrate 11 is extracted from FIG. 1 and is seen from the + Y side in the state which added the crystal orientation using the Miller index. It is a drawing which shows the plan view when only the 2nd clad layer 27 is extracted from FIG. 1 and is seen from the + Y side, with the crystal orientation using the Miller index added. It is another drawing which shows the plan view when only the 2nd clad layer 27 is extracted from FIG. 1 and is seen from the + Y side, with the crystal orientation using the Miller index added. It is sectional drawing in one step for demonstrating the manufacturing method of the LED element shown in FIG. It is a top view of the growth substrate 3 with the (001) plane as the upper surface. It is sectional drawing in one step for demonstrating the manufacturing method of the LED element shown in FIG. It is sectional drawing in one step for demonstrating the manufacturing method of the LED element shown in FIG. It is sectional drawing in one step for demonstrating the manufacturing method of the LED element shown in FIG. It is sectional drawing in one step for demonstrating the manufacturing method of the LED element shown in FIG. It is a top view of the support substrate 11 with the (001) plane as the upper surface. It is sectional drawing in one step for demonstrating the manufacturing method of the LED element shown in FIG. It is sectional drawing in one step for demonstrating the manufacturing method of the LED element shown in FIG. It is a drawing which shows typically an example of the method for keeping the state of alignment of a growth substrate 3 and a support substrate 11. It is a schematic drawing when the state shown in FIG. 8B is seen from the direction d1. It is sectional drawing in one step for demonstrating the manufacturing method of the LED element shown in FIG. It is sectional drawing in one step for demonstrating the manufacturing method of the LED element shown in FIG. It is sectional drawing in one step for demonstrating the manufacturing method of the LED element shown in FIG. It is sectional drawing in one step for demonstrating the manufacturing method of the LED element shown in FIG. It is sectional drawing in one step for demonstrating the manufacturing method of the LED element shown in FIG. It is sectional drawing in one step for demonstrating the manufacturing method of the LED element shown in FIG. It is sectional drawing in one step for demonstrating the manufacturing method of the LED element shown in FIG. It is sectional drawing in one step for demonstrating the manufacturing method of the LED element shown in FIG. It is a photograph of the back surface side of the support substrate 11 of the LED element of Example 1. It is a photograph of the back surface side of the support substrate 11 of the LED element of Comparative Example 1.

An embodiment of the LED element and the method for manufacturing the LED element according to the present invention will be described with reference to the drawings. The following drawings are schematically shown, and the dimensional ratios on the drawings do not always match the actual dimensional ratios. In addition, the dimensional ratios may not match between the drawings.

In the present specification, the expression "the layer B is formed on the upper layer of the layer A" means that the thin film is formed on the surface of the layer A as well as the case where the layer B is directly formed on the surface of the layer A. It is intended to include the case where the layer B is formed through the layer B. The term "thin film" as used herein refers to a layer having a film thickness of 10 nm or less, and may preferably refer to a layer having a film thickness of 5 nm or less.

FIG. 1 is a cross-sectional view schematically showing the structure of the LED element of the present embodiment. The LED element 1 shown in FIG. 1 includes an epitaxial layer 20 formed on an upper layer of a support substrate 11. The LED element 1 shown in FIG. 1 corresponds to a schematic cross-sectional view when cut along an XY plane at a predetermined position. In the following description, the XYZ coordinate system attached to FIG. 1 is referred to as appropriate.

In the following description, when the positive and negative directions are distinguished when expressing the direction, they are described with positive and negative signs such as "+ X direction" and "-X direction". Further, when expressing a direction without distinguishing between positive and negative directions, it is simply described as "X direction". That is, in the present specification, when simply described as "X direction", both "+ X direction" and "-X direction" are included. The same applies to the Y direction and the Z direction.

In the LED element 1 of the present embodiment, infrared light L is generated in the epitaxial layer 20 (more specifically, in the active layer 25 described later). More specifically, as shown in FIG. 1, the infrared light L (L1, L2) is taken out in the + Y direction with respect to the active layer 25. As an example, the infrared light L is light having a peak wavelength of 1000 nm or more and 2000 nm or less.

[Element structure]
Hereinafter, the structure of the LED element 1 will be described in detail.

(Support board 11)
The support substrate 11 is made of Si and is doped with a dopant at a high concentration so as to exhibit conductivity. As an example, a Si substrate having a resistivity of 10 mΩcm or less, which is doped with B (boron) at a dopant concentration of 1 × 10 ¹⁹ / cm ³ or more, is used. As the dopant, for example, P, As, Sb and the like can be used in addition to B (boron). Conductivity is ensured by doping the dopant to a high concentration. Further, by using the Si substrate, high heat dissipation can be ensured and the manufacturing cost can be reduced.

The thickness (length in the Y direction) of the support substrate 11 is not particularly limited, but is, for example, 50 μm or more and 500 μm or less, preferably 100 μm or more and 300 μm or less.

One of the main surfaces of the support substrate 11 is the (001) surface.

(Joint layer 13)
The LED element 1 shown in FIG. 1 includes a bonding layer 13 formed on the upper layer of the support substrate 11. The bonding layer 13 is made of a solder material having a low melting point, and is composed of, for example, Au, Au-Zn, Au-Sn, Au-In, Au-Cu-Sn, Cu-Sn, Pd-Sn, Sn and the like. As will be described later with reference to FIG. 8A, the bonding layer 13 is used for bonding the growth substrate 3 on which the epitaxial layer 20 is formed on the upper surface and the support substrate 11. The thickness of the bonding layer 13 is not particularly limited, but is, for example, 0.5 μm or more and 5.0 μm or less, preferably 1.0 μm or more and 3.0 μm or less.

(Barrier layer 14, barrier layer 16)
The LED element 1 shown in FIG. 1 includes a barrier layer (14, 16). The barrier layers (14, 16) are provided for the purpose of suppressing the diffusion of the solder material constituting the bonding layer 13, and are not limited to the materials as long as such functions are realized. For example, it can be realized with a material containing Ti, Pt and the like. As an example, it is composed of a laminated body of Ti / Pt / Au.

The thickness of the barrier layer (14, 16) is not particularly limited, but is, for example, 0.05 μm or more and 3 μm or less, preferably 0.2 μm or more and 1 μm or less.

Although the barrier layer (14, 16) is formed in the LED element 1 shown in FIG. 1, it is arbitrary whether or not the barrier layer (14, 16) is provided in the present invention.

(Reflective layer 15)
The LED element 1 shown in FIG. 1 includes a reflective layer 15 formed on the upper layer of the bonding layer 13. The reflective layer 15 has a function of reflecting the infrared light L2 traveling toward the support substrate 11 side (−Y direction) among the infrared light L generated in the active layer 25 and guiding the infrared light L2 in the + Y direction. The reflective layer 15 is made of a conductive material and has a high reflectance with respect to infrared light L. The reflectance of the reflective layer 15 with respect to infrared light L is preferably 70% or more, more preferably 80% or more, and particularly preferably 90% or more.

When the peak wavelength of the infrared light L is 1000 nm or more and 2000 nm or less, a metal material such as Ag, Ag alloy, Au, Al, or Cu can be used for the reflective layer 15. The material constituting the reflective layer 15 is appropriately selected according to the wavelength of the light generated by the active layer 25.

The thickness of the reflective layer 15 is not particularly limited, but is, for example, 0.1 μm or more and 2.0 μm or less, preferably 0.3 μm or more and 1.0 μm or less.

As shown in FIG. 1, by forming the barrier layer 14 between the reflective layer 15 and the bonding layer 13, the material constituting the bonding layer 13 diffuses toward the reflective layer 15 to increase the reflectance of the reflective layer 15. It can be suppressed to decrease.

From the viewpoint of improving the light extraction efficiency, it is preferable that the LED element 1 includes the reflection layer 15, as shown in FIG. 1, but in the present invention, whether or not the LED element 1 includes the reflection layer 15. Is optional.

(Dielectric layer 17)
The LED element 1 shown in FIG. 1 includes a dielectric layer 17 formed on the upper layer of the reflective layer 15. The dielectric layer 17 is made of a material that exhibits electrical insulation and is highly transparent to infrared light L. The transmittance of the dielectric layer 17 with respect to infrared light L is preferably 70% or more, more preferably 80% or more, and particularly preferably 90% or more.

When the peak wavelength of the infrared light L is 1000 nm or more and 2000 nm or less, a material such as SiO ₂ , SiN, or Al ₂ O ₃ can be used for the dielectric layer 17. The material constituting the dielectric layer 17 is appropriately selected according to the wavelength of the light generated by the active layer 25.

(Epitaxial layer 20)
The LED element 1 shown in FIG. 1 has an epitaxial layer 20 formed on an upper layer of the dielectric layer 17. The epitaxial layer 20 is composed of a laminated body of a plurality of layers. Specifically, the epitaxial layer 20 includes a contact layer 21, a first clad layer 23, an active layer 25, and a second clad layer 27. Each semiconductor layer (21, 23, 25, 27) constituting the epitaxial layer 20 is made of a material capable of epitaxial growth in lattice matching with the growth substrate 3 described later.

<< Contact layer 21, first clad layer 23 >>
In the present embodiment, the contact layer 21 is composed of, for example, p-type GaInAsP. The thickness of the contact layer 21 is not limited, but is, for example, 10 nm or more and 1000 nm or less, preferably 50 nm or more and 500 nm or less. The p-type dopant concentration of the contact layer 21 is preferably 5 × 10 ¹⁷ / cm ³ or more and 3 × 10 ¹⁹ / cm ³ or less, and more preferably 1 × 10 ¹⁸ / cm ³ or more and 2 × 10 It is ¹⁹ / cm ³ or less.

In the present embodiment, the first clad layer 23 is formed on the upper layer of the contact layer 21, and is composed of, for example, a p-type InP. The thickness of the first clad layer 23 is not limited, but is, for example, 1000 nm or more and 10,000 nm or less, preferably 2000 nm or more and 5000 nm or less. The p-type dopant concentration of the first clad layer 23 is preferably 1 × 10 ¹⁷ / cm ³ or more and 3 × 10 ¹⁸ / cm ³ or less, more preferably 5 × 10 at a position away from the active layer 25. ¹⁷ / cm ³ or more and 3 × 10 ¹⁸ / cm ³ or less.

As the p-type dopant contained in the contact layer 21 and the first clad layer 23, Zn, Mg, Be and the like can be used, and Zn or Mg is preferable, and Zn is particularly preferable. In the present embodiment, the contact layer 21 and the first clad layer 23 correspond to the "first semiconductor layer".

<< Active layer 25 >>
In the present embodiment, the active layer 25 is composed of a semiconductor layer formed on the upper layer of the first clad layer 23. The active layer 25 is appropriately selected from materials capable of generating light having a target wavelength and capable of epitaxial growth in lattice matching with the growth substrate 3 described later with reference to FIGS. 4A and 4B.

For example, when it is desired to realize the LED element 1 that emits infrared light L having a peak wavelength of 1000 nm or more and 2000 nm or less, the active layer 25 may have a single layer structure of GaInAsP, AlGaInAs, or InGaAs, or GaInAsP, AlGaInAs. , Or an MQW (Multiple Quantum Well) structure including a well layer made of InGaAs and a barrier layer made of GaInAsP, AlGaInAs, InGaAs, or InP having a bandgap energy larger than that of the well layer may be used.

When the active layer 25 has a single layer structure, the film thickness of the active layer 25 is 50 nm or more and 2000 nm or less, preferably 100 nm or more and 300 nm or less. When the active layer 25 has an MQW structure, a well layer having a film thickness of 5 nm or more and 20 nm or less and a barrier layer are laminated in a range of 2 cycles or more and 50 cycles or less.

The active layer 25 may be doped with n-type or p-type, or may be undoped. When doped into an n-type, for example, Si can be used as the dopant.

<< Second clad layer 27 >>
In the present embodiment, the second clad layer 27 is formed on the upper layer of the active layer 25, and is composed of, for example, an n-type InP. The thickness of the second clad layer 27 is not limited, but is, for example, 100 nm or more and 10,000 nm or less, preferably 500 nm or more and 5000 nm or less. The n-type dopant concentration of the second clad layer 27 is preferably 1 × 10 ¹⁷ / cm ³ or more and 5 × 10 ¹⁸ / cm ³ or less, and more preferably 5 × 10 ¹⁷ / cm ³ or more and 4 × 10 It is ¹⁸ / cm ³ or less. As the n-type impurity material doped in the second clad layer 27, Sn, Si, S, Ge, Se and the like can be used, and Si is particularly preferable. The second clad layer 27 corresponds to the "second semiconductor layer".

The first clad layer 23 and the second clad layer 27 are materials that do not absorb the infrared light L generated by the active layer 25, and are lattice-matched with the growth substrate 3 (see FIGS. 4A and 4B described later). Then, it is appropriately selected from the materials capable of epitaxial growth. When an InP substrate is adopted as the growth substrate 3, materials such as GaInAsP and AlGaInAs can be used as the first clad layer 23 and the second clad layer 27 in addition to InP.

(Contact electrode 31)
The LED element 1 shown in FIG. 1 has a contact electrode 31 formed so as to penetrate the dielectric layer 17 in the Y direction at a plurality of locations in the dielectric layer 17. The contact electrode 31 connects the contact layer 21 formed on the + Y side of the dielectric layer 17 and the reflective layer 15 formed on the −Y side of the dielectric layer 17. That is, the reflective layer 15 and the first clad layer 23 (first semiconductor layer) are electrically connected via the contact electrode 31.

The contact electrode 31 is made of a material capable of ohmic contact with the contact layer 21. As an example, the contact electrode 31 is made of a material such as Au / Zn / Au, AuZn, AuBe, and may be provided with a plurality of these materials. These materials have a lower reflectance to infrared light L than the materials constituting the reflective layer 15.

The pattern shape of the contact electrode 31 when viewed in the Y direction is arbitrary. However, from the viewpoint of passing a current over a wide range in the active layer 25 in a direction parallel to the main surface (XZ plane, (001) plane) of the support substrate 11 (hereinafter, referred to as “plane direction”), the contact electrode 31 It is preferable that a plurality of the currents are dispersed in the plane direction and arranged in a plurality.

The total area of all the contact electrodes 31 when viewed in the Y direction is preferably 30% or less, preferably 20% or less, with respect to the area of the epitaxial layer 20 (for example, the active layer 25) in the plane direction. It is more preferably present, and particularly preferably 15% or less. When the total area of the contact electrode 31 becomes relatively large, the infrared light L2 traveling from the active layer 25 toward the support substrate 11 side (−Y direction) is absorbed by the contact electrode 31, and the extraction efficiency is lowered. On the other hand, if the total area of the contact electrodes 31 is too small, the resistance value becomes high and the forward voltage rises.

(First electrode 33)
The LED element 1 shown in FIG. 1 includes a first electrode 33 formed on a surface of the support substrate 11 opposite to the epitaxial layer 20 (−Y side). Ohmic contact is realized for the first electrode 33 with respect to the support substrate 11. As an example, the first electrode 33 is made of materials such as AuGe / Ni / Au, Pt / Ti, and Ge / Pt, and a plurality of these materials may be provided. The first electrode 33 is formed at a predetermined position on the back surface side of the support substrate 11, and does not necessarily have to be formed on the entire back surface.

(Second electrode 32)
The LED element 1 shown in FIG. 1 includes a second electrode 32 formed on the upper layer of the second clad layer 27. The second electrode 32 is preferably formed by being stretched in a grid pattern in the upper layer of the second clad layer 27 when viewed in the Y direction. As a result, the current flowing in the active layer 25 can be expanded in the plane direction, and light can be emitted in a wide range in the active layer 25. However, in the present invention, the pattern shape of the second electrode 32 is arbitrary.

As an example, the second electrode 32 is made of a material such as Au / Zn / Au, AuZn, AuBe, and may be provided with a plurality of these materials.

(Pad electrode 34)
The LED element 1 shown in FIG. 1 has a pad electrode 34 formed on the upper surface of the second electrode 32. In FIG. 1, the pad electrode 34 is shown so as to be formed on the entire upper surface of the second electrode 32, but this is due to the convenience of the illustration. Actually, the pad electrode 34 may be formed on a part of the surface of the second electrode 32 extending in the surface direction. The pad electrode 34 is composed of, for example, Ti / Au, Ti / Pt / Au, or the like.

The pad electrode 34 is provided for the purpose of securing a region for contacting the bonding wire for power supply, but it is arbitrary whether or not the pad electrode 34 is provided in the present invention.

[direction]
The LED element 1 shown in FIG. 1 has a structure in a chipped state. That is, as will be described later with reference to FIG. 10B, the structure is such that the wafer including the support substrate 11 is diced.

FIG. 2 is a drawing showing a plan view when only the support substrate 11 is extracted from the LED element 1 shown in FIG. 1 and viewed from the + Y side, with the crystal orientation using the Miller index added. As described above, the support substrate 11 is a Si substrate having a (001) plane as one main surface. Here, it is assumed that the epitaxial layer 20 is formed on the (001) plane of the support substrate 11. That is, FIG. 2 shows a plan view in which the (001) plane of the support substrate 11 faces the + Y side.

As shown in FIG. 2, the support substrate 11 has a rectangular plate shape having sides substantially parallel to the [110] direction and sides substantially parallel to the [1-10] direction. That is, of the four sides constituting the support board 11, the pair of two sides facing each other have an angle within a range of 2 ° or less with respect to the [110] direction of the support board 11, and the other pair of facing sides have an angle within a range of 2 ° or less. , The angle is within the range of 2 ° or less with respect to the [1-10] direction of the support substrate 11.

FIG. 3A shows a plan view when only the second clad layer 27 (second semiconductor layer) is extracted from the LED element 1 shown in FIG. 1 and viewed from the + Y side, with the crystal orientation using the Miller index added. It is a drawing shown by.

As will be described later with reference to FIG. 5A, the epitaxial layer 20 including the second clad layer 27 is formed by epitaxially growing on a growth substrate 3 having a (001) plane as a main surface. That is, each semiconductor layer constituting the epitaxial layer 20 grows while maintaining the crystal orientation of the growth substrate 3. Then, as will be described later with reference to FIGS. 8A and 8B, the growth substrate 3 is attached to the support substrate 11 with the epitaxial layer 20 facing the support substrate 11 side, and then removed. .. That is, the main surface of the epitaxial layer 20 is the (001) surface like the growth substrate 3, and this surface faces the support substrate 11 side. Therefore, FIG. 3A shows a plan view of the second clad layer 27 in a state where the (001) surface on the back side faces the + Y side with respect to the (001) surface. However, the epitaxial layer 20 may be formed on the (00-1) plane of the growth substrate 3.

As shown in FIGS. 2 and 3A, in the LED element 1 of the present embodiment, the [100] direction of the second clad layer 27 is substantially parallel to the [110] direction of the support substrate 11. That is, the angle formed by the [100] direction of the second clad layer 27 and the [110] direction of the support substrate 11 is within a range of 2 ° or less. The angle formed by the [100] direction of the second clad layer 27 and the [110] direction of the support substrate 11 can be measured by using, for example, an X-ray diffraction method (XRD method).

When evaluating the angle between directions, the positive and negative directions of each direction do not matter. That is, it is assumed that the [110] direction and the [-1-10] direction are the same direction, and similarly, the [1-10] direction and the [-110] direction are the same direction.

That is, as shown in FIGS. 2 and 3A, in the LED element 1 of the present embodiment, the [110] direction of the second clad layer 27 is substantially tilted by 45 ° with respect to the [110] direction of the support substrate 11. ing. This means that the [110] direction of each semiconductor layer constituting the epitaxial layer 20 is substantially tilted by 45 ° with respect to the [110] direction of the support substrate 11.

The fact that the [110] direction, which is the direction of one side of each semiconductor layer constituting the epitaxial layer 20, is substantially tilted by 45 ° with respect to the [110] direction of the support substrate 11, is a dicing step for chipping. At this time, it means that the dicing is performed along the direction inclined by 45 ° from the [110] direction of the support substrate. As a result, the chipping formed by dicing tends to proceed in a direction different from the cut surface. However, since the direction of the cut surface is substantially tilted by 45 ° from the direction of high cleavage, cleavage in another direction occurs before the chipping progresses to the large cleavage surface, and the cleavage is from an appropriate size. A large number of uneven portions are formed on the surface of the support substrate.

As a result, the anchor effect on the conductive adhesive is enhanced, and the die shear strength is improved. The point that the die share strength is improved by the configuration of the present invention will be described later with reference to Examples.

From the viewpoint that the dicing direction is substantially tilted by 45 ° with respect to the highly cleaveable direction ([110] direction) of the support substrate 11, as shown in FIG. 3B, the second clad layer 27 (that is, epitaxial). The layer 20) may be arranged so that the [010] direction and the support substrate 11 [110] direction (see FIG. 2) have an angle within a range of 2 ° or less.

[Production method]
An example of the manufacturing method of the LED element 1 described above will be described with reference to the respective drawings of FIGS. 4A to 11. 4A, 5A-5C, 6A, 7, 8A, 9A-9E, and 10A-11 are all cross-sectional views of one step in the manufacturing process. Other drawings will be described later.

(Step S1)
As shown in FIG. 4A, the growth substrate 3 is prepared. In the present embodiment, an InP substrate having the (001) plane as one of the main planes is preferably used. FIG. 4B is a plan view with the (001) plane of the growth substrate 3 as the upper surface. Here, as an example, an InP substrate provided with an orientation flat (OF) and an index flat (IF) is used as the growth substrate 3. The OF is formed on the (110) plane of the growth substrate 3, and the IF is formed on the (1-10) plane of the growth substrate 3.

The growth substrate 3 is not limited to InP as long as it can grow the epitaxial layer 20 to be formed in the next step, and GaAs or GaP can be used.

This step S1 corresponds to the step (a).

(Step S2)
As shown in FIG. 5A, the growth substrate 3 is conveyed into the MOCVD (Metal Organic Chemical Vapor Deposition) apparatus, and the buffer layer 29, the etching stop layer (ES layer) 28, and the third layer are placed on the (001) plane of the growth substrate 3. The biclad layer 27, the active layer 25, the first clad layer 23, and the contact layer 21 are sequentially epitaxially grown to form the epitaxial layer 20. In this step S2, the type and flow rate of the raw material gas, the treatment time, the environmental temperature, and the like are appropriately adjusted according to the material and the film thickness of the layer to be grown.

As an example, a buffer layer 29 is formed by forming an n-type InP having a Si dopant as a predetermined film thickness (for example, about 500 nm), and then a layer of a material different from that of the buffer layer 29 (here, an InGaAs layer). The ES layer 28 is formed by forming a film having a predetermined film thickness (for example, about 200 nm). After that, the second clad layer 27, the active layer 25, the first clad layer 23, and the contact layer 21 are sequentially formed in a state where the growth conditions are set so as to have the above-mentioned film thickness and composition.

This step S2 corresponds to the step (b).

(Step S3)
After the wafer on which the epitaxial layer 20 is formed is taken out from the MOCVD apparatus, a dielectric layer 17 made of, for example, SiO ₂ is formed by a plasma CVD method (see FIG. 5B). Next, a resist mask patterned by a photolithography method is formed on the surface of the dielectric layer 17. After the dielectric layer 17 formed in the resist opening is removed by an etching method using a predetermined chemical such as buffered hydrofluoric acid, a contact electrode 31 made of, for example, Au / Zn / Au is used by an EB vapor deposition apparatus. Material film is formed.

Next, after the resist mask is removed, the material film formed in the unnecessary region (excluding the region where the alignment mark is planned to be formed below is excluded) is lifted off to form the contact electrode 31. At this time, an alignment mark made of the same material as the contact electrode 31 is formed on a part of the upper surface of the epitaxial layer 20 with the OF formed on the growth substrate 3 as a reference. Preferably, the alignment marks are provided at two or three or more positions sufficiently distant from the planned formation region of the LED with respect to the plane direction of the growth substrate 3. After that, for example, an alloy treatment (annealing treatment) is performed by heat treatment at 450 ° C. for 10 minutes to realize ohmic contact between the contact layer 21 and the contact electrode 31.

(Step S4)
As shown in FIG. 5C, the reflective layer 15, the barrier layer 14, and the bonding layer 13a are sequentially formed. For example, an EB vapor deposition apparatus forms a reflective layer 15 by forming Al / Au with a predetermined film thickness, and subsequently, a barrier layer is formed by forming Ti / Pt / Au with a predetermined film thickness. 14 is formed, and subsequently, Ti / Au is formed into a film having a predetermined film thickness to form a bonding layer 13a. The bonding layer 13a may be made of the same material as the bonding layer 13 described above.

(Step S5)
As shown in FIG. 6A, a support substrate 11 different from the growth substrate 3 is prepared. In the present embodiment, a Si substrate having a (001) plane as one main plane and having a high concentration of B (boron) doped is used. The electrical resistivity of the support substrate 11 is preferably less than 100 mΩ · cm (= 1 mΩ · m).

FIG. 6B is a plan view with the (001) surface of the support substrate 11 as the upper surface. Here, as the support substrate 11, a Si substrate having an orientation flat (OF) formed on the (110) surface is used as an example.

This step S5 corresponds to the step (c).

(Step S6)
As shown in FIG. 7, the barrier layer 16 and the bonding layer 13b are formed on the main surface of the support substrate 11. The barrier layer 16 and the bonding layer 13b can be formed by the same method as the barrier layer 14 and the bonding layer 13a described above in step S4.

This step S6 corresponds to the step (g). Whether or not the barrier layer 16 is formed is arbitrary.

(Step S7)
As shown in FIG. 8A, the growth substrate 3 and the support substrate 11 are bonded to each other via the bonding layer 13 (13a, 13b). Preferably, the surfaces of the respective bonding layers 13 (13a, 13b) are laminated in a washed state.

During this superposition step, adjustments are made so that the positional relationship between the growth substrate 3 and the support substrate 11 does not shift. 8B and 8C are drawings schematically showing an example of a method for maintaining this alignment state, and FIG. 8C is a schematic drawing when FIG. 8B is viewed from the direction d1. A pressing member (53, 54) made of a leaf spring or the like and a positioning member (51, 52) made of a pin or the like are prepared (step (d1)).

The pressing member 53 and the positioning member 51 are used for positioning the support substrate 11 (here, the Si substrate), and the pressing member 54 and the positioning member 52 are used for positioning the growth substrate 3 (here, the InP substrate). .. That is, as shown in FIG. 8C, the positioning member 51 is composed of pins and the like protruding from the pedestal 58 at a height less than the thickness of the support substrate 11. Although not shown, the pressing member 53 is configured so that the side surface region of the support substrate 11 can be pressed and not pressed against the growth substrate 3. Further, as shown in FIG. 8C, the positioning member 52 is composed of a pin or the like that abuts only the side surface of the growth substrate 3, and the pressing member 54 can press and support the side surface region of the growth substrate 3. It is configured so that it cannot be pressed against the substrate 11.

Then, the OF of the growth substrate 3 (InP) and the OF of the support substrate 11 (Si) are adjusted to be substantially tilted by 45 ° (step (d2)). In other words, the [110] direction of the support substrate 11 and the [100] direction of the growth substrate 3 are adjusted to be substantially parallel (see FIG. 8B).

In this state, the support substrate 11 is pressed by the pressing member 53 toward the positioning member 51 side by the external force f53, and the growth substrate 3 is pressed by the pressing member 54 toward the positioning member 52 side by the external force f54. Be done. As a result, the [100] direction of the growth substrate 3 and the [110] direction of the support substrate 11 are held so as to be substantially parallel (step (d3)).

By performing this pressing, the temperature is raised while being pressurized by the wafer bonding apparatus while keeping the [100] direction of the growth substrate 3 and the [110] direction of the support substrate 11 substantially parallel (step (d4). )). As a result, the bonding layer 13a on the growth substrate 3 and the bonding layer 13b on the support substrate 11 are melted and integrated (bonding layer 13), and both substrates are bonded. As a result, even after the growth substrate 3 and the support substrate 11 are bonded together, the [100] direction of the growth substrate 3 and the [110] direction of the support substrate 11 are substantially parallel. In other words, the [110] direction of the growth substrate 3 and the [110] direction of the support substrate 11 are substantially tilted by 45 °.

This step S7 corresponds to the step (d).

(Step S8)
As shown in FIG. 9A, the growth substrate 3 is removed. As an example, the growth substrate 3 is removed by immersing the bonded substrate in a hydrochloric acid-based etchant. At this time, since the ES layer 28 formed of a material different from the growth substrate 3 and the buffer layer 29 is insoluble in the hydrochloric acid-based etchant, the etching process is stopped when the ES layer 28 is exposed.

This step S8 corresponds to the step (e).

(Step S9)
As shown in FIG. 9B, the ES layer 28 is removed to expose the second clad layer 27. For example, the ES layer 28 is removed by immersing it in a predetermined chemical solution that is soluble in the ES layer 28 and insoluble in the second clad layer 27 after washing with pure water as needed. .. As an example, a mixed solution of sulfuric acid and hydrogen peroxide solution (SPM) can be used.

(Step S10)
As shown in FIG. 9C, the second electrode 32 is formed on the surface of the exposed second clad layer 27. More specifically, a resist mask patterned by a photolithography method is formed on the surface of the second clad layer 27 with reference to the alignment mark formed in step S3. Next, the material for forming the second electrode 32 (for example, Au / Ge / Au) is formed by the EB vapor deposition apparatus, and then lifted off to form the second electrode 32. Then, in order to realize the ohmic property of the second electrode 32, an alloy treatment (annealing treatment) is performed, for example, by heat treatment at 450 ° C. for 10 minutes.

Next, the pad electrode 34 is formed at a predetermined position on the upper surface of the second electrode 32. In this case as well, it can be realized by the film formation by the EB vapor deposition apparatus and the lift-off process as in the case of the second electrode 32.

(Step S11)
As shown in FIG. 9D, mesa etching is performed on the epitaxial layer 20. More specifically, a resist patterned by a photolithography method is formed with reference to the alignment mark formed in step S3. Specifically, a resist having an opening region along the [110] direction and the [1-10] direction of the second clad layer 27 is formed. Next, by etching with a predetermined etchant using this resist as a mask, a predetermined portion of the epitaxial layer 20 is etched to expose the dielectric layer 17. After that, the resist is removed with a cleaning solution such as acetone.

By this step, dicing lines along the [110] direction and the [1-10] direction are formed in the epitaxial layer 20.

(Step S12)
As shown in FIG. 9E, after the thickness of the back surface side of the support substrate 11 is adjusted, the first electrode 33 is formed on the back surface side of the support substrate 11. As a specific method for forming the first electrode 33, as in the case of the second electrode 32, the material for forming the first electrode 33 (for example, Ti / Pt / Au) is formed by forming a film by an EB vapor deposition apparatus and then lifted off. can.

The thickness of the back surface side of the support substrate 11 may be adjusted as needed, and is not necessarily an essential process. Further, the degree of thickness is also appropriately set according to the application and the like.

(Step S13)
By dicing together with the support substrate 11, it is made into a chip. This process will be described with reference to FIGS. 10A and 10B.

FIG. 10A is a drawing schematically showing a cross section of the wafer at the time when step S12 is completed. Since the mesa etching step in step S11 is performed, a dicing line 38 for distinguishing each element is formed in the epitaxial layer 20, and each epitaxial layer 20 is placed on a common support substrate 11. It is formed.

In this state, dicing is performed together with the support substrate 11 along the dicing line 38 formed in step S11 using, for example, a diamond blade (see FIG. 10B). More specifically, the blade 41 is inserted and dicing is performed in a state where the back surface side (first electrode 33 side) of the support substrate 11 is attached to and fixed to the dicing tape 40. At that time, the cut thickness (cut depth wd40) of the dicing tape 40 is appropriately set.

After cutting, cutting dust of dicing is removed by a process such as cleaning as appropriate.

Before the start of step S13, the epitaxial layer 20 is formed with a dicing line 38 along the [110] direction and the [1-10] direction. Then, in step S7, the support substrate 11 and the growth substrate 3 are bonded so that the [100] direction of the growth substrate 3 and the [110] direction of the support substrate 11 are substantially parallel to each other. That is, in a state where the [110] direction of the epitaxial layer 20 and the [110] direction of the support substrate 11 are substantially tilted by 45 °, along the [110] direction and the [1-10] direction of the epitaxial layer 20. Dicing is performed.

As a result, dicing is performed on the support substrate 11 along the dicing line 38 that is substantially tilted by 45 ° with respect to the [110] direction and the [1-10] direction of the support substrate 11. Since the dicing direction is substantially tilted by 45 ° with respect to the direction parallel to the highly cleaveable {110} plane of the support substrate 11, before the chipping generated during dicing progresses to the large cleavage plane, Cleavage occurs in the other direction, and a large number of uneven portions made of chipping of an appropriate size are formed on the surface of the support substrate 11.

This step S13 corresponds to the step (f).

(Step S14)
The chipped LED element 1 is mounted on a stem 61 or the like using a conductive adhesive 62 such as Ag paste (see FIG. 11). As described above, since the surface of the support substrate 11 has minute uneven portions, the anchor effect acts on the Ag paste and high die shear strength is ensured.

This step S14 corresponds to the step (h).

[inspection]
Hereinafter, the point that the die share strength can be improved by the above LED element will be verified by using an example.

(Example 1)
The LED element manufactured by the method of steps S1 to S13 described above was designated as Example 1. Here, in step S7, the bonding was performed in a state where the OF of the growth substrate 3 (InP) and the OF of the support substrate 11 (Si) were adjusted and held so as to be approximately 45 °. At this time, the angle between the [110] direction of the growth substrate 3 and the [110] direction of the support substrate 11 was 45.3 °. This angle was measured by a metallurgical microscope equipped with a coordinate measurement function.

Further, in step S13, the dicing pitch (that is, corresponding to the tip width) was set to 350 μm. The width of the calf (dicing cutting groove) formed on the support substrate 11 after the completion of step S13 was 30 μm on average.

In step S11, since the mesa etching is performed based on the alignment mark attached to the epitaxial layer 20 in step S3, the direction of the mesa etching (direction of the dicing line) is [110] of the growth substrate 3. ] Direction and [1-10] direction within ± 0.3 °, and the same direction as the [110] direction and [1-10] direction of the growth substrate 3. Can be regarded.

(Example 2)
The LED element manufactured by the same method as in the first embodiment was used as the second embodiment except that the accuracy of the alignment adjustment in step S7 was relaxed. At this time, the angle between the [110] direction of the growth substrate 3 and the [110] direction of the support substrate 11 was 43.3 °.

(Comparative Example 1)
In step S7, after the OF of the growth substrate 3 (InP) and the OF of the support substrate 11 (Si) are simply oriented in the same direction without using a jig such as a positioning member 51 or a pressing member 52. The LED element manufactured by the same method as in Example 1 was used as Comparative Example 1 except that the bonding was performed. At this time, the angle between the [110] direction of the growth substrate 3 and the [110] direction of the support substrate 11 was 4.0 °.

12A to 12B are photographs of the back surface side of the support substrate 11 included in the LED elements of Example 1 and Comparative Example 1, respectively. Specifically, after the pad electrode 34 side of the LED element is attached to a dicing tape different from the dicing tape 40 used in step S13, the dicing tape 40 is peeled off, and each LED element is detached from the first electrode 33 side. It is a photograph when observed with a dicing microscope.

In each photograph, the rectangular region is the chip portion, and the boundary thereof corresponds to the gap between the adjacent chips after dicing. It is confirmed that in the photograph of FIG. 12A, more zigzag-shaped irregularities are formed in the boundary region as compared with the photograph of FIG. 12B.

(test)
The LED elements of Examples 1 and 2 and Comparative Example 1 manufactured through the steps up to step S13 were mounted on an iron stem Au-plated with Ag paste in the same manner as in step S14 (see FIG. 11). A die-share test was performed on the LED elements after mounting (the number of samples is 48 each) by a method according to IEC 60749-19. The results are shown in Table 1 below.

It can be seen that the die share strength of Comparative Example 1 is lower than that of Example 1 and Example 2. For this reason as well, according to the LED elements of Examples 1 and 2, the formation of minute irregularities on the surface of the support substrate 11 after dicing improves the bonding strength to the conductive adhesive and causes die share. It can be seen that the strength has been increased.

As a precaution, when the t-test of the two-sided test was performed for each data of Example 1 and Comparative Example 1 at the significance level of 5%, t (94) = -6.6, P = 2 × 10 ^-9 . there were. From this, it is determined that there is a superior difference between Example 1 and Comparative Example 1. Moreover, when the t-test of the two-sided test was performed on each of the data of Example 2 and Comparative Example 1 at the significance level of 5%, it was t (94) =-3.6, P = 4 × 10 ^-4 . As a result, it is determined that there is a significant difference between Example 2 and Comparative Example 1.

[Another Embodiment]
Hereinafter, another embodiment will be described.

<1> In the LED element 1 shown in FIG. 1, an uneven portion may be formed on the surface of the second clad layer 27 on the + Y side. By forming the uneven portion, the amount of infrared light L (L1, L2) traveling in the + Y direction from the active layer 25 is reflected on the surface of the second clad layer 27 toward the active layer 25, and the light is reduced. Extraction efficiency is improved.

This uneven portion is formed, for example, by performing wet etching on the surface of the second clad layer 27 in the region where the second electrode 32 is not formed after step S10.

<2> The order of each of the above-mentioned steps S1 to S14 may be appropriately changed as long as it does not affect the manufacture of the LED element 1.

<3> In step S7 described above, the positioning member 51 and the pressing member 52 are used to perform bonding while maintaining the alignment state. However, the method of maintaining the alignment state is not limited to this method. As another method, any method may be used as long as the alignment can be performed with higher accuracy than the simple visual alignment. For example, a method of aligning an orientation flat or an alignment mark using a bond aligner can be used.

1: LED element 3: Growth substrate 11: Support substrate 13: Bonding layer 13a: Bonding layer 13b: Bonding layer 14: Barrier layer 15: Reflective layer 16: Barrier layer 17: Dielectric layer 20: epitaxial layer 21: Contact layer 23 : First clad layer 25: Active layer 27: Second clad layer 28: ES layer 29: Buffer layer 31: Contact electrode 32: Second electrode 33: First electrode 34: Pad electrode 38: Dicing line 40: Dicing tape 41 : Blade 51: Positioning member 52: Positioning member 53: Pushing member 54: Pushing member 58: Pedestal 61: Stem 62: Conductive adhesive f52: External force L: Infrared light wd40: Cut depth

Claims (12)

A support board made of Si and
A bonding layer formed on the upper layer of the support substrate and made of a metal material,
An n-type or p-type first semiconductor layer formed on the upper layer of the bonding layer,
The active layer formed on the upper layer of the first semiconductor layer and
A second semiconductor layer formed on the upper layer of the active layer and having a different conductive type from the first semiconductor layer is provided.
The support substrate exhibits a rectangular plate shape having a (001) plane as one main surface and having sides substantially parallel to the [110] direction and sides substantially parallel to the [1-10] direction. ,
The second semiconductor layer has a (001) plane as one main surface, and the [100] direction or the [010] direction of the second semiconductor layer is substantially parallel to the [110] direction of the support substrate. An LED element characterized by being. The LED element according to claim 1, wherein the angle between the [100] direction or the [010] direction of the second semiconductor layer and the [110] direction of the support substrate is 2 ° or less. Of the main surface of the support substrate, the first electrode formed on the main surface opposite to the side on which the bonding layer is formed, and
The LED element according to claim 1 or 2, further comprising a second electrode formed on the upper layer of the second semiconductor layer. A reflective layer made of a material formed at the position of the upper layer of the bonding layer and the position of the lower layer of the first semiconductor layer and having a reflectance to light generated by the active layer higher than that of the bonding layer.
The dielectric layer formed at the position of the upper layer of the reflective layer and the position of the lower layer of the first semiconductor layer,
In a partial region of the dielectric layer, a contact electrode that penetrates the inside of the dielectric layer in a direction orthogonal to the main surface of the support substrate and electrically connects the reflection layer and the first semiconductor layer is provided. The LED element according to claim 3, wherein the LED element is provided. Any of claims 1 to 4, wherein the first semiconductor layer, the active layer, and the second semiconductor layer are all made of a material that can be lattice-matched to a growth substrate made of InP. The LED element according to item 1. The first semiconductor layer, the active layer, and the second semiconductor layer are all composed of one or more kinds belonging to the group consisting of InP, GaInAsP, AlGaInAs, AlInAs, and InGaAs. The LED element according to any one of claims 1 to 5. The LED element according to any one of claims 1 to 6, wherein the active layer produces infrared light having a peak wavelength of 1000 nm or more and less than 2000 nm. The method for manufacturing an LED element according to claim 1.
(001) A step (a) of preparing a growth substrate having one surface as a main surface, and
The step (b) of forming the epitaxial layer by epitaxially growing the second semiconductor layer, the active layer, and the first semiconductor layer on the (001) plane of the growth substrate.
(001) The step (c) of preparing the support substrate having one surface as one main surface, and
While holding the [110] direction of the support substrate and the [100] direction or the [010] direction of the growth substrate substantially in parallel, the epitaxial layer formed on the growth substrate is placed on the support substrate side. In the step (d) of laminating the support substrate and the growth substrate in a state of facing toward
The step (e) of peeling the growth substrate after the step (d),
With the support substrate side fixed, the direction substantially parallel to the [100] direction of the second semiconductor layer from the side of the epitaxial layer located on the side opposite to the support substrate, and the first. (Ii) A method for manufacturing an LED element, which comprises a step (f) of dicing along a direction substantially parallel to the [010] direction of the semiconductor layer. The LED according to claim 8, further comprising a step (h) of mounting the LED on the stem using a conductive adhesive with the support substrate side facing the stem after the step (f). Manufacturing method of the element. In the step (d), the support substrate and the support substrate are held while holding the orientation flat formed on the support substrate and the orientation flat or the index flat formed on the growth substrate in a substantially tilted state of 45 °. The method for manufacturing an LED element according to claim 8 or 9, wherein the LED element is bonded to a growth substrate. Prior to the step (d), there is a step (g) of forming the bonding layer on the upper layer of the epitaxial layer and the upper layer of the support substrate.
The step (d) is
The step of preparing the pressing member and the positioning member (d1), and
A step of adjusting the orientations of the support substrate and the growth substrate so that the [110] direction of the support substrate and the [100] direction or the [010] direction of the growth substrate are substantially parallel to each other (d2). )When,
In order to maintain the orientation adjusted by the step (d2), the support substrate and the growth substrate are pressed against the positioning member by the pressing member (d3).
It has a step (d4) of bonding the support substrate and the growth substrate via the bonding layer by pressurizing the overlapped support substrate and the growth substrate while executing the step (d3). The method for manufacturing an LED element according to any one of claims 8 to 10, wherein the LED element is manufactured. The growth substrate is an InP substrate and is an InP substrate.
Any of claims 8 to 11, wherein the first semiconductor layer, the active layer, and the second semiconductor layer are all made of a material that can be lattice-matched to the growth substrate made of InP. The method for manufacturing an LED element according to item 1.

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