TW202236697A - LED element and manufacturing method thereof - Google Patents

Abstract

In an LED element in which an epitaxial layer is formed on a support substrate different from a growth substrate, the occurrence of debris on the back surface side of the support substrate is suppressed. An LED element is provided with: a support substrate comprising Si; a bonding layer formed on an upper layer of the support substrate and made of a metal material; an n-type or p-type first semiconductor layer formed on an upper layer of the bonding layer; an active layer formed on the upper layer of the first semiconductor layer; and a second semiconductor layer which is formed on the upper layer of the active layer and has a conductivity type different from that of the first semiconductor layer. The support substrate has a (001) plane as one main surface, and has a rectangular plate shape having a side substantially parallel to the [110] direction and a side substantially parallel to the [1-10] direction. The second semiconductor layer has a (001) plane as one main surface, and the [110] direction or the [1-10] direction of the second semiconductor layer is substantially parallel to the [110] direction of the support substrate.

Description

LED element and manufacturing method thereof

The present invention relates to an LED element and a manufacturing method thereof.

In recent years, semiconductor light-emitting devices that use the infrared region with a wavelength of 1000 nm or more as the emission wavelength have been widely used in crime prevention, surveillance cameras, gas detectors, medical sensors, and industrial equipment.

A semiconductor light emitting element having an emission wavelength of 1000 nm or more has been generally manufactured by the following procedure (see Patent Document 1 described later). That is, on the InP substrate as the growth substrate, the semiconductor layer of the first conductivity type, the active layer (also known as the "light-emitting layer") and the second conductivity type are sequentially epitaxially grown to match the InP substrate. the semiconductor layer. Afterwards, electrodes for injecting current are formed on the semiconductor wafer and cut into wafers for manufacture.

Conventionally, as a semiconductor light-emitting element with an emission wavelength of 1000 nm or more, there has been an advance in the development of a semiconductor laser element. On the other hand, the development of LED components is slower than that of laser components because there are not many uses.

However, in recent years, due to the wide application of applications, the improvement of light output is gradually required for infrared LED components. The InP substrate is the same as the GaAs substrate used in the visible light region, and exhibits a high refractive index of 3 or more. Therefore, when light is extracted through the InP substrate, total reflection due to the difference in refractive index at the interface with air occurs, and the light extraction efficiency is limited to be low. Furthermore, since the thermal resistance of the InP substrate is large, the light output is likely to become saturated during high current driving. From such a situation, the structure disclosed in Patent Document 1 is not suitable for obtaining an LED element with a high light output.

As a method of obtaining a higher light output than the structure disclosed in Patent Document 1, for example, adoption of the structure disclosed in Patent Document 2 is conceivable. That is, it is presumed that the structure realized by removing the growth substrate is effective after bonding the growth substrate on which the epitaxial layer is formed on a support substrate showing high heat dissipation conductivity (Si substrate doped with B at a high concentration, etc.). [Prior Art Literature] [Patent Document]

[Patent Document 1] Japanese Patent Application Laid-Open No. 4-282875 [Patent Document 2] Japanese Patent Laid-Open No. 2013-030606 [Patent Document 3] Japanese Patent Laid-Open No. 2011-198962 [Patent Document 4] Japanese Patent Laid-Open No. 2007-194247

[Problem to be Solved by the Invention]

According to the keen research of the inventors of this case, after laminating the InP substrate (growth substrate) forming the epitaxial layer and the Si substrate as the supporting substrate, removing the InP substrate, and then performing dicing for wafering, especially the Si substrate On the back side of the film, traces of peeling off of a plurality of small pieces called chipping were confirmed. In particular, when large-scale and many cracks occur, a shape difference may occur among a plurality of chipped LED elements, and there is a possibility that the appearance yield of the product may decrease.

Furthermore, the techniques of the aforementioned Patent Document 3 and Patent Document 4 are disclosed as methods for suppressing cracks and cracks occurring at the wafer level during bonding of dissimilar substrates. However, all of these documents target the suppression of damage and cracks at the wafer level, and particularly focus on the technology of damage and cracks in the epitaxial layer. Even with these methods, the effect of suppressing cracks on the back side of the wafered Si substrate cannot be expected.

The present invention is made in view of the aforementioned problems, and it is an object of the present invention to suppress the occurrence of cracks on the back side of a support substrate in an LED element in which an epitaxial layer is formed on a support substrate other than a growth substrate. [Means to solve the problem]

LED element of the present invention is characterized in that possessing: The supporting substrate is made of Si; The bonding layer is formed on the upper layer of the aforementioned support substrate and is made of metal materials; The n-type or p-type first semiconductor layer is formed on the upper layer of the aforementioned bonding layer; The active layer is formed on the upper layer of the aforementioned first semiconductor layer; and The second semiconductor layer is formed on the upper layer of the aforementioned active layer, and its conductivity type is different from that of the aforementioned first semiconductor layer; The above-mentioned supporting substrate is a rectangular plate having a side substantially parallel to the [110] direction and a side substantially parallel to the [1-10] direction with the (001) plane as one main surface; The second semiconductor layer has a (001) plane as one main surface, and the [110] direction or [1-10] direction of the second semiconductor layer is substantially parallel to the [110] direction of the support substrate.

In this specification and drawings, (hkl) described using three integers h, k, and l represents a plane orientation. Also, [hkl] represents the normal direction of the surface (hkl). Here, h, k, and l are the same or different integers, and are called Miller indices. The "-" shown before the Miller index is what is shown above the head of the original number, which is called "superscript". For the convenience of recording, it is described before the Miller index in this manual and drawings.

In this specification, a certain direction d1 is "substantially parallel" to other directions d2, which is of course the condition that the straight line Ld1 parallel to the direction d1 is completely parallel to the straight line Ld2 parallel to the direction d2, that is, the two straight lines (Ld1 , Ld2) The situation that the angle formed by these two straight lines is 0° also means that the angle formed by these two straight lines is less than 2°. Furthermore, in the case where the direction d1 is "substantially parallel" to the direction d2, the angle formed by the straight line Ld1 parallel to the direction d1 and the straight line Ld2 parallel to the direction d2 is preferably 1.5° or less, more preferably 1° or less.

In this specification, the expression "GaInAsP" represents a mixed crystal of Ga, In, As, and P, and the description of the composition ratio is simply omitted. The same applies to other descriptions such as "AlGaInAs".

In this specification, "peak wavelength" refers to the wavelength of the highest light output in the emission spectrum.

In the conventional method, when the growth substrate and the support substrate are bonded together, the growth substrate is peeled off, and then dicing is performed for wafering, the reason why a large crack occurs on the back side of the support substrate is as follows. study.

When laminating the growth substrate (such as an InP substrate) on which the epitaxial layer is formed and the Si substrate as the supporting substrate, from the viewpoint of stable bonding strength and ensuring electrical conductivity, generally, the two substrates are separately formed into films made of solder, etc. In the state of the bonding layer made of metal, the bonding layers are bonded to each other. In this bonding process, there is a degree of freedom in the rotation direction of both substrates.

After attaching the growth substrate and the support substrate, the epitaxial layer is left and the growth substrate is removed. Afterwards, the wafer is chipped by dicing. Here, the epitaxial layer is mechanically fragile due to its thin film thickness, and cutting the epitaxial layer may cause fatal damage to the device, such as peeling of the film from the epitaxial layer. Therefore, generally speaking, before the dicing process, the epitaxial layer formed at the dicing site is removed by etching (Mesa etching).

The epitaxial layer grown on the main surface of the growth substrate made of InP substrate is due to its chemical properties, along the [110] direction and [1-10] direction of the original InP substrate, in other words, along the epitaxial layer. If the [110] direction and the [1-10] direction of the crystal layer are etched, a highly linear shape can be obtained. That is, after the plateau etching process, dicing lines along the [110] direction and the [1-10] direction are formed. Therefore, cutting works are carried out along this cutting line.

Furthermore, even when a GaAs substrate is used as the growth substrate, if the epitaxial layer is etched along the [110] direction and the [1-10] direction similarly, a highly linear shape can be obtained. Therefore, at this time, the cutting process is also performed along the [110] direction and the [1-10] direction.

The dicing process is carried out by cutting the supporting substrate with a high-speed rotating blade (typically a diamond knife). In this case, cracks inevitably occur on the back side of the supporting substrate. Several reasons are conceivable as the cause of the fracture, but, for example, it is estimated that abrasive grains (typically diamond fine powder) contact the support substrate at high speed, cutting chips are involved in the cutting interface, and the blade has Rotation shaking (eccentric), cutting different materials together (such as Si substrate and dicing tape, etc.), etc.

As the supporting substrate, a Si single crystal substrate is generally used from the viewpoint of obtaining high electrical conductivity and high thermal conductivity. The single crystal substrate has splitting properties, and it is easy to split along the direction of the plane where the atoms are aligned (that is, the predetermined crystal orientation). Therefore, once a small crack occurs, the force of mechanical cutting will not be dispersed, and cracks will occur along the crystal orientation. Therefore, depending on the cutting orientation of the substrate, small cracks trigger the occurrence of large cracks (detachment marks, notches), resulting in unsightly appearance.

According to the LED element of the present invention, the second semiconductor layer forming the epitaxial layer has the (001) plane as the main surface in the same state as the supporting substrate, and the [110] direction or the [1-10] direction of the second semiconductor layer is , constituted substantially parallel to the [110] direction of the supporting substrate. As mentioned above, in the mesa etching process performed before wafering, dicing lines along the [110] direction and the [1-10] direction are formed in the epitaxial layer including the second semiconductor layer.

Here, since the [110] direction or the [1-10] direction of the second semiconductor layer is substantially parallel to the [110] direction of the supporting substrate, the direction of the cutting line is relative to the [110] direction and the [1-10] direction of the supporting substrate. 1-10] directions are substantially parallel. The crystal structure of Si is a diamond structure, and comparing the (110) plane and the (100) plane, which are two planes perpendicular to the (001) plane, the (110) plane is more cleavable than the (100) plane. Furthermore, the (110) plane, (-1-10) plane, (1-10) plane, and (-110) plane are equal in consideration of crystal symmetry, and can be collectively referred to as {110} planes. Similarly, the (100) plane, (-100) plane, (010) plane, and (0-10) plane are equal in consideration of crystal symmetry, and can be collectively called {100} planes. When described using this generic term, in a supporting substrate made of Si, the splitting property of the {110} plane is higher than that of the {100} plane.

That is, if the supporting substrate made of Si is cut along the cutting line formed substantially parallel to the [110] direction and the [1-10] direction of the supporting substrate, the direction of the cutting becomes parallel to the cleavage property. The orientation of the tall {110} faces. As a result, if a minute crack occurs, even if a crack occurs starting from the crack, the crack will easily propagate in the [110] direction and the [1-10] direction which are the same as the cutting direction. That is, cracks tend to propagate in a direction parallel to the fractured surface due to dicing, and are difficult to propagate toward the inner side of the wafer. As a result, the size and number of cracks can be suppressed.

However, on the growth substrate and the supporting substrate, generally, an orientation flat for confirming the orientation of the crystal is formed (hereafter, it is briefly described as "OF (orientation flat)"). In the past, when laminating the growth substrate and the support substrate, there were cases where alignment was performed using this OF. However, this engineering department does not exist on purpose, and it is only a process of aligning a certain degree of direction.

As described above, since there is a degree of freedom in the direction of rotation when bonding these two types of different substrates, it is impossible to make the directions the same in a strict sense only by aligning the directions of OF. In addition, although it will be described later in the item of "Detailed Description of the Invention", when only aligning the OF direction of two substrates and bonding them, it can be confirmed that [110] of the bonded support substrate The orientation deviates by an angle of 4˚ from [110] of the growth substrate. If the mesa etching is performed in the state where this angle deviation occurs, one direction of the dicing line formed after the mesa etching, that is, the [110] direction of the first semiconductor layer (epitaxy layer) is not the [110] direction of the supporting substrate. ] directions are substantially parallel to each other with an angular deviation of about 4°.

Furthermore, it is described as "4° degree" here because the direction of the plateau etching (the direction of the dicing line) formed on the epitaxial layer is not strictly consistent with the [110] direction (and [1-10] direction), There is a possibility that it deviates from the range within ±0.3˚.

When cutting along the cutting line in this state, the crack is easy to spread, and the [110] direction and [1-10] direction of the support substrate have an angle of about 4° from the cutting direction, so the cracking tends to be closer to the wafer than the cutting direction inner extension.

On the other hand, according to the structure of the present invention, the support substrate has the (001) plane as one main surface, and has a side substantially parallel to the [110] direction and a side substantially parallel to the [1-10] direction. The first semiconductor layer has a (001) plane as one main plane, and the [110] direction or the [1-10] direction is substantially parallel to the [110] direction of the supporting substrate. That is to say, with this structure, the direction of propagation of the crack starting from the crack generated during the dicing process is along the direction of the side of the supporting substrate, so that the crack is difficult to propagate in the direction inside the wafer, and the scale and size of the crack can be suppressed. Expansion of the number of occurrences.

Furthermore, from the aforementioned point of view, the growth substrate for growing the epitaxial layer is not limited to the situation of InP, and the LED element having the epitaxial layer grown on the growth substrate having the same crystal structure as InP in the cleave orientation , can also achieve the same effect. As an example, as a growth substrate, GaAs and GaP can be used in addition to InP. That is, in the LED element of the present invention, as the first semiconductor layer, the active layer, and the second semiconductor layer, any materials may be used as long as they can be lattice-matched to the aforementioned growth substrate. Since the emission wavelength of the LED element depends on the bandgap energy of the constituent materials of the active layer, the LED element of the present invention is not limited to the infrared LED element, and can also be applied to LED elements in a part of the visible range.

As an example, when the growth substrate is an InP substrate, any of the first semiconductor layer, the active layer, and the second semiconductor layer can belong to the group consisting of InP, GaInAsP, AlGaInAs, AlInAs, and InGaAs. One or two or more components. Any of these materials are lattice-matched to the InP substrate. With this structure, an LED element that generates infrared light with a peak wavelength of 1000 nm or more and less than 2000 nm can be realized.

As another example, when the growth substrate is a GaAs substrate, any of the aforementioned first semiconductor layer, the aforementioned active layer, and the aforementioned second semiconductor layer can belong to the group consisting of GaAs, AlGaInAs, AlGaAs, GaAsP, and GaP. One or two or more components. Any of these materials are lattice-matched to the GaAs substrate. With this structure, an LED element that generates visible light or near-infrared light having a peak wavelength of 600 nm or more and less than 1000 nm can be realized.

The angle between the [110] direction or the [1-10] direction of the second semiconductor layer and the [110] direction of the support substrate is preferably 2° or less. Furthermore, the angle is more preferably 1.5° or less, and particularly preferably 1° or less. The smaller the angle, the more difficult it is for the debris to push to the inside of the wafer.

The above-mentioned LED element may also include: a first electrode formed on the main surface of the above-mentioned support substrate, which is opposite to the side where the bonding layer is formed; and a second electrode formed on the upper layer of the second semiconductor layer. .

The foregoing LED components may also have: The reflective layer is formed on the upper layer of the bonding layer, and the lower layer of the first semiconductor layer is made of a material that has a higher reflectance to the light generated in the active layer than the bonding layer; The dielectric layer is formed at the position of the upper layer of the aforementioned reflective layer, and at the position of the lower layer of the aforementioned first semiconductor layer; and The contact electrode is in a part of the dielectric layer, penetrating through the dielectric layer in a direction perpendicular to the main surface of the support substrate, and electrically connecting the reflective layer and the first semiconductor layer.

According to this structure, among the light emitted from the active layer, the light traveling on the side of the supporting substrate can be returned to the side of the second semiconductor layer corresponding to the light extraction surface, thereby improving the light extraction efficiency.

Furthermore, if the purpose is only to return the light rays traveling on the support substrate side to the light extraction surface side, a structure in which the reflective layer directly contacts the entire surface of the first semiconductor layer (more specifically, the contact layer) is also good. However, in order to reduce the contact resistance between the contact layer made of a semiconductor material and the reflective layer made of a metal material, both need to be heat-treated. When heat treatment is performed by contacting the contact layer made of semiconductor material and the reflective layer made of metal material by this heat treatment, the metal material constituting the reflective layer and the contact layer are alloyed, resulting in a decrease in reflectance. According to a related point of view, the reflective layer cannot directly contact the contact layer. Therefore, from the viewpoint of ensuring the electrical connection between the reflective layer and the contact layer, as in the aforementioned structure, in order to electrically connect the first semiconductor layer and the reflective layer while forming the reflective layer on the lower layer of the dielectric layer, a through hole is provided. Contact electrodes within the dielectric layer.

Although the reflectance of the contact electrode is lower than that of the reflective layer, it is made of a material that is easily alloyed with the contact layer and can realize low contact resistance. As an example, AuZn, AuBe, Au/Zn/Au layer structure, etc. can be used for a contact electrode. In addition, as the dielectric layer, a material that exhibits insulating properties, high thermal stability, and high transmittance to light emitted from the active layer is appropriately selected. As an example, SiO ₂ , SiN, Al ₂ O ₃ or the like can be used for the dielectric layer. Thereby, light emitted from the active layer and traveling toward the support substrate passes through a region in the dielectric where no contact electrode is formed, is reflected by the reflective layer formed therebelow, and is guided to the light extraction surface.

From the viewpoint of improving light extraction efficiency, it is preferable to minimize the area of the region where the contact electrodes are formed in the direction parallel to the (001) plane (hereinafter simply referred to as the "plane direction") which is the main surface of the support substrate. On the other hand, if the area is reduced too much, the path of the current flowing in the semiconductor layer will be concentrated in one part, and the resistance will increase. From a related point of view, it is preferable that the contact electrodes are formed at a plurality of discrete positions in the plane direction.

Also, the present invention is a method of manufacturing an LED element showing the aforementioned structure, and is characterized in that it has: Process (a) of preparing a growth substrate with the (001) plane as one main surface; Step (b) of sequentially epitaxially growing the aforementioned second semiconductor layer, the aforementioned active layer, and the aforementioned first semiconductor layer on the (001) plane of the aforementioned growth substrate to form the aforementioned epitaxial layer; The process (c) of preparing the aforementioned support substrate with the (001) plane as one of the principal planes; While keeping the [110] direction of the aforementioned support substrate substantially parallel to the [110] direction or the [1-10] direction of the aforementioned growth substrate, the aforementioned epitaxial layer formed on the aforementioned growth substrate is directed towards the aforementioned supporting substrate. The process (d) of laminating the aforementioned support substrate and the aforementioned growth substrate in the state of the side; After the aforementioned process (d), the process (e) of stripping the aforementioned growth substrate; and In the state where the support substrate side is fixed, from the side of the epitaxial layer located on the opposite side to the support substrate, along a direction substantially parallel to the [110] direction of the second semiconductor layer, and to the second A process (f) of cutting in a direction substantially parallel to the [1-10] direction of the semiconductor layer.

Thereby, the cutting direction of the dicing process of the process (f) can be made parallel to the {110} plane with high cleaveability of the support substrate, so that cracks starting from the cracks generated during the dicing can be made The direction of extension is along the direction of the edge of the supporting substrate. This makes it difficult for cracks to spread in the direction of the inside of the wafer, and can suppress the expansion of the scale and number of occurrences of cracks.

In the process (d), the support substrate and the growth substrate may be bonded together while maintaining the orientation plane formed on the support substrate in the same direction as the orientation plane or index plane formed on the growth substrate. .

In addition, the method of manufacturing the LED element may include the step (g) of forming the bonding layer on the upper layer of the epitaxial layer and the upper layer of the support substrate before the step (d). The aforementioned project (d) has: Preparation of works for pushing components and positioning components (d1); The step of adjusting the directions of the support substrate and the growth substrate so that the [110] direction of the support substrate is substantially parallel to the [110] direction or the [1-10] direction of the growth substrate (d2) ; A step (d3) of pushing the support substrate and the growth substrate toward the positioning member by the pushing member in order to maintain the direction adjusted by the step (d2); and A step (d4) of laminating the support substrate and the growth substrate through the bonding layer by applying pressure to the stacked support substrate and the growth substrate while performing the step (d3).

Because of this method, the degree of freedom regarding the rotation direction in the state where the two substrates are overlapped and aligned is suppressed, so dicing can be performed while maintaining the direction adjusted in the process (d2). [Effect of the invention]

According to the present invention, in an LED element formed by forming an epitaxial layer on a support substrate other than a growth substrate, occurrence of cracks in the back side of the support substrate can be suppressed, and the appearance yield of the product can be improved.

Embodiments of the LED element and its manufacturing method of the present invention will be described with reference to the drawings. Furthermore, the following drawings are for illustrative purposes only, and the size ratios in the drawings are not necessarily the same as the actual size ratios. In addition, there are cases where the dimensional ratio does not match among the respective drawings.

In this specification, the expression "formation of layer B on the upper layer of layer A" includes, of course, the case where layer B is formed directly on the surface of layer A, and also includes the case where layer B is formed on the surface of layer A with a thin film interposed therebetween. intent of the situation. In addition, the term "thin film" here refers to a layer having a film thickness of 10 nm or less, preferably a layer of 5 nm or less.

FIG. 1 is a cross-sectional view schematically showing the structure of an LED element according to this embodiment. The LED element 1 shown in FIG. 1 includes an epitaxial layer 20 formed on the upper layer of a support substrate 11 . The LED element 1 shown in FIG. 1 corresponds to a schematic cross-sectional view taken along the XY plane at a predetermined position. In the following description, refer appropriately to the XYZ coordinate system attached to FIG. 1 .

In addition, in the following description, when expressing a direction and distinguishing a positive and negative direction, it will add the sign of plus and minus like "+X direction" and "-X direction". In addition, when expressing a direction without distinguishing between positive and negative directions, it is only described as "X direction". That is, in this specification, when only "X direction" is described, both "+X direction" and "-X direction" are included. The same applies to the Y direction and the Z direction.

The LED element 1 of the present embodiment generates infrared light L in the epitaxial layer 20 (more specifically, in the active layer 25 described later). More specifically, as shown in FIG. 1 , the infrared light L ( L1 , L2 ) is taken out in the +Y direction based on the active layer 25 . Infrared light L is, for example, light having a peak wavelength of not less than 1000 nm and not more than 2000 nm.

[Component structure] Hereinafter, the structure of the LED element 1 will be described in detail.

(Supporting substrate 11 ) The supporting substrate 11 is made of Si and is doped with a high concentration of dopant so as to exhibit conductivity. As an example, a Si substrate doped with B (boron) at a dopant concentration of 1×10 ¹⁹ /cm ³ or more and having a resistivity of 10 mΩcm or less is used. As a dopant, for example, P, As, Sb, etc. can be used other than B (boron). Conductivity is ensured by doping dopants at a high concentration. In addition, by using the Si substrate, high heat dissipation can be ensured, and the manufacturing cost can be reduced.

The thickness (length in the Y direction) of the supporting substrate 11 is not particularly limited, but is, for example, 50 μm or more and 500 μm or less, preferably 100 μm or more and 300 μm or less.

One main surface of the supporting substrate 11 is a (001) surface.

(bonding layer 13) The LED element 1 shown in FIG. 1 includes the bonding layer 13 formed on the upper layer of the support substrate 11 . The bonding layer 13 is made of a low-melting solder material, such as Au, Au—Zn, Au—Sn, Au—In, Au—Cu—Sn, Cu—Sn, Pd—Sn, Sn, and the like. As will be described later with reference to FIG. 8A , this bonding layer 13 is used for bonding the growth substrate 3 and the supporting substrate 11 formed on the upper surface of the epitaxial layer 20 . The thickness of the bonding layer 13 is not particularly limited, but is, for example, not less than 0.5 μm and not more than 5.0 μm, preferably not less than 1.0 μm and not more than 3.0 μm.

(barrier layer 14, barrier layer 16) The LED element 1 shown in FIG. 1 is provided with barrier layers (14, 16). The barrier layers ( 14 , 16 ) are provided to suppress the diffusion of the solder material constituting the bonding layer 13 , and the materials are not limited as long as the related functions can be realized. For example, Ti, Pt, W, Mo, Ni, etc. can be used. As an example, it is comprised by the laminated body of Ti/Pt/Au.

The thickness of the barrier layer (14, 16) is not particularly limited, but is, for example, not less than 0.05 μm and not more than 3 μm, preferably not less than 0.2 μm and not more than 1 μm.

In addition, in the LED element 1 shown in FIG. 1, the barrier layer (14, 16) was formed, However, In this invention, it is optional whether to provide the barrier layer (14, 16).

(reflective layer 15) The LED element 1 shown in FIG. 1 includes a reflective layer 15 formed on an upper layer of the bonding layer 13 . The reflective layer 15 functions to guide the infrared light L2 traveling toward the support substrate 11 side (−Y direction) out of the infrared light L generated in the active layer 25 in the +Y direction. The reflective layer 15 is made of a conductive material and a material that exhibits high reflectivity with respect to infrared light L. As shown in FIG. The reflectance of the reflective layer 15 with respect to the infrared light L is preferably 70% or higher, more preferably 80% or higher, and particularly preferably 90% or higher.

In the case where the peak wavelength of the infrared light L is not less than 1000 nm and not more than 2000 nm, metal materials such as Ag, Ag alloy, Au, Al, and Cu can be used for the reflective layer 15 . The material constituting the reflective layer 15 is properly selected according to the wavelength of the light generated in the active layer 25 .

The thickness of the reflective layer 15 is not particularly limited, but is, for example, not less than 0.1 μm and not more than 2.0 μm, preferably not less than 0.3 μm and not more than 1.0 μm.

As shown in FIG. 1 , by forming the barrier layer 14 between the reflective layer 15 and the bonding layer 13 , the material constituting the bonding layer 13 diffuses on the reflective layer 15 side, thereby suppressing a decrease in the reflectance of the reflective layer 15 .

Furthermore, from the viewpoint of improving light extraction efficiency, as shown in FIG. 1 , it is preferable that the LED element 1 has a reflective layer 15 . In the present invention, whether or not the LED element 1 is equipped with a reflective layer 15 is optional.

(dielectric layer 17) The LED element 1 shown in FIG. 1 includes a dielectric layer 17 formed on a reflective layer 15 . The dielectric layer 17 is made of a material that exhibits electrical insulation and has high transmittance to infrared light L. As shown in FIG. The transmittance of the dielectric layer 17 to the infrared light L is preferably 70% or higher, more preferably 80% or higher, and particularly preferably 90% or higher.

In the case where the peak wavelength of the infrared light L is not less than 1000 nm and not more than 2000 nm, a material such as SiO ₂ , SiN, Al ₂ O ₃ can be used for the dielectric layer 17 . The material constituting the dielectric layer 17 is appropriately selected according to the wavelength of the light generated in the active layer 25 .

(epitaxy layer 20) The LED element 1 shown in FIG. 1 includes an epitaxial layer 20 formed on a dielectric layer 17 . The epitaxial layer 20 is composed of a multi-layer laminate. Specifically, the epitaxial layer 20 includes a contact layer 21 , a first covering layer 23 , an active layer 25 , and a second covering layer 27 . Each semiconductor layer (21, 23, 25, 27) constituting the epitaxial layer 20 is composed of a material which is lattice-matched to the growth substrate 3 described later and which enables epitaxial growth.

<<Contact Layer 21, First Covering Layer 23>> In this embodiment, the contact layer 21 is made of, for example, p-type GaInAsP. The thickness of the contact layer 21 is not limited, but is, for example, not less than 10 nm and not more than 1000 nm, preferably not less than 50 nm and not more than 500 nm. Also, the p-type dopant concentration of the contact layer is preferably not less than 5×10 ¹⁷ /cm ³ and not more than 3×10 ¹⁹ /cm ³ , more preferably not less than 1×10 ¹⁸ /cm ³ and not more than 2×10 ¹⁹ /cm3 ³ or less.

In this embodiment, the first cladding layer 23 is formed on the upper layer of the contact layer 21 , and is made of, for example, p-type InP. The thickness of the first covering layer 23 is not limited, but is, for example, not less than 1000 nm and not more than 10000 nm, preferably not less than 2000 nm and not more than 5000 nm. The p-type dopant concentration of the first cladding layer 23 is in a position separated from the active layer 25, and is preferably 1×10 ¹⁷ /cm ³ or more and 3×10 ¹⁸ /cm ³ or less, more preferably 5×10 10 /cm 3 or less. More than ¹⁷ /cm ³ and less than 3×10 ¹⁸ /cm ³ .

As the p-type dopant material contained in the contact layer 21 and the first cladding layer 23, Zn, Mg, Be, etc. can be used, Zn or Mg is preferable, and Zn is particularly preferable. In this embodiment, the contact layer 21 and the first covering layer 23 correspond to the "first semiconductor layer".

"Active layer 25" In this embodiment, the active layer 25 is composed of a semiconductor layer formed on the upper layer of the first cladding layer 23 . The active layer 25 is a material capable of generating light of a target wavelength, lattice-matched with the growth substrate 3 described later with reference to FIGS. 4A and 4B , and capable of epitaxial growth.

For example, when the LED element 1 that emits infrared light L having a peak wavelength of 1000 nm or more and 2000 nm or less is not realized, the active layer 25 may be a single-layer structure of GaInAsP, AlGaInAs, or InGaAs. An MQW (Multiple Quantum Well) structure of a quantum well layer made of InGaAs and a barrier layer made of GaInAsP, AlGaInAs, InGaAs, or InP having a band gap energy larger than that of the quantum well layer may also be used.

The film thickness of the active layer 25 is not less than 50 nm and not more than 2000 nm, preferably not less than 100 nm and not more than 300 nm, when the active layer 25 has a single-layer structure. Also, when the active layer 25 has an MQW structure, quantum well layers and barrier layers having a film thickness of 5 nm to 20 nm are stacked in a range of 2 to 50 cycles.

The active layer 25 may be doped n-type or p-type, or undoped. When n-type is doped, Si can be used as a dopant, for example.

<<Second Covering Layer 27>> In the present embodiment, the second covering layer 27 is formed on the upper layer of the active layer 25, and is made of, for example, n-type InP. The thickness of the second covering layer 27 is not limited, but is, for example, not less than 100 nm and not more than 10000 nm, preferably not less than 500 nm and not more than 5000 nm. The n-type dopant concentration of the second covering layer 27 is preferably not less than 1×10 ¹⁷ /cm ³ and not more than 5×10 ¹⁸ /cm ³ , more preferably not less than 5×10 ¹⁷ /cm ³ and not more than 4×10 ¹⁸ /cm 3 . ^cm3 or less. As the n-type impurity material doped in the second cladding layer 27, Sn, Si, S, Ge, Se, etc. can be used, and Si is particularly preferable. The second covering layer 27 corresponds to a "second semiconductor layer".

The first covering layer 23 and the second covering layer 27 are materials that do not absorb the infrared light L generated in the active layer 25, and are capable of lattice matching with the growth substrate 3 (see FIGS. The material for crystal growth is appropriately selected. When an InP substrate is used as the growth substrate 3 , a material such as GaInAsP, AlGaInAs or the like can be used other than InP as the first covering layer 23 and the second covering layer 27 .

(contact electrode 31) The LED element 1 shown in FIG. 1 is equipped with the contact electrode 31 formed to penetrate the dielectric material layer 17 in the Y direction at a plurality of places in the dielectric material layer 17 . The contact electrode 31 is connected to the contact layer 21 formed on the +Y side of the dielectric layer 17 and the reflective layer 15 formed on the −Y side of the dielectric layer 17 . That is, through the contact electrode 31 , the reflective layer 15 is electrically connected to the first covering layer 23 (first semiconductor layer).

The contact electrode 31 is made of a material which makes ohmic contact with the contact layer 21 . The contact electrode 31 is made of a material such as Au/Zn/Au, AuZn, AuBe as an example, and may be provided with a plurality of these materials. These materials have relatively lower reflectivity for infrared light L than the materials constituting the reflective layer 15 .

The pattern shape of the contact electrode 31 when viewed in the Y direction is arbitrary. However, the contact electrode 31 is a It is preferable to arrange|position plural number dispersedly in a surface direction.

The total area of all the contact electrodes 31 when viewed in the Y square is relative to the area of the epitaxial layer 20 (such as the active layer 25) in the plane direction, preferably less than 30%, more preferably less than 20%, and less than 15%. Especially ideal. If the total area of the contact electrodes 31 is relatively large, the infrared light L2 traveling from the active layer 25 to the support substrate 11 side (−Y direction) will be absorbed by the contact electrodes 31 , resulting in lower extraction efficiency. On the other hand, if the total area of the contact electrodes 31 is too small, the resistance value increases and the forward voltage increases.

(first electrode 33) The LED element 1 shown in FIG. 1 includes the first electrode 33 formed on the surface of the support substrate 11 opposite to the epitaxial layer 20 (-Y side). The first electrode 33 realizes ohmic contact with the support substrate 11 . The first electrode 33 is made of a material such as AuGe/Ni/Au, Pt/Ti, Ge/Pt, etc. as an example, and may have a plurality of these materials. The first electrode 33 is formed at a predetermined position on the rear surface side of the support substrate 11, and may not necessarily be formed on the entire rear surface.

(second electrode 32) The LED element 1 shown in FIG. 1 includes the second electrode 32 formed on the upper layer of the second covering layer 27 . It is preferable that the second electrode 32 is formed extending in a lattice shape on the upper layer of the second covering layer 27 when viewed in the Y direction. Thereby, the current flowing in the active layer 25 can be diffused in the surface direction, and light can be emitted in a wide range of the active layer 25 . However, in the present invention, the pattern shape of the second electrode 32 is arbitrary.

The second electrode 32 is made of materials such as Au/Zn/Au, AuZn, and AuBe as an example, and may include a plurality of these materials.

(sheet electrode 34) The LED element 1 shown in FIG. 1 includes a sheet electrode 34 formed on the upper surface of the second electrode 32 . In addition, in FIG. 1, although the sheet|seat electrode 34 is shown in the form which formed the whole upper surface of the 2nd electrode 32, this is for convenience of illustration. Actually, the chip electrode 34 may be formed on a part of the surface of the second electrode 32 extending in the plane direction. The sheet electrode 34 is made of, for example, Ti/Au, Ti/Pt/Au, or the like.

The sheet electrode 34 is provided in order to secure a region in contact with the bonding wire for power supply, however, whether or not the sheet electrode 34 is provided in the present invention is optional.

[direction] The LED element 1 shown in FIG. 1 has the structure of the wafer state. That is, as will be described later with reference to FIG. 10B , the wafer including the support substrate 11 is diced.

FIG. 2 is a diagram showing a plan view when only the support substrate 11 is extracted from the LED element 1 shown in FIG. 1 and viewed from the +Y side with crystal orientations using Miller indices added. As described above, the supporting substrate 11 is a Si substrate having the (001) plane as one main surface. Here, it is assumed that the epitaxial layer 20 is formed on the (001) plane of the support substrate 11 . That is, in FIG. 2 , a plan view of a state in which the (001) plane of the support substrate 11 faces the +Y side is shown.

As shown in FIG. 2 , the support substrate 11 is in the shape of a rectangular plate having a side substantially parallel to the [110] direction and a side substantially parallel to the [1-10] direction. That is, among the four sides constituting the support substrate 11, one pair of two sides facing each other is an angle within the range of 2° or less with respect to the [110] direction of the support substrate 11, and the other pair of two sides facing each other is The [1-10] direction of the support substrate 11 is an angle within a range of 2° or less.

3A is a diagram showing a top view when only the second coating layer 27 (second semiconductor layer) is extracted from the LED element 1 shown in FIG. 1 and viewed from the +Y side, with crystal orientations using Miller indices added. .

As described later with reference to FIG. 5A , the epitaxial layer 20 including the second coating layer 27 is formed by epitaxial growth on the growth substrate 3 whose main surface is the (001) plane. That is, each semiconductor layer constituting the epitaxial layer 20 is grown while maintaining the crystal orientation of the growth substrate 3 . Thereafter, as will be described later with reference to FIGS. 8A and 8B , the growth substrate 3 is removed after being bonded to the support substrate 11 with the epitaxial layer 20 facing the support substrate 11 side. That is, the principal surface of the epitaxial layer 20 is the same (001) plane as that of the growth substrate 3 , and this plane faces the supporting substrate 11 side. Therefore, FIG. 3A shows a plan view of a state where the (00-1) plane on the back side faces the +Y side with respect to the (001) plane of the second covering layer 27 . However, the epitaxial layer 20 may be formed on the (00-1) plane of the growth substrate 3 .

As shown in FIGS. 2 and 3A , in the LED element 1 of the present embodiment, the [110] direction of the second covering layer 27 is substantially parallel to the [110] direction of the support substrate 11 . That is, the angle formed by the [110] direction of the second covering layer 27 and the [110] direction of the supporting substrate 11 is within a range of 2° or less. Furthermore, when evaluating the angles between directions, the positive and negative directions of each direction are irrelevant. That is, the [110] direction and the [-1-10] direction are regarded as the same direction, and similarly, the [1-10] direction and the [-110] direction are regarded as the same direction.

In addition, the angle formed by the [110] direction of the second coating layer 27 and the [110] direction of the support substrate 11 can be measured, for example, using an X-ray diffraction method (XRD method).

In other words, the aforementioned content means that the [110] direction of each semiconductor layer constituting the epitaxial layer 20 is substantially parallel to the [110] direction of the supporting substrate 11 . In the supporting substrate 11 made of Si, the splitting property of the {110} plane is higher than that of the {100} plane. Then, the [110] direction, which is the direction of one side of each semiconductor layer constituting the epitaxial layer 20, becomes substantially parallel to the [110] direction of the support substrate 11, which means that during the dicing process for wafering, the direction along the support substrate 11 [110] direction for cutting. Therefore, the cracks starting from the cracks on the back side of the support substrate 11 generated during the dicing process can be extended along the dicing direction. Thereby, the propagation of cracks toward the inside of the wafer can be suppressed, and the size and amount of cracks can be suppressed. Details will be described later.

Moreover, from the viewpoint of setting the cutting direction substantially parallel to the direction with high cleaveability of the supporting substrate 11, as shown in FIG. 3B , the [1- 10] direction, and the [1-10] direction (see FIG. 2 ) of the support substrate 11 may be arranged so as to have an angle within the range of 2° or less.

[Production method] An example of the manufacturing method of the LED element 1 mentioned above is demonstrated with reference to each figure shown to FIG. 4A - FIG. 10B. 4A, 5A-5C, 6A, 7, 8A, 9A-9E, and 10A-10B are cross-sectional views of a process in the manufacturing process. About other drawings, it mentions later below.

(step S1) As shown in FIG. 4A , a growth substrate 3 is prepared. In this embodiment, an InP substrate having a (001) plane as one main surface is ideally used. FIG. 4B is a plan view with the (001) plane of the growth substrate 3 as the upper surface. Here, as an example, an InP substrate provided with an orientation plane (OF) and an index plane (IF) is used as the growth substrate 3 . The OF system is formed on the (110) plane of the growth substrate 3 , and the IF system is formed on the (1-10) plane of the growth substrate 3 .

It should be noted that the growth substrate 3 is not limited to InP as long as it can grow the epitaxial layer 20 to be formed in the next process, and GaAs or GaP may be used.

This step S1 corresponds to process (a).

(step S2) As shown in FIG. 5A, the growth substrate 3 is transported into a MOCVD (Metal Organic Chemical Vapor Deposition) device, and on the (001) surface of the growth substrate 3, a buffer layer 29, an etch stop layer (ES layer) 28, a second The coating layer 27 , the active layer 25 , the first coating layer 23 and the contact layer 21 are epitaxially grown sequentially to form the epitaxial layer 20 . In this step S2, according to the material and film thickness of the growing layer, the type and flow rate of the raw material gas, processing time, ambient temperature, etc. are adjusted appropriately.

As an example, n-type InP with Si as a dopant is formed into a film with a predetermined film thickness (for example, about 500 nm) to form the buffer layer 29, and thereafter, the film-forming material is different from that of the buffer layer with a predetermined film thickness (for example, about 200 nm). 29 layer (here InGaAs layer) to form ES layer 28. Thereafter, the second covering layer 27 , the active layer 25 , the first covering layer 23 , and the contact layer 21 are sequentially formed in a state where the growth conditions are set so as to have the above-mentioned film thickness and composition.

This step S2 corresponds to process (b).

(Step S3 ) After the wafer on which the epitaxial layer 20 is formed is taken out from the MOCVD apparatus, a dielectric layer 17 made of, for example, SiO ₂ is formed by plasma CVD (refer to FIG. 5B ). Next, a photoresist mask patterned by photolithography is formed on the surface of the dielectric layer 17 . After removing the dielectric layer 17 formed in the opening of the photoresist by an etching method using a predetermined chemical such as buffered hydrofluoric acid, a contact made of, for example, Au/Zn/Au is formed by an EB evaporation device. The material film of the electrode 31 .

Next, the contact electrode 31 is formed by removing the photoresist mask and peeling off the material film formed in the unnecessary area (except for the area to be formed with an alignment mark described later). At this time, an alignment mark made of the same material as the contact electrode 31 is formed on a part of the upper surface of the epitaxial layer 20 with reference to the OF formed on the growth substrate 3 . Preferably, the alignment marks are provided at two or more positions sufficiently separated from the area where the LEDs are to be formed in the surface direction of the growth substrate 3 . Thereafter, ohmic contact between the contact layer 21 and the contact electrode 31 is achieved by applying an alloy treatment (annealing treatment) by, for example, heating at 450° C. for 10 minutes.

(step S4) As shown in FIG. 5C , the reflective layer 15 , the barrier layer 14 , and the bonding layer 13 a are sequentially formed. For example, using an EB vapor deposition device to form a film of Al/Au with a predetermined film thickness to form the reflective layer 15, and then forming a film of Ti/Pt/Au with a predetermined film thickness to form the barrier layer 14, followed by Next, a Ti/Au film is formed with a predetermined film thickness to form the bonding layer 13a. The bonding layer 13a may be made of the same material as the bonding layer 13 described above.

(step S5) As shown in FIG. 6A, another supporting substrate 11 different from the growth substrate 3 is prepared. In the present embodiment, a conductive Si substrate doped with B (boron) at a high concentration with the (001) plane as one main surface is used. The resistivity of the supporting substrate 11 is preferably less than 100 mΩ·cm (=1 mΩ·m).

FIG. 6B is a plan view with the (001) plane of the support substrate 11 as the upper surface. Here, as the supporting substrate 11 , an Si substrate having an orientation flat (OF) formed on a (110) plane is used as an example.

This step S5 corresponds to process (c).

(step S6) As shown in FIG. 7 , on the main surface of the support substrate 11 , a barrier layer 16 and a bonding layer 13 b are formed. The barrier layer 16 and the bonding layer 13b are formed by the same method as the above-mentioned barrier layer 14 and bonding layer 13a in step S4.

This step S6 corresponds to process (g). In addition, whether to form the barrier layer 16 is optional.

(step S7) Next, as shown in FIG. 8A , the growth substrate 3 and the support substrate 11 are bonded together through the bonding layer 13 ( 13 a , 13 b ). Ideally, they are stacked and aligned in a state where the surfaces of the bonding layers 13 (13a, 13b) have been cleaned.

During this stacking and alignment process, adjustments are made so that the positional relationship between the growth substrate 3 and the support substrate 11 does not deviate. FIG. 8B is a diagram schematically showing an example of a method for maintaining the aligned state. A pressing member 52 made of a leaf spring or the like, and a positioning member 51 made of a pin or the like are prepared (process (d1)). Then, adjustment is performed so that the OF of the growth substrate 3 (InP) and the OF of the support substrate 11 (Si) become in the same direction (process (d2)). In this state, the pressing member 52 is pressed toward the positioning member 51 side by the external force f52. Thereby, the [110] direction of the growth substrate 3 and the [110] direction of the support substrate 11 are held so as to be substantially parallel (process (d3)).

By performing this pressing, the [110] direction of the growth substrate 3 and the [110] direction of the support substrate 11 are kept substantially in parallel, and the temperature is increased while being pressurized by the wafer bonding apparatus (process (d4)). Thereby, the bonding layer 13 a on the growth substrate 3 and the bonding layer 13 b on the support substrate 11 are melted and integrated (bonding layer 13 ), so that both substrates are bonded. As a result, after the growth substrate 3 and the support substrate 11 are bonded, the [110] direction of the growth substrate 3 and the [110] direction of the support substrate 11 also become substantially parallel.

This step S7 corresponds to process (d).

(step S8) As shown in FIG. 9A , the growth substrate 3 is removed. As an example, the growth substrate 3 is removed by immersing the bonded substrates in a hydrochloric acid-based etchant. At this time, since the ES layer 28 formed of a material different from that of the growth substrate 3 and the buffer layer 29 is insoluble in the hydrochloric acid-based etchant, the etching process is stopped when the ES layer 28 is exposed.

This step S8 corresponds to process (e).

(step S9) As shown in FIG. 9B , the ES layer 28 is removed to expose the second covering layer 27 . For example, if necessary, after washing with pure water, the ES layer 28 is removed by immersing in a predetermined chemical solution that is soluble to the ES layer 28 but insoluble to the second coating layer 27 . As an example, a mixed solution (SPM) of sulfuric acid and hydrogen peroxide water can be used.

(step S10) As shown in FIG. 9C , the second electrode 32 is formed on the exposed surface of the second covering layer 27 . More specifically, a photoresist mask patterned by photolithography is formed on the surface of the second coating layer 27 based on the calibration mark formed in step S3. Next, the material for forming the second electrode 32 (for example, Au/Ge/Au) is formed into a film by an EB vapor deposition device, and then the second electrode 32 is formed by lift-off. After that, in order to realize the ohmic contact of the second electrode 32, alloying treatment (annealing treatment) is applied by, for example, heating treatment at 450° C. for 10 minutes.

Next, a sheet electrode 34 is formed at a predetermined position on the upper surface of the second electrode 32 . In this case, similarly to the second electrode 32 , it can be realized by a film formation and peeling process by an EB vapor deposition device.

(step S11) As shown in FIG. 9D , mesa etching is performed on the epitaxial layer 20 . More specifically, a photoresist patterned by photolithography is formed based on the calibration mark formed in step S3. Specifically, a photoresist with branch opening regions along the [110] direction and the [1-10] direction of the second cladding layer 27 is formed. Next, the photoresist is used as a mask to perform etching with a predetermined etchant to etch a predetermined position of the epitaxial layer 20 to expose the dielectric layer 17 . Thereafter, the photoresist is removed with a cleaning solution such as acetone.

Through this process, dicing lines along the [110] direction and the [1-10] direction are formed on the epitaxial layer 20 .

(step S12) As shown in FIG. 9E , after adjusting the thickness of the back side of the support substrate 11 , the first electrode 33 is formed on the back side of the support substrate 11 . As a specific method of forming the first electrode 33 , similarly to the second electrode 32 , the material for forming the first electrode 33 (for example, Ti/Pt/Au) is deposited by an EB vapor deposition device, and then formed by lift-off.

In addition, adjustment of the thickness of the back side of the support substrate 11 may be performed as needed, and is not necessarily an essential process. In addition, the degree of thickness is also appropriately set depending on the application and the like.

(step S13) Wafering is performed by dicing each support substrate 11 . This process will be described with reference to FIG. 10A and FIG. 10B .

FIG. 10A is a diagram schematically showing a cross-section of the wafer at the point in time when step S12 is completed. By performing the step S11 of the high platform etching process, a cutting line 38 for distinguishing each element is formed on the epitaxial layer 20 , and each epitaxial layer 20 is respectively formed on the common support substrate 11 .

In this state, dicing is performed together with the supporting substrate 11 along the dicing line 38 formed in step S11 using, for example, a diamond knife or the like (see FIG. 10B ). More specifically, the blade 41 is inserted to perform dicing in a state where the back side (first electrode 33 side) of the support substrate 11 is attached to the dicing tape 40 and fixed. At this time, the cutting thickness (cutting depth wd40 ) of the dicing tape 40 is appropriately set.

After cutting, it is necessary to remove cutting debris by proper cleaning and other processes.

At a point before the start of step S13 , cutting lines 38 along the [110] direction and the [1-10] direction are formed on the epitaxial layer 20 . Then, in step S7 , the support substrate 11 and the growth substrate 3 are bonded such that the [110] direction of the growth substrate 3 and the [110] direction of the support substrate 11 are substantially parallel. That is, in a state where the [110] direction of the epitaxial layer 20 is substantially parallel to the [110] direction of the support substrate 11 , the dicing is performed along the [110] direction and the [1-10] direction of the epitaxial layer 20 .

Thereby, the support substrate 11 is also diced along the dicing lines 38 formed substantially parallel to the [110] direction and the [1-10] direction of the support substrate 11 . The [110] direction and the [1-10] direction of the support substrate 11 are directions parallel to the {110} plane with high cleavability, so it is assumed that even if the back side of the support substrate 11 is cracked during the execution of step S13, It is also possible to make the crack starting from this crack be along the cutting direction. Thereby, the wafer obtained after the execution of step S13 can suppress the propagation of cracks towards the inside of the wafer.

This step S13 corresponds to process (f).

[verify] Hereinafter, it will be verified using the examples regarding the places where cracks can be suppressed according to the aforementioned LED elements.

(Example 1) The LED element manufactured by the method of the above-mentioned steps S1 to S13 was taken as Example 1. Here, in step S7, bonding is carried out in a state where the OF of the growth substrate 3 (InP) and the OF of the support substrate 11 (Si) are adjusted and held in the same direction. At this time, the angle formed by the [110] direction of the growth substrate 3 and the [110] direction of the support substrate 11 is 0.4°. This angle is measured with a metal microscope equipped with a coordinate measuring function.

Also, in step S13, the dicing pitch (that is, the corresponding wafer width) is set to 350 μm. The width of the cuts (cutting grooves) formed in the support substrate 11 after step S13 was completed was 30 μm on average.

Furthermore, in step S11, according to the alignment marks added to the epitaxial layer 20 in step S3, the plateau etching is performed, so the direction of plateau etching (the direction of the cutting line) is relative to the [110] direction and the [ The 1-10] direction suppresses deviation within the range of ±0.3°, and the [110] direction and the [1-10] direction of the growth substrate 3 can be regarded as the same direction.

(Example 2) Except that in step S7, the OF of the growth substrate 3 (InP) and the OF of the support substrate 11 (Si) are adjusted and held in the same direction, and bonding is carried out, the same as in Example 1 will be used. The LED element manufactured by the same method is used as Example 2. At this time, the angle formed by the [1-10] direction of the growth substrate 3 and the [110] direction of the support substrate 11 is 0.6°.

(Example 3) An LED element manufactured by the same method as in Example 1 was used as Example 2 except that the accuracy of alignment adjustment in step S7 was eased. At this time, the angle formed by the [110] direction of the growth substrate 3 and the [110] direction of the support substrate 11 is 1.7°.

(comparative example 1) Except in step S7, no jigs such as the positioning member 51 and the pressing member 52 are used, and only the OF of the growth substrate 3 (InP) and the OF of the support substrate 11 (Si) are brought into the same direction, and then bonded. Except that, the LED element manufactured by the method similar to Example 1 was made into the comparative example 1. At this time, the angle formed by the [110] direction of the growth substrate 3 and the [110] direction of the support substrate 11 is 4.0°.

11A to 11C are photographs of the back side of the supporting substrate 11 included in the LED elements of Example 1, Example 2, and Comparative Example 1. FIG. In detail, after attaching the sheet electrode 34 side of the LED element to another dicing tape different from the dicing tape 40 used in step S13, the dicing tape 40 is peeled off, and each LED is observed with a ranging microscope from the first electrode 33 side. Photos of the components.

In any of the photographs, the rectangular areas are wafer portions, and the edges correspond to the gaps between adjacent wafers after dicing. Comparing the photographs of FIG. 11A and FIG. 11B , according to the photograph of FIG. 11C , it can be confirmed that the gap enters the inner side of the wafer from the marginal area between the diced wafers. The extent of this entry corresponds to the rupture entry length c1.

According to the photo of FIG. 11C, it can be inferred that the direction of the line formed by the marginal regions of the wafers after dicing is inclined to some extent (inclination angle 4°) to the [110] direction of the support substrate 11, resulting in crack penetration. chip inside.

Table 1 described below is a table summarizing the evaluations of Examples 1 to 3 and Comparative Example 1. As an evaluation standard, the crack entry length c1 of each sample is more than 50% of the slit width, that is, more than 15 μm is regarded as a defective product, and the appearance defect rate is calculated.

According to Table 1, the [110] direction or [1-10] direction of the growth substrate 3 is almost parallel to the [110] direction of the support substrate 11, in other words, the second coating layer 27 In Example 1 and Example 2 in which the [110] direction or the [1-10] direction is almost parallel to the [110] direction of the support substrate 11, the defect rates were 0% and 2%, respectively, and it was confirmed that cracking could be suppressed to the inside of the wafer. carried out. Also, the angle formed by the [110] direction of the growth substrate 3 and the [110] direction of the support substrate 11 is 1.7°. In other words, the [110] direction of the second coating layer 27 and the [110] direction of the support substrate 11 In Example 3 where the direction is 1.7°±0.3°, compared with Comparative Example 1, the defect rate can be reduced to 1/4 or less, and it is confirmed that cracks can be suppressed from progressing inside the wafer.

As described above, it can be estimated that in the LED element of Comparative Example 1, only the OF of the growth substrate 3 (InP) and the OF of the support substrate 11 (Si) are set in the same direction, but the [110 ] directions parallel to each other while maintaining the direction, and the relative positional relationship between the growth substrate 3 and the support substrate 11 is moved to the rotation direction, the [110] direction of the growth substrate 3 (InP) and the [110] direction of the support substrate 11 The formed angle becomes 4°. In other words, the [110] direction or the [1-10] direction of the second coating layer 27 cannot be substantially parallel to the [110] direction of the supporting substrate 11 only by the degree of alignment. That is, when bonding, the [110] direction of the support substrate 11 is adjusted to be substantially parallel to the [110] direction or the [1-10] direction of the growth substrate 3, and bonded while maintaining the relationship. The [110] direction or [1-10] direction of the second coating layer 27 of the LED element obtained after dicing is substantially parallel to the [110] direction of the support substrate 11, which can suppress the occurrence of cracks.

[Other Embodiments] Hereinafter, other embodiments will be described.

<1> In the LED element 1 shown in FIG. 1 , an uneven portion may be formed on the surface on the +Y side of the second covering layer 27 . By forming the concave-convex portion, the amount of infrared light L ( L1 , L2 ) traveling in the +Y direction from the active layer 25 is reflected on the surface of the second coating layer 27 to the active layer 25 side is reduced, and the light extraction efficiency is improved.

The concavo-convex portion is formed, for example, by applying wet etching to the surface of the second covering layer 27 in the region where the second electrode 32 is not formed after step S10 .

<2> Each of the steps S1 to S13 described above may be appropriately changed back and forth as long as the order does not affect the manufacture of the LED element 1 .

<3> In the above step S7, the positioning member 51 and the pressing member 52 are used to bond while maintaining the aligned state. However, the method of maintaining the state of the bit is not limited to this method. As another method, any method can be used as long as it can perform alignment with higher accuracy than the alignment only by visual inspection. For example, a method of aligning the alignment plane and the alignment mark using a bond aligner (Bond aligner) can be used. method etc.

1: LED components 3: Growth substrate 11: Support substrate 13:The next layer 13a: bonding layer 13b: bonding layer 14: Barrier layer 15: reflective layer 16: Barrier layer 17: Dielectric layer 20: epitaxial layer 21: Contact layer 23: The first covering layer 25: active layer 27: Second coating layer 28: ES layer 29: buffer layer 31: contact electrode 32: Second electrode 33: The first electrode 34: Sheet electrode 38: Cutting line 40: Cutting Tape 41: blade 51: Positioning components 52: push member c1: burst entry length f52: external force L, L1, L2: infrared light wd40: cutting depth

[ Fig. 1] Fig. 1 is a cross-sectional view schematically showing the structure of an embodiment of the LED element of the present invention. [ Fig. 2 ] A diagram showing a plan view when only the support substrate 11 is extracted from Fig. 1 and viewed from the +Y side, with crystal orientations using Miller indices added. [FIG. 3A] A diagram showing a plan view when only the second coating layer 27 is extracted from FIG. 1 and viewed from the +Y side with crystal orientations using Miller indices added. [ FIG. 3B ] Another diagram showing a top view when only the second coating layer 27 is extracted from FIG. 1 and viewed from the +Y side, with crystal orientations using Miller indices added. [FIG. 4A] A cross-sectional view illustrating one step of the method of manufacturing the LED element shown in FIG. 1. [FIG. [ FIG. 4B ] A plan view with the (001) plane of the growth substrate 3 as the upper surface. [FIG. 5A] A cross-sectional view illustrating one step of the manufacturing method of the LED element shown in FIG. 1. [FIG. [FIG. 5B] A cross-sectional view illustrating one step of the method of manufacturing the LED element shown in FIG. 1. [FIG. [FIG. 5C] A cross-sectional view illustrating one step of the manufacturing method of the LED element shown in FIG. 1. [FIG. [FIG. 6A] A cross-sectional view illustrating one step of the method of manufacturing the LED element shown in FIG. 1. [FIG. [ FIG. 6B ] A plan view with the (001) plane of the support substrate 11 as the upper surface. [ Fig. 7] Fig. 7 is a cross-sectional view illustrating one step of the method of manufacturing the LED element shown in Fig. 1 . [FIG. 8A] A cross-sectional view illustrating one step of the method of manufacturing the LED element shown in FIG. 1. [FIG. [ FIG. 8B ] A diagram schematically showing an example of a method for maintaining the aligned state of the growth substrate 3 and the support substrate 11 . [FIG. 9A] A cross-sectional view illustrating one step of the method of manufacturing the LED element shown in FIG. 1. [FIG. [ Fig. 9B ] A cross-sectional view illustrating one step of the method of manufacturing the LED element shown in Fig. 1 . [FIG. 9C] A cross-sectional view illustrating one process of the manufacturing method of the LED element shown in FIG. 1. [FIG. [FIG. 9D] A cross-sectional view illustrating one step of the manufacturing method of the LED element shown in FIG. 1. [FIG. [FIG. 9E] A cross-sectional view illustrating one process of the manufacturing method of the LED element shown in FIG. 1. [FIG. [FIG. 10A] A cross-sectional view illustrating one step of the manufacturing method of the LED element shown in FIG. 1. [FIG. [FIG. 10B] A cross-sectional view illustrating one step of the method of manufacturing the LED element shown in FIG. 1. [FIG. [FIG. 11A] A photograph of the back side of the supporting substrate 11 of the LED element of Example 1. [FIG. [FIG. 11B] A photograph of the back side of the supporting substrate 11 of the LED element of Example 2. [FIG. [ FIG. 11C ] A photograph of the back side of the supporting substrate 11 of the LED element of Comparative Example 1. [ FIG.

1: LED components

11: Support substrate

13:The next layer

14: Barrier layer

15: reflective layer

16: Barrier layer

17: Dielectric layer

20: epitaxial layer

21: Contact layer

23: The first covering layer

25: active layer

27: Second coating layer

31: contact electrode

32: Second electrode

33: The first electrode

34: Sheet electrode

L, L1, L2: infrared light

Claims (11)

A kind of LED element, it is characterized in that possessing: The supporting substrate is made of Si; The bonding layer is formed on the upper layer of the aforementioned support substrate and is made of metal materials; The n-type or p-type first semiconductor layer is formed on the upper layer of the aforementioned bonding layer; The active layer is formed on the upper layer of the aforementioned first semiconductor layer; and The second semiconductor layer is formed on the upper layer of the aforementioned active layer, and its conductivity type is different from that of the aforementioned first semiconductor layer; The above-mentioned supporting substrate is a rectangular plate having a side substantially parallel to the [110] direction and a side substantially parallel to the [1-10] direction with the (001) plane as one main surface; The second semiconductor layer has a (001) plane as one main surface, and the [110] direction or [1-10] direction of the second semiconductor layer is substantially parallel to the [110] direction of the support substrate. The LED element as described in Claim 1, wherein, The angle formed by the [110] direction or the [1-10] direction of the second semiconductor layer and the [110] direction of the support substrate is 2° or less. The LED component as described in claim 1 or 2, wherein: The first electrode is formed on the main surface of the main surface of the support substrate, which is opposite to the side where the bonding layer is formed; and The second electrode is formed on the upper layer of the second semiconductor layer. The LED component as described in claim 3, wherein: The reflective layer is formed on the upper layer of the bonding layer, and the lower layer of the first semiconductor layer is made of a material that has a higher reflectance to the light generated in the active layer than the bonding layer; The dielectric layer is formed at the position of the upper layer of the aforementioned reflective layer, and at the position of the lower layer of the aforementioned first semiconductor layer; and The contact electrode is in a part of the dielectric layer, penetrating through the dielectric layer in a direction perpendicular to the main surface of the support substrate, and electrically connecting the reflective layer and the first semiconductor layer. The LED element as described in claim 1 or 2, wherein, All of the first semiconductor layer, the active layer, and the second semiconductor layer are made of a material capable of lattice matching with the growth substrate made of InP. The LED element as described in claim 1 or 2, wherein, Each of the first semiconductor layer, the active layer, and the second semiconductor layer is composed of one or two or more of the group consisting of InP, GaInAsP, AlGaInAs, AlInAs, and InGaAs. The LED element as described in claim 1 or 2, wherein, The active layer generates infrared light having a peak wavelength of not less than 1000 nm and less than 2000 nm. A method for manufacturing an LED element, which is the method for manufacturing an LED element described in claim 1, characterized in that it has: Process (a) of preparing a growth substrate with the (001) plane as one main surface; Step (b) of sequentially epitaxially growing the aforementioned second semiconductor layer, the aforementioned active layer, and the aforementioned first semiconductor layer on the (001) plane of the aforementioned growth substrate to form the aforementioned epitaxial layer; The process (c) of preparing the aforementioned support substrate with the (001) plane as one of the principal planes; While keeping the [110] direction of the aforementioned support substrate substantially parallel to the [110] direction or the [1-10] direction of the aforementioned growth substrate, the aforementioned epitaxial layer formed on the aforementioned growth substrate is directed towards the aforementioned supporting substrate. The process (d) of laminating the aforementioned support substrate and the aforementioned growth substrate in the state of the side; After the aforementioned process (d), the process (e) of stripping the aforementioned growth substrate; and In the state where the support substrate side is fixed, from the side of the epitaxial layer located on the opposite side to the support substrate, along a direction substantially parallel to the [110] direction of the second semiconductor layer, and to the second A process (f) of cutting in a direction substantially parallel to the [1-10] direction of the semiconductor layer. The method for manufacturing an LED element as described in claim 8, wherein, In the step (d), the support substrate and the growth substrate are bonded while keeping the orientation plane formed on the support substrate in the same direction as the orientation plane or index plane formed on the growth substrate. The method for manufacturing an LED element as described in claim 8 or 9, wherein: Before the aforementioned process (d), the process (g) of forming the aforementioned bonding layer on the upper layer of the aforementioned epitaxial layer and the upper layer of the aforementioned support substrate; The aforementioned project (d) has: Preparation of works for pushing components and positioning components (d1); The step of adjusting the directions of the support substrate and the growth substrate so that the [110] direction of the support substrate is substantially parallel to the [110] direction or the [1-10] direction of the growth substrate (d2) ; A step (d3) of pushing the support substrate and the growth substrate toward the positioning member by the pushing member in order to maintain the direction adjusted by the step (d2); and A step (d4) of laminating the support substrate and the growth substrate through the bonding layer by applying pressure to the stacked support substrate and the growth substrate while performing the step (d3). The method of manufacturing an LED element as described in claim 8 or 9, wherein, The aforementioned growth substrate is an InP substrate; All of the first semiconductor layer, the active layer, and the second semiconductor layer are made of a material capable of lattice matching with the growth substrate made of InP.

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