JP2023008413A - Infra-red led element - Google Patents

Abstract

To improve light extraction efficiency than before while realizing an infra-red LED element having a peak emission wavelength of 1000 nm or more with a vertical structure.SOLUTION: An infra-red LED element shows a peak emission wavelength of 1000 nm or more, and includes: a conductive support substrate; a conductive layer formed on an upper layer of the conductive support substrate; an insulation layer formed on an upper layer of the conductive layer; a p-type or n-type first semiconductor layer formed on an upper layer of the insulation layer; an active layer formed on an upper layer of the first semiconductor layer; a second semiconductor layer formed on an upper layer of the active layer and having a conductive type different from the first semiconductor layer; an inner electrode which electrically connects the first semiconductor layer and the support substrate while penetrating the insulation layer at a plurality of positions dispersed in a direction parallel to the main surface of the support substrate; an upper electrode formed on an upper layer of the second semiconductor layer; and an alloy layer which is formed in a boundary of the second semiconductor layer and the upper electrode, composed of an alloy of a constituent material of the upper electrode and a constituent material of the second semiconductor layer, and has an average thickness of 150 nm or less.SELECTED DRAWING: Figure 1

Description

TECHNICAL FIELD The present invention relates to an infrared LED element, and more particularly to an infrared LED element having a peak emission wavelength of 1000 nm or more.

In recent years, semiconductor light-emitting devices that emit light in the infrared region with a wavelength of 1000 nm or longer have been widely used in applications such as security/surveillance cameras, gas detectors, medical sensors, and industrial equipment.

A semiconductor light-emitting device with an emission wavelength of 1000 nm or more has been generally manufactured by the following procedure (see Patent Document 1 below). That is, on an InP substrate as a growth substrate, a semiconductor layer of a first conductivity type, an active layer (sometimes referred to as a “light-emitting layer”), and a semiconductor of a second conductivity type, which are lattice-matched to the InP substrate, are formed. The layers are epitaxially grown in sequence. After that, an electrode for current injection is formed on the semiconductor wafer, and the wafer is cut into chips.

Conventionally, as a semiconductor light emitting device having an emission wavelength of 1000 nm or more, there is a background that the development of a semiconductor laser device has been advanced. On the other hand, the development of LED elements has not progressed as much as that of laser elements, partly because there were not many uses for them.

However, in recent years, with the spread of applications, there has been a demand for an improvement in the light output of infrared LED elements as well. An InP substrate exhibits a high refractive index of 3 or more, like a GaAs substrate used in the visible light region. Therefore, when light is to be extracted through the InP substrate, total reflection occurs due to the difference in refractive index at the interface with air, limiting the light extraction efficiency to a low level. Furthermore, since the InP substrate has a high thermal resistance, the optical output tends to be saturated when driven with a large current. Due to these circumstances, the structure disclosed in Patent Document 1 is not suitable for realizing an LED element that obtains a high light output.

As a method of obtaining a higher light output than the structure disclosed in Patent Document 1, for example, adoption of the structure disclosed in Patent Document 2 is conceivable. That is, it is considered that a structure realized by removing the growth substrate after bonding the growth substrate on which the epitaxial layer is formed to the conductive support substrate exhibiting high heat dissipation is effective. However, the target wavelength of the light-emitting element described in Patent Document 2 is lower than 1000 nm.

JP-A-4-282875 JP 2012-129357 A

An LED element as described in Patent Document 2, that is, one electrode is arranged above the active layer and the other electrode is arranged below the active layer, and the active layer is perpendicular to the surface of the substrate. An LED element that emits light when a current is applied in a direction is sometimes called a "vertical structure."

An object of the present invention is to realize an infrared LED element having a peak emission wavelength of 1000 nm or more in a vertical structure and to improve the light extraction efficiency as compared with the conventional one.

An infrared LED element according to the present invention is an infrared LED element having a peak emission wavelength of 1000 nm or more,
a conductive support substrate;
a conductive layer formed on the support substrate;
an insulating layer formed on the conductive layer;
a p-type or n-type first semiconductor layer formed on the insulating layer;
an active layer formed on the first semiconductor layer;
a second semiconductor layer formed on the active layer and having a conductivity type different from that of the first semiconductor layer;
an internal electrode that penetrates the insulating layer at a plurality of positions dispersed in a direction parallel to the main surface of the supporting substrate and electrically connects the first semiconductor layer and the supporting substrate;
an upper electrode formed on the upper layer of the second semiconductor layer;
an alloy layer formed at the interface between the second semiconductor layer and the upper electrode, made of an alloy of the constituent material of the upper electrode and the constituent material of the second semiconductor layer, and having an average thickness of 150 nm or less. It is characterized by

From the viewpoint of ensuring good electrical connection (ohmic property) with the semiconductor layer, when forming an electrode (upper electrode) positioned above the semiconductor layer, an electrode material is deposited on the upper surface of the semiconductor layer. Annealing treatment is then performed. The annealing process forms an alloy layer at the interface between the semiconductor layer and the upper electrode.

The metal material used as the electrode material is determined according to the material of the semiconductor layer. This is because the metal that can reduce the contact resistance with respect to the semiconductor layer differs depending on the material of the semiconductor layer. That is, the type of electrode material is determined by the material of the semiconductor layer, in other words, the emission wavelength. As a semiconductor material capable of realizing a light-emitting device having a peak wavelength of 1000 nm or more, which is the object of the present invention, only InP, GaInAsP, AlGaInAs, and GaInAs semiconductors lattice-matched to an InP substrate have been put into practical use.

Conventionally, semiconductor light emitting devices exhibiting emission wavelengths of 1000 nm or more have been developed for use as lasers for optical communications. In the case of a laser element, since light is extracted from the end surface of the semiconductor layer, it is not assumed that the light is extracted from the main surface of the semiconductor layer (surface parallel to the main surface of the substrate).

On the other hand, as described above, when the annealing treatment is performed from the viewpoint of lowering the contact resistance, in the case of the vertical structure infrared LED element, the lower layer position of the main surface of the semiconductor layer constituting the light extraction surface An alloy layer is formed.

If the alloy layer were not present, part of the infrared light emitted from the active layer would enter the upper electrode. Since the upper electrode is made of a metal material, part of the infrared light incident on the upper electrode is reflected on the surface of the electrode. For this reason, the reflected light is returned toward the substrate side, reflected again by the layers in the infrared LED element, and extracted from the light extraction surface.

In other words, the presence of the alloy layer absorbs the infrared light emitted from the active layer, causing a decrease in light extraction efficiency.

On the other hand, when the alloy layer is completely eliminated, the contact resistance between the semiconductor layer and the upper electrode increases, leading to an increase in forward voltage. Furthermore, since the adhesion between the semiconductor layer and the upper electrode is lowered, the electrode may be peeled off during wire bonding. From this point of view, it is difficult to completely eliminate the alloy layer.

As a result of intensive research by the present inventors, it was found that when the average film thickness of the alloy layer exceeds 150 nm, the decrease in light extraction efficiency tends to be accelerated. Further, it was found that if the average film thickness of the alloy layer is within 150 nm, a light output comparable to that obtained without the alloy layer can be obtained.

In other words, according to the infrared LED element described above, it is possible to improve the light extraction efficiency while suppressing the two problems of an increase in forward voltage and peeling of the electrode.

The average film thickness of the alloy layer is obtained by setting measurement points evenly every 1 μm from within a range of 10 μm square or more when viewed from the direction perpendicular to the main surface of the support substrate, and measuring the thickness of the alloy layer at each measurement point. The value obtained by averaging can be adopted.

The second semiconductor layer may contain InP. The entire second semiconductor layer may be made of InP.

The second semiconductor layer includes a cladding layer located on the active layer side, and a contact layer located above the cladding layer and having at least one of a composition and a dopant concentration different from that of the cladding layer,
The constituent material of the contact layer may have a bandgap energy higher than the light energy of the peak emission wavelength.

In the case of an InP-based material, a material such as GaInAsP or GaInAs, which has a relatively small bandgap energy, is easier to form an ohmic junction than an InP layer. This is probably because the higher the In composition on the surface, the easier the natural oxide film is formed. However, even if the thickness of the alloy layer is reduced, the light extraction efficiency will decrease if the contact layer absorbs the light emitted from the active layer. As described above, by forming the contact layer with a material having a bandgap energy higher than the light energy of the peak emission wavelength, light absorption in the contact layer is suppressed, thereby ensuring high light extraction efficiency. be.

From this point of view, the contact layer is preferably made of InP having a higher dopant concentration than the clad layer. InP is composed of one type of group III element and one type of group V element, so composition deviation is less likely to occur. This also has the advantage of suppressing variations between devices during manufacturing and stably manufacturing infrared LED devices exhibiting uniform characteristics.

The alloy layer may be made of a material containing Ge.

The second semiconductor layer may have a dopant concentration of 5×10 ¹⁷ /cm ³ to 5×10 ¹⁸ /cm ³ at a portion adjacent to the alloy layer.

In order to achieve a low-resistance ohmic contact between the upper electrode and the second semiconductor layer, it is necessary to dope the second semiconductor layer appropriately. If the dopant concentration is less than 5×10 ¹⁷ /cm ³ , contact resistance between the second semiconductor layer and the upper electrode may increase. Also, excessive doping causes deterioration of crystallinity. In particular, when manufacturing the infrared LED element, the active layer is formed after forming the second semiconductor layer, so the second semiconductor layer serves as a base for forming the active layer. Therefore, from the viewpoint of ensuring high luminous efficiency in the active layer, it is necessary to avoid deterioration of the crystallinity of the second semiconductor layer. From this point of view, the dopant concentration of the second semiconductor layer is preferably 5×10 ¹⁸ /cm ³ or less.

The area occupied by the upper electrode may be 20% or less of the area occupied by the second semiconductor layer when viewed in a direction perpendicular to the main surface of the support substrate.

A light extraction surface is formed by the exposed surface of the second semiconductor layer. In other words, the larger the area occupied by the upper electrode, the smaller the area of the light extraction surface, and the lower the amount of light extraction. According to the above configuration, light absorption in the alloy layer is suppressed while ensuring the area of the light extraction surface, so high light extraction efficiency is realized.

According to the present invention, an infrared LED element having a vertical structure and having a peak emission wavelength of 1000 nm or more, which has an improved light extraction efficiency as compared with conventional ones, is realized.

1 is a cross-sectional view schematically showing the configuration of an embodiment of an infrared LED element of the present invention; FIG. 2 is a schematic plan view when the infrared LED element shown in FIG. 1 is viewed in the -Y direction; FIG. 2 is an enlarged sectional view of a position near an upper electrode in FIG. 1; FIG. It is a cross-sectional SEM photograph of the infrared LED element in the vicinity of the upper electrode. 1. It is sectional drawing in 1 process for demonstrating the manufacturing method of the LED element shown in FIG. FIG. 3 is a cross-sectional view in another step for explaining the manufacturing method of the LED element shown in FIG. 1; FIG. 3 is a cross-sectional view in another step for explaining the manufacturing method of the LED element shown in FIG. 1; FIG. 3 is a cross-sectional view in another step for explaining the manufacturing method of the LED element shown in FIG. 1; FIG. 3 is a cross-sectional view in another step for explaining the manufacturing method of the LED element shown in FIG. 1; FIG. 3 is a cross-sectional view in another step for explaining the manufacturing method of the LED element shown in FIG. 1; 4 is a graph showing the relationship between the light output and the average film thickness of the alloy layer; 4 is a graph showing the relationship between the forward voltage and the average film thickness of the alloy layer; FIG. 3 is a cross-sectional view schematically showing the configuration of another embodiment of the infrared LED element of the present invention;

An embodiment of an infrared LED element according to the present invention will be described with reference to the drawings. Each drawing below is shown schematically, and the dimensional ratio on the drawing does not necessarily match the actual dimensional ratio. Moreover, there are cases where the dimensional ratios do not match between the drawings.

In this specification, the expression "the layer Q2 is formed on the layer Q1" includes not only the case where the layer Q2 is formed directly on the surface of the layer Q1, but also the case where the layer Q2 is formed on the surface of the layer Q1 via a thin film. It is intended to include the case where the layer Q2 is formed over the layer. The term "thin film" as used herein refers to a layer having a thickness of 20 nm or less, preferably a layer having a thickness of 10 nm or less.

In this specification, the description "GaInAsP" means a mixed crystal of Ga, In, As, and P, and the description of the composition ratio is simply omitted. The same applies to other descriptions such as "AlGaInAs".

FIG. 1 is a cross-sectional view schematically showing the structure of the infrared LED element of this embodiment. The infrared LED element 1 shown in FIG. 1 includes a semiconductor laminate 20 formed on the upper layer of the support substrate 11 . FIG. 1 corresponds to a schematic cross-sectional view when the infrared LED element 1 is cut along the XY plane at a predetermined position. In the following description, the XYZ coordinate system attached to FIG. 1 will be referred to as appropriate.

In the following description, when distinguishing between positive and negative directions when expressing directions, positive and negative signs are added, such as “+X direction” and “−X direction”. Moreover, when expressing a direction without distinguishing between positive and negative directions, it is simply described as “X direction”. That is, in the present specification, the term “X direction” includes both “+X direction” and “−X direction”. The same applies to the Y direction and Z direction. In the following example, it is assumed that the main surface of the support substrate 11 is parallel to the XZ plane and light is extracted in the normal direction (Y direction).

In the infrared LED element 1 of the present embodiment, infrared light L is generated inside the semiconductor laminate 20 (particularly inside an active layer 25 described later). More specifically, as shown in FIG. 1, the infrared light L (L1, L2) is extracted in the +Y direction with the active layer 25 as a reference. The infrared light L has a peak wavelength of 1000 nm or more. The peak wavelength here corresponds to the wavelength with the highest optical output in the optical spectrum.

[Device structure]
The structure of the infrared LED element 1 will be described in detail below.

(Support substrate 11)
The support substrate 11 is made of, for example, a semiconductor such as Si or Ge, or a metal material such as Cu or CuW. When the support substrate 11 is made of a semiconductor, it may be doped with a dopant at a high concentration so as to exhibit conductivity. As an example, the support substrate 11 is a Si substrate doped with boron (B) at a dopant concentration of 1×10 ¹⁹ /cm ³ or more and having a resistivity of 10 mΩcm or less. As a dopant, phosphorus (P), arsenic (As), antimony (Sb), etc. can be used in addition to boron (B). From the viewpoint of achieving both high heat dissipation and low manufacturing cost, a Si substrate is preferably used as the support substrate 11 .

The thickness (length in the Y direction) of the support substrate 11 is not particularly limited, but is, for example, 50 μm to 500 μm, preferably 100 μm to 300 μm.

(Conductive layer 16)
The infrared LED element 1 shown in FIG. 1 has a conductive layer 16 formed on the support substrate 11 . In this embodiment, the conductive layer 16 more specifically includes the bonding layer 13 and the reflective layer 15 .

The bonding layer 13 is made of a solder material with a low melting point, such as Au, Au--Zn, Au--Sn, Au--In, Au--Cu--Sn, Cu--Sn, Pd--Sn, and Sn. As will be described later with reference to FIG. 4E, this bonding layer 13 is used to bond the growth substrate 3 having the semiconductor laminate 20 formed thereon and the support substrate 11 together. Although the thickness of the bonding layer 13 is not particularly limited, it is, for example, 0.5 μm to 5.0 μm, preferably 1.0 μm to 3.0 μm.

The reflective layer 15 has a function of reflecting infrared light L2 traveling toward the support substrate 11 (-Y direction) out of the infrared light L generated in the active layer 25 and guiding it in the +Y direction. The reflective layer 15 is made of a material that is a conductive material and exhibits a high reflectance with respect to the infrared light L. As shown in FIG. The reflectance of the reflective layer 15 to the infrared light L is preferably 70% or higher, more preferably 80% or higher, and particularly preferably 90% or higher.

When the peak wavelength of the infrared light L is 1000 nm to 2000 nm, the reflective layer 15 can be made of metal materials such as Ag, Ag alloys, Au, Al, and Cu. The material forming the reflective layer 15 is appropriately selected according to the wavelength of light generated by the active layer 25 .

The thickness of the reflective layer 15 is not particularly limited, but is, for example, 0.1 μm to 2.0 μm, preferably 0.3 μm to 1.0 μm.

Although not shown in FIG. 1, the conductive layer 16 may further include a barrier layer between the reflective layer 15 and the bonding layer 13 to suppress diffusion of the solder material forming the bonding layer 13 . The material of the barrier layer can be material containing, for example, Ti, Pt, W, Mo, Ni, or the like. As an example, it is composed of a laminate of Ti/Pt/Au. Although the thickness of the barrier layer is not particularly limited, it is, for example, 0.05 μm to 3 μm, preferably 0.2 μm to 1 μm. Interposition of this barrier layer can prevent the material of the bonding layer 13 from diffusing toward the reflective layer 15 and lowering the reflectance of the reflective layer 15 . A barrier layer may also be provided between the bonding layer 13 and the support substrate 11 .

From the viewpoint of improving light extraction efficiency, it is preferable for the infrared LED element 1 to have a reflective layer 15 as shown in FIG. or not is arbitrary.

(insulating layer 17)
The infrared LED element 1 shown in FIG. 1 has an insulating layer 17 formed on the reflective layer 15 . The insulating layer 17 is made of a material that is electrically insulating and highly transparent to the infrared light L. As shown in FIG. The transmittance of the insulating layer 17 to the infrared light L is preferably 70% or more, more preferably 80% or more, and particularly preferably 90% or more.

When the peak wavelength of the infrared light L is 1000 nm to 2000 nm, the insulating layer 17 can be made of SiO ₂ , SiN, Al ₂ O ₃ or the like. A material for the insulating layer 17 is appropriately selected according to the wavelength of light generated in the active layer 25 .

(Semiconductor laminate 20)
The infrared LED element 1 shown in FIG. 1 has a semiconductor laminate 20 formed on an insulating layer 17 . The semiconductor laminate 20 is a laminate of multiple semiconductor layers, and includes, for example, a contact layer 21 , a first clad layer 23 , an active layer 25 and a second clad layer 27 . As will be described later with reference to FIG. 7, the semiconductor laminate 20 may further include a contact layer 28 above the second clad layer 27 . Each semiconductor layer constituting the semiconductor laminate 20 is made of a material that is lattice-matched with the growth substrate 3 described later and capable of epitaxial growth.

<<Contact layer 21, first clad layer 23>>
In this embodiment, the contact layer 21 is made of, for example, p-type GaInAsP. Although the thickness of the contact layer 21 is not limited, it is, for example, 10 nm to 1000 nm, preferably 50 nm to 500 nm. The p-type dopant concentration of the contact layer 21 is preferably 5×10 ¹⁷ /cm ³ to 3×10 ¹⁹ /cm ³ , more preferably 1×10 ¹⁸ /cm ³ to 2×10 ¹⁹ /cm 3 . is ³ .

In this embodiment, the first cladding layer 23 is formed above the contact layer 21 and is made of, for example, p-type InP. Although the thickness of the first clad layer 23 is not limited, it is, for example, 1000 nm to 10000 nm, preferably 2000 nm to 5000 nm. The p-type dopant concentration of the first clad layer 23 is preferably 1×10 ¹⁷ /cm ³ to 3×10 ¹⁸ /cm ³ , more preferably 5×10 ¹⁷ /cm 3 at a position away from the active layer 25 . cm ³ to 3×10 ¹⁸ /cm ³ .

As the p-type dopant contained in the contact layer 21 and the first clad layer 23, Zn, Mg, Be or the like can be used, with Zn or Mg being preferred, and Zn being particularly preferred. In this embodiment, the contact layer 21 and the first clad layer 23 correspond to the "first semiconductor layer".

<<Active layer 25>>
In this embodiment, the active layer 25 is a semiconductor layer formed above the first clad layer 23 . The material of the active layer 25 is appropriately selected from materials that can generate light of a target wavelength and can be epitaxially grown by lattice matching with the growth substrate 3 described later with reference to FIG. 4A.

When it is desired to realize the infrared LED element 1 that emits infrared light L having a peak wavelength of 1000 nm to 2000 nm, the active layer 25 may have a single-layer structure of GaInAsP, AlGaInAs, or InGaAs. An MQW (Multiple Quantum Well) structure including well layers made of InGaAs and barrier layers made of GaInAsP, AlGaInAs, InGaAs, or InP having a bandgap energy larger than that of the well layers may be used.

The thickness of the active layer 25 is 50 nm to 2000 nm, preferably 100 nm to 300 nm, when the active layer 25 has a single layer structure. When the active layer 25 has the MQW structure, well layers and barrier layers with a film thickness of 5 nm to 20 nm are stacked in a range of 2 to 50 cycles.

The active layer 25 may be doped n-type or p-type, or may be undoped. For n-type doping, Si, for example, can be used as the dopant.

<<Second clad layer 27>>
In this embodiment, the second cladding layer 27 is formed above the active layer 25 and is, for example, n-type InP. Although the thickness of the second clad layer 27 is not limited, it is, for example, 100 nm to 10000 nm, preferably 500 nm to 5000 nm. The n-type dopant concentration of the second clad layer 27 is preferably 1×10 ¹⁷ /cm ³ to 5×10 ¹⁸ /cm ³ , more preferably 5×10 ¹⁷ /cm ³ to 4×10 ¹⁸ /cm 3 . is ³ . Sn, Si, S, Ge, Se, etc. can be used as the n-type impurity material with which the second clad layer 27 is doped, and Si is particularly preferable. In the infrared LED element 1 of this embodiment, the second clad layer 27 corresponds to the "second semiconductor layer".

In the example shown in FIG. 1, an uneven portion 27a is formed on the surface of the second cladding layer 27 on the +Y side. By forming the uneven portion 27a, the amount of infrared light L (L1, L2) traveling in the +Y direction from the active layer 25 and reflected by the surface of the second cladding layer 27 toward the active layer 25 is reduced. Light extraction efficiency is enhanced. However, in the present invention, it is optional whether or not the surface of the second cladding layer 27 is provided with the uneven portion 27a.

The material of the first clad layer 23 and the second clad layer 27 is a material that does not absorb the infrared light L generated in the active layer 25, and is lattice-matched with the growth substrate 3 (see FIG. 4 described later). It is appropriately selected from materials capable of epitaxial growth. When an InP substrate is used as the growth substrate 3, the material of the first clad layer 23 and the second clad layer 27 can be InP, GaInAsP, AlGaInAs, or the like.

In this embodiment, the first semiconductor layers (21, 23) are p-type semiconductors, and the second semiconductor layer (second cladding layer 27) is an n-type semiconductor. It doesn't matter if it's reversed.

(Internal electrode 31)
The infrared LED element 1 shown in FIG. 1 has internal electrodes 31 that penetrate through the insulating layer 17 in the Y direction at a plurality of locations. The internal electrode 31 electrically connects the first semiconductor layers ( 21 , 23 ) and the conductive layer 16 . The internal electrodes 31 are provided at a plurality of positions distributed in a direction parallel to the XZ plane (that is, a direction parallel to the main surface of the support substrate 11).

The internal electrode 31 is made of a material capable of forming an ohmic connection with the contact layer 21 . As an example, the internal electrode 31 is composed of AuZn, AuBe, or a laminated structure containing at least Au and Zn (for example, Au/Zn/Au, etc.). These materials have a lower reflectance with respect to the infrared light L than the material forming the reflective layer 15 .

The shape of the arrangement pattern of the internal electrodes 31 when viewed in the Y direction is arbitrary. However, from the viewpoint of uniform current flow over a wide range in the active layer 25 in the direction parallel to the main surface of the support substrate 11, the internal electrodes 31 have a regular shape in the plane direction along the XZ plane. It is preferably arranged in a distributed manner.

FIG. 2 is an example of a schematic plan view when the infrared LED element 1 is viewed from above the second clad layer 27 in the Y direction. However, FIG. 2 also shows the internal electrodes 31 from the viewpoint of facilitating understanding of the shape pattern of the internal electrodes 31 . FIG. 2 will be described in detail later in the description of the upper electrode 40. FIG. Note that FIG. 2 illustrates a case where the semiconductor stacked body 20 has a rectangular shape when viewed from above.

When the infrared LED element 1 is viewed in the Y direction, the total area of all the internal electrodes 31 is 30% or less of the area of the semiconductor laminate 20 (for example, the second clad layer 27) in the planar direction. preferably 20% or less, particularly preferably 15% or less. If the total area of the internal electrodes 31 is relatively large, the infrared light L2 traveling from the active layer 25 toward the support substrate 11 (-Y direction) is absorbed by the internal electrodes 31, resulting in a decrease in extraction efficiency. On the other hand, if the total area of the internal electrodes 31 is too small, the resistance value increases and the forward voltage increases.

(Back electrode 33)
The infrared LED element 1 shown in FIG. 1 includes a back electrode 33 formed on the surface of the support substrate 11 opposite to the semiconductor laminate 20 (−Y side). Ohmic contact is realized between the back electrode 33 and the support substrate 11 . As an example, the back electrode 33 is made of materials such as Ti/Au and Ti/Pt/Au, and a plurality of these materials may be provided.

(Upper electrode 40)
The infrared LED element 1 shown in FIG. 1 has an upper electrode 40 formed on the upper layer of the semiconductor laminate 20 . A plurality of upper electrodes 40 are typically formed to extend in a predetermined direction.

In FIG. 2, the upper electrode 40 includes a plurality of first upper electrodes 41 extending in the X direction and the Z direction along the sides of the semiconductor laminate 20, and the upper surface of the first upper electrode 41 at a specific location. A configuration including a formed second upper electrode 42 having a larger inner diameter in top view than the first upper electrode 41 is shown. The second upper electrode 42 is provided for the purpose of securing an area for contacting a bonding wire for power supply, and is sometimes called a pad electrode.

The arrangement pattern shape of the first upper electrode 41 is arbitrary, and may be, for example, a lattice shape or a spiral shape. The first upper electrode 41 of the upper electrodes 40 is formed over a wide range on the XZ plane while exposing the surface of the underlying semiconductor layer (here, the second cladding layer 27). As a result, the current flowing through the active layer 25 can be expanded in the direction parallel to the XZ plane, and light can be emitted over a wide range within the active layer 25 .

As an example, the first upper electrode 41 is made of materials such as AuGe/Ni/Au, Au/Ge/Au, Au/Zn/Au, AuZn, and AuBe, and may be provided with a plurality of these materials. The second upper electrode 42 is composed of, for example, Ti/Au, Ti/Pt/Au, or the like.

The second upper electrode 42 constituting the pad electrode has a circular shape with an inner diameter of about 90 μm to 120 μm when each side (chip size) of the semiconductor laminate 20 is about 800 μm to 2500 μm, for example. The line width of the first upper electrode 41 is approximately 10 μm to 30 μm. In the high-power infrared LED element 1 with a chip size exceeding 800 μm, it is preferable to provide the second upper electrodes 42 at a plurality of locations as shown in FIG. 2 from the viewpoint of injecting a high current.

When viewed in the Y direction, the area occupied by the upper electrode 40 (the first upper electrode 41 and the second upper electrode 42) is preferably 20% or less of the area occupied by the second clad layer 27, more preferably 15%. % or less. If the area occupied by the upper electrode 40 becomes too large, the area of the light extraction surface is reduced, which may reduce the light extraction efficiency. The area occupied by the upper electrode 40 is preferably 5% or more, more preferably 8% or more.

(alloy layer 35)
The infrared LED element 1 shown in FIG. 1 has an alloy layer 35 at the interface between the upper electrode 40 and the second clad layer 27 . The alloy layer 35 is an alloy of the metal material forming the upper electrode 40 and the semiconductor material forming the second clad layer 27 .

The alloy layer 35 is mainly present at a position facing the formation location of the upper electrode 40 (that is, a position immediately below the upper electrode 40). The thickness of the alloy layer 35 subtly changes depending on the position on the XZ plane, and the average thickness is 150 nm or less, more preferably 50 nm to 150 nm. The average film thickness of the alloy layer 35 is obtained by setting measurement points evenly every 1 μm from within a range of 10 μm square or more when viewed from the direction orthogonal to the main surface of the support substrate 11, that is, the Y direction, and measuring the alloy thickness at each measurement point. An average value of layer thicknesses can be employed.

FIG. 3A is an enlarged view of a position near the upper electrode 40. FIG. 3B is a cross-sectional SEM photograph of the infrared LED element 1 at a position near the upper electrode 40. FIG. Note that FIGS. 3A and 3B show the vicinity of a portion of the upper electrode 40 where the second upper electrode 42 is particularly formed.

In the example shown in FIGS. 3A-3B, the top electrode 40 has a first top electrode 41 and a second top electrode 42, and the position of the second top electrode 42 closest to the first top electrode 41 is, for example, An adhesion layer 45 made of Ti is included. The adhesion layer 45 is provided for the purpose of adhering the second upper electrode 42 constituting the pad electrode to the semiconductor laminate 20 side.

As shown in the SEM photograph shown in FIG. 3B, the alloy layer 35 is formed at the interface between the upper electrode 40 and the second clad layer 27, and its film thickness slightly changes depending on the location. there is As will be described later, the alloy layer 35 is separated from the electrode material by a heating process (annealing process) performed after the electrode material is deposited in the process of forming the upper electrode 40 (more specifically, the first upper electrode 41). It is formed by being alloyed with a semiconductor material. As shown in the SEM photograph of FIG. 3B, it is believed that the film thickness of the alloy layer 35 slightly changes depending on the location because the rate of progress of alloying due to the heating process slightly differs depending on the location. Presumed. In addition, in the SEM photograph of FIG. 3B, a layer with a different color is present at the boundary between the second upper electrode 42 and the first upper electrode 41, but this layer is one part of the second upper electrode 42 as described above. corresponds to the adhesion layer 45 forming the part.

According to the infrared LED element 1 of this embodiment, the average film thickness of the alloy layer 35 is 150 nm or less, so that the light extraction efficiency is enhanced. This point will be described later with reference to examples.

[Production method]
An example of a method for manufacturing the infrared LED element 1 described above will be described with reference to FIGS. 4A to 4F. 4A to 4F are cross-sectional views in one step in the manufacturing process. The order of the following procedures may be changed appropriately as long as it does not affect the manufacture of the infrared LED element 1 .

(Step S1)
As shown in FIG. 4A, a growth substrate 3 made of, for example, InP is transported into a MOCVD (Metal Organic Chemical Vapor Deposition) apparatus, and a second clad layer 27, an active layer 25, and a first clad layer 23 are formed on the growth substrate 3. And the contact layer 21 is epitaxially grown in sequence to form the semiconductor laminate 20 . In this step S1, the type and flow rate of the raw material gas, the processing time, the environmental temperature, etc. are appropriately adjusted according to the material and film thickness of the layer to be grown. Examples of materials for the semiconductor layers (21, 23, 25, 27) are as described above.

InP is preferably used as the growth substrate 3 . However, GaAs may be used as the growth substrate 3 when manufacturing the infrared LED element 1 with a peak wavelength of 1070 nm or less.

(Step S2)
The epitaxial wafer is taken out from the MOCVD apparatus, and a resist mask patterned by photolithography is formed on the surface of the contact layer 21 . After that, after forming a film of a material (for example, AuZn) for forming the internal electrodes 31 using a vacuum deposition device, the resist mask is removed by a lift-off method. After that, for example, alloy treatment (annealing treatment) is performed by heat treatment at 450° C. for 10 minutes, thereby realizing ohmic contact between the contact layer 21 and the internal electrode 31 .

Next, an insulating layer 17 made of, for example, SiO ₂ is deposited by plasma CVD. After that, the insulating layer 17 positioned above the internal electrodes 31 is removed by photolithography and etching to expose the internal electrodes 31 (see FIG. 4B).

(Step S3)
As shown in FIG. 4C, the reflective layer 15 is formed to cover the insulating layer 17 and the internal electrodes 31, and then the bonding layer 13a is formed. For example, a film of Al/Au with a predetermined thickness is formed by a vacuum deposition apparatus to form the reflective layer 15, and subsequently an Au—Sn film is formed with a predetermined thickness to form the bonding layer 13a. is formed. As described above, a barrier layer may be formed between the reflective layer 15 and the bonding layer 13a by depositing, for example, Ti/Pt/Au with a predetermined film thickness.

(Step S4)
As shown in FIG. 4D, a support substrate 11 is prepared separately from the growth substrate 3, and a bonding layer 13b made of, for example, Au—Sn is formed on its upper surface. Although not shown, a contact metal layer (for example, Ti) may be formed on the surface of the support substrate 11, and the bonding layer 13b may be formed thereon. Also, the above-described barrier layer may be formed before forming the bonding layer 13b.

(Step S5)
As shown in FIG. 4E, the growth substrate 3 and the support substrate 11 are bonded together via the bonding layers 13 (13a, 13b) at a temperature of 280° C. and a pressure of 1 MPa, for example. By this treatment, the bonding layer 13 a on the growth substrate 3 and the bonding layer 13 b on the support substrate 11 are melted and integrated as the bonding layer 13 .

(Step S6)
After the surface on the semiconductor laminate 20 side is coated with a resist to protect it, the exposed growth substrate 3 is subjected to a grinding and polishing process or a wet etching process using a hydrochloric acid-based etchant. As a result, the growth substrate 3 is peeled off to expose the second clad layer 27 (see FIG. 4F).

(Step S7)
An upper electrode 40 is formed at a predetermined position on the upper surface of the second clad layer 27 . The details are as follows.

First, a photoresist is applied to the upper surface of the second clad layer 27 . Next, while a photomask patterned according to the shape of the upper electrode 40 is placed at a predetermined position, light for exposure is applied through the photomask. Thereby, the photoresist is patterned into the shape of the upper electrode 40 to form a resist mask.

Next, a film of a material forming the upper electrode 40 is formed using, for example, a vacuum deposition apparatus. More specifically, AuGe/Ni/Au, Au/Ge/Au, or the like, which is the material of the film forming the first upper electrode 41, is deposited. Next, after the photoresist is removed, heat treatment (annealing treatment) is performed at 450° C. for 10 minutes, for example. Thereby, the first upper electrode 41 is formed.

It should be noted that the alloy layer 35 obtained by alloying the metal material forming the first upper electrode 41 and the semiconductor material forming the second clad layer 27 by this heat treatment forms the first upper electrode 41 and the second clad layer 27 . It forms at the interface with layer 27 (see FIG. 3A). Since Al, Ga, In, As, P, etc., which can be assumed as the semiconductor material forming the second clad layer 27, are not used as the metal material forming the first upper electrode 41, The presence of the alloy layer 35 can be detected by analyzing the composition of the region containing the by using, for example, XRF.

Next, a second upper electrode 42 is formed at a predetermined position on the top surface of the first upper electrode 41 . More specifically, Ti, which is the material of the film forming the adhesion layer 45, and Ti/Au, Ti/Pt/Au, etc., which are the materials of the film forming the second upper electrode 42, are deposited using a vacuum deposition apparatus. After filming, a lift-off process is performed (see FIGS. 1 and 2).

(Later process)
After step S7, for example, the following steps are executed. Note that the following procedures can be interchanged as appropriate.

Wet etching is applied to the surface of the second cladding layer 27 on which the upper electrode 40 is not formed to form an uneven portion 27a. After that, mesa etching is performed for separating each device. Specifically, wet etching is performed with a mixture of bromine and methanol while the non-etching region of the surface of the second cladding layer 27 is masked with a resist patterned by photolithography. This removes a portion of the semiconductor stack 20 located within the unmasked region (see FIG. 1).

After the thickness of the back side of the support substrate 11 is adjusted, the back electrode 33 is formed on the back side of the support substrate 11 . As a specific method of forming the back electrode 33, similarly to the upper electrode 40, the back electrode 33 can be formed by forming a film of the material (for example, Ti/Pt/Au) of the back electrode 33 with a vacuum deposition device and then lifting off the film.

Note that the adjustment of the thickness of the back side of the support substrate 11 may be performed as required, and is not necessarily an essential step. Also, the degree of thickness is appropriately set according to the application.

Thereafter, the support substrate 11 is diced into chips.

A bonding wire is then attached to the second top electrode 42 of each chip.

[Verification 1]
In step S7, the steps are performed under the same conditions except that the heating conditions of the heating process performed when forming the first upper electrode 41 are different. Samples #A1 to #A4 and #B1 were manufactured. Note that the sample #B1 is a sample manufactured without heat treatment in step S7, and is different from the other samples (#A1 to #A4) in that the alloy layer 35 is not provided. A plurality of samples (approximately 1000 pieces) of each of the samples #A1 to #A4 and #B1 were manufactured under the same manufacturing conditions.

For each sample #A1 to #A4, the average film thickness of the alloy layer 35 was measured based on the SEM image. As the average film thickness, the average value of the film thickness of the alloy layer 35 at a plurality of measurement points uniformly extracted every 1 μm from within the 15 μm square range of each SEM image was adopted. Each average film thickness is as shown in Table 1 below. Note that sample #B1 does not have the alloy layer 35, so the average film thickness is 0 nm. The point that the sample #B1 does not have the alloy layer 35 was also confirmed by the SEM image just in case.

The ratio (peeling rate) of samples in which the upper electrode 40 was pulled by the wire and peeled off during the wire bonding process was measured. Table 1 shows the results.

According to Table 1, in sample #B1 in which the alloy layer 35 was not formed, peeling of the upper electrode 4 occurred in 8 devices out of 1000 devices. On the other hand, peeling of the upper electrode 40 was not confirmed in any of the elements belonging to samples #A1 to #A4 in which the alloy layer 35 was formed. From this result, by performing the heating process when forming the first upper electrode 41 to increase the adhesion between the second cladding layer 27 and the upper electrode 40, peeling of the upper electrode 40 is suppressed during the wire bonding process. I understand.

[Verification 2]
The same forward current (20 mA) was supplied to the elements belonging to the respective samples (#A1 to #A4, #B1) in which no peeling of the upper electrode 40 occurred to turn them on, and the light output and the alloy layer 35 were measured. and the average film thickness of the alloy layer 35 and the relationship between the forward voltage and the average film thickness of the alloy layer 35 were measured. The results are shown in FIGS. 5 and 6. FIG. The light output shown in FIG. 5 was measured with an integrating sphere.

According to FIG. 5, sample #A3 and sample A4, in which the average film thickness of the alloy layer 35 is 270 nm or more, have significantly lower light output than sample #A1 and sample #A2, in which the average film thickness is 150 nm or less. I know you are. Also, it can be seen that sample #A1 and sample #A2 have substantially the same light output as sample #B1 in which the alloy layer 35 is not formed.

From this result, in the case of sample #A3 and sample A4, since the film thickness of the alloy layer 35 existing inside is large, the light amount of the infrared light L absorbed in the alloy layer 35 is relatively large. It is presumed that the optical output decreased.

On the other hand, according to FIG. 6, sample #A1 and sample #A2 in which the average thickness of the alloy layer 35 is 150 nm or less are equivalent to sample #A3 and sample A4 in which the average thickness of the alloy layer 35 is 270 nm or more. Forward voltage is shown. The forward voltage of the sample #B1 in which the alloy layer 35 is not provided is significantly higher than those of the samples #A1 and #A2. From this result, it can be seen that even when the film thickness of the alloy layer 35 is reduced to some extent, the effect of lowering the forward voltage can be obtained as compared with the structure in which the alloy layer 35 is not provided at all. Also, it can be seen that even if the film thickness of the alloy layer 35 is increased, the effect of lowering the forward voltage is not significantly enhanced.

In view of the above results, according to the infrared LED element 1 including the alloy layer 35 having an average film thickness of 150 nm or less, it is possible to suppress film peeling of the upper electrode 40 and suppress an increase in the forward voltage while simultaneously It can be seen that the light output can also be increased. From the above verification, it can be seen that the average film thickness of the alloy layer 35 is more preferably 50 nm to 150 nm.

[Another embodiment]
As shown in FIG. 7 , the infrared LED element 1 may include a contact layer 28 doped with a dopant at a higher concentration than the second clad layer 27 above the second clad layer 27 . When the second cladding layer 27 is an n-type semiconductor layer as in the above embodiment, the contact layer 28 is also composed of an n-type semiconductor layer. In this case, the second cladding layer 27 and contact layer 28 correspond to the "second semiconductor layer".

As an example, the contact layer 28 is composed of n-type InP. Although the thickness of the contact layer 28 is not limited, it is, for example, 10 nm to 1000 nm, preferably 50 nm to 500 nm. The n-type dopant concentration of the contact layer 28 is preferably 5×10 ¹⁷ /cm ³ to 1×10 ¹⁹ /cm ³ , more preferably 1×10 ¹⁸ /cm ³ to 5×10 ¹⁸ /cm ³ . be.

The infrared LED element 1 shown in FIG. 7 is manufactured in the same manner as described above, except that the contact layer 28 is formed before the second clad layer 27 is formed in the epitaxial process described above in step S1.

Reference Signs List 1: Infrared LED element 3: Growth substrate 11: Support substrate 13 (13a, 13b): Bonding layer 15: Reflective layer 16: Conductive layer 17: Insulating layer 20: Semiconductor laminate 21: Contact layer 23: First clad layer 25: Active layer 27: Second clad layer 27a: Concavo-convex portion 28: Contact layer 31: Internal electrode 33: Back electrode 35: Alloy layer 40: Upper electrode 41: First upper electrode 42: Second upper electrode 45: Adhesion layer L: Infrared light

Claims (6)

An infrared LED element having a peak emission wavelength of 1000 nm or more,
a conductive support substrate;
a conductive layer formed on the support substrate;
an insulating layer formed on the conductive layer;
a p-type or n-type first semiconductor layer formed on the insulating layer;
an active layer formed on the first semiconductor layer;
a second semiconductor layer formed on the active layer and having a conductivity type different from that of the first semiconductor layer;
an internal electrode that penetrates the insulating layer at a plurality of positions dispersed in a direction parallel to the main surface of the supporting substrate and electrically connects the first semiconductor layer and the supporting substrate;
an upper electrode formed on the upper layer of the second semiconductor layer;
an alloy layer formed at the interface between the second semiconductor layer and the upper electrode, made of an alloy of the constituent material of the upper electrode and the constituent material of the second semiconductor layer, and having an average thickness of 150 nm or less. An infrared LED element characterized by: 2. The infrared LED device according to claim 1, wherein said second semiconductor layer contains InP. The second semiconductor layer includes a cladding layer located on the active layer side, and a contact layer located above the cladding layer and having at least one of a composition and a dopant concentration different from that of the cladding layer,
3. The infrared LED element according to claim 1, wherein a constituent material of said contact layer has a bandgap energy higher than the light energy of said peak emission wavelength. 3. The infrared LED element according to claim 1, wherein said alloy layer is made of a material containing Ge. 3. The red semiconductor according to claim 1, wherein the second semiconductor layer has a dopant concentration of 5×10 ¹⁷ /cm ³ to 5×10 ¹⁸ /cm ³ in a portion adjacent to the alloy layer. Outer LED element. 3. The method according to claim 1, wherein an area occupied by the upper electrode is 20% or less of an area occupied by the second semiconductor layer when viewed in a direction perpendicular to the main surface of the support substrate. An infrared LED device as described.

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