TW202219918A - Electronic device - Google Patents

Abstract

An electronic device includes a substrate, first electrodes, second electrodes, and peripheral wiring pairs. The substrate has a first peripheral area, a working area, and a second peripheral area arranged along a first direction. The first electrodes are arranged on the working area, are structurally separated from each other, and are arranged along a second direction. The second electrodes are arranged in the working area, are structurally separated from each other, and are arranged along the first direction. Each of the peripheral wiring pairs includes a first peripheral wiring and a second peripheral wiring belonging to a first conductive layer and a second conductive layer, respectively. One of the first peripheral wiring and the second peripheral wiring is disposed on one of the first peripheral area and the second peripheral area. Another of the first peripheral wiring and the second peripheral wiring is disposed on another of the first peripheral area and the second peripheral area. The first peripheral wiring and the second peripheral wiring are electrically connected to a single first electrode. First peripheral wirings and second peripheral wiring of the peripheral wiring pairs are alternately arranged on the first peripheral area.

Description

electronic device

The present invention relates to an electronic device.

With the development of technology, electronic blackboards with display and touch functions are gradually being used in teaching situations to replace traditional blackboards. The large electronic blackboard is spliced by multiple touch display devices. In order to reduce the seam area between the plurality of touch display devices, each touch display device needs to have a narrow frame. Generally speaking, a plurality of touch electrodes of a touch display device need to be electrically connected to a plurality of pads below through a plurality of peripheral traces disposed on the left and right sides, so that the driving chip can pass through the plurality of pads and the plurality of pads. The peripheral traces drive a plurality of touch electrodes. However, the arrangement of a plurality of peripheral wirings makes it difficult to reduce the left and right frames of the touch display device.

The present invention provides an electronic device with good performance.

The electronic device of the present invention includes a substrate, a plurality of first electrodes, a plurality of second electrodes, a plurality of peripheral wiring pairs and an insulating layer. The substrate has a first peripheral area, a working area and a second peripheral area, wherein the first peripheral area, the working area and the second peripheral area are arranged along a first direction, and the working area is located between the first peripheral area and the second peripheral area. The plurality of first electrodes are disposed in the working area, are separated from each other in structure, and are arranged along a second direction, wherein the first direction and the second direction are staggered. The plurality of second electrodes are disposed in the working area, are structurally separated from each other, and are arranged along the first direction. Each peripheral wiring pair includes a first peripheral wiring and a second peripheral wiring respectively belonging to the first conductive layer and the second conductive layer, and one of the first peripheral wiring and the second peripheral wiring is disposed on the first periphery One of the edge area and the second peripheral area, the other of the first peripheral wiring and the second peripheral wiring is disposed in the other of the first peripheral area and the second peripheral area, and the first peripheral wiring and the second peripheral wiring are The peripheral traces are electrically connected to the same first electrode. The insulating layer is disposed between the first conductive layer and the second conductive layer. A plurality of first peripheral wirings and a plurality of second peripheral wirings of the plurality of peripheral wiring pairs are alternately arranged on the first peripheral area.

In an embodiment of the present invention, another plurality of first peripheral wirings and another plurality of second peripheral wirings of the above-mentioned plurality of peripheral wiring pairs are alternately arranged on the second peripheral area.

In an embodiment of the present invention, the first peripheral traces and the second peripheral traces of the above-mentioned two different peripheral trace pairs are respectively electrically connected to two adjacent first electrodes and located in the first peripheral area, which is located in the first peripheral area. The first peripheral traces and the second peripheral traces of two different peripheral trace pairs in a peripheral area at least partially overlap.

In an embodiment of the present invention, the other first peripheral wiring and the other second peripheral wiring of the above-mentioned two different peripheral wiring pairs are respectively electrically connected to two adjacent first electrodes and located at the second periphery In the second peripheral area, the other first peripheral wiring and the other second peripheral wiring of the two different peripheral wiring pairs in the second peripheral area at least partially overlap.

In an embodiment of the present invention, the thicknesses of the first peripheral wiring and the second peripheral wiring of each peripheral wiring pair are different.

In an embodiment of the present invention, the plurality of first electrodes mentioned above belong to the first conductive layer, the insulating layer is disposed on the first conductive layer and has a plurality of contact windows, and each first electrode is electrically connected through the contact windows of the insulating layer. The plurality of contact windows of the insulating layer include a plurality of first contact windows and a plurality of second contact windows respectively located in the first peripheral area and the second peripheral area, The plurality of first contact windows correspond to odd-numbered first electrodes, and the plurality of second contact windows correspond to even-numbered first electrodes.

In an embodiment of the present invention, the above-mentioned substrate further has a third peripheral area located beside the first peripheral area, the working area and the second peripheral area. The electronic device further includes a plurality of pads disposed in the third peripheral region, wherein each pad includes a first conductive pattern, a second conductive pattern and a metal oxide pattern that are sequentially stacked and electrically connected to each other. The first conductive pattern and the second conductive pattern is structurally separated from a plurality of peripheral wiring pairs; the first conductive pattern and the second conductive pattern of each pad are electrically connected to the first periphery of a corresponding peripheral wiring pair through the metal oxide pattern trace or a second perimeter trace.

Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and description to refer to the same or like parts.

It will be understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or Intermediate elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to a physical and/or electrical connection. Furthermore, "electrically connected" or "coupled" may refer to the existence of other elements between the two elements.

As used herein, "about," "approximately," or "substantially" includes the stated value and the average within an acceptable deviation from the particular value as determined by one of ordinary skill in the art, given the measurement in question and the A specific amount of measurement-related error (ie, the limitations of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, as used herein, "about", "approximately" or "substantially" may be used to select a more acceptable range of deviation or standard deviation depending on optical properties, etching properties or other properties, and not one standard deviation may apply to all properties. .

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be construed as having meanings consistent with their meanings in the context of the related art and the present invention, and are not to be construed as idealized or excessive Formal meaning, unless expressly defined as such herein.

FIG. 1 is a schematic top view of an electronic device 100 according to an embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view of the electronic device 100 according to an embodiment of the present invention. Fig. 2 corresponds to the section line A-A' in Fig. 1 .

FIG. 3 is a schematic cross-sectional view of the electronic device 100 according to an embodiment of the present invention. Fig. 3 corresponds to the section line B-B' in Fig. 1 .

FIG. 4 is a schematic cross-sectional view of the electronic device 100 according to an embodiment of the present invention. Fig. 3 corresponds to the line C-C' of Fig. 1 .

Referring to FIG. 1, the electronic device 100 includes a substrate 110 having a first peripheral area 110b, a working area 110a and a second peripheral area 110c, wherein the first peripheral area 110b, the working area 110a and the second peripheral area 110c are along a first direction d1 is arranged, and the working area 110a is located between the first peripheral area 110b and the second peripheral area 110c. For example, in this embodiment, the first peripheral area 110b and the second peripheral area 110c may be a left border and a right border of the electronic device 100, respectively. In addition, in the present embodiment, the substrate 110 further has a third peripheral area 110d located beside the first peripheral area 110b, the working area 110a and the second peripheral area 110c. For example, in this embodiment, the third peripheral region 110 d may be a lower border of the electronic device 100 . In this embodiment, the material of the substrate 110 may be glass, quartz, organic polymer, or other applicable materials.

Please refer to FIG. 1 , the electronic device 100 further includes a plurality of first electrodes Tx. The plurality of first electrodes Tx are disposed in the working area 110a, are separated from each other in structure, and are arranged along a second direction d2, wherein the first direction d1 and the second direction d2 are staggered. For example, in this embodiment, the first direction d1 and the second direction d2 may be perpendicular, but the invention is not limited to this.

In this embodiment, each first electrode Tx may include a plurality of first sensing pads 122 connected in series with each other, wherein two adjacent first sensing pads 122 are electrically connected to each other. For example, in this embodiment, each of the first sensing pads 122 may be a first metal mesh, but the invention is not limited thereto.

In this embodiment, the plurality of first electrodes Tx may selectively belong to the first conductive layer 120 . Based on the consideration of conductivity, the material of the first conductive layer 120 is generally a metal material. However, the present invention is not limited thereto, and in other embodiments, the first conductive layer 120 may also use other conductive materials, such as alloys, nitrides of metal materials, oxides of metal materials, oxynitrides of metal materials, or It is a stack of metal materials and other conductive materials.

Please refer to FIG. 1 , the electronic device 100 further includes a plurality of second electrodes Rx. The plurality of second electrodes Rx are disposed in the working area 110a, are structurally separated from each other, and are arranged along the first direction d1.

In this embodiment, each second electrode Rx may include a plurality of second sensing pads 142 connected in series with each other, wherein two adjacent second sensing pads 142 are electrically connected to each other. For example, in this embodiment, each of the second sensing pads 142 may be a second metal mesh, but the invention is not limited thereto.

In this embodiment, the plurality of second electrodes Rx may selectively belong to the second conductive layer 140 . Based on the consideration of conductivity, the material of the second conductive layer 140 is generally a metal material. However, the present invention is not limited thereto, and in other embodiments, the second conductive layer 140 may also use other conductive materials, such as alloys, nitrides of metal materials, oxides of metal materials, oxynitrides of metal materials, or It is a stack of metal materials and other conductive materials.

Referring to FIG. 1 and FIG. 2 , the electronic device 100 further includes an insulating layer 130 disposed between the first conductive layer 120 and the second conductive layer 140 . The insulating layer 130 is also called a protective layer. The material of the insulating layer 130 may be an inorganic material (eg, silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials), an organic material, or a combination thereof.

Referring to FIG. 1 , the electronic device 100 further includes a plurality of peripheral wiring pairs P. Each peripheral trace pair P includes a first peripheral trace 124 and a second peripheral trace 144 belonging to the first conductive layer 120 and the second conductive layer 140 respectively, wherein the first peripheral trace 124 and the second peripheral trace 144 One is disposed in one of the first peripheral area 110b and the second peripheral area 110c, and the other of the first peripheral wiring 124 and the second peripheral wiring 144 is disposed in the first peripheral area 110b and the second peripheral area 110c and the other, and the first peripheral wiring 124 and the second peripheral wiring 144 are electrically connected to the same first electrode Tx.

In short, both ends of each first electrode Tx are electrically connected to the first peripheral wiring 124 and the second peripheral wiring 144 belonging to different film layers, respectively. In this way, the resistance value difference of the plurality of peripheral wiring pairs P respectively used for driving the plurality of first electrodes Tx can be small, thereby achieving impedance balance.

Referring to FIG. 1 , a plurality of first peripheral wirings 124 and a plurality of second peripheral wirings 144 of a plurality of peripheral wiring pairs P are alternately arranged on the first peripheral region 110b. In this embodiment, the other plurality of first peripheral wirings 124 and the other plurality of second peripheral wirings 144 of the plurality of peripheral wiring pairs P are also alternately arranged on the second peripheral region 110c. In particular, the order of arrangement of the plurality of first peripheral wirings 124 and the plurality of second peripheral wirings 144 on the first peripheral region 110b is the same as that of the other plurality of first peripheral wirings 124 and the other plurality of peripheral wirings 144 The order of arrangement of the plurality of second peripheral wirings 144 on the second peripheral area 110c is different.

For example, in this embodiment, the plurality of first electrodes Tx include a first electrode Tx-1, a first electrode Tx-2, a first electrode Tx-3 and A first electrode Tx-4, wherein the left end of the first electrode Tx-1, the left end of the first electrode Tx-2, the left end of the first electrode Tx-3 and the left end of the first electrode Tx-4 are respectively aligned with the second periphery The line 144-1, the first peripheral wiring 124-2, the second peripheral wiring 144-3 and the first peripheral wiring 124-4 are electrically connected, and the right end of the first electrode Tx-1, the first electrode Tx-2 The right end of the first electrode Tx-3 and the right end of the first electrode Tx-4 are respectively connected with the first peripheral wiring 124-1, the second peripheral wiring 144-2, the first peripheral wiring 124-3 and the first peripheral wiring 124-1. The two peripheral traces 144-4 are electrically connected. In particular, in the first peripheral area 110b, the plurality of first peripheral wirings 124 and the plurality of second peripheral wirings 144 are the second peripheral wirings 144-1, the first peripheral wirings 124-2, and the second peripheral wirings 144-1. The order of the traces 144-3 and the first peripheral traces 124-4 is arranged in the second direction d2; however, in the second peripheral area 110c, the plurality of first peripheral traces 124 and the plurality of second peripheral traces 144 are The first peripheral wirings 124-1, the second peripheral wirings 144-2, the first peripheral wirings 124-3 and the second peripheral wirings 144-4 are arranged in the second direction d2 in order.

1 and FIG. 2 , in this embodiment, a first peripheral trace 124 and a second peripheral trace 144 of two different peripheral trace pairs P are respectively electrically connected to two adjacent first electrodes Tx They are both located in the first peripheral area 110b, and the first peripheral traces 124 and the second peripheral traces 144 of the two different peripheral trace pairs P in the first peripheral area 110b at least partially overlap. Referring to FIG. 1 , similarly, the other first peripheral wiring 124 and the other second peripheral wiring 144 of the two different peripheral wiring pairs P are respectively electrically connected to the two adjacent first electrodes Tx They are both located in the second peripheral area 110c, and the other first peripheral traces 124 and the other second peripheral traces 144 of the two different peripheral trace pairs P in the second peripheral area 110c at least partially overlap.

Referring to FIG. 1 , a plurality of peripheral wiring pairs P1 , P2 , P3 , and P4 are electrically connected to a plurality of first electrodes Tx-1 , Tx-2 , Tx-3 , and Tx-4 , respectively. For example, in this embodiment, a first peripheral trace 124-2 and a second peripheral trace 144-1 of two different peripheral trace pairs P1 and P2 are electrically connected to two adjacent first peripheral traces, respectively. The electrodes Tx-2 and Tx-1 are both located in the first peripheral region 110b, and both are located in the first peripheral wiring 124-2 and the second peripheral wiring 144 of the two different peripheral wiring pairs P1 and P2 of the first peripheral region 110b -1 at least partially overlap; the other first peripheral trace 124-1 and the other second peripheral trace 144-2 of the two different peripheral trace pairs P1, P2 are respectively electrically connected to the adjacent ones The two first electrodes Tx-1, Tx-2 are both located in the second peripheral region 110c, and both are located in the other first peripheral wiring 124 of the two different peripheral wiring pairs P1, P2 in the second peripheral region 110c -1 and the other second peripheral trace 144-2 at least partially overlap.

For example, in this embodiment, a first peripheral trace 124-4 and a second peripheral trace 144-3 of two different peripheral trace pairs P3 and P4 are electrically connected to two adjacent first peripheral traces, respectively. The electrodes Tx-4 and Tx-3 are both located in the first peripheral region 110b, and both are located in the first peripheral wiring 124-4 and the second peripheral wiring of two different peripheral wiring pairs P3 and P4 in the first peripheral region 110b 144-3 at least partially overlap; the other first peripheral wiring 124-3 and the other second peripheral wiring 144-4 of the two different peripheral wiring pairs P3, P4 are respectively electrically connected to the adjacent ones The two first electrodes Tx-3, Tx-4 are both located in the second peripheral region 110c, and both are located in the other first peripheral wiring 124 of the two different peripheral wiring pairs P3, P4 in the second peripheral region 110c -3 and another second peripheral trace 144-4 at least partially overlap.

It is worth mentioning that, in this embodiment, since the first peripheral traces 124 and the second peripheral traces 144 of two different peripheral trace pairs P are respectively electrically connected to the two adjacent first electrodes Tx and are located in the same In the peripheral area, the first peripheral traces 124 and the second peripheral traces 144 of different two peripheral trace pairs P in the same peripheral area at least partially overlap. Therefore, the electronic device 100 can not only achieve impedance balance, but also have the advantages of narrow frame (eg, narrow left frame and right frame).

Referring to FIG. 1 and FIG. 2 , in this embodiment, the thicknesses of the first peripheral wiring 124 and the second peripheral wiring 144 of each peripheral wiring pair P are different. For example, in this embodiment, the thickness T1 of the first peripheral wiring 124 belonging to the first conductive layer 120 may be greater than the thickness T2 of the second peripheral wiring 144 belonging to the second conductive layer 140 , but the present invention does not This is limited.

Please refer to FIG. 1 and FIG. 2 , in this embodiment, a plurality of first electrodes Tx belong to the first conductive layer 120 , the insulating layer 130 is disposed on the first conductive layer 120 and has a plurality of contact windows 132 , each of which is a first conductive layer 132 . The electrode Tx is electrically connected to the second peripheral wiring 144 of the corresponding peripheral wiring pair P through a contact window 132 of the insulating layer 130 . In particular, the plurality of contact windows 132 of the insulating layer 130 include a plurality of first contact windows 132a and a plurality of second contact windows 132b respectively located in the first peripheral region 110b and the second peripheral region 110c, and the plurality of first contact windows 132a correspond to odd-numbered first electrodes Tx, and a plurality of second contact windows 132b correspond to even-numbered first electrodes Tx.

Referring to FIG. 1 , for example, in this embodiment, the plurality of first electrodes Tx include a first first electrode Tx-1 and a second first electrode Tx-2 arranged in sequence along the second direction d2 , the third first electrode Tx-3 and the fourth first electrode Tx-4. The first first electrode Tx-1 is electrically connected to the second peripheral wiring 144-1 of the corresponding peripheral wiring pair P1 through the first contact window 132a located in the first peripheral region 110b, and the third first electrode Tx -3 is electrically connected to a second peripheral trace 144-3 of the corresponding peripheral trace pair P3 through the first contact window 132a located in the first peripheral area 110b; the second first electrode Tx-2 passes through the second peripheral trace The second contact window 132b of the peripheral area 110c is electrically connected to the second peripheral trace 144-2 of the corresponding peripheral trace pair P2, and the fourth first electrode Tx-4 passes through the second contact located in the second peripheral area 110c The window 132b is electrically connected to a second peripheral trace 144-4 of the corresponding peripheral trace pair P4. That is, the plurality of first contact windows 132a located in the first peripheral region 110b correspond to the odd-numbered first first electrodes Tx-1 and the third first electrodes Tx-3, while those located in the second peripheral region 110c The plurality of second contact windows 132b correspond to the even-numbered second first electrodes Tx-2 and fourth first electrodes Tx-4.

Referring to FIGS. 1 and 3 , in this embodiment, the electronic device 100 further includes a plurality of pads BP1 disposed on the third peripheral region 110 d , wherein each pad BP1 includes sequentially stacked and electrically connected to each other A first conductive pattern 128, a second conductive pattern 148 and a metal oxide pattern 158, the first conductive pattern 128 and the second conductive pattern 148 are structurally separated from a plurality of peripheral trace pairs P; the first conductive pattern 128 and the second conductive pattern 148 can selectively belong to the first conductive layer 120 and the second conductive layer 140 respectively; the first conductive pattern 128 and the second conductive pattern 148 of each pad BP1 are electrically connected through the metal oxide pattern 158 To a first peripheral trace 124 or a second peripheral trace 144 corresponding to a peripheral trace pair P, and then electrically connected to a first electrode Tx.

Referring to FIG. 1 , in this embodiment, the electronic device 100 further includes a plurality of peripheral wirings 146 , which are respectively electrically connected to the plurality of second electrodes Rx. Referring to FIG. 1 and FIG. 4 , in this embodiment, the electronic device 100 further includes a plurality of pads BP2 disposed on the third peripheral region 110 d , wherein each pad BP2 includes sequentially stacked and electrically connected A first conductive pattern 129, a second conductive pattern 149 and a metal oxide pattern 159, the first conductive pattern 129 and the second conductive pattern 149 are structurally separated from a plurality of peripheral traces 146; the first conductive pattern 129 and The second conductive pattern 149 can selectively belong to the first conductive layer 120 and the second conductive layer 140 respectively; the first conductive pattern 129 and the second conductive pattern 149 of each pad BP2 are electrically connected to the metal oxide pattern 159 through the metal oxide pattern 159 . A corresponding peripheral wiring 146 is further electrically connected to a second electrode Rx.

Please refer to FIG. 1 , FIG. 2 , FIG. 3 and FIG. 4 , for example, in this embodiment, the electronic device 100 further includes an insulating layer 160 disposed on the second conductive layer 140 , wherein the insulating layer 130 covers most of the The first conductive layer 120 (ie, the plurality of first electrodes Tx and most of each of the first peripheral wirings 124 ), the insulating layer 130 does not cover the third peripheral region 110d and the extension of each of the first peripheral wirings 124 to one end of the third peripheral region 110d; the insulating layer 160 covers most of the second conductive layer 140 (ie, the plurality of second electrodes Rx, most of each second peripheral wiring 144 and each peripheral wiring 146), the insulating layer 160 does not cover the third peripheral area 110d, one end of each first peripheral wiring 124 extending to the third peripheral area 110d, each second peripheral wiring 144 extending to the third peripheral area 110d One end of the peripheral area 110d and each peripheral wiring 146 extend to one end of the third peripheral area 110d.

1 and FIG. 3 , the first conductive pattern 128 and the second conductive pattern 148 of each pad BP1 are substantially overlapped and are in direct contact, and the first conductive pattern 128 and the second conductive pattern 148 of each pad BP1 are in contact with A corresponding first peripheral trace 124 or a second peripheral trace 144 is structurally separated, and two parts of the metal oxide pattern 158 of each pad BP1 directly cover the second conductive pattern 148 and the corresponding one, respectively. on the end of the first peripheral wiring 124 or a second peripheral wiring 144; thereby, each pad BP1 can be electrically connected to a corresponding first peripheral wiring 124 or a second peripheral wiring 144, Further, it is electrically connected to a first electrode Tx through a first peripheral wiring 124 or a second peripheral wiring 144 .

1 and FIG. 4 , the first conductive pattern 129 and the second conductive pattern 149 of each pad BP2 are substantially overlapped and in direct contact with each other, and the first conductive pattern 129 and the second conductive pattern 149 of each pad BP2 are A corresponding peripheral trace 146 is structurally separated, and two parts of the metal oxide pattern 159 of each pad BP2 directly cover the second conductive pattern 149 and the end of a corresponding peripheral trace 146; Therefore, each pad BP2 can be electrically connected to a corresponding peripheral wiring 146 , and further electrically connected to a second electrode Rx through the peripheral wiring 146 .

In this embodiment, the plurality of first electrodes Tx and the plurality of second electrodes Rx are, for example, touch electrodes, and the electronic device 100 includes, for example, a touch panel, but the invention is not limited thereto.

100: Electronics 110: Substrate 110a: Workspace 110b: First peripheral area 110c: Second peripheral area 110d: The third peripheral area 120: the first conductive layer 122: first sensing pad 124, 124-1, 124-2, 124-3, 124-4: the first peripheral wiring 128, 129: the first conductive pattern 130, 160: insulating layer 132: Contact window 132a: first contact window 132b: second contact window 140: the second conductive layer 142: Second Sensing Pad 144, 144-1, 144-2, 144-3, 144-4: Second peripheral wiring 146: Peripheral routing 148, 149: the second conductive pattern 158, 159: Metal oxide pattern A-A', B-B', C-C': section lines BP1, BP2: Pad d1: first direction d2: the second direction P, P1, P2, P3, P4: peripheral wiring pairs Rx: second electrode Tx, Tx-1, Tx-2, Tx-3, Tx-4: first electrode T1, T2: Thickness

FIG. 1 is a schematic top view of an electronic device 100 according to an embodiment of the present invention. FIG. 2 is a schematic cross-sectional view of the electronic device 100 according to an embodiment of the present invention. FIG. 3 is a schematic cross-sectional view of the electronic device 100 according to an embodiment of the present invention. FIG. 4 is a schematic cross-sectional view of the electronic device 100 according to an embodiment of the present invention.

100: Electronics

110: Substrate

110a: Workspace

110b: First peripheral area

110c: Second peripheral area

110d: The third peripheral area

120: the first conductive layer

122: first sensing pad

124, 124-1, 124-2, 124-3, 124-4: the first peripheral wiring

128, 129: the first conductive pattern

130, 160: insulating layer

132: Contact window

132a: first contact window

132b: second contact window

140: the second conductive layer

142: Second Sensing Pad

144, 144-1, 144-2, 144-3, 144-4: Second peripheral wiring

146: Peripheral routing

148, 149: the second conductive pattern

158, 159: Metal oxide pattern

A-A', B-B', C-C': section lines

BP1, BP2: Pad

d1: first direction

d2: the second direction

P, P1, P2, P3, P4: peripheral wiring pairs

Rx: second electrode

Tx, Tx-1, Tx-2, Tx-3, Tx-4: first electrode

Claims (7)

An electronic device, comprising: A substrate has a first peripheral area, a working area and a second peripheral area, wherein the first peripheral area, the working area and the second peripheral area are arranged along a first direction, and the working area is located in the first peripheral area between a peripheral area and the second peripheral area; a plurality of first electrodes, disposed in the working area, separated from each other in structure, and arranged along a second direction, wherein the first direction and the second direction are staggered; a plurality of second electrodes, disposed in the working area, separated from each other in structure, and arranged along the first direction; A plurality of peripheral wiring pairs, wherein each peripheral wiring pair includes a first peripheral wiring and a second peripheral wiring respectively belonging to a first conductive layer and a second conductive layer, the first peripheral wiring and the One of the second peripheral traces is disposed in one of the first peripheral area and the second peripheral area, and the other of the first peripheral trace and the second peripheral trace is disposed in the first peripheral area and the other of the second peripheral area, and the first peripheral wiring and the second peripheral wiring are electrically connected to the same first electrode; and an insulating layer disposed between the first conductive layer and the second conductive layer; Wherein, a plurality of first peripheral wirings and a plurality of second peripheral wirings of the peripheral wiring pairs are alternately arranged on the first peripheral region. The electronic device of claim 1, wherein the other plurality of first peripheral wires and the other plurality of second peripheral wires of the peripheral wire pairs are alternately arranged on the second peripheral area. The electronic device of claim 1, wherein a first peripheral wiring and a second peripheral wiring of the two different peripheral wiring pairs are respectively electrically connected to two adjacent first electrodes and located on the first periphery In a border area, the first peripheral wiring and the second peripheral wiring of the two different peripheral wiring pairs in the first peripheral area at least partially overlap. The electronic device of claim 3, wherein the other first peripheral wiring and the other second peripheral wiring of the two different peripheral wiring pairs are respectively electrically connected to the two adjacent first electrodes and located in In the second peripheral area, the other first peripheral wiring and the other second peripheral wiring of the two different peripheral wiring pairs in the second peripheral area at least partially overlap. The electronic device of claim 1, wherein the thicknesses of the first peripheral wiring and the second peripheral wiring of each peripheral wiring pair are different. The electronic device of claim 1, wherein the first electrodes belong to the first conductive layer, the insulating layer is disposed on the first conductive layer and has a plurality of contact windows, and each of the first electrodes penetrates the insulating layer A contact window of the layer is electrically connected to the second peripheral wiring of a corresponding peripheral wiring pair; the contact windows of the insulating layer include a plurality of first peripheral areas respectively located in the first peripheral area and the second peripheral area. A contact window and a plurality of second contact windows, the first contact windows correspond to odd-numbered first electrodes, and the second contact windows correspond to even-numbered first electrodes. The electronic device according to claim 1, wherein the substrate further has a third peripheral area located beside the first peripheral area, the working area and the second peripheral area; the electronic device further comprises: A plurality of pads are disposed in the third peripheral area, wherein each pad includes a first conductive pattern, a second conductive pattern and a metal oxide pattern that are sequentially stacked and electrically connected to each other, the first conductive pattern The pattern and the second conductive pattern are structurally separated from the peripheral traces; the first conductive pattern and the second conductive pattern of each pad are electrically connected to a corresponding peripheral trace through the metal oxide pattern The first peripheral trace or the second peripheral trace of the pair.

Images