TW202209797A - Power path switch circuit - Google Patents

Abstract

The present invention discloses a power path switch circuit including: a power transistor unit including: a first vertical double-diffused metal oxide semiconductor (VDMOS) element, wherein a first current outflow end of the first VDMOS element is coupled to an output end of a power path; and a second VDMOS element, wherein a first current inflow end of the first VDMOS element and a second current inflow end of the second VDMOS element are coupled with a supply end of the power path; and a voltage fixing circuit coupled to the first current outflow end and the second current outflow end respectively for fixing a voltage of the second current outflow end to a voltage of the first current outflow end, so as to render a first turn-on current flowing through the first VDMOS element and a second turn-on current flowing through the second VDMOS element to have a preset ratio.

Description

Power Path Switch Circuit

The present invention relates to a power path switch circuit, and in particular, to a power path switch circuit capable of reducing the wiring area of a printed circuit board.

FIG. 1 shows a secondary side circuit of a conventional flyback power supply circuit. As shown in FIG. 1 , the secondary side circuit of the conventional flyback power supply circuit uses the resistor Rcs to detect the current on the secondary side, and uses the transistor bMOS to switch the current. The resistor Rcs needs to use a high-accuracy resistor for sensing current, so it is expensive and requires extra printed circuit board space to accommodate the resistor Rcs.

In view of this, the present invention proposes an innovative power path switch circuit aiming at the above-mentioned deficiencies of the prior art.

In one aspect, the present invention provides a power path switch circuit for turning on or off a power path, the power path switch circuit comprising: a power transistor unit coupled to a supply end of the power path and an output Between the terminals, the power transistor unit includes: a first vertical double-diffused metal oxide semiconductor (VDMOS) element having a first current inflow terminal, a first current outflow terminal, and a first current outflow terminal. a first control terminal, wherein the first current inflow terminal is coupled to the supply terminal, the first current outflow terminal is coupled to the output terminal, and the first control terminal receives a control signal and is turned on or turned on according to the operation The power path is not turned on; and a second VDMOS element has a second current inflow terminal, a second current outflow terminal and a second control terminal, wherein the second current inflow terminal is coupled to the supply terminal, and the first current inflow terminal is coupled to the supply terminal. Two control terminals receive the control signal; and a voltage locking circuit, respectively coupled to the first current outflow terminal and the second current outflow terminal, to lock the voltage of the second current outflow terminal to the first current outflow terminal voltage, so that a first conduction current flowing through the first VDMOS element and a second conduction current flowing through the second VDMOS element have a predetermined ratio.

In one embodiment, the voltage locking circuit includes: an error amplifier having a non-inverting input terminal and an inverting input terminal, respectively coupled to the first current outflow terminal and the second current outflow terminal; a lateral A double-diffused metal oxide semiconductor (LDMOS) device, the gate of which is coupled to the output end of the error amplifier, and a third current inflow end and the second current outflow end of the LDMOS device coupled, and a current sensing element coupled between a third current outflow terminal of the LDMOS element and a ground potential to provide a current sensing signal, wherein the current sensing signal is used to indicate the first The level of on-current.

In one embodiment, the power transistor unit and the voltage locking circuit are both integrated circuits, and the power transistor unit and the voltage locking circuit are combined into a multi-chip module (MCM).

In one embodiment, the power path is used for a secondary side circuit of a flyback power supply circuit.

In one embodiment, the power path is used for a protocol circuit, wherein the protocol circuit communicates with a load circuit using a communication protocol, and generates the control signal to determine whether to turn on or off the power path , wherein the power path is used to provide a power supply to the load circuit.

In one embodiment, the predetermined ratio of the first on-current to the second on-current is M:1, where M is a positive real number greater than 1.

One advantage of the present invention is that the present invention can omit the resistor Rcs and the transistor bMOS, so that the wiring area of the printed circuit board can be reduced, thereby reducing the size of the transformer.

The following describes in detail with specific embodiments, when it is easier to understand the purpose, technical content, characteristics and effects of the present invention.

The drawings in the present invention are schematic, mainly intended to represent the coupling relationship between the circuits and the relationship between the signal waveforms, and the circuits, signal waveforms and frequencies are not drawn to scale.

FIG. 2 is a schematic diagram showing a power path switch circuit according to an embodiment of the present invention. The power path switch circuit 20 of the present invention can be applied to any type of power path 203 . As shown in FIG. 2 , the power path switch circuit 20 includes a power transistor unit 201 and a voltage lock circuit 202 . The power transistor unit 201 is coupled between a supply terminal IN and an output terminal OUT of the power path 203 .

The power transistor unit 201 includes a first vertical double-diffused metal oxide semiconductor (VDMOS) element 2011 and a second VDMOS element 2012 . The first VDMOS device 2011 has a first current inflow terminal 2011i, a first current outflow terminal 2011o and a first control terminal 2011g. The first current inflow terminal 2011i is coupled to the supply terminal IN, and the first current outflow terminal 2011o is coupled to the output terminal OUT. The first control terminal 2011g receives a control signal VG, and operates to turn on or off the power path 203 according to the operation.

The second VDMOS device 2012 has a second current inflow terminal 2012i, a second current outflow terminal 2012o and a second control terminal 2012g. The second current inflow terminal 2012i is coupled to the supply terminal IN, and the second current outflow terminal 2012o is coupled to the output terminal OUT. The second control terminal receives the control signal VG, and operates to turn on or off the power path according to the operation.

The voltage locking circuit 202 is respectively coupled to the first current outflow terminal 2011o and the second current outflow terminal 2012o to lock the voltage of the second current outflow terminal 2012o to the voltage of the first current outflow terminal 2011o, and the first current outflow terminal 2011o It is not directly electrically connected to the second current outflow terminal 2012o, so that a first conduction current Im flowing through the first VDMOS element 2011 and a second conduction current I1 flowing through the second VDMOS element 2012 have a predetermined ratio. That is to say, by electrically connecting the current inflow terminals of the first VDMOS element 2011 and the second VDMOS element 2012 (ie, the first current inflow terminal 2011i and the second current inflow terminal 2012i ), the first VDMOS element 2011 and the second current inflow terminal 2012i are electrically connected. The control terminals of the two VDMOS elements 2012 (ie the first control terminal 2011g and the second control terminal 2012g) are electrically connected (both receive the control signal VG), and the currents of the first VDMOS element 2011 and the second VDMOS element 2012 flow out of the terminals (ie The first current outflow terminal 2011o and the second current outflow terminal 2012o) are locked to the same voltage through the voltage locking circuit 202, wherein the current outflow terminals of the first VDMOS element 2011 and the second VDMOS element 2012 are not directly electrically connected to each other; The first on-current Im and the second on-current I1 are maintained at the preset ratio. In one embodiment, the predetermined ratio of the first on-current Im to the second on-current I1 is M:1, where M is a positive real number greater than 1. In an embodiment, M may be, for example, but not limited to, a positive real number greater than 100. In a preferred embodiment, M may be, but not limited to, 2000 or 500.

In one embodiment, the power transistor unit 201 and the voltage locking circuit 202 are both integrated circuits. In a preferred embodiment, the power transistor unit 201 and the voltage locking circuit 202 can be combined into a multi-chip module (MCM). The power path switch circuit 20 of the present invention as described above can be applied to any type of power path. For example, in one embodiment, the power path 203 can be used for the secondary side circuit of a flyback power supply circuit. In another embodiment, the power path 203 can be used for a protocol circuit, wherein the protocol circuit communicates with a load circuit using a communication protocol, and generates the control signal to determine whether to turn on or off the A power path 203, wherein the power path 203 is used to provide a power supply to the load circuit. In yet another embodiment, the power path 203 can be used for an AC-DC conversion system circuit.

3 is a schematic diagram showing a secondary side circuit of a flyback power supply circuit according to an embodiment of the present invention. The embodiment shown in FIG. 3 applies the power path switch circuit 30 of the present invention to the secondary side circuit of the flyback power supply circuit, such as but not limited to the power path switch circuit 30 and the second flyback power supply circuit The secondary side circuit is integrated into a chip module. Thereby, the resistor Rcs and the transistor bMOS (blocking MOS) can be eliminated on the printed circuit board, thereby reducing the wiring space of the printed circuit board and saving the manufacturing cost. In one embodiment, the voltage locking circuit in the power path switch circuit 30 can also be integrated into the integrated circuit of the aforementioned secondary side circuit, and only the power transistor unit 201 in the power path switch circuit 30 is independent of the secondary side circuit. Outside the integrated circuit of the side circuit.

4 is a schematic diagram showing a power path switch circuit applied to a secondary side circuit of a flyback power supply circuit according to an embodiment of the present invention. As shown in FIG. 4 , the power path switch circuit 40 of the present invention can be used to turn on or turn off a power path from the supply terminal VD to the voltage bus Vbus. The power path switch circuit 40 may include a power transistor unit 401 and a voltage lock circuit 402 . In one embodiment, the voltage locking circuit 402 may be disposed in the controller of the secondary side circuit. The power transistor unit 401 is coupled between a supply terminal VD of the power path and an output terminal Vs of the controller of the secondary side circuit. The supply terminal VD here corresponds to the pin VDD in FIG. 3 . In one embodiment, the power transistor unit 401 includes a first vertical double-diffused metal oxide semiconductor (VDMOS) device 4011 and a second VDMOS device 4012 . The first VDMOS element 4011 has a first current inflow terminal 4011i, a first current outflow terminal 4011o and a first control terminal 4011g. The first current inflow terminal 4011i is coupled to the supply terminal VD through the equivalent resistance Rd1 of the D terminal, and the first current outflow terminal 4011o is coupled to the output terminal Vs1 through the equivalent resistance Rs1 of the S terminal. The first control terminal 4011g receives a control signal VG, and operates to turn on or off the power path according to the operation.

The second VDMOS device 4012 has a second current inflow terminal 4012i, a second current outflow terminal 4012o and a second control terminal 4012g. The second current inflow terminal 4012i is coupled to the supply terminal VD through the equivalent resistance Rd2 of the D terminal, and the second current outflow terminal 4012o is coupled to the output terminal Vs2 through the equivalent resistance Rs2 of the S terminal. The second control terminal 4012g receives the control signal VG, and operates to turn on or off the power path according to the operation. In one embodiment, the equivalent resistances Rd1 and Rd2 are in a specific proportional relationship. In one embodiment, the equivalent resistances Rs1 and Rs2 are in a specific proportional relationship. In one embodiment, the channel resistance Ron1 of the first VDMOS element 4011 and the channel resistance Ron2 of the second VDMOS element 4012 are in a specific proportional relationship.

The voltage locking circuit 402 is respectively coupled to the first current outflow terminal 4011o and the second current outflow terminal 4012o, and the first current outflow terminal 4011o and the second current outflow terminal 4012o are not directly electrically connected, so as to connect the second current outflow terminal 4012o to each other. The voltage is locked to the voltage of the first current outflow terminal 4011o, so that a first conduction current Im flowing through the first VDMOS element 4011 and a second conduction current I1 flowing through the second VDMOS element 4012 have a predetermined ratio. In one embodiment, the predetermined ratio of the first on-current Im to the second on-current I1 is M:1, where M is a positive real number greater than 1. In an embodiment, M may be, for example, but not limited to, a positive real number greater than 100. In a preferred embodiment, M may be, but not limited to, 2000 or 500.

The voltage lock circuit 402 may include an error amplifier 4021 , a lateral double-diffused metal oxide semiconductor (LDMOS) element 4022 and a current sensing element 4023 . The error amplifier 4021 has a non-inverting input terminal and an inverting input terminal, and is coupled to the first current outflow terminal 4011o and the second current outflow terminal 4012o through the resistor Rb3 and the resistor Rb2, respectively. The first current outflow terminal 4011o and the second current outflow terminal 4012o are respectively coupled to the non-inverting input terminal and the inverting input terminal of the error amplifier 4021. Through the loop design of the error amplifier 4021, the first current outflow terminal 4011o and the The second current outflow terminal 4012o is locked to the same voltage.

The gate 4022g of the LDMOS element 4022 is coupled to the output terminal of the error amplifier 4021, and a third current inflow terminal 4022i of the LDMOS element 4022 is coupled to the second current outflow terminal 4012o through the resistor Rb4. The current sensing element 4023 is coupled between a third current outflow terminal 4022o of the LDMOS element 4022 and a ground potential to provide a current sensing signal, which is the sensing signal of the second conduction current I1 , since the first on-current Im and the second on-current I1 have a predetermined ratio, the level of the first on-current Im can be known accordingly. Therefore, the current sensing signal can be used to indicate the level of the first on-current Im. According to the present invention, the voltage locking and current sensing are accomplished through different nodes and paths in a Kelvin Sense manner, so as to avoid parasitic elements (eg, parasitic resistance) from affecting the accuracy of voltage locking and current sensing. As shown in FIG. 4 , the voltage bus Vbus is coupled to the first current outflow terminal 4011o through the resistor Rb1. Thereby, the current can be detected through the current sensing element 4023, and the voltage can be detected through the voltage bus Vbus.

In one embodiment, the power transistor unit 401 and the voltage locking circuit 402 are both integrated circuits. In a preferred embodiment, the power transistor unit 401 and the voltage locking circuit 402 may be formed on separate chips on substrates, and may be combined into a multi-chip module (MCM). It should be noted that, in one embodiment, the resistors Rb1 ˜ Rb4 in FIG. 4 may correspond to the parasitic resistances of the bonding wires, and the two ends of the resistors Rb1 ˜ Rb4 are connected in the square containing a cross in FIG. 4 . The box symbols correspond, for example, to pads on the wafer or on the lead frame. In addition, as shown in FIG. 4, the equivalent resistances Rs1-Rs2 and Rd1-Rd2 may correspond to the parasitic resistances of the corresponding source or drain of the VDMOS element. In one embodiment, the layout metal lines on the chip are also included. parasitic resistance.

It should be noted that the power path switching circuit of the present invention can be applied to any type of power path. For example, in one embodiment, the power path can be used for the secondary side circuit of a flyback power supply circuit. In another embodiment, the power path can be used for a protocol circuit, wherein the protocol circuit communicates with a load circuit by a communication protocol, and generates the control signal to determine whether to turn on or off the power supply a path, wherein the power path is used to provide a power supply to the load circuit. In yet another embodiment, the power path can be used in an AC-DC conversion system circuit.

As described above, the power path switch circuit of the present invention can omit the resistor Rcs and the transistor bMOS, so that the wiring area of the printed circuit board can be reduced, and the size of the transformer can be reduced.

The present invention has been described above with respect to the preferred embodiments, but the above descriptions are only intended to make the content of the present invention easy for those skilled in the art to understand, and are not intended to limit the broadest scope of rights of the present invention. The described embodiments are not limited to be used alone, but can also be used in combination. For example, two or more embodiments can be used in combination, and some components in one embodiment can also be used to replace those in another embodiment. corresponding components. In addition, under the same spirit of the present invention, those skilled in the art can think of various equivalent changes and various combinations. According to the signal itself, when necessary, the signal is subjected to voltage-to-current conversion, current-to-voltage conversion, and/or ratio conversion, etc., and then processed or calculated according to the converted signal to generate an output result. It can be seen from this that under the same spirit of the present invention, those skilled in the art can think of various equivalent changes and various combinations, and there are many combinations, which are not listed and described here. Accordingly, the scope of the present invention should cover the above and all other equivalent changes.

20, 30, 40: Power Path Switch Circuits 201, 401: Power Transistor Unit 2011, 4011: The first vertical double-diffused metal-oxide-semiconductor (VDMOS) device 2011g, 4011g: The first control terminal 2011i, 4011i: First current inflow terminal 2011o, 4011o: The first current outflow terminal 2012, 4012: Second VDMOS device 2012g, 4012g: Second control terminal 2012i, 4012i: Second current inflow terminal 2012o, 4012o: Second current outflow terminal 202, 402: Voltage Lockout Circuits 203: Power Path 4021: Error Amplifier 4022: Lateral Double Diffused Metal Oxide Semiconductor (LDMOS) Devices 4022g: Gate 4022i: The third current inflow terminal 4022o: The third current outflow terminal 4023: Current Sensing Element aIFB:Node bMOS: Transistor CC1, CC2, CS+, CS-, D+, D-, GND, OPTO, RT, USBP, V2, VDD, VFB: Pin I1: second on-current IN, VD: Supply side Im: first on-current OUT, Vs, Vs1, Vs2: Output terminal Rb1, Rb2, Rb3, Rb4, Rcs: Resistors Rd1, Rd2, Rs1, Rs2: Equivalent resistance Ron1, Ron2: channel resistance Vbus: Voltage Bus VG: control signal

FIG. 1 is a schematic diagram showing a secondary side circuit of a conventional flyback power supply circuit.

FIG. 2 is a schematic diagram showing a power path switch circuit according to an embodiment of the present invention.

3 is a schematic diagram showing a secondary side circuit of a flyback power supply circuit according to an embodiment of the present invention.

4 is a schematic diagram showing a power path switch circuit applied to a secondary side circuit of a flyback power supply circuit according to an embodiment of the present invention.

20: Power path switch circuit

201: Power Transistor Unit

2011: First Vertical Double Diffused Metal Oxide Semiconductor (VDMOS) device

2011g: The first console

2011i: The first current inflow terminal

2011o: The first current outflow terminal

2012: Second VDMOS device

2012g: Second console

2012i: Second current inflow terminal

2012o: The second current outflow terminal

202: Voltage lock circuit

203: Power Path

I1: second on-current

Im: first on-current

IN: Supply side

OUT: output terminal

VG: control signal

Claims (6)

A power path switch circuit for conducting or non-conducting a power path, the power path switch circuit comprising: A power transistor unit coupled between a supply end and an output end of the power path, the power transistor unit comprising: A first vertical double-diffused metal oxide semiconductor (VDMOS) device has a first current inflow terminal, a first current outflow terminal and a first control terminal, wherein the first current inflow terminal The end is coupled to the supply end, the first current outflow end is coupled to the output end, and the first control end receives a control signal and operates to conduct or not conduct the power path according to the operation; and A second VDMOS device has a second current inflow terminal, a second current outflow terminal and a second control terminal, wherein the second current inflow terminal is coupled to the supply terminal, and the second control terminal receives the control signal ;as well as a voltage locking circuit, respectively coupled to the first current outflow terminal and the second current outflow terminal, to lock the voltage of the second current outflow terminal to the voltage of the first current outflow terminal, so as to make the voltage flowing through the current outflow terminal A first on-current of the first VDMOS element and a second on-current flowing through the second VDMOS element have a predetermined ratio. The power path switch circuit of claim 1, wherein the voltage lock circuit comprises: an error amplifier, having a non-inverting input terminal and an inverting input terminal, respectively coupled to the first current outflow terminal and the second current outflow terminal; a lateral double-diffused metal oxide semiconductor (LDMOS) device, the gate of which is coupled to the output terminal of the error amplifier, and a third current inflow terminal of the LDMOS device and the second current outflow coupling; and a current sensing element coupled between a third current outflow terminal of the LDMOS element and a ground potential to provide a current sensing signal, wherein the current sensing signal is used to indicate the level of the first on-current allow. The power path switch circuit of claim 1, wherein the power transistor unit and the voltage locking circuit are both integrated circuits, and the power transistor unit and the voltage locking circuit are combined into a multi-chip module module, MCM). The power path switch circuit of claim 1, wherein the power path is used for a secondary side circuit of a flyback power supply circuit. The power path switch circuit of claim 1, wherein the power path is used for a protocol circuit, wherein the protocol circuit communicates with a load circuit by a communication protocol, and generates the control signal to determine The power path is turned on or off, wherein the power path is used to provide a power supply to the load circuit. The power path switch circuit of claim 1, wherein the predetermined ratio of the first on-current to the second on-current is M:1, wherein M is a positive real number greater than 1.

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