TWI696339B - Switching power converter circuit and cascoded transistor circuit thereof - Google Patents

Abstract

A cascoded transistor circuit includes: a first normally-ON transistor, which is connected to a silicon field effect transistor in series between a current inflow terminal and a current outflow terminal; a second normally-ON transistor, which has a drain coupled to the current inflow terminal to provide a supply current; a voltage regulator circuit, which generates a supply voltage according to the supply current; and a control circuit, which controls the silicon field effect transistor to control a current path between the current inflow terminal and the current outflow terminal. The control circuit includes at least an active device which is controlled by the control circuit powered by the supply voltage.

Description

Switching power supply circuit and its stacked transistor circuit

The invention relates to a stacked transistor circuit, in particular to a stacked transistor circuit that generates a current source and supplies a voltage to a control circuit with a preset conduction transistor. The invention also relates to a switching power supply circuit using stacked transistor circuits.

The previous cases related to this case are: US patent application US 2017/0005583 A1 and US patent US8598937B2.

In FIG. 1, US Patent No. US20140146428A1 discloses a prior art cascoded transistor circuit (cascaded transistor circuit 1), in which gallium nitride transistor 10 and silicon MOS transistor 12 are connected in series to control the current path, In the prior art, a discrete capacitor C1 and a diode D1 or D2 are included to store charge and supply the power required by the control circuit that controls the MOS transistor 12.

The disadvantage of the prior art shown in Figure 1 is that the discrete capacitor C1 is used to provide power. Therefore, at least three dies composed of different substrates are required to form the stacked transistor circuit 1. The manufacturing process is complicated and the cost is relatively high. It is tall and large in size. In addition, since its charging source comes from the drain of the MOS transistor 12, or the switching signal for controlling the MOS transistor 12, the ripple of the power provided by the discrete capacitor C1 will be larger. Furthermore, since the parasitic capacitance of the MOS transistor 12 is large, when the stacked transistor circuit 1 is switched, the drain of the MOS transistor 12 will have a large surge.

Compared with the prior art of FIG. 1, the present invention requires fewer die to form a stacked transistor circuit. The manufacturing process is simpler, the cost is lower and the size is smaller. In addition, since the power source of the related control circuit is stable, The ripple of the power supply will be smaller. The present invention also effectively improves the aforementioned problem of surge.

A cascoded transistor circuit includes: a first preset-on transistor with a drain coupled to a current inflow terminal of the cascoded transistor circuit; a current source circuit including at least A transistor of the same type as the first preset conducting transistor, the first end of the current source circuit is coupled to the current inflow terminal, and the current source circuit is used to provide a supply through the second end of the current source circuit Current; a voltage regulating circuit, coupled to the second end of the current source circuit, for generating a supply voltage according to the supply current, wherein the supply voltage is substantially adjusted to a predetermined voltage value; a silicon field effect power A crystal, the drain of which is coupled to the source of the first preset conducting transistor, the source of which is coupled to a current outflow end of the stacked transistor circuit; and a control circuit for The input signal received by a signal input terminal of the transistor circuit controls the switching of the silicon field effect transistor to control the current path between the current inflow terminal and the current outflow terminal, wherein the control circuit includes at least one active element, The control circuit uses the supply voltage as a power source to control the active device.

In a preferred embodiment, the current source circuit includes a second preset conducting transistor, the drain of which is coupled to the current inflow terminal, the source of which is coupled to the second terminal of the current source circuit, and the gate The coupling method of the pole is one of the following: (1) its gate is coupled to the current outflow end; (2) its gate is coupled to the source of the second preset conducting transistor; or (3) The gate is coupled to a preset bias voltage; the second preset conducting transistor provides the supply current; wherein the first preset conducting transistor and the second preset conducting transistor are formed on the first semiconductor substrate.

In a preferred embodiment, both the first predetermined conduction transistor and the second predetermined conduction transistor are gallium nitride transistors, or both are silicon carbide transistors.

In a preferred embodiment, the gate of the first predetermined conducting transistor is coupled to the current outflow end.

In a preferred embodiment, the voltage regulator circuit includes a zener diode or a shunt regulator.

In a preferred embodiment, the silicon field effect transistor is a normally-OFF transistor.

In a preferred embodiment, the control circuit includes at least one of the following protection operations: (1) according to the drain voltage of the silicon field effect transistor to determine whether to perform an over-high voltage protection; (2) according to the silicon Determine whether an over-high current protection is performed based on the current of the field effect transistor; or (3) Determine whether to perform an over-high temperature protection according to a temperature.

In a preferred embodiment, the stacked transistor circuit does not include discrete capacitors.

In a preferred embodiment, the silicon field effect transistor, the voltage adjustment circuit and the control circuit are formed on the second semiconductor substrate.

In a preferred embodiment, the stacked transistor circuit further includes a voltage limiting circuit connected in parallel to the silicon field effect transistor to limit the drain voltage of the silicon field effect transistor, wherein the voltage limit The circuit includes a voltage control voltage source for adjusting the voltage of the voltage control voltage source according to the drain voltage of the silicon field effect transistor to limit the drain voltage of the silicon field effect transistor not to exceed a voltage limit Or, the voltage limiting circuit includes a voltage control current source for adjusting the current of the voltage control current source according to the drain voltage of the silicon field effect transistor to limit the drain voltage of the silicon field effect transistor Does not exceed a voltage limit.

In a preferred embodiment, the silicon field effect transistor, the voltage regulating circuit and the control circuit are formed on a second semiconductor substrate; wherein the first semiconductor substrate and the second semiconductor substrate are integrated and packaged in an integrated circuit package .

From another point of view, the present invention also provides a switching power supply circuit including: the stacked transistor circuit as described in item 1; and an inductor or a transformer coupled to the stacked power supply Crystal circuit; wherein the stacked transistor circuit is used to switch the inductor or the transformer to convert an input power to generate an output power.

From another point of view, the present invention also provides a stacked transistor circuit, including: a first preset-on (normally-ON) transistor whose drain is coupled to a current inflow terminal of the stacked transistor circuit A silicon field effect transistor, the drain of which is coupled to the source of the first predetermined conducting transistor, the source of which is coupled to a current outflow end of the stacked transistor circuit; and a voltage limiting circuit, Parallel to the silicon field effect transistor to limit the drain voltage of the silicon field effect transistor, wherein the voltage limiting circuit includes one of the following: (1) The voltage limiting circuit includes a voltage control voltage source The drain voltage of the silicon field effect transistor to adjust the voltage of the voltage control voltage source to limit the drain voltage of the silicon field effect transistor to not exceed a voltage limit; or (2) the voltage limiting circuit includes a The voltage control current source is used to adjust the current size of the voltage control current source according to the drain voltage of the silicon field effect transistor to limit the drain voltage of the silicon field effect transistor to not exceed a voltage limit.

The detailed description will be given below through specific embodiments, so that it is easier to understand the purpose, technical content, characteristics and achieved effects of the present invention.

The drawings in the present invention are schematic, mainly intended to show the coupling relationship between the circuits and the relationship between the signal waveforms. The circuits, signal waveforms and frequencies are not drawn to scale.

FIG. 2 shows a schematic diagram of an embodiment of the stacked transistor circuit of the present invention. As shown in FIG. 2, in one embodiment, the cascoded transistor circuit 100 includes a first normally-on transistor HT1, a current source circuit 11, a voltage adjustment circuit 21, and a silicon field effect Transistor MT3 and control circuit 22.

The drain of the first preset on transistor HT1 is coupled to the current inflow terminal NH of the stacked transistor circuit 100, the first end of the current source circuit 11 is coupled to the current inflow terminal NH, and the current source circuit 11 is used to pass current The second end of the source circuit 11 provides a supply current IS; in one embodiment, the current source circuit 11 includes at least one transistor of the same type as the first preset on transistor HT1, and specific embodiments thereof will be described in detail later.

The voltage adjusting circuit 21 is coupled to the second end of the current source circuit 11 for generating a supply voltage VDD according to the supply current IS, wherein the supply voltage VDD is substantially adjusted to a predetermined voltage value. The drain of the silicon field effect transistor MT3 is coupled to the source of the first predetermined turn-on transistor HT1, and the source of the silicon field effect transistor MT3 is coupled to the current outflow terminal NL of the stacked transistor circuit 100, in other words, The silicon field effect transistor MT3 and the first preset conductive transistor HT1 are connected in series with each other to control the current path between the current inflow terminal NH and the current outflow terminal NL of the stacked transistor circuit 100.

The control circuit 22 is used to generate a control signal CTL based on the input signal SI received through the signal input terminal NS of the stacked transistor circuit 100 to control the switching of the silicon field effect transistor MT3 to control the current inflow terminal NH and current outflow In the current path between the terminals NL, the control circuit 22 includes at least one active component. The control circuit 22 uses the supply voltage VDD as a power source to control the active component. Specific embodiments will be described in detail later.

FIGS. 3A to 3C show schematic diagrams of several embodiments of the stacked transistor circuit of the present invention. As shown in FIG. 3A, in an embodiment, the current source circuit 11 includes a second preset on transistor HT2, and in an embodiment, the second preset on transistor HT2 and the first preset on transistor HT1 Transistors of the same type. For example, in one embodiment, both the first predetermined conduction transistor HT1 and the second predetermined conduction transistor HT2 are gallium nitride (GaN) transistors. In another embodiment, the first predetermined conduction The conductive crystal HT1 and the second predetermined conductive transistor HT2 are both silicon carbide (SiC) transistors. This type of transistor is also generally called HEMT (High Electron Mobility Transistor). In a preferred embodiment, the preset on transistor (in this embodiment, the first preset on transistor HT1 and the second preset on transistor HT2, the same below) are gates in the form of Schottky Structure (Schottky gate) transistor. In another preferred embodiment, the on transistor is preset to be a depletion transistor.

It should be noted that the term “preset conduction” mentioned in this article refers to conduction when the gate-source voltage of the preset conduction transistor is 0. From another point of view, "preset on transistor" refers to a transistor whose on-voltage threshold is negative (in the case where the drain-source current increases as the gate-source voltage increases).

Please continue to refer to FIG. 3A. The drain of the second preset conducting transistor HT2 is coupled to the current inflow terminal NH, and its source is coupled to the second end of the current source circuit 11. In this embodiment, its gate is coupled G2 is connected to the current outgoing end NL; in other embodiments, the gate G2 of the second preset conducting transistor HT2 can be coupled to the source of the second preset conducting transistor HT2 (as shown in FIG. 3B), or The gate G2 of the second preset on transistor HT2 can be coupled to a preset bias voltage VB (as shown in FIG. 3C), wherein the preset bias voltage VB can be generated inside the stacked transistor circuit 100 or received from the stacked junction The exterior of the transistor circuit 100. The above-mentioned various gate control methods can enable the second preset conducting transistor HT2 to provide the supply current IS at the current outflow terminal NL.

Please continue to refer to FIG. 3A. In an embodiment, the first preset on transistor HT1 and the second preset on transistor HT2 are formed on the same semiconductor substrate (such as the first semiconductor substrate 10 shown in the figure). In one embodiment, the silicon field effect transistor MT3, the voltage adjustment circuit 21 and the control circuit 22 are formed on the second semiconductor substrate 20. In one embodiment, the first semiconductor substrate 10 and the second semiconductor substrate 20 are integrated and packaged in an integrated circuit package 110.

Please continue to refer to FIG. 3A. In an embodiment, the gate G1 of the first preset conduction transistor HT1 is coupled to the current outflow terminal NL. In the case where the second preset conduction transistor HT2 is controlled to be on, because The gate-source voltage of the first preset on transistor HT1 is substantially 0, therefore, the first preset on transistor HT1 is also on when the second preset on transistor HT2 is controlled to be on.

FIG. 4A shows a schematic diagram of an embodiment of a voltage regulating circuit in the stacked transistor circuit of the present invention. As shown in FIG. 4A, in one embodiment, the voltage regulating circuit 21 includes a Zener diode DZ, which generates a supply voltage VDD according to the supply current IS provided by the current source circuit 11.

FIG. 4B shows a schematic diagram of another embodiment of the voltage regulating circuit in the stacked transistor circuit of the present invention. As shown in FIG. 4B, in one embodiment, the voltage regulator circuit 21 includes a shunt regulator 211, and the shunt regulator 211 generates the supply voltage VDD according to the supply current IS provided by the current source circuit 11 . Please refer to FIG. 4C. FIG. 4C shows a schematic diagram of a specific embodiment of the voltage regulating circuit in the stacked transistor circuit of the present invention. As shown in FIG. 4B, in this embodiment, the shunt adjustment circuit 211 includes an amplifier circuit A1 for controlling the amplifier transistor M21 according to the difference between the supply voltage VDD and the reference signal to generate the supply voltage VDD, wherein the supply current IS is coupled to the current input terminal of the amplifying transistor M21. It should be noted that, in one embodiment, as shown in the figure, the current output terminal of the amplifying transistor M21 is coupled to the ground potential. In one embodiment, the ground potential is electrically connected to the stacked transistor circuit 100 The current flows out of terminal NL.

Please continue to refer to FIG. 2. In one embodiment, the silicon field effect transistor MT3 is a normally-off transistor. In a preferred embodiment, the silicon field effect transistor MT3 is an N-type MOS (Metal Oxide Silicon) transistor. In a preferred embodiment, the silicon field effect transistor MT3 is an enhancement mode (NMOS transistor) .

It should be noted that the term "default non-conduction" mentioned in this article refers to non-conduction when the gate-source voltage of the default non-conduction transistor is 0.

FIGS. 5A to 5C show schematic diagrams of embodiments of several protection operations of the control circuit 22 in the stacked transistor circuit of the present invention. As shown in FIG. 5A, in this embodiment, the control circuit 22 includes a comparison circuit 221 for determining whether to perform over-voltage protection according to the drain voltage VD3 of the silicon field effect transistor MT3. Specifically, the comparison circuit 221 compares the drain voltage VD3 of the silicon field effect transistor MT3 with the voltage threshold VTV to determine whether to perform over-voltage protection.

As shown in FIG. 5B, in this embodiment, the control circuit 22' includes a comparison circuit 222 for determining whether to perform over-current protection based on the current ID3 of the silicon field effect transistor MT3. Specifically, the comparison circuit 222 compares the drain current ID3 of the silicon field effect transistor MT3 with the current threshold VTC to determine whether to perform overcurrent protection.

As shown in FIG. 5C, in this embodiment, the control circuit 22" includes a comparison circuit 223 for judging whether to perform over-temperature protection based on the temperature signal ST. Specifically, the comparison circuit 223 compares the temperature signal ST with a temperature threshold VTT to determine whether the over-temperature protection is performed. It should be noted that the temperature signal ST indicates the temperature during operation of the stacked transistor circuit 100, and it is common knowledge in the art to sense the temperature during operation of the stacked transistor circuit 100. They are well known and will not repeat them here.

In one embodiment, in the above protection operation, when it is determined that the protection operation needs to be performed, the control circuit (22, 22', 22") controls the silicon field effect transistor MT3 to be turned off to cut off the current flowing into the terminal NH The current path between the current outflow terminal NL.

It should be noted that the above-mentioned comparison circuit includes at least one active element, and uses the aforementioned supply voltage VDD as a power source to perform the above-mentioned protection operation. For example, the comparison circuit may include, for example, a differential pair composed of transistors (corresponding to active elements), using the aforementioned supply voltage VDD as a power source, and performing the aforementioned signal comparison to determine whether to perform the aforementioned protection operation.

6A to 6C show schematic diagrams of embodiments of the stacked transistor circuit of the present invention. Since the parasitic capacitance of the first preset on transistor HT1 is usually much smaller than the parasitic capacitance of the silicon field effect transistor MT3, when the stacked transistor circuit 101 is switched, the drain of the silicon field effect transistor MT3 may be more Big surge. To solve this problem, as shown in FIG. 6A, in this embodiment, the stacked transistor circuit 101 includes a voltage limiting circuit 23 connected in parallel to the silicon field effect transistor MT3 to limit the drain of the silicon field effect transistor MT3 Voltage VD3. Specifically, as shown in FIG. 6B, in one embodiment, the voltage limiting circuit 23 includes a voltage control voltage source 231 for adjusting the voltage of the voltage control voltage source 231 according to the drain voltage of the silicon field effect transistor MT3 Size to limit the drain voltage of the silicon field effect transistor MT3 to not exceed the voltage limit. As shown in FIG. 6C, in another embodiment, the voltage limiting circuit 23 includes a voltage control current source 232 for adjusting the current size of the voltage control current source 232 according to the drain voltage of the silicon field effect transistor MT3, to Limit the drain voltage of the silicon field effect transistor MT3 to not exceed the voltage limit.

According to the present invention, the supply voltage VDD required by the control circuit 22 is provided by the cooperative operation of the current source circuit 11 composed of, for example, the second preset on transistor HT2 and the voltage regulating circuit 21, compared to the aforementioned According to the prior art, the stacked transistor circuit (such as the stacked transistor circuit 100) of this case preferably does not include a discrete capacitor for providing the supply voltage VDD. The “discrete” capacitor refers to a capacitor formed on a substrate different from the first semiconductor substrate 10 and the second semiconductor substrate 20.

In one embodiment, the aforementioned voltage regulator circuit 21 may further include a source follower coupled to the output of the shunt regulator circuit 211, which can further reduce the ripple of the supply voltage VDD, and thus also reduce the demand for capacitors .

From another point of view, in one embodiment, the stacked transistor circuit 100 in this case does not include a capacitor equal to or greater than 1000 pF to provide a supply voltage VDD. In another embodiment, the stacked The transistor-connected circuit 100 does not include a capacitor equal to or greater than 100 pF to provide the supply voltage VDD.

7A to 7B show schematic diagrams of embodiments of the stacked transistor circuit of the present invention applied to a switching power supply circuit. As shown in FIG. 7A, in one embodiment, the switching power supply circuit 200 includes, for example, a stacked transistor circuit (for example, corresponding to the aforementioned stacked transistor circuit 100), coupled to the inductor 210, wherein the stacked The transistor circuit 100 is used to switch the inductor 210 to convert the input power VIN to generate the output power VOUT. Specifically, the switching power supply circuit 200 may be, for example but not limited to, a buck, boost, buck-boost, or a reverse-flow switching power supply circuit, and the stacked transistor circuit 100 may correspond to The power switch in the above-mentioned various switching power supply circuits.

As shown in FIG. 7B, in one embodiment, the switched-mode power supply circuit 200 includes, for example, a stacked transistor circuit (for example, corresponding to the aforementioned stacked transistor circuit 100), coupled to the transformer 220, wherein the stacked power The crystal circuit 100 is used to switch the transformer 220 to convert the input power VIN to generate the output power VOUT. Specifically, the switching power supply circuit 200 may be, for example but not limited to, a flyback switching power supply circuit, and the stacked transistor circuit 100 may correspond to the primary side of the above-mentioned flyback switching power supply circuit or Secondary power switch.

The present invention has been described above with reference to preferred embodiments, but the above are only for the purpose of making the person skilled in the art easy to understand the content of the present invention, and are not intended to limit the scope of the present invention. The illustrated embodiments are not limited to individual applications, but can also be used in combination. For example, two or more embodiments can be used in combination, and some components in one embodiment can also be used to replace another embodiment. Corresponding components. In addition, under the same spirit of the present invention, those skilled in the art can think of various equivalent changes and various combinations. For example, in the foregoing embodiment, a period of time in the initialization phase or display screen interval is used as a test Stage, but as other forms of display interval, for example, the "processing or operation according to a signal or produce an output result" in the present invention is not limited to the signal itself, but also includes the voltage of the signal when necessary Current conversion, current-voltage conversion, and/or proportional conversion, etc., and then perform processing or operation according to the converted signal to produce an output result. It can be seen that, under the same spirit of the present invention, those skilled in the art can think of various equivalent changes and various combinations, and there are many combinations, which are not described here one by one. Therefore, the scope of the present invention should cover all the above and other equivalent changes.

10: The first semiconductor substrate 100, 101: stacked transistor circuit 11: Current source circuit 110: Integrated circuit package 20: Second semiconductor substrate 200: switching power supply circuit 21: Voltage regulation circuit 210: inductor 211: Shunt regulation circuit 22, 22’, 22”: control circuit 220: transformer 221, 222, 223: comparison circuit 23: Voltage limiting circuit 231: voltage control voltage source 232: Voltage controlled current source A1: Amplifying circuit CTL: control signal DZ: Zener diode G1, G2: Gate HT1: The first preset-on (normally-ON) transistor HT2: second preset conduction transistor ID3: Drain current IS: Supply current M21: Amplified transistor MT3: silicon field effect transistor NH: Current flowing into the terminal NL: current outflow end NS: signal input SI: input signal ST: temperature signal VB: preset bias VD3: Drain voltage VDD: supply voltage VIN: input power VTC: current threshold VTT: temperature threshold VTV: voltage threshold

Figure 1 shows a schematic diagram of a prior art stacked transistor circuit.

FIG. 2 shows a schematic diagram of an embodiment of the stacked transistor circuit of the present invention.

FIGS. 3A to 3C show schematic diagrams of several embodiments of the stacked transistor circuit of the present invention.

FIG. 4A shows a schematic diagram of an embodiment of a voltage regulating circuit in the stacked transistor circuit of the present invention.

FIG. 4B shows a schematic diagram of an embodiment of a voltage regulating circuit in the stacked transistor circuit of the present invention.

FIG. 4C shows a schematic diagram of a specific embodiment of a voltage regulating circuit in the stacked transistor circuit of the present invention.

5A to 5C show schematic diagrams of several embodiments of the control circuit 22 in the stacked transistor circuit of the present invention.

6A to 6C are schematic diagrams of an embodiment of the stacked transistor circuit of the present invention.

7A to 7B show schematic diagrams of embodiments of the stacked transistor circuit of the present invention applied to a switching power supply circuit.

no

10: The first semiconductor substrate

100: stacked transistor circuit

11: Current source circuit

110: Integrated circuit package

20: Second semiconductor substrate

21: Voltage regulation circuit

22: control circuit

CTL: control signal

G1, G2: gate

HT1: The first preset-on (normally-ON) transistor

HT2: second preset conduction transistor

IS: Supply current

MT3: silicon field effect transistor

NH: Current flowing into the terminal

NL: current outflow end

NS: signal input

SI: input signal

VDD: supply voltage

Claims (12)

A cascoded transistor circuit includes: a first preset-on transistor with a drain coupled to a current inflow terminal of the cascoded transistor circuit; a current source circuit including at least A transistor of the same type as the first preset conducting transistor, the first end of the current source circuit is coupled to the current inflow terminal, and the current source circuit is used to provide a supply through the second end of the current source circuit Current; a voltage regulating circuit, coupled to the second end of the current source circuit, for generating a supply voltage according to the supply current, wherein the supply voltage is substantially adjusted to a predetermined voltage value; a silicon field effect power A crystal, the drain of which is coupled to the source of the first predetermined conducting transistor, the source of which is coupled to a current outgoing end of the stacked transistor circuit; and a control circuit for controlling the power according to the stacked The input signal received at a signal input terminal of the crystal circuit controls the switching of the silicon field effect transistor to control the current path between the current inflow terminal and the current outflow terminal, wherein the control circuit includes at least one active element, the The control circuit uses the supply voltage as a power source to control the active device. The stacked transistor circuit as described in item 1 of the patent application scope, wherein the current source circuit includes a second predetermined conducting transistor, the drain of which is coupled to the current inflow terminal, and the source of which is coupled to the current source For the second end of the circuit, the gate coupling method is as follows: (1) its gate is coupled to the current outflow end; (2) its gate is coupled to the second preset conducting transistor The source of; or (3) its gate is coupled to a preset bias; The second preset conducting transistor provides the supply current; wherein the first preset conducting transistor and the second preset conducting transistor are formed on the first semiconductor substrate. The stacked transistor circuit as described in item 1 of the patent application scope, wherein the first predetermined conduction transistor and the second predetermined conduction transistor are both gallium nitride transistors or silicon carbide transistors . The stacked transistor circuit as described in item 1 of the patent application scope, wherein the gate electrode of the first predetermined conducting transistor is coupled to the current outflow end. The stacked transistor circuit as described in item 1 of the patent application scope, wherein the voltage regulator circuit includes a zener diode or a shunt regulator. The stacked transistor circuit as described in item 1 of the patent application scope, wherein the silicon field effect transistor is a normally-OFF transistor. The stacked transistor circuit as described in item 1 of the patent application scope, wherein the control circuit includes at least one of the following protection operations: (1) according to the drain voltage of the silicon field effect transistor to determine whether an excessively high Voltage protection; (2) judging whether to perform an over-high current protection according to the current of the silicon field effect transistor; or (3) judging whether to perform an over-high temperature protection according to a temperature. The stacked transistor circuit as described in item 1 of the scope of the patent application, wherein the stacked transistor circuit does not include a discrete capacitor. The stacked transistor circuit as described in item 1 of the patent application scope, wherein the silicon field effect transistor, the voltage regulating circuit and the control circuit are formed on the second semiconductor substrate. The stacked transistor circuit as described in item 1 of the patent application scope further includes a voltage limiting circuit connected in parallel to the silicon field effect transistor to limit the drain voltage of the silicon field effect transistor, wherein the voltage limit The circuit includes a voltage control voltage source for adjusting the voltage of the voltage control voltage source according to the drain voltage of the silicon field effect transistor to limit the drain voltage of the silicon field effect transistor not to exceed a voltage limit Or, the voltage limiting circuit includes a voltage control current source for adjusting the current of the voltage control current source according to the drain voltage of the silicon field effect transistor to limit the drain voltage of the silicon field effect transistor Does not exceed a voltage limit. The stacked transistor circuit as described in item 2 of the patent application scope, wherein the silicon field effect transistor, the voltage regulating circuit and the control circuit are formed on a second semiconductor substrate; wherein the first semiconductor substrate and the second semiconductor substrate Integrated packaging in an integrated circuit package. A switching power supply circuit, comprising: the stacked transistor circuit as described in item 1; and an inductor or a transformer coupled to the stacked transistor circuit; wherein the stacked transistor circuit is used To switch the inductor or the transformer to convert an input power to generate an output power.

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