JP5050628B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device including an output stage transistor and a drive circuit.

  Conventionally, a semiconductor device having a gate connected to gate wirings arranged in parallel on a semiconductor substrate, a source and a drain provided along the gate, and an output stage transistor composed of a plurality of lattice-shaped transistor cells The device is known.

  Such a semiconductor device includes a drive circuit composed of an inverter circuit or the like, and performs switching drive by an on / off signal or a high level signal (high potential signal) / low level signal (low potential signal) in the drive circuit, The output stage transistor is generally driven, and is often used to drive a power MOS (Metal Oxide Semiconductor) transistor.

  FIG. 5 is a diagram showing a conventional semiconductor device 200. In FIG. 5, the layout of the output stage transistor Q7 and the drive circuit 80 are shown. The semiconductor device 200 is configured as an IC (Integrated Circuit) including an element such as the output stage transistor Q7 and a circuit such as the drive circuit 80.

  In FIG. 5, the output stage transistor Q <b> 7 includes a plurality of gate wirings 71 arranged in parallel and a gate potential supply wiring 72 that supplies a potential to the gate wiring 71. For the gate potential supply wiring 72, for example, a good conductor such as aluminum is used. On both sides of the gate wiring 71, sources 73 and drains 74 are alternately arranged to form a transistor cell.

  In the transistor cell, when a voltage is applied to the gate connected to the gate wiring 71, an on / off switching operation is performed, and the output of the output stage transistor Q7 is output as a whole.

  The gate wiring 71 is connected to the gate potential supply wiring 72, and the gate potential supply wiring 72 is connected to the output terminal 82 of the drive circuit 80. The drive circuit 80 forms a CMOS (Complementary Metal Oxide Semiconductor) inverter circuit, and includes a p-channel MOS transistor Q8 and an n-channel MOS transistor Q9. When a signal is input to the gates of the transistors Q8 and Q9 from the input terminal 81 and a high level signal is input, the transistor Q9 is turned on, and the output terminal 82 of the drive circuit 80 has a low potential (low level). Level) ground potential 0V is output. On the other hand, when a low level signal is input to the transistors Q8 and Q9 via the input terminal 81, the transistor Q8 is turned on, so that the output terminal 82 of the drive circuit 80 has a high potential (high level). A power supply voltage Vdd is output.

  As described above, the drive circuit 80 is configured as an inverter circuit, and outputs a low level signal when a high level signal is input, and outputs a high level signal when a low level signal is input. Then, the drive circuit 80 can perform output drive control of the output stage transistor Q7 to obtain a desired output current. In particular, a power MOS transistor is often applied to the output stage transistor Q7, and desired power can be obtained by the configuration of the drive circuit 80 and the output stage transistor Q7.

Note that in a vertical structure MOSFET having parallel gate wirings provided on a semiconductor substrate, peripheral gate wirings connected to gate wire bonding pads are provided along two opposing sides in a rectangular semiconductor chip. In this wiring structure, parallel gate wiring is alternately connected to each side of the opposing peripheral gate wiring, and the current direction of the adjacent gate wiring is reversed, and the direction of the magnetic field generated by self-inductance is A semiconductor device having a MOSFET in which adjacent gate wirings are opposite to each other is known (for example, see Patent Document 1).
JP 2003-17697 A

  However, in the configuration of the conventional technique shown in FIG. 5 described above, there is a problem that high-speed switching operation is hindered by the influence of magnetic field energy due to self-inductance generated when the drive circuit 80 is switched on and off.

  In FIG. 5, considering the case where a high level signal is output from the drive circuit 80, the current flowing through the output stage transistor Q7 is represented by a broken line arrow. That is, the power supply voltage Vdd flows from the drain output to the input side end 72a of the gate potential supply wiring 72 through the transistor Q8, and then branches and flows from here to the gate potential supply wiring 72 which is branched vertically. The current that has branched and flowed up and down the gate potential supply wiring 72 flows into the gate wiring 71 from the top to the bottom in a substantially contrasted manner. At this time, according to Ampere's right-handed screw law, a magnetic field is generated around the current flowing in the direction of the broken line in the clockwise direction in the traveling direction of the current.

  Next, when the driving circuit 80 is turned on / off, the transistor Q9 is turned on, and the transistor Q8 is turned off, a current flows from the drain of the transistor Q9 to the ground. At this time, the current flowing through the gate line 71 is switched from the broken line in FIG. 5 to the direction of the solid line and flows in the opposite direction so far, so the direction of the magnetic field generated around the gate line 71 is also opposite. At this time, since the magnetic field has energy, the magnetic field energy before switching remains at the moment of switching, and extra energy is required to cancel this magnetic field energy. As a result, high-speed switching operation is hindered. In particular, when a power MOS transistor is applied to the output stage transistor Q7 and a relatively large current of about several amperes flows, the magnetic field energy generated by self-inductance increases, and the magnetic field energy that hinders high-speed switching operation is also large. turn into.

  Further, in the configuration described in Patent Document 1 described above, while the on state and the off state continue, the self-inductance generated by the adjacent gate wirings cancels each other. At the time of switching, since the direction of the current is switched, the magnetic field energy before switching also causes a problem of hindering the current flow after switching.

  Accordingly, an object of the present invention is to provide a semiconductor device including an output stage transistor and a drive circuit that can perform high-speed switching drive, eliminating adverse effects due to self-inductance even when the drive circuit is switched on and off. .

In order to achieve the above object, a semiconductor device (100, 100a, 100b, 100c) according to a first invention includes a plurality of gate wirings (11) arranged in parallel on a substrate and the plurality of gate wirings (11 ) Transistor cells (14, 15) connected in parallel to each other, a gate high potential supply wiring (12) connected only to one end of the plurality of gate wirings (11), and the plurality of gate wirings (11) Output stage transistors (Q1, Q5) including a gate low potential supply wiring (13) connected only to the other end of
A high potential output transistor (Q2, Q4) for outputting a high potential signal and a low potential output transistor (Q3) for outputting a low potential signal are provided, and the gate wiring (11) of the output stage transistor (Q1, Q5) is provided. A drive circuit (20, 20b, 20c) for switching and driving the transistor cells (14, 15) of the output stage transistors (Q1, Q5) by supplying the high potential signal or the low potential signal; ,
The output terminals (22, 22c) of the high potential output transistors (Q2, Q4) are connected to the gate high potential supply wiring (12, 12a), and the output terminals (23) of the low potential output transistor (Q3) are The gate low potential supply wiring (13, 13a) is connected.

  As a result, even when the high potential signal and low potential signal are switched by the drive circuit, the direction of the current flowing through the gate wiring of the output stage transistor is constant, and the direction of self-inductance does not change before and after switching on / off. The adverse effect caused by this can be eliminated, and a semiconductor device capable of high-speed switching drive can be obtained.

  According to a second invention, in the semiconductor device (100, 100a, 100b, 100c) according to the first invention, the output terminals (22, 22c) of the high potential output transistors (Q2, Q4) and the low potential output transistors ( The output terminal (23) of Q3) is connected to the opposing position of the gate high potential supply wiring (12, 12a) and the gate low potential supply wiring (13, 13a), respectively.

  As a result, the current flowing through each gate line is the same regardless of whether it is a high potential or a low potential, and current fluctuation when switching between a high potential and a low potential can be prevented.

A third invention is a semiconductor device according to the second invention (100, 100a, 100b, 100c),
The opposing positions are the ends (A, B) of the gate high potential supply wiring (12, 12a) and the gate low potential supply wiring (13, 13a) on the drive circuit (20, 20b, 20c) side. It is characterized by being.

  As a result, the connection wiring between the drive circuit and the output stage transistor can be shortened, the drive speed of the output stage transistor can be increased, and the space occupied in the semiconductor device can be reduced.

A fourth invention is a semiconductor device (100, 100a, 100b, 100c) according to any one of the first to third inventions,
The gate wiring (11) is formed of a polysilicon film,
The gate high potential supply wiring (12, 12a) and the gate low potential supply wiring (13, 13a) are formed of a metal containing aluminum.

  As a result, the potential supply to the gate wiring is performed by the metal containing aluminum, which is a good conductor, so that the potential can be supplied to the gate wiring almost evenly even if the gate wiring is distant.

A fifth invention is a semiconductor device (100, 100a, 100b) according to any one of the first to fourth inventions,
The drive circuit (20, 20b) includes a p-channel MOS transistor and an n-channel MOS transistor,
The output terminal (22) of the high potential output transistor (Q2) is the drain of the p-channel MOS transistor,
The output terminal (23) of the low potential output transistor (Q3) is the drain of the n-channel MOS transistor.

  Thereby, the drive circuit of the output stage transistor can be controlled with the drive circuit having the same transistor structure as that of the CMOS inverter.

A sixth invention is a semiconductor device (100c) according to any one of the first to fourth inventions,
The drive circuit (20c) includes two n-channel MOS transistors,
The output terminal (22c) of the high potential output transistor (Q4) is the source of one of the n-channel MOS transistors,
The output terminal (23) of the low potential output transistor (Q3) is the drain of the other n-channel MOS transistor.

  As a result, a drive circuit can be configured by an n-channel MOS transistor capable of high-speed operation, thereby enabling higher-speed switching drive.

  Note that the reference numerals in the parentheses are given for easy understanding, are merely examples, and are not limited to the illustrated modes.

  According to the present invention, when switching between a high potential output and a low potential output of the drive circuit, adverse effects due to self-inductance generated in the output stage transistor can be prevented, and high-speed switching drive can be performed.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

[Example 1]
FIG. 1 is a configuration diagram of a semiconductor device 100 according to a first embodiment to which the present invention is applied. In particular, a circuit configuration diagram of the drive circuit 20 and a layout configuration diagram of the output stage transistor Q1 are shown.

  In FIG. 1, a semiconductor device 100 according to the first embodiment includes an output stage transistor Q1 and a drive circuit. The semiconductor device 100 may be configured as a semiconductor chip or an IC (Integrated Circuit) as a whole, and may include other necessary circuits.

  The output stage transistor Q1 is a transistor element for outputting a final output voltage and output current. The output stage transistor Q1 is formed on a semiconductor substrate such as a semiconductor wafer and has a plurality of gate wirings 11 arranged in parallel. The gate wires arranged in parallel may be formed with gate electrodes arranged at predetermined intervals (not shown), and the source 13 and the drain 14 are alternately formed so as to sandwich the gate electrode. It's okay. A set of transistor cells is formed by the gate electrode and the source and drain disposed adjacent to the gate. The transistor cell is driven and controlled by applying a voltage to the gate electrode through the gate wiring 11. The gate wiring 11 may be formed of, for example, a polysilicon film, a conductor, and a preferable material for the gate wiring 11 may be applied. As described above, the output stage transistor Q1 may include a plurality of transistor cells formed on a substrate such as a semiconductor wafer, and the plurality of transistor cells may constitute one output stage transistor Q1.

  The output stage transistor Q1 includes gate potential supply wirings 12 and 13 that are connected to the gate wiring 11 and supply a potential to the gate wiring 11. The gate potential supply lines 12 and 13 include a gate high potential supply line 12 that supplies a high potential signal to the gate line 11 and a gate low potential supply line 13 that supplies a low potential signal to the gate line 11. The gate potential supply lines 12 and 13 are arranged substantially perpendicular to the parallel rows of the gate lines 11, and are connected to different ends of the gate lines 11. That is, the gate high potential supply wiring 12 is connected only to the upper end portion of the gate wiring 11 in FIG. 1, and the gate low potential supply wiring 13 is connected only to the lower end portion of the gate wiring 11 in the drawing.

  The gate high potential supply wiring 12 and the gate low potential supply wiring 13 may be made of a good conductor metal such as aluminum or a metal including the same, or may be made of a metal having as little resistance as possible. In addition, for example, good conductors such as gold and copper may be used.

  The gate high potential supply wiring 12 and the gate low potential supply wiring 13 are not directly connected but are all connected through the gate wiring 11. Therefore, when a high potential signal is supplied to the gate wiring 11, it is always supplied via the gate high potential supply wiring 12. Conversely, when a low potential signal is supplied, the gate low potential supply wiring 13 is always supplied. Is supplied through. In the configuration of the conventional output stage transistor Q7 shown in FIG. 5, since the gate potential supply wiring 72 is connected to both ends of the gate wiring 71, current flows from both ends, but according to the present embodiment of FIG. In the configuration of the output stage transistor Q1, the current is always supplied from one of the gate lines 11.

  As the output stage transistor Q1, various types of transistors having a plurality of gate wirings 11 arranged in parallel may be applied. For example, a power MOS transistor that performs power output control may be applied. Power MOS transistors are used with a relatively large current of about several amperes flowing through them. The amount of self-inductance generated during energization is large, and the amount of change in self-inductance that occurs when switching between high and low potentials or on / off Therefore, the driving switching speed can be greatly improved by applying this embodiment. In addition, since the vertical MOS transistor and IGBT (Insulated Gate Bipolar Transistor) also have a wiring structure in which a plurality of gate wirings 11 are arranged in parallel, the semiconductor device 100 according to this embodiment is preferably used. Applicable. In FIG. 1, the source 14 and the drain 15 are shown as an example of a wiring structure, and even if they are arranged in a vertical configuration or replaced with other types of electrode components, This embodiment may be applied if 11 is similarly arranged.

  The output stage transistor Q1 may include power output terminals 16 and 17 that perform final output of the semiconductor device 100. Since the output stage transistor Q1 is the final output stage of the semiconductor device 100, the output stage transistor Q1 has a high potential side power output terminal 16 and a low potential side power output terminal 17 as terminals for outputting this, and the power supply output from these terminals. May be done.

  The drive circuit 20 is a drive circuit for driving the output stage transistor Q1 by outputting a high potential signal or a low electronic signal to the output stage transistor Q1. In this embodiment, a high potential signal may be referred to as a high level signal or an on signal, and similarly a low potential signal may be referred to as a low level signal or an off signal.

  The drive circuit 20 includes two transistors Q2 and Q3, and includes a high potential output transistor Q2 that outputs a high potential signal and a low potential output transistor Q3 that outputs a low potential signal. In FIG. 1, a p-channel MOS transistor is applied to the high potential output transistor Q2, and an n-channel MOS transistor is applied to the low potential output transistor Q3. This is the same transistor configuration as the CMOS inverter.

  However, as shown in FIG. 5, in the conventional CMOS inverter configuration, the drain of the high-potential output transistor Q8 and the drain of the low-potential output transistor Q9 are connected and have a common output terminal 82. In the drive circuit 20 according to this embodiment of FIG. 1, the output terminal (drain) 22 of the high potential output transistor Q2 and the output terminal (drain) 23 of the low potential output transistor Q3 are not directly connected. The output terminal (drain) 22 of the high potential output transistor Q2 is connected only to the gate high potential supply wiring 12, and the output terminal (drain) 23 of the low potential output transistor Q3 is connected only to the gate low potential supply wiring 13. Yes. As a result, when the high potential output transistor Q2 is turned on to output a high potential (Vdd), the high potential signal from the output terminal 22 is directly output only to the gate high potential supply wiring 12. Similarly, when the low potential output transistor Q3 is turned on to output a low potential (ground 0 V), the low potential signal from the output terminal 23 is output only to the gate low potential supply wiring 13.

  Next, the drive operation of the drive circuit 20 configured as described above will be described.

  When a high potential signal is input to the input terminal 21, the transistor Q2 is turned off and the transistor Q3 is turned on, and a low potential output signal is output from the output terminal 23 of the transistor Q3. In FIG. Is done. At this time, the current flowing through the gate wiring 11 of the output stage transistor Q1 is in the direction of the solid line in FIG. 1, and a downward current flows from the gate wiring 11 to the ground via the transistor Q3.

  On the other hand, when a low potential signal is input to the input terminal 21, the transistor Q2 is turned on and the transistor Q3 is turned off, and the power supply voltage Vdd, which is a high potential output signal, is output from the output terminal 22 of the transistor Q2. The high potential supply wiring 12 is supplied. At this time, the direction of the current flowing through the gate wiring 11 of the output stage transistor Q1 is the direction of the broken line in FIG. 1, and the direction is a downward current flowing from the gate wiring 11 to the ground side. Become.

  Therefore, according to the drive circuit 20 and the output stage transistor Q1 of the semiconductor device 100 according to the present embodiment, the direction of the current flowing through the gate wiring 11 of the output stage transistor Q1 even when the drive circuit 20 is switched on / off. Is constant. Accordingly, the self-inductance and magnetic field energy generated according to Ampere's right-handed screw rule are always in a constant direction regardless of the switching operation of the drive circuit 20. Therefore, according to the configuration of the drive circuit 20 and the output stage transistor Q1 according to the present embodiment, the reverse residual magnetic field energy that hinders the switching operation of the drive circuit 20 can be eliminated, and the high-speed switching operation can be performed.

  The change in the self-inductance is caused not only by the change in the direction of the current flowing through the gate wiring 11 but also when the switching operation of the drive circuit 20 is switched. The magnitude and distribution of the flowing current is preferably constant. For this reason, it is preferable to use transistors having the same characteristics as the high-potential output transistor Q2 and the low-potential output transistor Q3 of the drive circuit 20. The connection point A between the output terminal 22 of the high potential output transistor Q2 and the gate high potential supply wiring 12 and the connection point B between the output terminal 23 of the low potential output transistor Q3 and the gate low potential supply wiring 13 are also connected to the gate wiring. It is preferable that the position is an opposite position, which is a contrast with respect to 11. In FIG. 1, both the connection point A and the connection point B are opposed to each other through the gate wiring 11, and both are arranged at the end on the drive circuit 20 side. As described above, the connection point A between the high potential output transistor Q2 and the gate high potential supply wiring 12 and the connection point B between the low potential output transistor Q3 and the gate low potential supply wiring 13 are provided in a contrasting or opposing position. As a result, the current distribution of the current flowing through the gate wiring 11 is less changed before and after switching driving is turned on and off, and higher-speed switching driving can be performed. In addition, since the connection points A and B are provided at the end portion on the drive circuit 20 side, the wiring between the drive circuit 20 and the output stage transistor Q1 can be shortened. Space saving in 100 can be achieved.

  If priority is given to the uniformity of the current distribution, for example, the connection point C near the center of the gate high potential supply wiring 12 and the connection point D near the center of the gate low potential supply wiring 13 opposed thereto are The output terminal 22 of the high potential output transistor Q2 may be connected to the output terminal 23 of the low potential output transistor Q3. The arrangement of these connection points may be appropriately set at a desired position according to the application.

  FIG. 2 is a diagram illustrating a circuit configuration of a semiconductor device 100a according to a modification of the first embodiment. In particular, a circuit diagram of the drive circuit 20 applied to the semiconductor device 100a and a layout configuration of the output stage transistors Q1 and Q5 are shown.

  2, the semiconductor device 100a according to the modification is different from the first embodiment according to FIG. 1 in that an output stage transistor Q5 is further provided in parallel in addition to the output stage transistor Q1. When it is desired to drive and control the two output stage transistors Q1 and Q5 by the drive circuit 20, the gate high potential supply wirings 12 and 12a of the output stage transistors Q1 and Q5 are connected in parallel to the output terminal 22 of the high potential output transistor Q2. The gate low potential supply wirings 13 and 13a of the output stage transistors Q1 and Q5 may be connected in parallel to the output terminal 23 of the low potential output transistor Q3. Thereby, the two output stage transistors Q1 and Q5 can be driven by one drive circuit 20, and the semiconductor device 100a capable of supplying larger power can be obtained.

  FIG. 3 is a diagram showing a circuit configuration of a semiconductor device 100b according to a modification of the first embodiment different from that in FIG. In particular, a circuit diagram of a drive circuit 20b applied to the semiconductor device 100b and a layout configuration of the output stage transistor Q1 are shown.

  In FIG. 3, the semiconductor device 100b according to the present modification is the same as the semiconductor device 100 according to the first embodiment of FIG. 1 in the configuration of the output stage transistor Q1. Further, in the final stage of the drive circuit 20, the p-channel MOS transistor is applied to the high-potential output transistor Q2 and the n-channel MOS transistor is applied to the low-potential output transistor Q3. 100. However, the semiconductor device 100b according to the present modification is different from the semiconductor device 100 according to the first embodiment of FIG. 1 in that the two inverters 24 and 25 are provided before the final stage of the drive circuit 20b. ing.

  In FIG. 3, the final stage of the drive circuit 20b is a drive circuit that can be referred to as a modified CMOS inverter circuit in which the output terminal of the CMOS inverter circuit is separated, but has the function of an inverter that inverts and outputs an input signal as it is. ing. Further, since the inverters 24 and 25 are also composed of two stages in the preceding stage, the signal input to the input terminal 21c of the inverter 24 is inverted by the first stage inverter 24 and the second stage inverter 25. Repeatedly, it will output the same result as not reversed. Therefore, the drive circuit 20b is configured such that a signal having the same potential level as the signal having the potential level input to the input terminal 21b is input to the final stage. The configuration of the final stage of the drive circuit 20b is the same as the configuration of the drive circuit 20 according to the first embodiment of FIG. 1, and thus the drive circuit 20b of the semiconductor device 100b according to the present modified embodiment is the same as that of the first embodiment. The drive circuit 20 and the logic circuit of the semiconductor device 100 have the same configuration.

  In the drive circuit 20b according to the present modification, the inverters 24 and 25 substantially serve as a buffer circuit that performs impedance conversion. As described above, the configuration on the logic circuit is the same as that of the drive circuit 20 according to the first embodiment, the buffer circuit is provided before the final stage input of the drive circuit 20b, impedance conversion is performed, and the input signal of the drive circuit 20b is converted. A function of stabilizing the potential level may be added.

  Thus, if the relationship between the output stage transistor Q1 and the high-potential output transistor Q2 and the low-potential output transistor Q3 in the final stage of the drive circuit 20b connected to the output stage transistor Q1 is made constant, Various modifications can be added as appropriate according to the application.

[Example 2]
FIG. 4 is a diagram illustrating the layout of the output stage transistor Q1 and the circuit configuration of the drive circuit 20c in the semiconductor device 100c according to the second embodiment. In addition, about the component similar to the component demonstrated in Example 1, the same referential mark is attached | subjected and the description is abbreviate | omitted.

  4, the layout configuration of the output stage transistor Q1 is the same as that of the output stage transistor Q1 of the semiconductor device 100 according to the first embodiment of FIG. 1, but the circuit configuration of the drive circuit 20c is the semiconductor device 100 according to the first embodiment. This is different from the drive circuits 20 and 20b.

  The drive circuit 20c according to the second embodiment includes an inverter 24, a buffer 26, an inverter 27, a high potential output transistor Q4, and a low potential output transistor Q3.

  In FIG. 4, the n-channel MOS transistor Q3 is used as the low-potential output transistor Q3, which is similar to the drive circuits 20 and 20b of the semiconductor devices 100, 100a, and 100b according to the first embodiment. The transistor Q4 is different from the drive circuits 20 and 20b of the semiconductor devices 100, 100a, and 100b according to the first embodiment in that an n-channel MOS transistor is applied.

  An n-channel MOS transistor can generally operate at a higher speed than a p-channel MOS transistor. Therefore, when it is required to operate at a higher speed and an n-channel MOS transistor is applicable, it is preferable to apply an n-channel MOS transistor to the high potential output transistor Q4. In this embodiment, the inverter circuit at the final stage of the drive circuit 20c is realized by using only two n-channel MOS transistors. As a result, higher-speed switching driving is possible.

  In the drive circuit 20c, by applying an n-channel MOS transistor to the high potential output transistor Q4, the output terminal 22c of the high potential output transistor Q4 is changed to a source electrode. Note that the output terminal 23 of the low-potential output transistor Q3 remains a drain, as in the semiconductor devices 100, 100a, and 100b according to the first embodiment.

  Next, the operation of the drive circuit 20c configured as described above will be described.

  When a high potential signal is input to the input terminal 21c of the drive circuit 20c, the inverter 24 inverts the signal to a low potential signal, and the buffer 26 and the inverter 27 input the low potential signal. A low potential signal is output as it is from the buffer 26 and is input to the gate of the high potential output transistor Q4. On the other hand, the inverter 27 inverts and outputs a high potential signal, which is input to the gate of the low potential output transistor Q3.

  The high potential output transistor Q4 is turned off when a low potential signal is input thereto. On the other hand, since the high potential signal is input to the low potential output transistor Q3, it is turned on, and the ground potential is output from the output terminal 23. Therefore, the direction of the current flowing through the gate wiring 11 is downward.

  Next, when a low potential signal is input to the input terminal 21 c of the drive circuit 20 c, a high potential signal is output from the inverter 24 and input to the buffer 26 and the inverter 27. A high potential signal is output from the buffer 26 as it is. Further, the inverter 27 inverts and outputs a low potential signal.

  Therefore, since the high potential signal is inputted to the gate of the high potential output transistor Q4, this is turned on, and the low potential signal is inputted to the gate of the low potential output transistor Q3, so this is turned off. . Accordingly, the high power supply potential Vdd is output from the output terminal 22c of the high potential output transistor Q4, and the output stage transistor Q1 is turned on. At this time, the current flowing through the gate wiring 11 is also downward, and is constant even when the output of the drive circuit 20c changes to a high potential. Therefore, adverse effects on the switching operation due to self-inductance are still prevented.

  Thus, the present invention can be applied even if the final stage transistor of the drive circuit 20c is formed of an n-channel MOS transistor. According to the semiconductor device 100c according to the present embodiment, an n-channel that can be driven at a higher speed than the p-channel MOS transistor is applied to the drive circuit 20c, whereby the semiconductor device 100c that can be driven at a higher switching speed can be obtained.

  The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the present invention. Can be added.

1 is a circuit and layout configuration diagram of a semiconductor device 100 according to Example 1. FIG. 6 is a circuit and layout configuration diagram of a semiconductor device 100a according to a modification of Example 1. FIG. FIG. 10 is a circuit and layout configuration diagram of a semiconductor device 100b according to a modification of the first embodiment different from FIG. FIG. 6 is a circuit and layout configuration diagram of a semiconductor device 100c according to a second embodiment. FIG. 6 is a circuit and layout configuration diagram of a conventional semiconductor device 200.

Explanation of symbols

11, 71 Gate wiring 12 Gate high potential supply wiring 13 Gate low potential supply wiring 14, 73 Source 15, 74 Drain 16, 17 Power output terminal 20, 20b, 20c Drive circuit 21, 21b, 21c, 81 Input terminal 22, 22c , 23, 82 Output terminal 24, 25, 27 Inverter 72, 72a Gate potential supply wiring 100, 100a, 100b, 100c, 200 Semiconductor device

Claims (6)

A plurality of gate lines arranged in parallel on the substrate; transistor cells connected in parallel to the plurality of gate lines; a gate high-potential supply line connected only to one end of the plurality of gate lines; An output stage transistor including a gate low potential supply line connected only to the other end of the plurality of gate lines;
A high potential output transistor that outputs a high potential signal and a low potential output transistor that outputs a low potential signal, and supplying the high potential signal or the low potential signal to the gate wiring of the output stage transistor, A drive circuit for switching and driving the transistor cell of the output stage transistor,
An output terminal of the high potential output transistor is connected to the gate high potential supply wiring, and an output terminal of the low potential output transistor is connected to the gate low potential supply wiring.   The output terminal of the high-potential output transistor and the output terminal of the low-potential output transistor are respectively connected to opposing positions of the gate high-potential supply wiring and the gate low-potential supply wiring. The semiconductor device described.   The semiconductor device according to claim 2, wherein the facing position is an end of the gate high potential supply wiring and the gate low potential supply wiring on the drive circuit side. The gate wiring is formed of a polysilicon film,
4. The semiconductor device according to claim 1, wherein the gate high potential supply wiring and the gate low potential supply wiring are formed of a metal containing aluminum. 5. The driving circuit includes a p-channel MOS transistor and an n-channel MOS transistor,
The output terminal of the high potential output transistor is the drain of the p-channel MOS transistor,
5. The semiconductor device according to claim 1, wherein the output terminal of the low potential output transistor is a drain of the n-channel MOS transistor. The drive circuit includes two n-channel MOS transistors,
The output terminal of the high potential output transistor is the source of one of the n-channel MOS transistors,
5. The semiconductor device according to claim 1, wherein an output terminal of the low potential output transistor is a drain of the other n-channel MOS transistor.

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