JP4101096B2 - MOS transistor device - Google Patents

MOS transistor device Download PDF

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Publication number
JP4101096B2
JP4101096B2 JP2003094974A JP2003094974A JP4101096B2 JP 4101096 B2 JP4101096 B2 JP 4101096B2 JP 2003094974 A JP2003094974 A JP 2003094974A JP 2003094974 A JP2003094974 A JP 2003094974A JP 4101096 B2 JP4101096 B2 JP 4101096B2
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mos transistor
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bare chip
pin terminal
package
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JP2004303949A (en
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幹将 圓井
隆史 秋庭
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H01L2924/12032—Schottky diode
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    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明はロードスイッチング回路等に用いられる複数個のＭＯＳトランジスタを同一パッケージに内臓したＭＯＳトランジスタ装置に関する。
【０００２】
【従来の技術】
パワーＭＯＳトランジスタと制御ＭＯＳトランジスタとを組合せロードスイッチング回路を形成することが行われている。
【０００３】
図２は一般的なパワーＭＯＳトランジスタを用いたロードスイッチング回路である。スイッチング用ＰチャンネルのパワーＭＯＳトランジスタ１のソース電極Ｓ１は電源端子に接続され電源電圧ＶＣＣが加えられる。またパワーＭＯＳトランジスタ１のドレイン電極Ｄ１には負荷２が接続される。
【０００４】
Ｎチャンネルの制御ＭＯＳトランジスタ３のドレイン電極Ｄ２にはパワーＭＯＳトランジスタ１のゲート電極Ｇ１が接続され、制御ＭＯＳトランジスタ３のソース電極Ｓ２はアースされている。さらに制御ＭＯＳトランジスタ３のゲート電極Ｇ２には制御端子４からのスイッチング信号ＳＷが加えられる。
【０００５】
今制御端子４に加えられるスイッチング信号ＳＷがハイレベルのとき、制御ＭＯＳトランジスタ３のゲート電極Ｇ２はハイレベルとなる。従って制御ＭＯＳトランジスタ３はオンされ、ドレイン電極Ｄ２とソース電極Ｓ２間はローインピーダンスにされ、パワーＭＯＳトランジスタ１のゲート電極Ｇ１はローレベルとなる。そのためパワーＭＯＳトランジスタ１はオンし、電源からの電源電圧ＶＣＣはパワーＭＯＳトランジスタ１を通って負荷２に供給される。
【０００６】
次に制御端子４に加えられるスイッチング信号ＳＷがローレベルとなると、制御ＭＯＳトランジスタ３のゲート電極Ｇ２はローレベルとなる。そのため制御ＭＯＳトランジスタ３はオフされ、ドレイン電極Ｄ２とソース電極Ｓ２間はハイインピーダンスにされ、パワーＭＯＳトランジスタ１のゲート電極Ｇ１はハイレベルとなり、パワーＭＯＳトランジスタ１はオフし、電源からの電源電圧ＶＣＣは負荷２に供給されなくなる。斯かる動作を繰返し、パワーＭＯＳトランジスタ１がオン・オフされ負荷２に所望の大きさの負荷電圧を供給する。
【０００７】
図３は前述したパワーＭＯＳトランジスタ１と制御ＭＯＳトランジスタ３の２チップを１パッケージに収納したＭＯＳトランジスタ装置の平面図である。パワーＭＯＳトランジスタ１はオン抵抗を小さくするため、フレーム状のヘッダーに搭載される。
【０００８】
樹脂で形成されたパッケージ５には従来同一サイズのアイランドとなる第１のヘッダー６及び第２のヘッダー７が設けられている。第１ヘッダー６の先端はパッケージ５から突出し、ピン端子８を形成する。同様に第２ヘッダー７の先端もパッケージ５から突出し、ピン端子９を形成する。さらにパッケージ５の片側にはピン端子８と共に独立したピン端子１１、１２が設けられ、パッケージ５の反対側にはピン端子１４、１５が設けられている。
【０００９】
第１のヘッダー６にはパワーＭＯＳトランジスタ１のベアチップのドレイン電極が直接搭載されている。そしてピン端子８はパワーＭＯＳトランジスタ１のドレイン電極Ｄ１となす。またピン端子１４とパワーＭＯＳトランジスタ１のソース電極は両端をボンディングした金属細線１６で接続されソース電極Ｓ１となし、ピン端子１５とゲート電極Ｇ１とは同様に金属細線１７で接続し、ゲート電極Ｇ１となしている。
【００１０】
さらにピン端子１１と制御ＭＯＳトランジスタ３のソース電極は両端をボンディングした金属細線１８で接続されソース電極Ｓ２となし、ピン端子１２とゲート電極Ｇ２とは同様に金属細線１９で接続し、ゲート電極Ｇ２となしている。そして制御ＭＯＳトランジスタ３のドレイン電極Ｄ２となるピン端子９パワーＭＯＳトランジスタ１のベアチップ２１のゲート電極Ｇ１となるピン端子１５とを外部で接続し、図２のロードスイッチング回路を構成する。
【００１１】
【特許文献１】
米国特許第６，３０７，７５５号明細書
【００１２】
【発明が解決しようとする課題】
前述したように、従来はパッケージに同一サイズのアイランド２個からなるヘッダーを設け、夫々にパワーＭＯＳトランジスタと制御トランジスタのベアチップを設けていた。しかしパワーＭＯＳトランジスタはオン抵抗を小さくするために、ヘッダーを大きくする必要がある。
【００１３】
図４に示すように、パワーＭＯＳトランジスタ１のベアチップを搭載する第１のヘッダー６を大きくすると、パッケージ５の大きさが決められているためピン端子１５の位置までおよび、本来であるなら制御ＭＯＳトランジスタ３のゲート電極となるピン端子１５を独自に設けることができなくなる。
【００１４】
そのため、パワーＭＯＳトランジスタ１と共に２端子のショットキーダイオードを第２のヘッダー７に搭載できるが、制御ＭＯＳトランジスタ３を搭載したときゲート電極となるピン端子１５を設けることができず、２個のＭＯＳトランジスタを同一パッケージに内蔵できない。
【００１５】
【課題を解決するための手段】
本発明はパワーＭＯＳトランジスタのオン抵抗を小さくするため、パワーＭＯＳトランジスタのベアチップを搭載するヘッダーを大きくしても同一パッケージ内に制御ＭＯＳトランジスタを搭載するヘッダーを収納可能にしたもので、同一のパッケージ内に設けられ、外部に突出するピン端子を形成した第１のヘッダーと該第１のヘッダーよりも小さいサイズの第２のヘッダーと、前記ピン端子と共にパッケージの側面に突出させ設けられた複数個のピン端子と、第１のヘッダーにドレイン電極が直接に搭載された第１のＭＯＳトランジスタのベアチップと、第２のヘッダーにドレイン電極が直接に搭載された第２のＭＯＳトランジスタのベアチップとよりなり、第１及び第２のヘッダーに夫々搭載された第１及び第２のＭＯＳトランジスタのベアチップに形成されたソース電極を前記パッケージに設けられたピン端子に金属細線で夫々接続し、第１のＭＯＳトランジスタのベアチップに形成したゲート電極を第２のヘッダーに連なる第２ＭＯＳトランジスタのベアチップのドレイン電極となるピン端子に金属細線で接続するＭＯＳトランジスタ装置を提供する。
【００１６】
本発明は前記第１のＭＯＳトランジスタのベアチップはパワーＭＯＳトランジスタのベアチップであり、第２のＭＯＳトランジスタのベアチップは制御ＭＯＳトランジスタのベアチップであるＭＯＳトランジスタ装置を提供する。
【００１７】
【発明の実施の形態】
本発明の半導体装置を図１及び図２に従って説明する。
【００１８】
図２はパワーＭＯＳトランジスタを用いたロードスイッチング回路である。
【００１９】
スイッチング用に用いられるＰチャンネルのパワーＭＯＳトランジスタ１はソース電極Ｓ１、ドレイン電極Ｄ１及びゲート電極Ｇ１を有する。パワーＭＯＳトランジスタ１のソース電極Ｓ１は電源端子に接続され電源電圧ＶＣＣが加えられる。またパワーＭＯＳトランジスタ１のドレイン電極Ｄ１には負荷２が接続される。
【００２０】
Ｎチャンネルの制御ＭＯＳトランジスタ３はパワーＭＯＳトランジスタ１を制御するもので、ドレイン電極Ｄ２にはパワーＭＯＳトランジスタ１のゲート電極Ｇ１が接続され、制御ＭＯＳトランジスタ３のソース電極Ｓ２はアースされている。さらに制御ＭＯＳトランジスタ３のゲート電極Ｇ２には制御端子４からのスイッチング信号ＳＷが加えられる。
【００２１】
制御端子４にはパルス状のスイッチング信号が加えられる。今スイッチング信号ＳＷがハイレベルのとき、制御ＭＯＳトランジスタ３のゲート電極Ｇ２はハイレベルとなる。従って制御ＭＯＳトランジスタ３はオンされ、ドレイン電極Ｄ２とソース電極Ｓ２間はローインピーダンスにされ、パワーＭＯＳトランジスタ１のゲート電極Ｇ１はローレベルとなる。そのためパワーＭＯＳトランジスタ１はオンし、電源からの電源電圧ＶＣＣはパワーＭＯＳトランジスタ１を通って負荷２に供給される。
【００２２】
次に制御端子４に加えられるスイッチング信号ＳＷがローレベルとなると、制御ＭＯＳトランジスタ３のゲート電極Ｇ２はローレベルとなる。そのため制御ＭＯＳトランジスタ３はオフされ、ドレイン電極Ｄ２とソース電極Ｓ２間はハイインピーダンスにされ、パワーＭＯＳトランジスタ１のゲート電極Ｇ１はハイレベルとなり、パワーＭＯＳトランジスタ１はオフし、電源からの電源電圧ＶＣＣは負荷２に供給されなくなる。斯かる動作を繰返してパワーＭＯＳトランジスタ１がオン・オフされ負荷２に所望の大きさの負荷電圧を供給する。
【００２３】
図１は本発明のＭＯＳトランジスタ装置の平面図で、負荷２に所定の電源電圧ＶＣＣを供給するために用いられた前述のパワーＭＯＳトランジスタ１のベアチップ２０と制御ＭＯＳトランジスタ３のベアチップ２１の２チップを１パッケージに収納している。パワーＭＯＳトランジスタ１のベアチップ２０はオン抵抗を小さくするため、ヘッダーに搭載される。
【００２４】
パッケージ２３は樹脂で形成され、第１のヘッダー２４及び第２のヘッダー２５が設けられている。第１ヘッダー２４はパワーＭＯＳトランジスタ１のベアチップ２０のドレイン電極を直接に搭載するものである。第１のヘッダー２４は搭載されるパワーＭＯＳトランジスタ１のベアチップ２０オン抵抗を小さくするために、サイズを大きくしている。
【００２５】
パッケージ２３の一側には第１のヘッダー２４の先端をパッケージ２３から突出しドレイン電極Ｄ１となるピン端子２６Ａを形成した他、パッケージ２３の中央に本来なら独立したゲート電極Ｇ１となるピン端子２６Ｂを形成する。しかし第1のヘッダー２４はサイズを大きくしたため、ピン端子２６Ｂは独立したものとはならず、ピン端子２６Ａと連続したピン端子となる。
【００２６】
パッケージ２３のピン端子２６Ａ、２６Ｂが設けられた一側には第２のヘッダー２５の先端をパッケージ２３から突出し、ドレイン電極Ｄ２となるピン端子２７を形成する。さらにパッケージ２３のピン端子２６Ａ、２６Ｂ、２７が設けられたのと反対側にはソース電極Ｓ１となるピン端子２８、ゲート電極Ｇ２となるピン端子３０及びソース電極Ｓ２となるピン端子２９が設けられている。
【００２７】
第１のヘッダー２４にはパワーＭＯＳトランジスタ１のベアチップ２０のドレイン電極が直接搭載されている。そしてピン端子２６Ａ、２６ＢはパワーＭＯＳトランジスタ１のベアチップ２０のドレイン電極Ｄ１となす。また第２のヘッダー２５には制御ＭＯＳトランジスタ３のベアチップ２１のドレイン電極が搭載される。そしてピン端子２７はベアチップ２１のドレイン電極Ｄ２となる。
【００２８】
ピン端子２８とパワーＭＯＳトランジスタ１のベアチップ２０のソース電極は両端をボンディングした金属細線３２で接続しソース電極Ｓ１となす。さらにピン端子２９と制御ＭＯＳトランジスタ３のベアチップ２１のソース電極は両端をボンディングした金属細線３３で接続しソース電極Ｓ２となし、ピン端子３０とベアチップ２１のゲート電極とは同様に金属細線３４で接続し、ゲート電極Ｇ２となしている。
【００２９】
ところでパワーＭＯＳトランジスタ１のベアチップ２０にあるゲート電極は本来であるならピン端子２６Ｂに金属細線で接続し、ピン端子２６Ｂとピン端子２７とを外部で接続し、図２に示すロードスイッチング回路を構成している。しかし、本発明ではパワーＭＯＳトランジスタ１のベアチップ２０を搭載する第１のヘッダー２４のサイズを大きくしたので、ピン端子２６Ｂを独立して設けられない。
【００３０】
そこで本発明はパワーＭＯＳトランジスタ１のベアチップ２０のゲート電極を金属細線３５で制御トランジスタ３のベアチップ２１のドレイン電極Ｄ２となるピン端子２７に接続する。それによりパワーＭＯＳトランジスタ１のゲート電極Ｇ１と制御ＭＯＳトランジスタ３のドレイン電極Ｄ２とは外部で接続することなく接続される。
【００３１】
【発明の効果】
本発明のＭＯＳトランジスタ装置はパワーＭＯＳトランジスタのベアチップに形成されたドレイン電極をサイズの大きい第１のヘッダーに直接搭載し、第２のＭＯＳトランジスタのベアチップに形成されたドレイン電極を第２のヘッダーに直接搭載し、第１のＭＯＳトランジスタのベアチップに形成したゲート電極を第２のヘッダーに連なる第２ＭＯＳトランジスタのベアチップに形成したドレイン電極となるピン端子に金属細線で直接に接続したので、パワーＭＯＳトランジスタのオン抵抗を小さくするため、第１のヘッダーのサイズを大きくしても同一パッケージ内に制御ＭＯＳトランジスタを搭載する第２のヘッダーを内蔵することができる。
【００３２】
またパワーＭＯＳトランジスタを搭載する第１のヘッダーのサイズを大きくしたので、放熱効果が増加する。
【００３３】
さらにパワーＭＯＳトランジスタのゲート電極と制御トランジスタのゲート電極はパッケージ内で接続されているので、外部で接続する手間が省ける。
【図面の簡単な説明】
【図１】本発明のＭＯＳトランジスタ装置の平面図である。
【図２】本発明及び従来のＭＯＳトランジスタ装置を用いたロードスイッチング回路の回路図である。
【図３】従来のＭＯＳトランジスタ装置の平面図である。
【図４】従来のＭＯＳトランジスタ装置のヘッダーの平面図である。
【符号の説明】
２０ パワーＭＯＳトランジスタのベアチップ
２１ 制御ＭＯＳトランジスタのベアチップ
２３ パッケージ
２４ 第１のヘッダー
２５ 第２のヘッダー
２７ ピン端子[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a MOS transistor device in which a plurality of MOS transistors used in a load switching circuit or the like are incorporated in the same package.
[0002]
[Prior art]
A load switching circuit is formed by combining a power MOS transistor and a control MOS transistor.
[0003]
FIG. 2 shows a load switching circuit using a general power MOS transistor. The source electrode S1 of the switching P-channel power MOS transistor 1 is connected to the power supply terminal to which the power supply voltage VCC is applied. A load 2 is connected to the drain electrode D1 of the power MOS transistor 1.
[0004]
The drain electrode D2 of the N-channel control MOS transistor 3 is connected to the gate electrode G1 of the power MOS transistor 1, and the source electrode S2 of the control MOS transistor 3 is grounded. Further, the switching signal SW from the control terminal 4 is applied to the gate electrode G2 of the control MOS transistor 3.
[0005]
When the switching signal SW applied to the control terminal 4 is at a high level now, the gate electrode G2 of the control MOS transistor 3 is at a high level. Accordingly, the control MOS transistor 3 is turned on, the drain electrode D2 and the source electrode S2 are set to low impedance, and the gate electrode G1 of the power MOS transistor 1 is set to the low level. Therefore, the power MOS transistor 1 is turned on, and the power supply voltage VCC from the power supply is supplied to the load 2 through the power MOS transistor 1.
[0006]
Next, when the switching signal SW applied to the control terminal 4 becomes low level, the gate electrode G2 of the control MOS transistor 3 becomes low level. Therefore, the control MOS transistor 3 is turned off, the drain electrode D2 and the source electrode S2 are set to high impedance, the gate electrode G1 of the power MOS transistor 1 becomes high level, the power MOS transistor 1 is turned off, and the power supply voltage VCC from the power supply Is not supplied to the load 2. By repeating such an operation, the power MOS transistor 1 is turned on / off, and a load voltage having a desired magnitude is supplied to the load 2.
[0007]
FIG. 3 is a plan view of a MOS transistor device in which two chips of the power MOS transistor 1 and the control MOS transistor 3 are accommodated in one package. The power MOS transistor 1 is mounted on a frame-like header in order to reduce the on-resistance.
[0008]
A package 5 made of resin is conventionally provided with a first header 6 and a second header 7 which are islands of the same size. The tip of the first header 6 protrudes from the package 5 to form a pin terminal 8. Similarly, the tip of the second header 7 protrudes from the package 5 to form a pin terminal 9. Further, independent pin terminals 11 and 12 are provided along with the pin terminal 8 on one side of the package 5, and pin terminals 14 and 15 are provided on the opposite side of the package 5.
[0009]
The drain electrode of the bare chip of the power MOS transistor 1 is directly mounted on the first header 6. The pin terminal 8 serves as the drain electrode D1 of the power MOS transistor 1. The pin terminal 14 and the source electrode of the power MOS transistor 1 are connected by a metal thin wire 16 bonded at both ends to form a source electrode S1, and the pin terminal 15 and the gate electrode G1 are similarly connected by a metal thin wire 17 to form a gate electrode G1. It is done.
[0010]
Further, the pin terminal 11 and the source electrode of the control MOS transistor 3 are connected by a metal thin wire 18 bonded at both ends to form a source electrode S2, and the pin terminal 12 and the gate electrode G2 are similarly connected by a metal thin wire 19, and the gate electrode G2 It is done. The pin terminal 9 serving as the drain electrode D2 of the control MOS transistor 3 and the pin terminal 15 serving as the gate electrode G1 of the bare chip 21 of the power MOS transistor 1 are externally connected to constitute the load switching circuit of FIG.
[0011]
[Patent Document 1]
US Pat. No. 6,307,755 specification
[Problems to be solved by the invention]
As described above, a header having two islands of the same size is conventionally provided in a package, and a power MOS transistor and a control transistor bare chip are provided in each package. However, the power MOS transistor needs to have a large header in order to reduce the on-resistance.
[0013]
As shown in FIG. 4, when the size of the first header 6 on which the bare chip of the power MOS transistor 1 is mounted is increased, the size of the package 5 is determined, so that the position of the pin terminal 15 is reached. The pin terminal 15 that becomes the gate electrode of the transistor 3 cannot be provided independently.
[0014]
Therefore, a two-terminal Schottky diode can be mounted on the second header 7 together with the power MOS transistor 1, but when the control MOS transistor 3 is mounted, the pin terminal 15 serving as a gate electrode cannot be provided, and two MOS Transistors cannot be built in the same package.
[0015]
[Means for Solving the Problems]
In the present invention, in order to reduce the on-resistance of the power MOS transistor, the header for mounting the control MOS transistor can be accommodated in the same package even when the header for mounting the bare chip of the power MOS transistor is enlarged. provided within a plurality provided projecting a second header of a size smaller than the first header and the first header forming a pin terminal projecting outside the side surface of the package with the pin terminals A first MOS transistor bare chip with a drain electrode mounted directly on the first header, and a second MOS transistor bare chip with a drain electrode mounted directly on the second header. And first and second MOS transistors mounted on the first and second headers, respectively. The source electrode formed on the bare chip is connected to the pin terminal provided on the package with a thin metal wire, and the gate electrode formed on the bare chip of the first MOS transistor is connected to the drain of the bare chip of the second MOS transistor connected to the second header. Provided is a MOS transistor device that is connected to a pin terminal serving as an electrode by a thin metal wire.
[0016]
The present invention provides a MOS transistor device in which the bare chip of the first MOS transistor is a bare chip of a power MOS transistor, and the bare chip of the second MOS transistor is a bare chip of a control MOS transistor.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
The semiconductor device of the present invention will be described with reference to FIGS.
[0018]
FIG. 2 shows a load switching circuit using a power MOS transistor.
[0019]
A P-channel power MOS transistor 1 used for switching has a source electrode S1, a drain electrode D1, and a gate electrode G1. The source electrode S1 of the power MOS transistor 1 is connected to the power supply terminal and applied with the power supply voltage VCC. A load 2 is connected to the drain electrode D1 of the power MOS transistor 1.
[0020]
The N-channel control MOS transistor 3 controls the power MOS transistor 1. The drain electrode D2 is connected to the gate electrode G1 of the power MOS transistor 1, and the source electrode S2 of the control MOS transistor 3 is grounded. Further, the switching signal SW from the control terminal 4 is applied to the gate electrode G2 of the control MOS transistor 3.
[0021]
A pulsed switching signal is applied to the control terminal 4. When the switching signal SW is at a high level now, the gate electrode G2 of the control MOS transistor 3 is at a high level. Accordingly, the control MOS transistor 3 is turned on, the drain electrode D2 and the source electrode S2 are set to low impedance, and the gate electrode G1 of the power MOS transistor 1 is set to the low level. Therefore, the power MOS transistor 1 is turned on, and the power supply voltage VCC from the power supply is supplied to the load 2 through the power MOS transistor 1.
[0022]
Next, when the switching signal SW applied to the control terminal 4 becomes low level, the gate electrode G2 of the control MOS transistor 3 becomes low level. Therefore, the control MOS transistor 3 is turned off, the drain electrode D2 and the source electrode S2 are set to high impedance, the gate electrode G1 of the power MOS transistor 1 becomes high level, the power MOS transistor 1 is turned off, and the power supply voltage VCC from the power supply Is not supplied to the load 2. By repeating such an operation, the power MOS transistor 1 is turned on / off to supply a load voltage having a desired magnitude to the load 2.
[0023]
FIG. 1 is a plan view of a MOS transistor device according to the present invention. Two chips of the bare chip 20 of the power MOS transistor 1 and the bare chip 21 of the control MOS transistor 3 used for supplying a predetermined power supply voltage VCC to the load 2 are shown. Are stored in one package. The bare chip 20 of the power MOS transistor 1 is mounted on the header in order to reduce the on-resistance.
[0024]
The package 23 is made of resin, and a first header 24 and a second header 25 are provided. The first header 24 directly mounts the drain electrode of the bare chip 20 of the power MOS transistor 1. The size of the first header 24 is increased in order to reduce the on-resistance of the bare chip 20 of the power MOS transistor 1 to be mounted.
[0025]
On one side of the package 23, the tip of the first header 24 protrudes from the package 23 to form a pin terminal 26 A that becomes the drain electrode D 1, and a pin terminal 26 B that originally becomes an independent gate electrode G 1 in the center of the package 23. Form. However, since the size of the first header 24 is increased, the pin terminal 26B is not independent, but is a pin terminal continuous with the pin terminal 26A.
[0026]
On one side of the package 23 where the pin terminals 26A and 26B are provided, the tip of the second header 25 protrudes from the package 23 to form a pin terminal 27 serving as the drain electrode D2. Further, on the opposite side of the package 23 where the pin terminals 26A, 26B, and 27 are provided, a pin terminal 28 that becomes the source electrode S1, a pin terminal 30 that becomes the gate electrode G2, and a pin terminal 29 that becomes the source electrode S2 are provided. ing.
[0027]
The drain electrode of the bare chip 20 of the power MOS transistor 1 is directly mounted on the first header 24. The pin terminals 26A and 26B serve as the drain electrode D1 of the bare chip 20 of the power MOS transistor 1. The drain electrode of the bare chip 21 of the control MOS transistor 3 is mounted on the second header 25. The pin terminal 27 becomes the drain electrode D2 of the bare chip 21.
[0028]
The pin electrode 28 and the source electrode of the bare chip 20 of the power MOS transistor 1 are connected by a thin metal wire 32 bonded at both ends to form a source electrode S1. Further, the pin terminal 29 and the source electrode of the bare chip 21 of the control MOS transistor 3 are connected by a metal thin wire 33 bonded at both ends to form a source electrode S2, and the pin terminal 30 and the gate electrode of the bare chip 21 are similarly connected by a metal thin wire 34. The gate electrode G2.
[0029]
By the way, if the gate electrode of the bare chip 20 of the power MOS transistor 1 is originally connected to the pin terminal 26B with a thin metal wire, the pin terminal 26B and the pin terminal 27 are connected externally to constitute the load switching circuit shown in FIG. is doing. However, since the size of the first header 24 on which the bare chip 20 of the power MOS transistor 1 is mounted is increased in the present invention, the pin terminal 26B cannot be provided independently.
[0030]
Therefore, in the present invention, the gate electrode of the bare chip 20 of the power MOS transistor 1 is connected to the pin terminal 27 serving as the drain electrode D2 of the bare chip 21 of the control transistor 3 by a thin metal wire 35. Thereby, the gate electrode G1 of the power MOS transistor 1 and the drain electrode D2 of the control MOS transistor 3 are connected without being connected externally.
[0031]
【The invention's effect】
In the MOS transistor device of the present invention, the drain electrode formed on the bare chip of the power MOS transistor is directly mounted on the first header having a large size, and the drain electrode formed on the bare chip of the second MOS transistor is used as the second header. Since the gate electrode formed directly on the bare chip of the first MOS transistor is directly connected to the pin terminal serving as the drain electrode formed on the bare chip of the second MOS transistor connected to the second header with a thin metal wire, the power MOS transistor In order to reduce the on-resistance, even if the size of the first header is increased, the second header for mounting the control MOS transistor can be incorporated in the same package.
[0032]
Further, since the size of the first header on which the power MOS transistor is mounted is increased, the heat dissipation effect is increased.
[0033]
Further, since the gate electrode of the power MOS transistor and the gate electrode of the control transistor are connected in the package, it is possible to save the trouble of external connection.
[Brief description of the drawings]
FIG. 1 is a plan view of a MOS transistor device of the present invention.
FIG. 2 is a circuit diagram of a load switching circuit using the present invention and a conventional MOS transistor device.
FIG. 3 is a plan view of a conventional MOS transistor device.
FIG. 4 is a plan view of a header of a conventional MOS transistor device.
[Explanation of symbols]
20 Bare chip of power MOS transistor 21 Bare chip of control MOS transistor 23 Package 24 First header 25 Second header 27 Pin terminal

Claims (3)

同一のパッケージ内に設けられ、外部に突出するピン端子を形成した第１のヘッダーと該第１のヘッダーよりも小さいサイズの第２のヘッダーと、
前記第１及び前記第２のヘッダーに形成されたピン端子と共に前記パッケージの側面に突出させ設けられた複数個の他のピン端子と、
前記第１のヘッダーにドレイン電極が直接に搭載された第１のＭＯＳトランジスタのベアチップと、前記第２のヘッダーにドレイン電極が直接に搭載された第２のＭＯＳトランジスタのベアチップとよりなり、
前記第１及び前記第２のヘッダーに夫々搭載された前記第１及び前記第２のＭＯＳトランジスタのベアチップに形成したソース電極を前記パッケージに設けられた前記他のピン端子に金属細線で夫々接続し、
前記第１のＭＯＳトランジスタのベアチップに形成したゲート電極を前記第２のヘッダーに連なる前記第２ＭＯＳトランジスタのベアチップに形成したドレイン電極となる前記ピン端子に金属細線で接続することを特徴とするＭＯＳトランジスタ装置。A first header provided in the same package and formed with a pin terminal projecting to the outside; a second header having a size smaller than the first header;
A plurality of the other pin terminals provided to project on the side surfaces of the package together with the first and the second pin terminals formed in the header,
A bare chip of the first MOS transistor, wherein the first header to the drain electrode is mounted directly to, and more becomes a bare chip of the second MOS transistor having a drain electrode is mounted directly to the second header,
Respectively connected with said first and said second header to respective onboard the first and the second MOS transistor the other metal to a pin terminal thin line source electrode formed on the bare chip mounted on the package ,
MOS transistors, characterized in that the connection by a metal thin wire to the pin terminal to be the first drain electrode formed on the bare chip of the first 2MOS transistor gate electrode formed on the bare chip of the MOS transistor connected to the second header apparatus. 前記第１のＭＯＳトランジスタのベアチップはパワーＭＯＳトランジスタのベアチップであり、前記第２のＭＯＳトランジスタのベアチップは制御ＭＯＳトランジスタのベアチップであることを特徴とする請求項１記載のＭＯＳトランジスタ装置。2. The MOS transistor device according to claim 1, wherein the bare chip of the first MOS transistor is a bare chip of a power MOS transistor, and the bare chip of the second MOS transistor is a bare chip of a control MOS transistor. 前記第１のＭＯＳトランジスタ及び前記第２のＭＯＳトランジスタでロードスイッチング回路を構成することを特徴とする請求項１記載のＭＯＳトランジスタ装置。MOS transistor device according to claim 1, characterized in that it constitutes a load switching circuit in said first MOS transistor and said second MOS transistor.
JP2003094974A 2003-03-31 2003-03-31 MOS transistor device Expired - Fee Related JP4101096B2 (en)

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