TW202209435A - Circuit and fabrication method thereof - Google Patents

Abstract

A circuit substrate includes a patterned substrate, a patterned insulating structure and a signal line. The patterned insulating structure includes device parts and circuit parts. The device parts are located on the patterned substrate. The circuit parts are located on the patterned substrate and connected to a corresponding device part. At least one circuit part includes a first insulating part doped with ions and a second insulating part connected to the first insulating part. The signal line is located on the first insulating part.

Description

Circuit substrate and method of making the same

The present invention relates to a circuit substrate, and more particularly, to a stretchable circuit substrate and a method of making the same.

With the high development of electronic technology, electronic products are constantly innovating. In order to enable electronic products to be applied in various fields, the characteristics of stretchability, thinness and unrestricted appearance have gradually been paid more and more attention. That is to say, electronic products are gradually required to have different shapes according to different application methods and application environments, so electronic products need to be stretchable.

However, when the electronic product is stretched, it may cause structural fracture due to stress, and even further cause the internal circuit to be disconnected. Therefore, how to make stretchable electronic products have good manufacturing yield and product reliability is an urgent problem to be solved at present.

The invention provides a circuit substrate, which can improve the problem that the circuit substrate is broken due to expansion and contraction.

The present invention provides a method for manufacturing a circuit substrate, which can improve the problem that the circuit substrate is broken due to expansion and contraction.

At least one embodiment of the present invention provides a circuit substrate. The circuit substrate includes a patterned substrate, a patterned insulating structure and a signal line. The patterned insulating structure includes a plurality of device parts and a plurality of line parts. A plurality of device portions are located on the patterned substrate. A plurality of circuit parts are located on the patterned substrate and are connected to corresponding device parts. At least one line portion includes an ion-doped first insulating portion and a second insulating portion connected to the first insulating portion. The signal line is located on the first insulating part.

At least one embodiment of the present invention provides a method for manufacturing a circuit substrate, including: providing a substrate; forming an insulating structure on the substrate; forming a mask layer on the insulating structure; using the mask layer as a mask, performing a first step on the insulating structure Ion doping process; patterning the insulating structure to obtain the patterned insulating structure; forming signal lines on the substrate before or after patterning the insulating structure. The patterned insulating structure includes a plurality of device parts and a plurality of line parts. The line part is connected to the corresponding device part. At least one line portion includes a first insulating portion and a second insulating portion connected to the first insulating portion. The first insulating portion is ion-doped in the first ion-doping process. The signal line overlaps the first insulating portion.

1A to 1J are schematic cross-sectional views of a method for manufacturing a circuit substrate according to an embodiment of the present invention.

Referring to FIG. 1A , a substrate 100 is provided. The substrate 100 has elasticity and extensibility. In other words, the substrate 100 can be stretched. For example, in this embodiment, the material of the substrate 100 may include polyimide (PI), polyethylene naphthalate (PEN), polyethylene terephthalate (polyethylene terephthalate) ; PET), polycarbonate (polycarbonates; PC), polyether sulfone (PES) or polyarylate (polyarylate), other suitable materials or a combination of at least two of the foregoing materials, but the present invention does not This is limited.

The insulating structure 110 is formed on the substrate 100 . The insulating structure 110 is a single-layer or multi-layer structure. In this embodiment, the insulating structure 110 is a multi-layer structure, and includes a first insulating layer 112 , a second insulating layer 114 , a third insulating layer 116 and a fourth insulating layer 118 that are sequentially stacked upward from the substrate 100 . In this embodiment, the materials of the first insulating layer 112 and the third insulating layer 116 include silicon nitride, and the materials of the second insulating layer 114 and the fourth insulating layer 118 include silicon oxide. In other words, the insulating structure 110 includes a stacked layer of silicon nitride and silicon oxide.

Referring to FIG. 1B , a plurality of semiconductor layers 120 are formed on the insulating structure 110 . FIG. 1B only shows one of the semiconductor layers 120 , and the other semiconductor layers 120 on the insulating structure 110 are omitted. In this embodiment, the circuit substrate has a device region R1 and a bridge region R2, and the semiconductor layer 120 is formed in the device region R1.

The semiconductor layer 120 is a single-layer or multi-layer structure, which includes amorphous silicon, polysilicon, microcrystalline silicon, single crystal silicon, organic semiconductor materials, oxide semiconductor materials (for example: indium zinc oxide, indium gallium zinc oxide or other suitable materials, or a combination of the above) or other suitable materials or a combination of the above.

A gate insulating layer 130 is formed on the semiconductor layer 120 and the insulating structure 110 . The gate insulating layer 130 is, for example, an organic material or an inorganic material.

Referring to FIG. 1C , a plurality of shielding conductive layers G are formed on the semiconductor layer 120 . The gate insulating layer 130 is located between the shielding conductive layer G and the semiconductor layer 120 . In FIG. 1B , only one shielding conductive layer G is shown, and the shielding conductive layer G of the other semiconductor layer 120 on the gate insulating layer 130 is omitted. Each shielding conductive layer G overlaps the middle of the corresponding semiconductor layer 120 and does not overlap both ends of the corresponding semiconductor layer 120 .

A mask layer PR is formed on the insulating structure 110 . The mask layer PR is, for example, photoresist or other suitable materials. The mask layer PR has an opening O1 and an opening O2. The opening O1 and the opening O2 are located in the device region R1 and the bridging region R2, respectively. The opening O1 and the opening O2 expose the gate insulating layer 130 . The opening O1 overlaps the corresponding shielding conductive layer G and the corresponding semiconductor layer 120 . Viewed in a direction perpendicular to the substrate 100 , both ends of the semiconductor layer 120 are located between the sidewalls of the opening O1 and the shielding conductive layer G.

Using the mask layer PR and the mask conductive layer G as masks, a first ion doping process P1 is performed on the insulating structure 110 and the semiconductor layer 120 to form a plurality of doped regions 120a and 120b in the semiconductor layer 120, and the insulating structure 110 and the semiconductor layer 120 are subjected to a first ion doping process P1 A doped region 110a is formed in the structure 110 . The doped regions 120a and 120b overlap the gap between the mask layer PR and the mask conductive layer G, and the doped region 110a overlaps the opening O2 of the mask layer PR. In some embodiments, part of the insulating structure 110 overlaps the opening O1, and does not overlap the semiconductor layer 120, the mask layer PR, and the gate G. Therefore, after the first ion doping process P1 is performed, the insulating structure 110 overlaps the opening O1. Part of the insulating structure 110 has doped regions 110b and 110c, but the invention is not limited thereto. In other embodiments, the insulating structure 110 overlapping the opening O1 is covered by the semiconductor layer 120 , so the doped regions 110b and 110c overlapping the opening O1 are not formed in the insulating structure 110 .

In this embodiment, both the insulating structure 110 and the semiconductor layer 120 are doped in the first ion doping process P1 . Therefore, the first ion doping process P1 selects elements that can change the conductivity of the semiconductor layer 120 for doping , such as phosphorus, boron, or other materials suitable for doping. In other embodiments, the insulating structure 110 and the semiconductor layer 120 are doped in different processes. For example, the insulating structure 110 and the semiconductor layer 120 use different masks to perform an ion doping process, so the dopant (such as carbon, hydrogen, oxygen, nitrogen or other elements) used for doping the insulating structure 110 can be Different from the dopant used for doping the semiconductor layer 120 .

Referring to FIG. 1D , the masking conductive layer G is etched to form a gate G' on the semiconductor layer 120 . The size of the gate electrode G' is smaller than that of the shielding conductive layer G.

Referring to FIG. 1E , using the mask layer PR and the gate G′ as masks, a second ion doping process P2 is performed on the insulating structure 110 and the semiconductor layer 120 to form a plurality of doped regions 120 c , 120d. The doped regions 120c and 120d overlap the gap between the mask layer PR and the gate electrode G'. In some embodiments, the doping concentration of the doped regions 120c, 120d is less than the doping concentration of the doped regions 120a, 120b. In this embodiment, the second ion doping process P2 and the first ion doping process P1 use the same dopant for doping, such as phosphorus, boron or other materials suitable for doping. In this embodiment, both the second ion doping process P2 and the first ion doping process P1 use the mask layer PR as a mask, but the invention is not limited thereto. In other embodiments, before the second ion doping process P2 is performed, the mask layer PR is removed and other photoresist layers are formed as masks.

Referring to FIG. 1F , the mask layer PR is removed. An interlayer dielectric layer 140 is formed on the gate electrode G' and the gate insulating layer 130 . The interlayer dielectric layer 140 has a single-layer or multi-layer structure. In this embodiment, the interlayer dielectric layer 140 includes a first insulating layer 142 and a second insulating layer 144 stacked in sequence. The first insulating layer 142 includes silicon nitride, and the second insulating layer 144 includes silicon oxide, but the invention is not limited thereto.

Referring to FIG. 1G , the interlayer dielectric layer 140 and the gate insulating layer 130 are patterned to form openings H1 , H2 , H3 and H4 . The openings H1 , H2 and H3 penetrate through the interlayer dielectric layer 140 and the gate insulating layer 130 . The openings H1 and H2 respectively expose the doped regions 120a and 120b of the semiconductor layer 120 . The opening H3 exposes the insulating structure 110 . The opening H4 exposes the gate electrode G'.

In this embodiment, the gate insulating layer 130 and the interlayer dielectric layer 140 are patterned to form a plurality of gate insulating structures 130' and the interlayer dielectric structures 140'. The gate insulating structure 130' and the interlayer dielectric structure 140' are located in the device region R1 and between the gate G' and the semiconductor layer 120. In this embodiment, there is a gate insulating structure 130' between each gate G' and the corresponding semiconductor layer 120. The interlayer dielectric structure 140' includes a patterned first insulating layer 142' and a patterned second insulating layer 144'.

Referring to FIG. 1H , the insulating structure 110 is patterned. Part of the insulating structure 110 is removed to reduce the thickness of the part of the insulating structure 110 . In the present embodiment, the third insulating layer 116 and the fourth insulating layer 118 in the bridge region R2 are removed, and part of the third insulating layer 116 and the fourth insulating layer 118 in the device region R1 are removed. In this embodiment, after removing part of the insulating structure 110, the thickness of the doped region 110a is reduced.

Referring to FIG. 1I , signal lines 150 are formed on the substrate 100 . In this embodiment, the signal line 150 , the source electrode S, the drain electrode D and the transfer electrode TE are formed on the substrate 100 . The signal line 150, the source electrode S, the drain electrode D and the transfer electrode TE belong to the same film layer.

The source electrode S, the drain electrode D and the transfer electrode TE are formed in the device region R1. The source electrode S and the drain electrode D are respectively filled in the openings H1 and H2 and are electrically connected to the doped regions 120 a and 120 b of the semiconductor layer 120 , respectively. The transfer electrode TE fills the opening H4 and is electrically connected to the gate electrode G'.

The signal line 150 is formed in the bridge region R2. The signal line 150 overlaps the doped region 110 a of the thinned insulating structure 110 .

In some embodiments, the signal line L is selectively formed in the device region R1. The signal line L is a signal line for transmitting various electronic signals (eg gate signal line, data line or power line).

FIG. 2 is a schematic top view of a circuit substrate according to an embodiment of the present invention. FIG. 1J corresponds to the line A-A' in FIG. 2 , and FIG. 2 depicts the patterned insulating structure 110', the patterned substrate 100', the signal line 150 and a simplified active element, and other components are omitted.

1J and FIG. 2 , the thinned insulating structure 110 is patterned to form a plurality of first openings TH1 in the thinned part of the insulating structure 110 to obtain the patterned insulating structure 110'. The patterned insulating structure 110' includes a device portion TP and a wiring portion WP. The width W1 of the line portion WP is smaller than the width W2 of the device portion TP. The device portion TP and the line portion WP are located in the device region R1 and the line region R2, respectively. The line portion WP is connected to the corresponding device portion TP. In some embodiments, the patterned insulating structure 110' includes a stacked structure of silicon oxide and silicon nitride.

Each of the first openings TH1 is surrounded by the corresponding four device parts TP and the corresponding four wire parts WP. In this embodiment, part of the first openings TH1 extends along the first direction E1, and another part of the first openings TH1 extends along the second direction E2. Part of the first openings TH1 extending along the first direction E1 and another part of the first openings TH1 extending along the second direction E2 are alternately arranged, thereby improving the flexibility of the circuit substrate 10 . In the present embodiment, part of the wire portion WP extends along the first direction E1, and another portion of the wire portion WP extends along the second direction E2.

In this embodiment, the thickness X1 of the wiring portion WP is smaller than the thickness X2 of the device portion TP overlapping the semiconductor layer 120 , thereby improving the scalability of the circuit substrate 10 . In some embodiments, the thickness X1 of the wiring portion WP is 0.1 μm to 3 μm, and the thickness X2 of the device portion TP overlapping the semiconductor layer 120 is 0.1 μm to 5 μm.

At least one wire portion WP includes an ion-doped first insulating portion WPa and a second insulating portion WPb connected to the first insulating portion WPa. In this embodiment, the first insulating portion WPa is ion-doped in the first ion doping process, and the first insulating portion WPa is equal to the doped region 110a. In other embodiments, since part of the doped region 110a is removed when the insulating structure 110 is patterned to obtain the patterned insulating structure 110', the size of the first insulating portion WPa may be smaller than that of the doped region 110a.

The first insulating portion WPa is ion-doped (eg, the first ion doping process and/or the second ion doping process) to increase at least one chemical element (eg, phosphorus, boron, carbon, hydrogen, oxygen) in the first insulating portion WPa , nitrogen or other elements), the concentration of the aforementioned chemical element in the first insulating portion WPa is greater than that of the aforementioned chemical element in the second insulating portion WPb by an order of magnitude or more. In some embodiments, the first insulating portion WPa is doped with the aforementioned chemical elements, and the second insulating portion WPb does not contain the aforementioned chemical elements. In some embodiments, the concentration of the aforementioned chemical elements in the first insulating portion WPa ranges from 1E16 cm ⁻³ to 1E24 cm ⁻³ , and the concentration of the aforementioned chemical elements in the second insulating portion WPb ranges from 1E15 cm ⁻³ to 1E15 cm −3 . 1E23 cm ^-3 .

The signal line 150 overlaps the first insulating portion WPa. In some embodiments, part of the signal lines 150 extend along the first direction E1, and another part of the signal lines 150 extend along the second direction E2. The signal line 150 extending along the first direction E1 is located on the line portion WP extending along the first direction E1. The signal line 150 extending along the second direction E2 is located on the line portion WP extending along the second direction E2. In this embodiment, one or more than two signal lines 150 are disposed on each line portion WP.

In some embodiments, since the first insulating portion WPa is doped (eg, doped with phosphorus, boron, carbon, nitrogen, oxygen, or a combination of the foregoing), the first insulating portion WPa has residual compressive stress, and Tensile stress remains in the second insulating portion WPb. In this embodiment, the first insulating portion WPa is closer to the long side of the first opening TH1 than the second insulating portion WPb, thereby preventing the signal line 150 on the first insulating portion WPa from being broken due to the stretching F. question.

In this embodiment, the signal line 150 , the signal line L, the source electrode S, the drain electrode D and the transfer electrode TE are formed before the patterned insulating structure 110 is formed to form the patterned insulating structure 110 ′, but this is not the case in the present invention limit. In other embodiments, the signal line 150, the signal line L, the source electrode S, the drain electrode D, and the transfer electrode TE are formed after the patterning of the insulating structure 110 to form the patterned insulating structure 110'.

A dielectric layer IL, an organic light emitting diode OLED, a patterned planarization layer PL, a pixel definition layer PDL, a blocking member DAM and an insulating structure OBP are formed on the substrate 100 .

The dielectric layer IL covers the device portion TP. The patterned planarization layer PL covers the device portion TP and the line portion WP. In this embodiment, the patterned planarization layer PL fills the first opening TH1 and contacts the sidewall of the device portion TP and the sidewall of the line portion WP. The material of the patterned planarization layer PL includes organic insulating materials or other suitable materials.

The active elements are located on the device portion TP, and each active element includes a semiconductor layer 120, a source electrode S, a drain electrode D, and a gate electrode G'. In other words, the semiconductor layer 120, the source electrode S, the drain electrode D, and the gate electrode G' are located on the device portion TP. In this embodiment, the semiconductor layer 120 and the first insulating portion WPa of the wiring portion WP include the same ion-doped material (eg, phosphorus, boron, or a combination of the foregoing materials).

An organic light emitting diode OLED or other display element is located on the device portion TP. The organic light emitting diode OLED includes a first electrode ET1, an organic light emitting semiconductor SM, and a second electrode ET2 that are sequentially stacked.

The pixel definition layer PDL and the insulating structure OBP are located on the patterned planarization layer PL. The blocking member DAM is located on the dielectric layer IL. In some embodiments, the pixel definition layer PDL, the blocking member DAM and the insulating structure OBP are formed in the same process, but the invention is not limited thereto.

A patterning process is performed on the substrate 100 to form a patterned substrate 100'. The patterned substrate 100' includes a plurality of second openings TH2. The second opening TH2 overlaps the first opening TH1. The size of the second opening TH2 is smaller than that of the first opening TH1 . In this embodiment, part of the second opening TH2 extends along the first direction E1, and another part of the second opening TH2 extends along the second direction E2. Part of the second openings TH2 extending along the first direction E1 and another part of the second openings TH2 extending along the second direction E2 are alternately arranged, thereby improving the flexibility of the circuit substrate 10 .

In this embodiment, each device portion TP may include one or more active elements and an organic light emitting diode OLED. For example, each device portion TP includes a red organic light emitting diode, a green organic light emitting diode, and a blue organic light emitting diode, so that each device portion TP has one pixel. In other embodiments, the device portion TP has inorganic light emitting diodes - or other forms of display elements thereon. In other embodiments, the device portion TP has other electronic components on it.

Based on the above, in this embodiment, the line portion WP includes the ion-doped first insulating portion WPa and the second insulating portion WPb connected to the first insulating portion WPa, and the signal line 150 is located on the first insulating portion WPa, so , the problem that the signal line 150 is broken due to stretching F can be avoided.

3 is a schematic top view of a circuit substrate according to an embodiment of the present invention. It must be noted here that the embodiment of FIG. 3 uses the element numbers and part of the content of the embodiment of FIG. 2 , wherein the same or similar numbers are used to represent the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted part, reference may be made to the foregoing embodiments, which will not be repeated here.

The difference between the circuit substrate 20 of FIG. 3 and the circuit substrate 10 of FIG. 2 is that each line portion WP of the circuit substrate 10 includes the first insulating portion WPa, while the circuit substrate 20 has only the line portion extending along the first direction E1 WP includes the first insulating portion WPa.

Referring to FIG. 3 , in this embodiment, an ion doping process is performed on the line portion WP extending along the first direction E1 , so that the line portion WP extending along the first direction E1 includes the line portion WP extending along the first direction E1 The ion-doped first insulating portion WPa and the ion-doped second insulating portion WPb.

In this embodiment, the first insulating portion WPa extending along the first direction E1 helps to avoid the signal lines 150 extending along the first direction E1 caused by the stretching F of the circuit substrate 20 parallel to the first direction E1 There is a breakage problem.

In this embodiment, the ion doping process is performed on each line portion WP extending along the first direction E1, but the invention is not limited thereto. In other embodiments, the ion doping process is performed on one or more wire portions WP extending along the first direction E1.

4 is a schematic top view of a circuit substrate according to an embodiment of the present invention. It must be noted here that the embodiment of FIG. 4 uses the element numbers and part of the content of the embodiment of FIG. 2 , wherein the same or similar numbers are used to represent the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted part, reference may be made to the foregoing embodiments, which will not be repeated here.

The difference between the circuit substrate 30 of FIG. 4 and the circuit substrate 10 of FIG. 2 is that each line portion WP of the circuit substrate 10 includes the first insulating portion WPa, while the circuit substrate 30 has only the line portion extending along the second direction E2 WP includes the first insulating portion WPa.

Referring to FIG. 4 , in this embodiment, an ion doping process is performed on the line portion WP extending along the second direction E2 , so that the line portion WP extending along the second direction E2 includes the line portion WP extending along the second direction E2 The ion-doped first insulating portion WPa and the ion-doped second insulating portion WPb.

In this embodiment, the first insulating portion WPa extending along the second direction E2 helps to avoid the signal line 150 extending along the second direction E2 caused by the stretching F of the circuit substrate 30 parallel to the second direction E2 There is a breakage problem.

In this embodiment, the ion doping process is performed on each line portion WP extending along the second direction E2, but the invention is not limited thereto. In other embodiments, the ion doping process is performed on one or more wire portions WP extending along the second direction E2.

5 is a schematic top view of a circuit substrate according to an embodiment of the present invention. It must be noted here that the embodiment of FIG. 5 uses the element numbers and part of the content of the embodiment of FIG. 2 , wherein the same or similar numbers are used to represent the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted part, reference may be made to the foregoing embodiments, which will not be repeated here.

The difference between the circuit substrate 40 of FIG. 5 and the circuit substrate 10 of FIG. 2 is that the circuit substrate 40 further includes a plurality of reinforcing structures 200 .

The reinforcement structure 200 is disposed on the second insulating portion WPb of the wiring portion WP and is spaced apart from the signal line 150 . In some embodiments, the reinforcing structure 200 can be adjusted at the neutral axis position of the wiring portion WP to reduce the risk of disconnection of the signal line 150 due to stretching. In addition, since the reinforcement structure 200 is separated from the signal line 150 , even if a crack occurs in the reinforcement structure 200 , the crack is not easily extended to the signal line 150 , causing the signal line 150 to be disconnected. In some embodiments, the reinforcement structure 200 may be a spare wire.

To sum up, the circuit portion of the patterned insulating structure of the present invention includes a first insulating portion doped with ions and a second insulating portion connected to the first insulating portion, and the signal line is located on the first insulating portion. Therefore, it can be Avoid the problem of breakage of the signal line due to stretching.

10, 20, 30, 40: circuit substrate 100: base 110: Insulation structure 110': Patterned insulating structure 110a, 110b, 110c, 120a, 120b, 120c, 120d: doped regions 112: first insulating layer 114: Second insulating layer 116: The third insulating layer 118: Fourth insulating layer 120: Semiconductor layer 130: gate insulating layer 130': gate insulation structure 140: Interlayer dielectric layer 140': Interlayer Dielectric Structure 142, 142': the first insulating layer 144, 144': the second insulating layer 150: Signal line 200: Strengthen the structure D: drain DAM: Blocker E1: first direction E2: Second direction ET1: first electrode ET2: Second electrode F: stretch G: shielding conductive layer G': gate H1, H2, H3, H4: Opening IL: Dielectric Layer L: signal line OBP: insulating structure OLED: Organic Light Emitting Diode PDL: Pixel Definition Layer PL: Patterned planarization layer PR: mask layer R1: Device area R2: Bridging area S: source SM: Organic Light Emitting Semiconductor TE: transfer electrode TH1: The first opening TH2: The second opening TP: Device Department W1, W2: width WP: Line Department WPa: Second insulating part WPb: Second insulating part X1, X2: Thickness

1A to 1J are schematic cross-sectional views of a method for manufacturing a circuit substrate according to an embodiment of the present invention. FIG. 2 is a schematic top view of a circuit substrate according to an embodiment of the present invention. 3 is a schematic top view of a circuit substrate according to an embodiment of the present invention. 4 is a schematic top view of a circuit substrate according to an embodiment of the present invention. 5 is a schematic top view of a circuit substrate according to an embodiment of the present invention.

10: circuit substrate

100: base

110': Patterned insulating structure

110b, 110c, 120a, 120b, 120c, 120d: doped regions

112: first insulating layer

114: Second insulating layer

116: The third insulating layer

118: Fourth insulating layer

120: Semiconductor layer

130': gate insulation structure

140': Interlayer Dielectric Structure

142': first insulating layer

144': Second insulating layer

150: Signal line

D: drain

DAM: Blocker

ET1: first electrode

ET2: Second electrode

G': gate

IL: Dielectric Layer

L: signal line

OBP: insulating structure

OLED: Organic Light Emitting Diode

PDL: Pixel Definition Layer

PL: Patterned planarization layer

R1: Device area

R2: Bridging area

S: source

SM: Organic Light Emitting Semiconductor

TE: transfer electrode

TH1: The first opening

TH2: The second opening

TP: Device Department

WP: Line Department

WPa: Second insulating part

WPb: Second insulating part

X1, X2: Thickness

Claims (17)

A circuit substrate, comprising: a patterned substrate; A patterned insulating structure, comprising: a plurality of device portions on the patterned substrate; and a plurality of circuit parts located on the patterned substrate and connected to the corresponding device parts, wherein at least one of the circuit parts includes a first insulating part doped with ions and a second insulating part connected to the first insulating part Department; and A signal line is located on the first insulating part. The circuit substrate of claim 1, wherein the first insulating portion is ion-doped to increase the concentration of at least one chemical element in the first insulating portion, and the concentration of the chemical element in the first insulating portion is greater than that of the chemical element The concentration of the element in the second insulating portion is one order of magnitude or more. The circuit substrate of claim 1, wherein the first insulating portion is doped with a chemical element, and the second insulating portion does not contain the chemical element. The circuit substrate of claim 1, wherein the widths of the circuit portions are smaller than the widths of the device portions, and the patterned insulating structure comprises a plurality of first openings, and each of the first openings is corresponding to four The device parts and the corresponding four circuit parts are surrounded. The circuit substrate of claim 4, wherein the first insulating portion is closer to the long sides of the first openings than the second insulating portion. The circuit substrate of claim 4, a part of the first openings extend along a first direction, and another part of the first openings extend along a second direction, wherein the first openings extend along the first direction A part of the first openings and another part of the first openings extending along the second direction are alternately arranged. The circuit substrate according to claim 1, further comprising: a plurality of semiconductor layers located on the device portions, wherein the semiconductor layers and the first insulating portion of the circuit portions comprise the same ion dopant material; a plurality of gate electrodes, overlapping the semiconductor layers; a plurality of gate insulating structures located between the gate electrodes and the semiconductor layers; and A plurality of source electrodes and a plurality of drain electrodes are electrically connected to the semiconductor layers. The circuit substrate of claim 1, wherein the patterned insulating structure comprises a stacked structure of silicon oxide and silicon nitride. The circuit substrate of claim 1, wherein the first insulating portion is doped with phosphorus, boron, carbon, nitrogen, oxygen, or a combination of the foregoing materials. The circuit substrate of claim 1, wherein the first insulating portion has residual compressive stress. The circuit substrate of claim 1, wherein the thickness of the circuit parts is smaller than the thickness of the device parts. The circuit substrate of claim 1, further comprising a reinforcing structure disposed on the second insulating portion. A manufacturing method of a circuit substrate, comprising: provide a base; forming an insulating structure on the substrate; forming a mask layer on the insulating structure; using the mask layer as a mask, performing a first ion doping process on the insulating structure; The insulating structure is patterned to obtain a patterned insulating structure, and the patterned insulating structure includes: a plurality of device sections; and A plurality of circuit parts are connected to the corresponding device parts, and at least one of the circuit parts includes a first insulating part and a second insulating part connected to the first insulating part, wherein the first insulating part is in the first insulating part. ion-doped during the doping process; and A signal line is formed on the substrate before or after patterning the insulating structure, wherein the signal line overlaps the first insulating portion. The method for manufacturing a circuit substrate as claimed in claim 13, further comprising: forming a plurality of semiconductor layers on the insulating structure; forming a gate insulating layer on the semiconductor layers and the insulating structure; forming a plurality of shielding conductive layers on the semiconductor layers, wherein each shielding conductive layer overlaps the middle of the corresponding semiconductor layer; Using the mask layer and the masking conductive layers as masks, the first ion doping process is performed on the insulating structure and the semiconductor layers to form a plurality of doped regions in the semiconductor layers. The method for manufacturing a circuit substrate as claimed in claim 14, further comprising: etching the shielding conductive layers to form the gates on the semiconductor layers, wherein each of the gates overlaps the middle of the corresponding semiconductor layer; and A second ion doping process is performed on the semiconductor layers by using the mask layer and the gates as masks. The method for manufacturing a circuit substrate as claimed in claim 14, further comprising: The gate insulating layer is patterned to form a plurality of gate insulating structures, the gate insulating structures are located between the gates and the semiconductor layers. The method for manufacturing a circuit substrate as claimed in claim 14, wherein the method for patterning the insulating structure comprises: removing a portion of the insulating structure to reduce the thickness of a portion of the insulating structure; and A plurality of first openings are formed in the thinned part of the insulating structure to form the device parts and the circuit parts, wherein each of the first openings is corresponding to four of the device parts and the corresponding four parts. Each of the circuit portions is surrounded, and the thickness of the circuit portions is smaller than the thickness of the device portions overlapping the semiconductor layers.

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