CN113838864B - Circuit substrate and method for manufacturing the same - Google Patents
Circuit substrate and method for manufacturing the same Download PDFInfo
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- CN113838864B CN113838864B CN202110771734.XA CN202110771734A CN113838864B CN 113838864 B CN113838864 B CN 113838864B CN 202110771734 A CN202110771734 A CN 202110771734A CN 113838864 B CN113838864 B CN 113838864B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
- H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/124—Insulating layers formed between TFT elements and OLED elements
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
Abstract
A circuit substrate and a manufacturing method thereof are provided, wherein the circuit substrate comprises a patterned substrate, a patterned insulating structure and a signal line. The patterned insulating structure comprises a plurality of device parts and a plurality of circuit parts. A plurality of device sites are located on the patterned substrate. The circuit parts are positioned on the patterned substrate and connected with the corresponding device parts. At least one of the line portions includes an ion doped first insulating portion and a second insulating portion connected to the first insulating portion. The plurality of signal lines are located on the first insulating portion.
Description
Technical Field
The present invention relates to a circuit substrate, and more particularly, to a scalable circuit substrate and a method of manufacturing the same.
Background
With the high development of electronic technology, electronic products are continuously promoted to be new. In order to make the electronic product applicable to various fields, the characteristics of being stretchable, light and thin and having an unlimited shape are increasingly paid attention to. That is, electronic products are increasingly required to have different shapes according to different application modes and application environments, so the electronic products need to have stretchability.
However, in the stretched state, the electronic product may be broken structurally due to the stress, and even further cause the disconnection of the internal circuit. Therefore, how to provide stretchable electronic products with good manufacturing yield (yield) and product reliability (reliability) is an urgent issue.
Disclosure of Invention
The invention provides a circuit substrate, which can solve the problem that the circuit substrate breaks due to expansion and contraction.
The invention provides a manufacturing method of a circuit substrate, which can solve the problem that the circuit substrate breaks due to stretching.
At least one embodiment of the present invention provides a circuit substrate. The circuit substrate comprises a patterned substrate, a patterned insulating structure and a signal line. The patterned insulating structure comprises a plurality of device parts and a plurality of circuit parts. A plurality of device sites are located on the patterned substrate. The circuit parts are positioned on the patterned substrate and connected with the corresponding device parts. At least one of the line portions includes an ion doped first insulating portion and a second insulating portion connected to the first insulating portion. The signal line is located on the first insulating portion.
At least one embodiment of the present invention provides a method for manufacturing a circuit substrate, including: providing a substrate; forming an insulating structure on the substrate; forming a mask layer on the insulating structure; performing a first ion doping process on the insulating structure by taking the mask layer as a mask; patterning the insulating structure to obtain a patterned insulating structure; signal lines are formed on the substrate before or after patterning the insulating structure. The patterned insulating structure comprises a plurality of device parts and a plurality of circuit parts. The circuit portion is connected with the corresponding device portion. At least one of the line portions includes a first insulating portion and a second insulating portion connected to the first insulating portion. The first insulating portion is ion doped in a first ion doping process. The signal line overlaps the first insulating portion.
Drawings
Fig. 1A to 1J are schematic cross-sectional views illustrating a method for manufacturing a circuit substrate according to an embodiment of the invention.
Fig. 2 is a top view of a circuit substrate according to an embodiment of the invention.
Fig. 3 is a top view of a circuit substrate according to an embodiment of the invention.
Fig. 4 is a top view of a circuit substrate according to an embodiment of the invention.
Fig. 5 is a top view of a circuit substrate according to an embodiment of the invention.
Reference numerals illustrate:
10. 20, 30, 40: circuit substrate
100: substrate
110: insulation structure
110': patterned insulation structure
110a, 110b, 110c, 120a, 120b, 120c, 120d: doped region
112: a first insulating layer
114: second insulating layer
116: third insulating layer
118: fourth insulating layer
120: semiconductor layer
130: gate insulating layer
130': gate insulation structure
140: interlayer dielectric layer
140': interlayer dielectric structure
142. 142': a first insulating layer
144. 144': second insulating layer
150: signal line
200: reinforcing structure
D: drain electrode
DAM: barrier element
E1: first direction
E2: second direction
ET1: first electrode
ET2: second electrode
F: stretching
G: masking conductive layer
G': grid electrode
H1, H2, H3, H4: an opening
IL: dielectric layer
L: signal line
OBP: insulation structure
OLED: organic light emitting diode
PDL: pixel definition layer
PL: patterning planarization layer
PR: mask layer
R1: device area
R2: bridging region
S: source electrode
SM: organic light-emitting semiconductor
TE: switching electrode
TH1: first open hole
TH2: second open hole
TP: device part
W1, W2: width of (L)
WP: line part
WPa: second insulating part
WPb: second insulating part
X1 and X2: thickness of (L)
Detailed Description
Fig. 1A to 1J are schematic cross-sectional views illustrating a method for manufacturing a circuit substrate according to an embodiment of the invention.
Referring to fig. 1A, a substrate 100 is provided. The substrate 100 is elastic and extensible. In other words, the substrate 100 may be stretchable. For example, in the present embodiment, the material of the substrate 100 may include Polyimide (PI), polyethylene naphthalate (polyethylene naphthalate; PEN), polyethylene terephthalate (polyethylene terephthalate; PET), polycarbonate (PC), polyethersulfone (polyether sulfone; PES) or polyarylate (polyarylate), other suitable materials, or a combination of at least two of the foregoing materials, but the present invention is not limited thereto.
An insulating structure 110 is formed on the substrate 100. The insulating structure 110 is a single-layer or multi-layer structure. In the present embodiment, the insulating structure 110 is a multi-layer structure, and includes a first insulating layer 112, a second insulating layer 114, a third insulating layer 116, and a fourth insulating layer 118 stacked in order from the substrate 100. In the present embodiment, the materials of the first insulating layer 112 and the third insulating layer 116 include silicon nitride, and the materials of the second insulating layer 114 and the fourth insulating layer 118 include silicon oxide. In other words, the insulating structure 110 includes a stacked layer of silicon nitride and silicon oxide.
Referring to fig. 1B, a plurality of semiconductor layers 120 are formed on the insulating structure 110. Fig. 1B is illustrated with only one of the semiconductor layers 120, and omits to depict the other semiconductor layers 120 on the insulating structure 110. In the present embodiment, the circuit substrate has a device region R1 and a bridge region R2, and the semiconductor layer 120 is formed on the device region R1.
The semiconductor layer 120 is a single-layer or multi-layer structure comprising amorphous silicon, polycrystalline silicon, microcrystalline silicon, single crystal silicon, organic semiconductor material, oxide semiconductor material (e.g., indium zinc oxide, indium gallium zinc oxide, or other suitable materials, or combinations thereof), or other suitable materials or combinations thereof.
A gate insulating layer 130 is formed on the semiconductor layer 120 and the insulating structure 110. The gate insulating layer 130 is, for example, an organic material or an inorganic material.
Referring to fig. 1C, a plurality of shielding conductive layers G are formed on the semiconductor layer 120. The gate insulating layer 130 is located between the shielding conductive layer G and the semiconductor layer 120. Fig. 1B is illustrated with only one of the shielding conductive layers G, and the shielding conductive layer G of the other semiconductor layer 120 on the gate insulating layer 130 is omitted. Each shielding conductive layer G overlaps with the middle of the corresponding semiconductor layer 120 and does not overlap with both ends of the corresponding semiconductor layer 120.
A mask layer PR is formed on the insulating structure 110. The mask layer PR is, for example, photoresist or other suitable material. The mask layer PR has an opening O1 and an opening O2. The opening O1 and the opening O2 are located in the device region R1 and the bridge region R2, respectively. The opening O1 and the opening O2 expose the gate insulating layer 130. The opening O1 overlaps the corresponding shielding conductive layer G and the corresponding semiconductor layer 120, and both ends of the semiconductor layer 120 are located between the sidewalls of the opening O1 and the sidewalls of the shielding conductive layer G, as viewed in a direction perpendicular to the substrate 100.
The first ion doping process P1 is performed on the insulating structure 110 and the semiconductor layer 120 with the mask layer PR and the shielding conductive layer G as masks, so as to form a plurality of doped regions 120a and 120b in the semiconductor layer 120, and form a doped region 110a in the insulating structure 110. The doped regions 120a and 120b overlap the gap between the mask layer PR and the shielding conductive layer G, and the doped region 110a overlaps the opening O2 of the mask layer PR. In some embodiments, the portion of the insulating structure 110 overlaps the opening O1 and does not overlap the semiconductor layer 120, the mask layer PR and the gate G, so after the first ion doping process P1 is performed, the portion of the insulating structure 110 overlapping the opening O1 has doped regions 110b and 110c, but the invention is not limited thereto. In other embodiments, the insulating structure 110 overlapping the opening O1 is covered by the semiconductor layer 120, so that the doped regions 110b and 110c overlapping the opening O1 are not formed in the insulating structure 110.
In the present embodiment, the insulating structure 110 and the semiconductor layer 120 are doped in the first ion doping process P1, and thus the first ion doping process P1 is doped with an element capable of changing the conductive property of the semiconductor layer 120, such as phosphorus, boron or other materials suitable for doping. In other embodiments, the insulating structure 110 and the semiconductor layer 120 are doped in different processes. For example, the insulating structure 110 and the semiconductor layer 120 are subjected to an ion doping process using a different mask, so that the dopant (e.g., carbon, hydrogen, oxygen, nitrogen, or other elements) used for doping the insulating structure 110 may be different from the dopant used for doping the semiconductor layer 120.
Referring to fig. 1D, the shielding conductive layer G is etched to form a gate G' on the semiconductor layer 120. The size of the gate electrode G' is smaller than the shielding conductive layer G.
Referring to fig. 1E, a second ion doping process P2 is performed on the insulating structure 110 and the semiconductor layer 120 with the mask layer PR and the gate G' as masks, so as to form a plurality of doped regions 120c and 120d in the semiconductor layer 120. The doped regions 120c, 120d overlap the gap between the mask layer PR and the gate G'. In some embodiments, the doping concentration of the doped regions 120c, 120d is less than the doping concentration of the doped regions 120a, 120b. In this embodiment, the second ion doping process P2 and the first ion doping process P1 use the same dopant for doping, such as phosphorus, boron or other materials suitable for doping. In the embodiment, the second ion doping process P2 and the first ion doping process P1 both use the mask layer PR as a mask, but the invention is not limited thereto. In other embodiments, the mask layer PR is removed and other photoresist layers are formed as a mask before the second ion doping process P2 is performed.
Referring to fig. 1F, the mask layer PR is removed. An interlayer dielectric layer 140 is formed on the gate electrode G' and the gate insulating layer 130. The interlayer dielectric layer 140 has a single-layer or multi-layer structure. In this embodiment, the interlayer dielectric layer 140 includes a first insulating layer 142 and a second insulating layer 144 stacked in order. The first insulating layer 142 includes silicon nitride, and the second insulating layer 144 includes silicon oxide, but the invention is not limited thereto.
Referring to fig. 1G, the interlayer dielectric layer 140 and the gate insulating layer 130 are patterned to form openings H1, H2, H3, and H4. The openings H1, H2, H3 penetrate the interlayer dielectric 140 and the gate insulating layer 130. The openings H1, H2 expose the doped regions 120a, 120b of the semiconductor layer 120, respectively. The opening H3 exposes the insulating structure 110. The opening H4 exposes the gate G'.
In the present embodiment, the gate insulating layer 130 and the interlayer dielectric layer 140 are patterned to form a plurality of gate insulating structures 130 'and interlayer dielectric structures 140'. The gate insulating structure 130' and the interlayer dielectric structure 140' are located in the device region R1 and between the gate G ' and the semiconductor layer 120. In this embodiment, there is a gate insulating structure 130 'between each gate G' and the corresponding semiconductor layer 120. The interlayer dielectric structure 140' includes a patterned first insulating layer 142' and a patterned second insulating layer 144'.
Referring to fig. 1H, an insulating structure 110 is patterned. A portion of the insulating structure 110 is removed to thin the thickness of the portion of the insulating structure 110. In the present embodiment, the third insulating layer 116 and the fourth insulating layer 118 in the bridge region R2 are removed, and portions of the third insulating layer 116 and the fourth insulating layer 118 in the device region R1 are removed. In this embodiment, after removing a portion of the insulating structure 110, the thickness of the doped region 110a is reduced.
Referring to fig. 1I, a signal line 150 is formed on a substrate 100. In this embodiment, the signal line 150, the source electrode S, the drain electrode D, and the transfer electrode TE are formed on the substrate 100. The signal line 150, the source electrode S, the drain electrode D, and the transfer electrode TE are all of the same layer.
The source S, the drain D, and the transfer electrode TE are formed in the device region R1. The source S and the drain D are filled into the openings H1 and H2, respectively, and are electrically connected to the doped regions 120a and 120b of the semiconductor layer 120, respectively. The transfer electrode TE fills the opening H4 and is electrically connected to the gate G'.
The signal line 150 is formed in the bridge region R2. The signal line 150 overlaps the doped region 110a of the thinned insulating structure 110.
In some embodiments, the signal line L is selectively formed in the device region R1. The signal line L is a signal line (e.g., a gate signal line, a data line, or a power line) that transmits various electronic signals.
Fig. 2 is a top view of a circuit substrate according to an embodiment of the invention. Fig. 1J corresponds to the line A-A ' of fig. 2, and fig. 2 depicts the patterned insulating structure 110', the patterned substrate 100', the signal line 150, and the simplified active element, and other components are omitted from illustration.
Referring to fig. 1J and fig. 2, the thinned insulating structure 110 is patterned to form a plurality of first openings TH1 in the thinned portion of the insulating structure 110, so as to obtain a patterned insulating structure 110'. The patterned insulating structure 110' includes a device portion TP and a wire portion WP. The width W1 of the wiring portion WP is smaller than the width W2 of the device portion TP. The device portion TP and the wiring portion WP are located in the device region R1 and the wiring region R2, respectively. The wiring portion WP is connected to the corresponding device portion TP. In some embodiments, the patterned insulating structure 110' includes a stacked structure of silicon oxide and silicon nitride.
Each first opening TH1 is surrounded by the corresponding four device portions TP and the corresponding four wiring portions WP. In the present embodiment, a portion of the first openings TH1 extends along the first direction E1, and another portion of the first openings TH1 extends along the second direction E2. The portion of the first openings TH1 extending along the first direction E1 and the other portion of the first openings TH1 extending along the second direction E2 are alternately arranged, thereby improving the stretchability of the circuit substrate 10. In the present embodiment, a part of the wiring portion WP extends along the first direction E1, and another part of the wiring portion WP extends along the second direction E2.
In the present embodiment, the thickness X1 of the wiring portion WP is smaller than the thickness X2 of the device portion TP overlapped with the semiconductor layer 120, thereby improving the scalability of the circuit substrate 10. In some embodiments, the thickness X1 of the wiring portion WP is 0.1 to 3 micrometers, and the thickness X2 of the device portion TP overlapped with the semiconductor layer 120 is 0.1 to 5 micrometers.
At least one wire portion WP includes an ion-doped first insulation portion WPa and a second insulation portion WPb connected to the first insulation portion WPa. In the present embodiment, the first insulation portion WPa is ion-doped in the first ion doping process, and the first insulation portion WPa is equal to the doped region 110a. In other embodiments, the first insulation portion WPa may be smaller in size than the doped region 110a because the partially doped region 110a is removed when the insulation structure 110 is patterned to obtain the patterned insulation structure 110'.
The first insulation portion WPa is ion doped (e.g., a first ion doping process and/or a second ion doping process) to increase a concentration of at least one chemical element (e.g., phosphorus, boron, carbon, hydrogen, oxygen, nitrogen, or other element) in the first insulation portion WPa, the concentration of the chemical element in the first insulation portion WPa being greater than the concentration of the chemical element in the second insulation portion WPb by more than an order of magnitude. In some embodiments, the first insulation portion WPa is doped with the aforementioned chemical elements, and the second insulation portion WPb does not include the aforementioned chemical elements. In some embodiments, the concentration of the chemical element in the first insulating portion WPa is between 1E16 cm -3 To 1E24 cm -3 And the concentration of the chemical element in the second insulation part WPb is 1E15 cm -3 To 1E23 cm -3 。
The signal line 150 overlaps the first insulating portion WPa. In some embodiments, a portion of the signal lines 150 extend along a first direction E1, and another portion of the signal lines 150 extend along a second direction E2. The signal line 150 extending along the first direction E1 is located on the wiring portion WP extending along the first direction E1. The signal line 150 extending along the second direction E2 is located on the wiring portion WP extending along the second direction E2. In the present embodiment, one or two or more signal lines 150 are provided for each wiring portion WP.
In some embodiments, since the first insulation portion WPa is doped (e.g., via phosphorus, boron, carbon, nitrogen, oxygen, or a combination of the foregoing materials), the first insulation portion WPa remains under compressive stress and the second insulation portion WPb remains under tensile stress. In the present embodiment, the first insulation portion WPa is closer to the long side of the first opening TH1 than the second insulation portion WPb, thereby avoiding the problem that the signal line 150 on the first insulation portion WPa breaks due to the stretching F.
In the present embodiment, the signal line 150, the signal line L, the source S, the drain D, and the transfer electrode TE are formed before the insulating structure 110 is patterned to form the patterned insulating structure 110', but the invention is not limited thereto. In other embodiments, the signal line 150, the signal line L, the source S, the drain D, and the transfer electrode TE are formed after patterning the insulating structure 110 to form the patterned insulating structure 110'.
A dielectric layer IL, an organic light emitting diode OLED, a patterned planarization layer PL, a pixel definition layer PDL, a barrier DAM, and an insulating structure OBP are formed on the substrate 100.
The dielectric layer IL covers the device portion TP. The patterned planarization layer PL covers the device portion TP and the wiring portion WP. In the present embodiment, the patterned planarization layer PL fills the first opening TH1 and contacts the sidewall of the device portion TP and the sidewall of the wiring portion WP. The material of the patterned planarization layer PL includes an organic insulating material or other suitable material.
The active devices are located on the device portion TP, and each active device includes a semiconductor layer 120, a source S, a drain D, and a gate G'. In other words, the semiconductor layer 120, the source electrode S, the drain electrode D, and the gate electrode G' are located on the device portion TP. In this embodiment, the semiconductor layer 120 includes the same ion-doped material (e.g., phosphorus, boron, or a combination of the foregoing materials) as the first insulating portion WPa of the wire portion WP.
An organic light emitting diode OLED or other display element is located on the device portion TP. The organic light emitting diode OLED includes a first electrode ET1, an organic light emitting semiconductor SM, and a second electrode ET2, which are sequentially stacked.
The pixel definition layer PDL and the insulating structure OBP are located on the patterned planarization layer PL. The barrier DAM is located on the dielectric layer IL. In some embodiments, the pixel defining layer PDL, the barrier DAM and the insulating structure OBP are formed in the same process, but the invention is not limited thereto.
A patterning process is performed on the substrate 100 to form a patterned substrate 100'. The patterned substrate 100' includes a plurality of second openings TH2. The second openings TH2 overlap the first openings TH1. The second openings TH2 have a smaller size than the first openings TH1. In the present embodiment, a portion of the second openings TH2 extends along the first direction E1, and another portion of the second openings TH2 extends along the second direction E2. The portion of the second openings TH2 extending along the first direction E1 and the other portion of the second openings TH2 extending along the second direction E2 are alternately arranged, thereby improving the stretchability of the circuit substrate 10.
In this embodiment, each device portion TP may include one or more active devices and an organic light emitting diode OLED. For example, each device portion TP includes a red organic light emitting diode, a green organic light emitting diode, and a blue organic light emitting diode, so that each device portion TP has one pixel thereon. In other embodiments, the device portion TP has an inorganic light emitting diode-or other form of display element thereon. In other embodiments, the device portion TP has other electronic components thereon.
Based on the above, in the present embodiment, the wiring portion WP includes the ion doped first insulation portion WPa and the second insulation portion WPb connected to the first insulation portion WPa, and the signal line 150 is located on the first insulation portion WPa, so that the problem of breakage of the signal line 150 due to the stretching F can be avoided.
Fig. 3 is a top view of a circuit substrate according to an embodiment of the invention. It should be noted that the embodiment of fig. 3 uses the element numbers and part of the content of the embodiment of fig. 2, where the same or similar numbers are used to denote the same or similar elements, and the description of the same technical content is omitted. Reference may be made to the foregoing embodiments for description of omitted parts, which are not repeated here.
The circuit substrate 20 of fig. 3 differs from the circuit substrate 10 of fig. 2 in that: each of the wiring portions WP of the circuit substrate 10 includes the first insulation portion WPa, and only the wiring portion WP extending along the first direction E1 of the circuit substrate 20 includes the first insulation portion WPa.
Referring to fig. 3, in the present embodiment, an ion doping process is performed on the line portion WP extending along the first direction E1, so that the line portion WP extending along the first direction E1 includes an ion doped first insulation portion WPa and an ion undoped second insulation portion WPb extending along the first direction E1.
In the present embodiment, the first insulation portion WPa extending along the first direction E1 helps to avoid the problem that the circuit substrate 20 breaks due to the stretching F parallel to the first direction E1, resulting in the signal line 150 extending along the first direction E1.
In the present embodiment, the ion doping process is performed for each of the line portions WP extending along the first direction E1, but the present invention is not limited thereto. In other embodiments, an ion doping process is performed on one or more wire portions WP extending along the first direction E1.
Fig. 4 is a top view of a circuit substrate according to an embodiment of the invention. It should be noted that the embodiment of fig. 4 uses the element numbers and part of the content of the embodiment of fig. 2, where the same or similar numbers are used to denote the same or similar elements, and the description of the same technical content is omitted. Reference may be made to the foregoing embodiments for description of omitted parts, which are not repeated here.
The circuit substrate 30 of fig. 4 differs from the circuit substrate 10 of fig. 2 in that: each of the wiring portions WP of the circuit substrate 10 includes the first insulation portion WPa, and only the wiring portion WP extending in the second direction E2 of the circuit substrate 30 includes the first insulation portion WPa.
Referring to fig. 4, in the present embodiment, an ion doping process is performed on the line portion WP extending along the second direction E2, so that the line portion WP extending along the second direction E2 includes an ion doped first insulation portion WPa and an ion undoped second insulation portion WPb extending along the second direction E2.
In the present embodiment, the first insulation portion WPa extending along the second direction E2 helps to avoid the problem that the circuit substrate 30 breaks due to the stretching F parallel to the second direction E2, resulting in the signal line 150 extending along the second direction E2.
In the present embodiment, the ion doping process is performed on each of the line portions WP extending along the second direction E2, but the present invention is not limited thereto. In other embodiments, an ion doping process is performed on one or more wire portions WP extending along the second direction E2.
Fig. 5 is a top view of a circuit substrate according to an embodiment of the invention. It should be noted that the embodiment of fig. 5 uses the element numbers and part of the content of the embodiment of fig. 2, where the same or similar numbers are used to denote the same or similar elements, and the description of the same technical content is omitted. Reference may be made to the foregoing embodiments for description of omitted parts, which are not repeated here.
The circuit substrate 40 of fig. 5 differs from the circuit substrate 10 of fig. 2 in that: the circuit substrate 40 further includes a plurality of reinforcing structures 200.
The reinforcing structure 200 is disposed on the second insulation portion WPb of the wire portion WP and spaced apart from the signal wire 150. In some embodiments, the stiffening structure 200 can adjust to the neutral axis position of the wire portion WP and reduce the risk of the signal wire 150 breaking due to stretching. In addition, since the reinforcing structure 200 is spaced apart from the signal line 150, even if the reinforcing structure 200 is broken, the broken line is not easily broken to the signal line 150, resulting in breakage of the signal line 150. In some embodiments, the reinforcing structure 200 may be a spare wire.
In summary, the circuit portion of the patterned insulating structure of the present invention includes the first insulating portion doped with ions and the second insulating portion connected to the first insulating portion, and the signal line is located on the first insulating portion, so that the problem of breakage of the signal line due to stretching can be avoided.
Claims (16)
1. A circuit substrate, comprising:
a patterned substrate;
a patterned insulating structure, comprising:
a plurality of device portions on the patterned substrate; and
the circuit parts are positioned on the patterned substrate and connected with the corresponding device parts, wherein at least one circuit part comprises a first insulating part doped with ions and a second insulating part connected with the first insulating part; and
a signal line on the first insulating portion,
the width of the circuit parts is smaller than that of the device parts, and the patterned insulating structure comprises a plurality of first openings, wherein each first opening is surrounded by the corresponding four device parts and the corresponding four circuit parts.
2. The circuit substrate of claim 1, wherein the first insulating portion is ion doped to increase a concentration of at least one chemical element in the first insulating portion, the concentration of the chemical element in the first insulating portion being greater than the concentration of the chemical element in the second insulating portion by more than an order of magnitude.
3. The circuit substrate of claim 1, wherein the first insulating portion is doped with a chemical element and the second insulating portion does not include the chemical element.
4. The circuit substrate of claim 1, wherein the first insulating portion is closer to the long sides of the first openings than the second insulating portion.
5. The circuit substrate of claim 1, wherein a portion of the first openings extend along a first direction and another portion of the first openings extend along a second direction, wherein the portion of the first openings extending along the first direction and the another portion of the first openings extending along the second direction are alternately arranged.
6. The circuit substrate of claim 1, further comprising:
a plurality of semiconductor layers on the device portions, wherein the semiconductor layers and the first insulating portions of the line portions comprise the same ion-doped material;
a plurality of grid electrodes overlapped with the semiconductor layers;
a plurality of grid insulation structures positioned between the grids and the semiconductor layers; and
the source electrodes and the drain electrodes are electrically connected to the semiconductor layers.
7. The circuit substrate of claim 1, wherein the patterned insulating structure comprises a stack of silicon oxide and silicon nitride.
8. The circuit substrate of claim 1, wherein the first insulating portion is doped with phosphorus, boron, carbon, nitrogen, oxygen, or a combination thereof.
9. The circuit substrate of claim 1, wherein the first insulating portion is subjected to residual compressive stress.
10. The circuit substrate of claim 1, wherein the thickness of the circuit portions is less than the thickness of the device portions.
11. The circuit substrate of claim 1, further comprising a reinforcement structure disposed on the second insulating portion.
12. A method of manufacturing a circuit substrate, comprising:
providing a substrate;
forming an insulating structure on the substrate;
forming a mask layer on the insulating structure;
performing a first ion doping process on the insulating structure by using the mask layer as a mask;
patterning the insulating structure to obtain a patterned insulating structure, the patterned insulating structure comprising:
a plurality of device units; and
the circuit parts are connected with the corresponding device parts, and at least one circuit part comprises a first insulating part and a second insulating part connected with the first insulating part, wherein the first insulating part is subjected to ion doping in the first ion doping process; and
forming a signal line on the substrate before or after patterning the insulating structure, wherein the signal line overlaps the first insulating portion,
the width of the circuit parts is smaller than that of the device parts, and the patterned insulating structure comprises a plurality of first openings, wherein each first opening is surrounded by the corresponding four device parts and the corresponding four circuit parts.
13. The method of manufacturing a circuit substrate of claim 12, further comprising:
forming a plurality of semiconductor layers on the insulating structure;
forming a gate insulating layer on the semiconductor layers and the insulating structure;
forming a plurality of shielding conductive layers on the semiconductor layers, wherein each shielding conductive layer is overlapped in the middle of the corresponding semiconductor layer;
and performing the first ion doping process on the insulating structure and the semiconductor layers by taking the mask layer and the shielding conductive layers as masks so as to form a plurality of doped regions in the semiconductor layers.
14. The method of manufacturing a circuit substrate of claim 13, further comprising:
etching the shielding conductive layers to form the grid electrodes on the semiconductor layers, wherein each grid electrode is overlapped in the middle of the corresponding semiconductor layer; and
and performing a second ion doping process on the semiconductor layers by using the mask layer and the grid electrodes as masks.
15. The method of manufacturing a circuit substrate of claim 13, further comprising:
the gate insulating layer is patterned to form a plurality of gate insulating structures, and the gate insulating structures are located between the gates and the semiconductor layers.
16. The method of manufacturing a circuit substrate of claim 13, wherein patterning the insulating structure comprises:
removing a portion of the insulating structure to reduce a thickness of the portion of the insulating structure; and
the first openings are formed in the thinned portion of the insulating structure to form the device portions and the circuit portions, and the thickness of the circuit portions is smaller than that of the device portions overlapped on the semiconductor layers.
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| US202063068435P | 2020-08-21 | 2020-08-21 | |
| US63/068,435 | 2020-08-21 | ||
| TW110103975 | 2021-02-03 | ||
| TW110103975A TWI758083B (en) | 2020-08-21 | 2021-02-03 | Circuit and fabrication method thereof |
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| CN113838864B true CN113838864B (en) | 2023-06-16 |
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| JPH10172927A (en) * | 1996-12-13 | 1998-06-26 | Hitachi Ltd | Semiconductor integrated circuit device and its manufacture |
| CN101236976A (en) * | 2008-03-04 | 2008-08-06 | 友达光电股份有限公司 | Active part array base plate, photoelectric device and its making method |
| CN111448511A (en) * | 2017-11-22 | 2020-07-24 | 微软技术许可有限责任公司 | Display substrate edge patterning and metallization |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103378129B (en) * | 2012-04-19 | 2016-03-23 | 中国科学院微电子研究所 | A kind of semiconductor structure and manufacture method thereof |
| TWI653747B (en) * | 2017-07-25 | 2019-03-11 | 友達光電股份有限公司 | Array substrate and method of manufacturing same |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10172927A (en) * | 1996-12-13 | 1998-06-26 | Hitachi Ltd | Semiconductor integrated circuit device and its manufacture |
| CN101236976A (en) * | 2008-03-04 | 2008-08-06 | 友达光电股份有限公司 | Active part array base plate, photoelectric device and its making method |
| CN111448511A (en) * | 2017-11-22 | 2020-07-24 | 微软技术许可有限责任公司 | Display substrate edge patterning and metallization |
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