TW202207472A - Power semiconductor device and methods forming the same - Google Patents

Abstract

A power semiconductor device including: a substrate; a stack on the substrate sequentially including a group III-V semiconductor buffer structure, a group III-V semiconductor channel structure, and a group III-V semiconductor barrier structure; a first electrode on the stack, wherein an ohmic contact is formed between the first electrode and the stack; a second electrode on the stack, wherein a Schottky contact is formed between the second electrode and the stack; and a group V element supplying layer under the second electrode, wherein the group V element supplying layer covers a portion of the surface of the group III-V semiconductor barrier structure.

Description

Power semiconductor element and method of forming the same

The present invention relates to a semiconductor element, especially a power semiconductor element.

A high electron mobility transistor (HEMT) is a field effect transistor (FET). Most of the gate metal layers of high electron mobility transistors use nickel metal to make contact with the underlying epitaxial layer, which is also called Schottky contact. High electron mobility transistors have physical properties such as high breakdown voltage and high energy gap, and can be placed in high temperature or high voltage and high current environments to operate. When the Schottky contact between the gate metal layer and the epitaxial layer is not sound, the element is prone to failure and has a short life.

A power semiconductor element, comprising: a substrate; a stack on the substrate, wherein the stack comprises a III-V semiconductor buffer structure, a III-V semiconductor channel structure, and a III-V semiconductor barrier structure in sequence; a first an electrode on the stack and forming ohmic contact with the stack; a second electrode on the stack and forming Schottky contact with the stack; and a group V element supply layer under the second electrode , and cover part of the surface of the III-V semiconductor barrier structure.

A method for forming a power semiconductor element, comprising: providing a substrate; forming a stack on the substrate, wherein the stack sequentially includes a III-V semiconductor buffer structure, a III-V semiconductor channel structure, and a III-V semiconductor barrier structure; forming a first electrode on the stack; forming a group V element supply layer on the stack and covering part of the surface of the III-V semiconductor barrier structure; and forming a second electrode on the group V element supply layer.

The following disclosure provides numerous embodiments for implementing various components of the present invention. Specific examples of components and configurations are described below, but these examples are not intended to limit embodiments of the invention. For example, where the description mentions that the first part is formed over the second part, this may include embodiments in which the first and second parts are in direct contact, or may include additional parts formed between the first and second parts , so that the first and second parts are not in direct contact with each other. Additionally, the present disclosure may repeat reference numerals and/or letters in various embodiments. Unless otherwise specified, similar reference numerals refer to similar elements, formed of the same or similar materials, using the same or similar methods.

Furthermore, spatially related terms such as "below", "below", "below", "above", "above" and similar terms may be used herein for descriptive purposes The relationship between one element or component and other elements or components is shown. These spatial terms are intended to encompass different orientations of the device in use or operation. When the device is rotated to other orientations (rotated by 90° or other orientations), the spatially relative descriptions used herein can also be interpreted in accordance with the rotated orientation.

Embodiments of the present invention provide a power semiconductor device and a method for forming the same, which are especially suitable for a high electron mobility transistor (HEMT). In some embodiments, a passivation layer is deposited to provide protection for the epitaxial layer on the substrate prior to constructing any transistor structures. In the process of making electrodes, the passivation layer needs to be etched in a predetermined area, so that the subsequently formed electrodes (eg gate electrodes) can form electrical contact with the underlying epitaxial layer (eg Schottky contact) . Since the plasma bombardment used to etch the passivation layer can damage the structure of the semiconductor compound in the epitaxial layer, it can cause defects. Defects on the epitaxial layer under the passivation layer caused by the etching process are repaired by depositing a compound containing group V elements after etching the passivation layer and before forming the electrodes. In this way, the problem of semiconductor element failure will be reduced, and the characteristics and reliability of the semiconductor element will be improved.

FIGS. 1A to 1G are schematic cross-sectional views illustrating intermediate stages of manufacturing steps of the power semiconductor device 10 according to some embodiments of the present invention. In this embodiment, the power semiconductor device 10 is a depletion mode (D-mode) HEMT. As shown in FIG. 1G , the power semiconductor device 10 includes a substrate 100 , and the stack 110 on the substrate 100 includes a III-V semiconductor nucleation layer 112 , a III-V semiconductor buffer structure 114 , and a III-V semiconductor channel The structure 116, the III-V semiconductor barrier structure 118, the dielectric layer 120 on a portion of the stack 110, the first electrode (eg source) 140 and the third electrode (eg drain) on the stack 110, respectively ) 150, a second electrode (eg, gate) 190 located on the stack 110 and between the first electrode 140 and the third electrode 150, and a group V element supply layer 170 located under the second electrode 190 covering the III- A portion of the surface of the group V semiconductor barrier structure 118 . The second electrode 190 includes a metal or a metal compound having a higher work function than the III-V semiconductor barrier structure 118 . A high resistance contact, such as a Schottky contact, is formed between the second electrode 190 and the III-V semiconductor barrier structure 118 .

In the manufacturing steps of the power semiconductor device 10 , as shown in FIG. 1A , a stack 110 is first formed on the substrate 100 . The formation of the stack 110 includes forming a III-V semiconductor nucleation layer 112 on the substrate 100, forming a III-V semiconductor buffer structure 114 on the III-V semiconductor nucleation layer 112, and forming a III-V semiconductor buffer structure 114 on the III-V semiconductor buffer A III-V semiconductor channel structure 116 is formed over the structure 114 , and a III-V semiconductor barrier structure 118 is formed over the III-V semiconductor channel structure 116 . The III-V semiconductor buffer structure 114 may comprise a single film layer or a multi-film layer (not shown) having a plurality of sub-layers. In some embodiments, the III-V semiconductor buffer structure includes a superlattice structure (not shown) formed by alternately stacking two sub-layers.

In some embodiments, the substrate 100 is a semiconductor substrate or an insulating substrate. The material of the insulating substrate includes sapphire. Materials of the semiconductor substrate include elemental semiconductors such as silicon or germanium, compound semiconductors such as silicon carbide, gallium nitride, aluminum nitride, aluminum gallium nitride, or combinations thereof. Alternatively, the substrate 100 is a multi-layered substrate, such as a silicon-on-insulator (SOI) substrate. In other embodiments, the stacked layer 110 formed by epitaxial growth on the growth substrate can be bonded to the substrate 100 through a wafer transfer process, and the growth substrate can be removed to continue the subsequent process. 100 includes glass, plastic, ceramic, metal and other materials. In this embodiment, the substrate 100 is, for example, a silicon substrate with a thickness of about 1000 μm to 1200 μm. For different epitaxial conditions, silicon substrates with different crystal planes can be used to grow epitaxial structures thereon, such as Si(111) or Si(110). The above-mentioned group III-V semiconductor nucleation layer 112 , group III-V semiconductor buffer structure 114 , group III-V semiconductor channel structure 116 , group III-V semiconductor barrier structure 118 are epitaxially grown on a silicon substrate ( 111) and grow along the [0001] direction.

In some embodiments, the materials of the III-V semiconductor nucleation layer 112 , the III-V semiconductor buffer structure 114 , the III-V semiconductor channel structure 116 , and the III-V semiconductor barrier structure 118 include III-V semiconductors Compound semiconductor materials such as Group III nitrides. Group III nitrides include InxAlyGa1-( _{x +y) N} , where 0≤x≤1, 0≤y≤1, x+y≤1, such as gallium nitride (GaN), aluminum nitride ( AlN), aluminum gallium nitride (AlGaN), aluminum indium nitride (InAlN), indium gallium nitride (InGaN), indium aluminum gallium nitride (InAlGaN), or a combination thereof. The above III-V can be formed by metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), other suitable processes, or a combination thereof Group compound semiconductor materials. The channel structure 116 and the barrier structure 118 may be composed of a single layer or multiple layers of sublayers, respectively.

The III-V semiconductor nucleation layer 112 has a thickness between about 1 nm and about 500 nm, eg, about 200 nm. The III-V semiconductor nucleation layer 112 can alleviate the lattice difference between the substrate 100 and the film layer grown above, so as to improve the epitaxial quality. In other embodiments, the III-V semiconductor buffer structure 114 may be formed directly on the substrate 100 without the III-V semiconductor nucleation layer 112 , so as to simplify the process steps and achieve improved effects.

In some embodiments, the material of the III-V semiconductor buffer structure 114 includes aluminum gallium nitride. The III-V semiconductor buffer structure 114 has a thickness of between about several micrometers (μm) or tens of micrometers, eg, between 4.0 μm and 5.0 μm, eg, about 4.5 μm. The material of the III-V semiconductor buffer structure 114 is a doped or undoped material. In some embodiments, the material of the III-V semiconductor buffer structure 114 is a carbon doped material to increase the resistance value of the III-V semiconductor buffer structure 114 , such as carbon-doped AlGaN ), the carbon doping concentration can be gradually changed with the growth thickness direction or can also be fixed. The III-V semiconductor buffer structure 114 can relieve the strain caused by the lattice mismatch between the substrate 100 and the III-V semiconductor channel structure 116 to prevent defects from forming in the upper III-V semiconductor channel structure 116.

In some embodiments, the material of the III-V semiconductor channel structure 116 has a first energy level and a first lattice constant, and the material of the III-V semiconductor barrier structure 118 has a second energy level and a second lattice constant . The second energy level is greater than the first energy level, and the second lattice constant is different from (eg, smaller than) the first lattice constant. In this embodiment, the III-V semiconductor channel structure 116 and the III-V semiconductor barrier structure 118 are intrinsic semiconductors. The III-V semiconductor channel structure 116 and the III-V semiconductor barrier structure 118 themselves form spontaneous polarization, and due to their different lattice constants, piezoelectric polarization is formed. The heterojunction between the group semiconductor channel structure 116 and the group III-V semiconductor barrier structure 118 generates a two-dimensional electron gas (not shown). Therefore, the material of the III-V semiconductor channel structure 116 includes gallium nitride, aluminum gallium nitride, indium gallium nitride or aluminum indium gallium nitride. The material of the III-V semiconductor barrier structure 118 includes gallium nitride, aluminum gallium nitride, indium gallium nitride or aluminum indium gallium nitride, and the energy level of the material is higher than that of the III-V semiconductor channel structure 116 energy level. In this embodiment, the III-V semiconductor channel structure 116 includes gallium nitride, and the material of the III-V semiconductor barrier structure 118 includes aluminum gallium nitride. The III-V semiconductor channel structure 116 has a thickness between about 100 nm and 300 nm, eg, about 200 nm. The III-V semiconductor barrier structure 118 (aluminum gallium nitride) has a thickness between about 10 nm and 30 nm, eg, about 20 nm.

According to some embodiments of the present invention, the III-V semiconductor barrier structure 118 includes a high energy level material layer and a capping layer (not shown) on the high energy level material layer. According to an embodiment of the present invention, the material energy level of the capping layer is higher than the energy level of the high-energy level material layer, and the overall energy level of the III-V semiconductor barrier structure 118 is increased by the capping layer, thereby increasing the concentration of the two-dimensional electron gas . According to an embodiment of the present invention, the energy level of the high-energy-level material layer is higher than that of the capping layer, and the material of the capping layer may be GaN with a thickness between about 1 nm and 50 nm, such as about 20 nm to 50 nm, or about 1nm to 10nm. According to some embodiments, the formation of the capping layer helps avoid current collapse of the device.

As shown in FIG. 1B, one or more dielectric layers 120 (also referred to as passivation layers) are formed over the III-V semiconductor barrier structures 118 to protect the III-V semiconductor barrier structures 118 from oxidized in the subsequent process. Materials of the dielectric layer 120 include oxides (eg, silicon oxide), nitrides (eg, silicon nitride or silicon carbonitride), silicides (eg, phospho-silicate glass (PSG), borosilicate glass) (boro-silicate glass, BSG), boron-doped phospho-silicate glass (BPSG)), oxynitride (eg, silicon oxynitride), or a combination thereof. The manner of forming the dielectric layer 120 includes, but is not limited to, physical vapor deposition (PVD), such as evaporation or sputtering, chemical vapor deposition (CVD), spin-on coating, or a combination thereof. Although only one dielectric layer 120 is shown in FIG. 1B , the present invention is not limited thereto, and the dielectric layer 120 may be a multi-film layer.

As shown in FIG. 1C , an opening 130S, an opening 130G, and an opening 130D are formed on the dielectric layer 120 to respectively expose a portion of the upper surface of the underlying III-V semiconductor barrier structure 118 . The opening 130S, the opening 130G, and the opening 130D will serve as positions for forming the first electrode 140, the second electrode 190, and the third electrode 150, respectively. The opening 130S, the opening 130G, and the opening 130D can be formed in the same process, or formed separately in different processes, for example, the opening 130S and the opening 130D are formed first, and then the opening 130G is formed in another process. Forming methods of the opening 130S, the opening 130G, and the opening 130D include, but are not limited to, a dry etching process, a wet etching process, or a combination thereof. The wet etching process includes dipping, spraying, etc., in acidic solutions such as dilute hydrofluoric acid (DHF), hydrofluoric acid (HF) solution, nitric acid (HNO ₃ ), and/or acetic acid (CH ₃ COOH), or an alkaline solution such as potassium hydroxide (potassium hydroxide, KOH) solution and/or ammonia (ammonia), or other suitable wet etchants. The dry etching process includes plasma etching (plasma etching), inductively coupled plasma etching (ICP), reactive ion etching (RIE), or a combination thereof. In this embodiment, the formation of the opening 130G uses a dry etching process.

As shown in FIG. 1D, a first electrode 140 and a third electrode 150 are formed in the opening 130S and the opening 130D, respectively. In some embodiments, low resistance contacts, such as ohmic contacts, are formed between the first electrode 140 and the third electrode 150 and the III-V semiconductor barrier structure 118 . The first electrode 140 and the third electrode 150 include metals with work functions between 4.1 and 4.3, such as silver, aluminum, tungsten, tantalum, cadmium, zirconium, titanium, or combinations thereof. The material layers of the first electrode 140 and the third electrode 150 may be formed using physical vapor deposition, atomic layer deposition, plating, or a combination thereof. After that, the first electrode 140 and the third electrode 150 are formed using a lithography process and an etching process. In some embodiments, a rapid thermal annealing process is performed after the first electrode 140 and the third electrode 150 are formed, so that the first electrode 140 and the third electrode 150 respectively form an alloy with the underlying stack 110 to reduce the resistance value of the ohmic contact .

In some embodiments, surface treatment 135 is performed in opening 130G (the area where the second electrode is expected to be formed). The surface treatment 135 includes, but is not limited to, treating the surface of the III-V semiconductor barrier structure 118 with an acidic species. For example, the surface treatment 135 is accomplished by dipping, spraying, or other means using phosphorus pentachloride (PCl ₅ ), hydrochloric acid (HCl), or a combination thereof.

The inventors of the present application found that, in the power semiconductor device manufacturing process, for example, an etching process (eg, dry etching) used to form openings in the dielectric layer 120 may cause defects on the surface of the III-V semiconductor barrier structure 118 , for example, due to etching The process causes the surface to lose the group V elements in its composition, thereby causing, for example, the vacancy of the group V element on the upper surface of the portion of the III-V semiconductor barrier structure 118 exposed by the opening such as the opening 130G, and/or generating excess group III on the surface thereof. Surface defects such as aggregates of elements such as gallium or aluminum. The group V element vacancies and the group III element aggregates make the surface of the group III-V semiconductor barrier structure 118 uneven. In some embodiments, the surface treatment 135 is performed to remove the group III element accumulation, which facilitates the coating of various layers in the subsequent process, and/or facilitates the formation of the group V element supply layer 170 in the subsequent process to the group III-V semiconductor. The group V element vacancies on the surface of the barrier structure 118 are repaired. The mechanism of the surface treatment 135 will be described in detail later in a schematic way.

3A to 3D are schematic diagrams illustrating structural changes of the III-V semiconductor layer 32 , such as the surface 30 of the III-V semiconductor barrier structure 118 , before and after the surface treatment 42 is performed according to some embodiments of the present invention.

As shown in FIG. 3A, the group III-V semiconductor layer 32 includes, for example, aluminum gallium nitride, wherein aluminum and gallium are group III elements, and nitrogen is group V element. As shown in FIG. 3B , during the dry etching process such as the plasma etching process 38 , the surface 30 of the III-V semiconductor layer 32 is impacted by the plasma. Due to the relatively low atomic mass of nitrogen, the process of plasma etching 38 will bombard the nitrogen in the III-V semiconductor layer 32 , resulting in the formation of V vacancies (nitrogen vacancies) on the surface 30 , and the III-V The semiconductor layer 32 is transformed into the nitrogen-deficient compound layer 34 . In some embodiments, the surface of the nitrogen-deficient compound layer 34 exists in the form of dangling bonds.

After the dry etch process, the surface 30 also has the Group III accumulations 40 (aluminum and gallium) deposited thereon. Surface treatment 42 on the surface 30 of the nitrogen-deficient compound layer 34 may use an acidic species to remove the Group III element aggregates 40 .

Next, as shown in FIG. 1E, a group V element supply layer 170 is conformally deposited on the surfaces of the dielectric layer 120, the first electrode 140, and the third electrode 150, and on the surface of the opening 130G where the surface treatment 135 is completed. side walls and bottom. According to some embodiments of the present invention, before fabricating the second electrode 190 , the group V element supply layer 170 is deposited first to repair the group V element vacancy, which will be described in detail later in the form of schematic diagrams ( FIGS. 3C and 3D ). .

In some embodiments, the group V element supply layer 170 is a low dielectric constant (low k) dielectric layer, such as a dielectric constant of not greater than silicon dioxide, such as not greater than 3.7. In some embodiments, the material of the group V element supply layer 170 includes a group V element compound such as a nitride. In some embodiments, the nitrides include metal nitrides comprising metal elements such as Group III metals such as titanium or indium. In this embodiment, the material of the group V element supply layer 170 includes titanium nitride (TiN). According to some embodiments of the present invention, the thickness of the group V element supply layer 170 may be between 50 Å and 150 Å, eg, between about 80 Å and 150 Å. If the thickness of the group V element supply layer 170 is less than 50 Å, it is difficult to form a film because the thickness is too small. If the thickness of the group V element supply layer 170 is greater than 150 Å, discontinuity of the energy band will be caused, and a capacitance effect will be generated to reduce the breakdown voltage. The group V element supply layer 170 may be formed using physical vapor deposition (eg, evaporation or sputtering), chemical vapor deposition, spin coating, or a combination thereof, or other similar methods.

As shown in FIG. 3C, in some embodiments, a substance (or its constituents) 44 formed by the surface treatment 42, such as negatively charged ions of an acidic substance, may temporarily exist on the surface of the stack 30, such as negatively charged ions and surface ions. Dangling bonds form temporary bonds. A group V element supply layer deposition process 46 is then performed on the surface 30 of the nitrogen-deficient compound layer 34 to form a group V element supply layer 48 on the surface 30 . As shown in FIG. 3D, in this embodiment, when a group V element supply layer 48 (eg, titanium nitride) is deposited on the surface 30, the acidic species (or components thereof) 44 will be displaced from the stack surface 30, Group V elements (eg, nitrogen elements) of the group V element supply layer 48 enter the crystal structure of the surface 30 and form chemical bonds with the group III elements of the surface 30 to form the repair compound layer 36 . In other words, the group V element supply layer deposition process 46 on the stack surface 30 may provide a group V element (eg, nitrogen element) to repair the group V element vacancy on the surface of the nitrogen deficient compound layer 34 . In some embodiments, the group III element (eg, gallium) may produce a chemical shift of 0.5 eV after chemical bonding with the group V element of the group V element supply layer 48 .

In addition, in some embodiments, after the step of surface treatment 42 as described in FIGS. 3A to 3B , the step of depositing the group V element supply layer 170 may be omitted, and the second electrode 190 may be directly deposited on the group III-V semiconductor The area on the barrier structure 118 corresponding to the opening 130G. In other embodiments, the surface treatment step 42 as described in FIGS. 3A to 3B can be omitted, and the group V element supply layer 170 is directly deposited on the III-V semiconductor barrier structure 118 in the region corresponding to the opening 130G, and then A second electrode 190 is deposited.

Next, as shown in FIG. 1F, a second electrode 190 is deposited on the group V element supply layer 170, corresponding to the region of the opening 130G. In some embodiments, the material of the second electrode 190 includes a conductive material, such as a metal, a metal compound, or a combination thereof. For example, metals include gold, nickel, platinum, palladium, iridium, titanium, chromium, tungsten, aluminum, copper, silver, alloys thereof, multilayer structures thereof, or combinations thereof; metal compounds include compounds of the foregoing metals, such as nitrides Titanium (TiN). In some embodiments, a Schottky contact is formed between the second electrode 190 and the III-V semiconductor barrier structure 118 . The second electrode 190 is composed of a metal or a metal compound having a work function greater than 4.5 eV. The second electrode 190 may be formed in the same manner as the first electrode 140 or the third electrode 150 . In some embodiments, defects in the III-V semiconductor barrier structure 118 are repaired by the group V element supply layer 170 to enable Schottky contact characteristics between the second electrode 190 and the III-V semiconductor barrier structure 118 More preferably, the leakage current of the power semiconductor device 10 can be reduced, and the threshold voltage can be maintained within a normal operating range.

In some embodiments, the surface treatment and the formation of the group V element supply layer 170 may be performed simultaneously in the opening 130G, the opening 130S, and the opening 130D. The steps of forming the first electrode 140 , the third electrode 150 and the second electrode 190 can also be formed in the same process. For example, after the opening 130S, the opening 130G, and the opening 130D are formed, surface treatment is performed on the opening 130G, and/or the opening 130S and the opening 130D. Next, the group V element supply layer 170 is formed on the opening 130G, and then the first electrode 140 , the third electrode 150 and the second electrode 190 are formed at the positions corresponding to the opening 130S, the opening 130D and the opening 130G in the same process or different processes.

Next, as shown in FIG. 1G , the exposed portion of the group V element supply layer 170 (the portion not covered by the second electrode 190 ) is removed using the aforementioned dry etching process, wet etching process, or a combination thereof. According to some embodiments of the present invention, after the exposed portion of the group V element supply layer 170 is removed, the process of the power semiconductor device 10 is completed.

Although the foregoing embodiment only refers to the process of the second electrode 190, the present invention is not limited thereto. For example, a planarized protective layer (not shown) may be further covered on the surface of the power semiconductor element 10, and openings (not shown) are formed over the first electrode 140 and the third electrode 150 through a patterning process, respectively, and Bonding pad metal (not shown) is deposited in the opening to directly contact the first electrode 140 and the third electrode 150 .

FIGS. 2A to 2H are schematic cross-sectional views illustrating intermediate stages of manufacturing steps of the power semiconductor device 20 according to another embodiment of the present invention. In this embodiment, the power semiconductor device 20 is an enhancement mode (E-mode) HEMT. As shown in FIG. 2H, the power semiconductor device 20 includes a substrate 200, and the stack 210 on the substrate 200 includes a III-V semiconductor nucleation layer 212, a III-V semiconductor buffer structure 214, and a III-V semiconductor channel The structure 216, and the III-V semiconductor barrier structure 218, the dielectric layer 220 on a portion of the stack 210, the first electrode 240 (eg, the source electrode) and the third electrode 250 (eg, the source electrode) on the stack 210, respectively drain), a second electrode 290 (eg, gate) on the stack 210 and between the first electrode 240 and the third electrode 250 , and a group V element supply layer 270 under the second electrode 290 . The second electrode 290 includes a metal or metal compound having a higher work function than the III-V semiconductor channel structure 218 . The structural difference between the power semiconductor device 20 and the power semiconductor device 10 is that the group V element supply layer 270 of the power semiconductor device 20 covers a part of the surface of the III-V group semiconductor channel structure 216, and further includes an insulating layer 280 located on the group V element supply layer between the layer 270 and the second electrode 290 . A high resistance contact, such as a Schottky contact, is formed between the second electrode 290 and the III-V semiconductor channel structure 216 .

As shown in FIGS. 2A to 2D , a stack 210 is formed over the substrate 200 . The formation of the stack 210 includes sequentially forming a III-V semiconductor nucleation layer 212 , a III-V semiconductor buffer structure 214 , a III-V semiconductor channel structure 216 , and a III-V semiconductor barrier structure on the substrate 200 . 218. Next, one or more dielectric layers 220 are formed on the III-V semiconductor barrier structure 218 , and openings 230S, 230G, and 230D are formed on the dielectric layer 220 to expose the underlying III-V groups, respectively. A portion of the upper surface of the semiconductor barrier structure 218 . Then, a first electrode 240 and a third electrode 250 are formed in the opening 230S and the opening 230D, respectively.

In this embodiment, the substrate 200 of the power semiconductor device 20 , the III-V semiconductor nucleation layer 212 , the III-V semiconductor buffer structure 214 , the III-V semiconductor channel structure 216 , and the III-V semiconductor barrier structure 218, the dielectric layer 220, the opening 230S, the opening 230G, the opening 230D, the first electrode 240 and the third electrode 250 can use the substrate 100 of the power semiconductor element 10, the III-V semiconductor nucleation layer 112, the III-V The group semiconductor buffer structure 114, the group III-V semiconductor channel structure 116, the group III-V semiconductor barrier structure 118, the dielectric layer 120, the opening 130S, the opening 130G, the opening 130D, the dielectric layer 120, the first electrode 140 and the first The three electrodes 150 are formed of the same material and process, so they are not repeated here.

Referring to FIG. 2E, the difference between the power semiconductor device 20 and the power semiconductor device 10 is that a groove 260 is etched in the III-V semiconductor barrier structure 218 through the opening 230G, and the groove 260 extends downward along the opening 230G, Part of the upper surface of the III-V semiconductor channel structure 216 is exposed. In some embodiments, the sidewalls of the recess 260 are formed by the sides of the III-V semiconductor barrier structure 218 , and the bottom surface of the recess 260 is formed by a portion of the upper surface of the III-V semiconductor channel structure 216 . In other embodiments, the sidewalls of the recess 260 are formed by the sidewalls of the III-V semiconductor barrier structure 218 and the III-V semiconductor channel structure 216 .

In some embodiments, the role of the groove 260 is to remove a portion of the III-V semiconductor barrier structure 218 to reduce the concentration of the 2D electron gas under it or make it free from the existence of the 2D electron gas under it, thereby powering the The semiconductor element 20 is normally off when the second electrode 290 is not biased. The process of forming the groove 260 can be formed by the dry etching process, the wet etching process, or a combination thereof as described above, and details are not described herein again. According to certain embodiments, the formation of the recess 260 includes an anisotropic dry etching process followed by an isotropic wet etching process. Anisotropic dry etching processes may use argon plasma, while isotropic wet etching processes may use hydrogen chloride, oxo acids (eg, phosphoric acid or sulfuric acid), or combinations thereof.

In some embodiments, the III-V semiconductor nucleation layer 212 , the III-V semiconductor buffer structure 214 , the III-V semiconductor channel structure 216 , and the III-V semiconductor barrier structure 218 in the stack 210 Material and etch select ratio differences are not significant. Therefore, it is difficult to accurately grasp the etching depth in the dry etching process. For example, when the III-V semiconductor barrier structure 218 is to be etched, it is very likely that a significant part of the underlying III-V semiconductor channel structure 216 will be etched away together. . In other embodiments, a wet etching process is used in conjunction with the original dry etching process to form the structure of the groove 260 . Among the predetermined depths of the grooves 260, a dry etching process is used to etch a predetermined depth between about 60% and 80%, and then a wet etching process is used to etch the remaining between about 20% and 40%. A preset depth between %. In some embodiments, the contour of the groove 260 has straight sidewalls formed by the anisotropic dry etching process at the upper portion and non-straight sidewalls formed by the isotropic wet etching process at the lower portion. The portion of the upper surface of the III-V semiconductor channel structure 216 exposed by the groove 260 may maintain a certain integrity.

Referring to FIG. 2E, in some embodiments, the sidewalls (ie, the sides of the III-V semiconductor barrier structure 218 ) and/or the bottom surface (ie, the upper surface of the III-V semiconductor channel structure 216 ) of the recess 260 are Surface Treatment 235. The process of the surface treatment 235 of the power semiconductor element 20 is the same as the process of the surface treatment 135 of the power semiconductor element 10, so it is not repeated here. In addition, referring to the schematic diagrams of the structural changes of the surface 30 before and after the surface treatment 42 as shown in FIGS. 3A to 3D, in this embodiment, the surface 30 is the side surface of the III-V semiconductor barrier structure 218 and the /or the upper surface of the III-V semiconductor channel structure 216 . Through the step of surface treatment 235, surface defects such as group V element vacancies generated by the etching process on the side surface of the III-V semiconductor barrier structure 218 and/or the upper surface of the III-V semiconductor channel structure 216 can be more effectively eliminated. Repaired by group V element supply layer 270 .

As shown in FIG. 2F , a group V element supply layer 270 is conformally deposited on the surfaces of the dielectric layer 220 , the first electrode 240 , and the third electrode 250 , and the sidewalls and/or bottom surfaces of the recess 260 . The material of the group V element supply layer 270 is the same as the material of the group V element supply layer 170 of the foregoing embodiments. Next, an insulating layer 280 is conformally deposited on the group V element supply layer 270 . In some embodiments, the insulating layer 280 is a high dielectric constant (high k) dielectric layer, which effectively prevents the shift of the threshold voltage, so that the power semiconductor device 20 remains normally off in the operating range. The insulating layer 280 may be formed in the same manner as the group V element supply layer 270 . In addition, in other embodiments, after the step of performing the surface treatment 235 , the step of depositing the group V element supply layer 270 may be omitted, and the insulating layer 280 may be directly deposited on the sidewalls and bottom surfaces of the groove 260 .

As shown in FIGS. 2G to 2H , a second electrode 290 is deposited on the insulating layer 280 , corresponding to the region of the groove 260 and filling the groove 260 , and the dry etching process, wet etching process or the above-mentioned process is used as described above. The combination removes the parts of the group V element supply layer 270 and the insulating layer 280 that are not covered by the second electrode 290 , and thus completes the process of the power semiconductor device 20 .

Although the foregoing embodiment only refers to the process of the second electrode 290, the present invention is not limited thereto. For example, a planarized protective layer (not shown) can be further covered on the surface of the power semiconductor element 20, and openings (not shown) are formed over the first electrode 240 and the third electrode 250 through a patterning process, respectively, and Bonding pad metal (not shown) is deposited in the opening to directly contact the first electrode 240 and the third electrode 250 .

The second electrode 290 of the power semiconductor element 20 has a mixed dielectric layer structure composed of a low-k dielectric layer (eg, group V element supply layer 270 ) and a high-k dielectric layer (eg, insulating layer 280 ) at the same time . The hybrid dielectric layer structure of the power semiconductor device 20 can not only repair the vacancies of group V elements on the sidewalls and/or bottom surfaces of the recesses 260 due to the etching process, but also maintain the threshold voltage within a normal operating range.

According to some embodiments, the power semiconductor element 20 has a lower leakage current than the power semiconductor element 10 . The power semiconductor element 10 and the power semiconductor element 20 of the above-mentioned embodiments are transistors with three terminals, that is, they have first electrodes 140 and 240 (eg, source electrodes), and third electrodes 150 and 250 (eg, drain electrodes). electrode) and a triode of second electrodes 190 and 290 (eg gate electrodes). In other embodiments, the group V element supply layer described in the above embodiments can also be applied to a diode with two terminals, such as a first electrode (such as an ohmic electrode) and a second electrode. A Schottky Barrier Diode (SBD) with two electrodes (eg, Schottky electrodes). For example, the structure of the Schottky barrier diode is similar to that of the power semiconductor devices 10 and 20, and may include a substrate, a III-V semiconductor nucleation layer, a III-V semiconductor buffer structure, and a III-V semiconductor channel structure , III-V semiconductor barrier structures, dielectric layers, group V element supply layers, and/or grooves and insulating layers. The difference between the Schottky barrier diodes and the power semiconductor elements 10 and 20 is that the Schottky barrier diodes only have two kinds of electrodes, the Schottky electrode and the ohmic electrode. The material of the Schottky electrode includes the same material as that of the second electrodes 190 and 290 of the power semiconductor elements 10 and 20 , and a Schottky contact is formed between the epitaxial layer below it, and the material of the ohmic electrode includes the same material as the power semiconductor element 10 . , 20 , the first electrodes 140 and 240 , and/or the third electrodes 150 and 250 are of the same material, and an ohmic contact is formed between the epitaxial layers below them. Similarly, the group V element supply layer as described in the previous embodiment can be formed on the surface of the stack (eg, the surface of the III-V semiconductor barrier structure or the surface of the III-V semiconductor channel structure), and then the Schottky electrode is deposited Above the group V element supply layer to improve device characteristics and reliability.

The components of several embodiments are summarized above so that those skilled in the art to which the invention pertains may better understand the concept of the present invention. Those skilled in the art to which the present invention pertains should appreciate that they can easily use the embodiments of the present invention as a basis to design or modify other processes and structures to achieve the same purposes and/or advantages of the embodiments described herein . It should be understood that such equivalent structures do not depart from the spirit and scope of the present invention, and various changes, substitutions and substitutions can be made without departing from the spirit and scope of the present invention.

10,20: Power semiconductor components 30: Surface 32: III-V semiconductor layer 34: Nitrogen-deficient compound layer 36: Patch Compound Layer 38: Plasma Etching 40: Group III element aggregates 42: Surface treatment 44: Substance (or its constituents) 46: Group V element supply layer deposition process 48: Group V element supply layer 100,200: Substrate 110, 210: Laminate 112,212: III-V semiconductor nucleation layer 114,214: III-V semiconductor buffer structures 116,216: III-V semiconductor channel structures 118,218: III-V semiconductor barrier structures 120,220: Dielectric layer 130S, 130G, 130D, 230S, 230G, 230D: Opening 135,235: Surface Treatment 140, 240: First electrode 150,250: The third electrode 260: Groove 170,270: Group V element supply layer 280: Insulation layer 190,290: Second electrode

Various aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that the various features are not drawn to scale. In fact, the dimensions of elements may be arbitrarily enlarged or reduced to clearly represent the features of the present disclosure. FIGS. 1A-1G are schematic cross-sectional views illustrating intermediate stages of forming a power semiconductor device according to an embodiment of the present invention. FIGS. 2A-2H are schematic cross-sectional views illustrating intermediate stages of forming a power semiconductor device according to another embodiment of the present invention. FIGS. 3A-3D are schematic diagrams illustrating structural changes of the surface of the III-V semiconductor layer before and after surface treatment according to some embodiments of the present invention.

10: Power semiconductor components

100: Substrate

110: Laminate

112: III-V semiconductor nucleation layer

114: III-V semiconductor buffer structure

116: III-V semiconductor channel structure

118: III-V semiconductor barrier structures

120: Dielectric layer

140: First electrode

150: Third electrode

170: Group V element supply layer

190: Second Electrode

Claims (23)

A power semiconductor component, comprising: a substrate; a stack on the substrate, wherein the stack sequentially includes a III-V semiconductor buffer structure, a III-V semiconductor channel structure, and a III-V semiconductor barrier structure; a first electrode located on the stack and forming ohmic contact with the stack; a second electrode on the stack and forming Schottky contact with the stack; and A group V element supply layer is located under the second electrode and covers a portion of the surface of the III-V semiconductor barrier structure and/or the III-V semiconductor channel structure. The power semiconductor device of claim 1, further comprising a third electrode located on the stack and forming ohmic contact with the stack. The power semiconductor device of claim 2, wherein the first electrode is a source electrode, the second electrode is a gate electrode, and the third electrode is a drain electrode. The power semiconductor device of claim 1, wherein the material of the group V element supply layer comprises a group V element compound. The power semiconductor device of claim 4, wherein the V group element compound is a metal nitride. The power semiconductor device of claim 5, wherein the metal nitride comprises titanium nitride (TiN). The power semiconductor device of claim 1, wherein the group V element supply layer has a thickness between about 50 Å and 150 Å. The power semiconductor device of claim 1, wherein the group V element of the group V element supply layer forms a chemical bond with the group III element of the group III-V semiconductor barrier structure. The power semiconductor device of claim 8, wherein the group III element in the group III-V semiconductor barrier structure has a chemical shift of 0.5 eV. The power semiconductor device of claim 1 or 2, further comprising a dielectric layer over the stack, wherein the dielectric layer has an opening exposing a portion of the upper surface of the III-V semiconductor barrier structure, the V The group element supply layer is compliantly disposed on a bottom and a sidewall of the opening, and the second electrode is filled in the opening. The power semiconductor device of claim 1 or 2, further comprising a dielectric layer overlying the stack and having an opening, wherein the stack has a groove extending downward along the opening, exposing the III-V group A part of the upper surface of the semiconductor channel structure, the V group element supply layer is compliantly disposed on a bottom and a sidewall of the groove, and the second electrode is filled in the groove. A method for forming a power semiconductor element, comprising: providing a substrate; forming a stack on the substrate, wherein the stack sequentially includes a III-V semiconductor buffer structure, a III-V semiconductor channel structure, and a III-V semiconductor barrier structure; forming a group V element supply layer on the stack and covering a portion of the surface of the III-V semiconductor barrier structure; and A second electrode is formed on the group V element supply layer. The method for forming a power semiconductor device of claim 12, further comprising depositing a dielectric layer on the stack before forming the group V element supply layer, and etching an opening on the dielectric layer to expose the III - A portion of the upper surface of the group V semiconductor barrier structure; wherein the group V element supply layer is formed on the portion of the upper surface. The method for forming a power semiconductor device as claimed in claim 13, further comprising, before forming the group V element supply layer, after etching the opening on the dielectric layer, on the exposed portion of the III-V semiconductor barrier structure A surface treatment is performed on the surface. The method for forming a power semiconductor device as claimed in claim 14, wherein the surface treatment includes using an acidic substance. The method for forming a power semiconductor device of claim 12, wherein the step of forming the group V element supply layer further comprises: connecting the group V element of the group V element supply layer with the group III-V semiconductor barrier structure. Group III elements form chemical bonds. The method for forming a power semiconductor element as claimed in claim 12, further comprising: depositing a dielectric layer on the stack prior to forming the group V element supply layer; and etching a groove through the III-V semiconductor barrier structure and exposing a portion of the upper surface of the III-V semiconductor channel structure, wherein a sidewall and a bottom of the groove are respectively blocked by the III-V semiconductor A part of the surface of the structure and a part of the upper surface of the III-V semiconductor channel structure are formed; The V group element supply layer is deposited on the bottom and sidewalls of the groove, and before the second electrode is formed, an insulating layer is deposited on the V group element supply layer. The method for forming a power semiconductor device as claimed in claim 17, wherein before the formation of the group V element supply layer, a surface treatment is performed on a bottom and a sidewall of the groove. The method for forming a power semiconductor device as claimed in claim 18, wherein the surface treatment includes using an acidic substance. The method for forming a power semiconductor device as claimed in claim 17, wherein the insulating layer has a high dielectric constant (high k). The method for forming a power semiconductor device as claimed in claim 20, wherein the material of the insulating layer comprises nitride, oxide, oxynitride, or a combination thereof. The method for forming a power semiconductor device as claimed in claim 17, wherein the formation of the groove includes sequentially using a dry etching process and a wet etching process. The method for forming a power semiconductor device as claimed in claim 12, further comprising forming a first electrode and/or a third electrode on the stack.

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