TW202207373A - Non-volatile memory structure and method of manufacturing the same - Google Patents

Abstract

A non-volatile memory structure includes a substrate and a tunnel dielectric layer on the substrate, a plurality of gate structures separately formed on the substrate, wherein the gate structures are disposed within an array region of the substrate, and each of the gate structures includes a floating gate and a control gate on the floating gate. A first dielectric layer is formed above the substrate and covers the top surface of the tunnel dielectric layer. The first dielectric layer also covers the side surfaces and the top surface of each of the gate structures. Space between the portions of the first dielectric layer on the side surfaces of two adjacent gate structures is fully filled with an airgap. A plurality of insulating block are formed on the first dielectric layer and corresponding to each of the gate structures. Also, a second dielectric layer is formed on the insulating blocks and covers the insulating blocks and the airgaps.

Description

Nonvolatile memory structure and method of making the same

The present invention relates to a non-volatile memory structure and a method of fabricating the same, and more particularly, to a non-volatile memory structure having a uniform height of air gaps and a method of fabricating the same.

In the non-volatile memory, according to whether the data in the memory can be rewritten at any time when using the computer, it can be divided into two types of products, namely read-only memory (ROM) and flash memory (flash memory). memory). Among them, flash memory has gradually become the mainstream technology of non-volatile memory due to its low cost.

Generally speaking, a flash memory includes two gates, the first gate is a floating gate for storing data, and the second gate is a control gate for data input and output. The floating gate is located below the control gate and is in a "floating" state. Floating means surrounding and isolating the floating gate with insulating material to prevent charge loss. The control gate is connected to the word line to control the device. One of the advantages of flash memory is block-by-block erasing. Flash memory is widely used in enterprise server, storage, and networking technologies, as well as in a wide range of consumer electronics, such as flash drives for flash drives, mobile phones, digital cameras, tablets, notebook PCs, and PC sockets. Embedded controllers, etc.

In the existing non-volatile memory, the air gap between adjacent control gates is not uniform in height and profile, which affects the stability of the electrical performance of the memory. Furthermore, in the conventional non-volatile memory, the height of the air gap is lower than that of the control gate, so the dielectric layer (eg, oxide layer) deposited over the control gate also fills in between adjacent control gates. In other words, in addition to the air gap, a dielectric layer (such as an oxide layer) also exists between adjacent control gates, resulting in the problem of leakage current, which reduces the electrical performance and reliability of the memory.

Therefore, although the existing non-volatile memory formation methods are sufficient for their original intended use, they have not yet fully met the requirements in all aspects. Therefore, there are still problems to be overcome in the non-volatile memory technology. .

Some embodiments of the present invention disclose a non-volatile memory structure comprising: a substrate and a tunneling dielectric layer on the substrate, wherein the substrate includes an array region. A plurality of gate structures located above the substrate and in the array area, and the gate structures are disposed apart from each other, each gate structure includes a floating gate on the tunnel dielectric layer, and a floating gate on the floating gate A control gate of the square. a first dielectric layer overlying the substrate and covering the top surface of the tunneling dielectric layer and covering the side and top surfaces of the gate structures, wherein the first dielectric layer between the first dielectric layers on the sides of adjacent gate structures The space system fills the air gap. A plurality of insulating blocks are located on the first dielectric layer and correspond to the gate structures respectively. a second dielectric layer on the insulating block, the second dielectric layer covering the insulating block and the air gap.

Some embodiments of the present invention disclose a method for fabricating a non-volatile memory structure, including: providing a substrate and forming a tunnel dielectric layer on the substrate, wherein the substrate includes a first region and a second region. forming a plurality of first stacking structures and a plurality of second stacking structures on the tunnel dielectric layer, and these stacking structures are disposed apart from each other, wherein the first stacking structures and the second stacking structures are located in the first region and the second respectively in the area. A first dielectric layer is formed above the substrate, and the first dielectric layer covers the top surface of the tunnel dielectric layer and the top surface and side surfaces of the first stack structure and the second stack structure. A plurality of insulating blocks are formed on the first dielectric layer, and the insulating blocks correspond to the top surface of the first stack structure and the top surface of the second stack structure respectively. A second dielectric layer is formed over the first stack structure and the second stack structure, and an air gap is formed. The second dielectric layer covers the insulating blocks and the air gaps, wherein the air gaps are filled between the first dielectric layers on the sides of the adjacent first stacked structures.

The present invention is more fully described with reference to the drawings of embodiments of the invention. However, the present invention may be embodied in various forms and should not be limited to the embodiments described herein. The thicknesses of layers and regions in the drawings are exaggerated for clarity. The same or similar element numbers refer to the same or similar elements, and the following paragraphs will not describe them one by one.

The non-volatile memory structures proposed in the embodiments can be different types of non-volatile memory structures, and the memory structures including floating gates can be applied to the embodiments of the present disclosure. A non-volatile memory structure may include multiple stacked structures. In an example, a plurality of first stacking structures and a plurality of second stacking structures are arranged in the first area (eg, the array area, or the active area) and the second area (eg, the peripheral area) of the substrate, and a dielectric The layers cover the top and side surfaces of the aforementioned stack. Each stack structure includes at least a floating gate above the substrate, a control gate, and an inter-gate dielectric layer between the floating gate and the control gate, wherein the dielectric on the sides adjacent to the first stack structure There are highly consistent air gaps between the layers. According to some embodiments of the present disclosure, the air gaps fill the spaces between the first dielectric layers on the sides of adjacent first stack structures. The aforementioned air gap has a sufficient width to expose all the dielectric layers covering the side surfaces of the first stacked structure. The details of the fabrication method and the fabricated structure will be described later. In order to simplify the description, the accompanying drawings in the embodiment are drawn three first stack structures and one second stack structure above the substrate and the air gaps extending between the first stack structures for non-volatile memory. Example of structure.

1A-1I are schematic cross-sectional views corresponding to different intermediate stages of fabricating a non-volatile memory structure according to some embodiments of the present disclosure. Referring to FIG. 1A , a substrate 10 is provided, and a tunnel dielectric layer 12 is formed on the substrate 10 . In some embodiments, the substrate 10 includes a first area (eg, an array area) A ₁ and a second area (eg, a peripheral area) A ₂ . The material of the substrate 10 may include silicon, gallium arsenide, gallium nitride, germanium silicide, silicon on insulator (SOI), other suitable materials, or a combination of the foregoing. In some embodiments, the material of the tunnel dielectric layer 12 is, for example, silicon oxide or a high dielectric constant material (for example, the dielectric constant is greater than 4). The high dielectric constant material may include, for example, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, or hafnium tantalum oxide. In one embodiment, the thickness of the tunnel dielectric layer 12 may range from about 3 nm to about 10 nm.

Referring to FIG. 1A again, a plurality of stacked structures are formed on the tunnel dielectric layer 12, for example, the stacked structure S1 and the stacked structure S2 are formed in the _first area A1 and the _second area A2, respectively, and the aforementioned stacked structure is tied in An arrangement that is spaced from each other in the direction D1 (eg, the X direction). Furthermore, each stacked structure includes two or more material layers stacked vertically in the direction D2 (eg, the Z direction) and extending in the direction D3 (eg, the Y direction).

In one embodiment, the stack structure S1 is a plurality of gate structures 14 located in the array area, each gate structure includes a floating gate 141 , an inter-gate dielectric layer 142 and a control gate CG, wherein The floating gate 141 is located on the tunnel dielectric layer 12 , the control gate CG is located above the floating gate 141 , and the inter-gate dielectric layer 142 is located between the floating gate 141 and the control gate CG.

In some embodiments, the floating gate 141 includes polysilicon. In one embodiment, the inter-gate dielectric layer 142 may be a single-layer structure or a multi-layer structure, and the material of the inter-gate dielectric layer 142 may include silicon oxide, silicon nitride, or a combination thereof. For example, the inter-gate dielectric layer 142 may be a silicon oxide/silicon nitride/silicon oxide structure (ONO structure), or a NONON structure. Furthermore, the control gate CG may be a single-layer or multi-layer structure. In some embodiments, the material of the control gate CG includes polysilicon, metal, metal silicide or other conductive materials. For example, the metal may include titanium, tantalum, tungsten, aluminum, or zirconium. The metal silicide may include nickel silicide, titanium silicide, tungsten silicide, or cobalt silicide. In this example, the control gate CG includes a polysilicon gate 144 and a metal gate 145 located on the polysilicon gate 144. The metal gate 145 includes, for example, a metal silicide, such as cobalt silicide. In addition, in this example, the stacked structure S2 includes the same material layer stack as that of the stacked structure S1, and details are not repeated here.

Referring to FIG. 1B , a dielectric layer 16 is formed over the substrate 10 , and the dielectric layer 16 covers the top surface of the tunnel dielectric layer 12 and the top and side surfaces of the stacked structures S1 and S2 . In this example, the dielectric layer 16 includes a first portion 161 located on the top surface of the stack structure S1 (eg, the top surface 145a of the metal gate 145), a second portion 162 located between adjacent stack structures S1, The third portion 163 located between adjacent stacked structures S2 and the fourth portion 164 located on the top surface of the stacked structure S2. Wherein, the second portion 162 and the third portion 163 are respectively formed as a liner between adjacent stacked structures S1 and between adjacent stacked structures S2. As shown in FIG. 1B , the second portion 162 covers the side surface of the floating gate 141 , the side surface of the inter-gate dielectric layer 142 , and the side surface of the control gate CG (eg, including the polysilicon gate 144 and the metal gate 145 ) . Furthermore, in one embodiment, the dielectric layer 16 is a nitride layer, such as silicon nitride.

As shown in FIG. 1B, after the dielectric layer 16 is formed, there are first trenches 171 between the adjacent stacked structures S1, and second trenches are formed between the adjacent stacked structures S1 and S2 172. In one example, the stacked structure S1 is located in the array region of the substrate 10 (ie, the aforementioned first region A ₁ ), and the stacked structure S2 is located at the peripheral region of the substrate 10 (ie, the aforementioned second region A ₂ ). Compared with the stacked structures S2, the stacked structures S1 are arranged more densely, and the stacked structures S1 in the array area and the stacked structures S2 in the peripheral area have a wider distance. Therefore, the second trenches 172 in the direction The width on D1 is greater than the width of the first trench 171 in the direction D1.

Next, a plurality of insulating blocks (such as the insulating blocks 211 ′ and 214 ′ shown in FIG. 1H ) are formed on the dielectric layer 16 , and these insulating blocks correspond to the stacking structure S1 and the stacking structure S2 respectively. top. The following is a schematic cross-sectional view corresponding to a manufacturing method of an insulating block according to an embodiment of the present disclosure with reference to FIGS. 1C-1H.

Referring to FIG. 1C , an oxide layer 18 is formed on the dielectric layer 16 . For example, oxide layer 18 is deposited on dielectric layer 16 by non-conformal deposition. Since the stacked structure S1 is more densely arranged than the stacked structure S2, the width of the first trench 171 is smaller, and the width of the second trench 172 is larger, so the oxide layer 18 is not filled into the first trench after deposition. Slot 171 (ie, above first trench 171 ), but may fill larger second trench 172 .

Referring to FIG. 1D , then, a portion of the oxide layer 18 is removed to expose the dielectric layer 16 and the first trench 171 , and the remaining portion 182 of the oxide layer fills the second trench 172 . Specifically, for example, chemical mechanical polishing (CMP) is used to remove part of the oxide layer 18, and after the removal, the first trench 171 and the dielectric layer 16 covering the stack structure S1 are exposed, and the second trench The top surface 182a of the portion 182 of the oxide layer left in 172 is substantially coplanar with the top surface of the adjacent fourth portion 164 of the dielectric layer 16 (over the stack structure S2). In this example, the dielectric layer 16 may act as a polish stop while removing portions of the oxide layer 18 .

Referring to FIG. 1E , next, a flowable material 19 is deposited over the dielectric layer 16 and over the portion 182 of the remaining oxide layer, wherein the flowable material 19 fills the first trench 171 . The flowable material 19 is, for example, a material containing carbon and oxygen and having flowable properties. In some embodiments, the flowable material 19 includes an organic dielectric layer (ODL), spin-on carbon, photoresist layer, bottom anti-reflective coating (BARC), deep ultraviolet light absorption layer (deep UV light absorbing oxide, DUO), or other suitable materials. In this example, the flowable material 19 is an organic dielectric layer.

Referring to FIG. 1F, then, part of the flowable material 19 is removed to expose the dielectric layer 16 and the remaining part 182 of the oxide layer, so that the flowable material corresponding to the first trench 171 is recessed ( recessed). As shown in FIG. 1F, after a portion of the flowable material 19 is removed, a recessed portion 1710 is formed over the flowable material 191 left in the first trench 171 . In this example, the recesses 1710 expose at least a part of the dielectric layer 16 covering the side surface of the stacked structure S1.

Furthermore, according to the present disclosure, the recessed depth of the flowable material 19 (ie, the height of the recessed portion 1710 in the direction D2 ) should not be too deep to prevent the recessed portion 1710 from being closed when the insulating material layer is subsequently deposited. The recessed depth of the flowable material 19 should not be too shallow, so as to avoid that the thickness difference between the insulating material layer deposited on the stacked structure and the insulating material layer deposited in the recessed portion is too small. If the aforementioned thickness difference is too small, after the process of removing the material layer filled in the first trench, an insulating block with sufficient thickness cannot be left on the stacked structure, thereby affecting the height of the final air gap. As for the value of the recessed depth of the flowable material 19, it can be appropriately adjusted according to the size (including depth and width) of the groove in practical application.

In some embodiments, after removing part of the flowable material 19, the top surface 191a of the flowable material 191 left in the first trench 171 is lower than the top surface of the stacked structure S1. For example, as shown in FIG. 1F, in this example, the top surface 191a of the flowable material 191 left in the first trench 171 is lower than the top surface 145a of the metal gate 145 in the stack structure S1, but not lower than The top surface 144a of the polysilicon gate 144 in the stacked structure S1. However, in the present disclosure, the top surface of the flowable material 191 left in the first groove 171 after the flowable material 19 is recessed is not limited to the aforementioned position.

Referring to FIG. 1G , then, D1 forms an insulating material layer 21 on the dielectric layer 16 , the remaining portion 182 of the oxide layer, and the remaining fluid material 191 . An insulating material layer 21 is deposited on the dielectric layer 16 by conformal deposition. In this example, the insulating material layer 21 includes a first portion 211 located on the top surface of the stacked structure S1 (eg, the top surface 145 a of the metal gate 145 ), a second portion 211 deposited on the sidewall and bottom surface of the recess 1710 Portions 212s and 212b, a third portion 213 on the remaining oxide layer 182, and a fourth portion 214 on the top surface of the stack structure S2. In addition, the insulating material layer 21 is, for example, an oxide layer.

Furthermore, due to the denser arrangement of the stacked structure S1, the width of the first trench 171 is smaller, so the thicknesses of the second portions 212s and 212b of the insulating material layer 21 deposited on the sidewalls and bottom surfaces of the recessed portion 1710 are smaller than those deposited thereon. The thickness on the top surface of the stacked structure S1. That is, the thickness T _S0 of the first portion 211 (in the direction D2 ) of the insulating material layer 21 is greater than the thickness T _S1 of the second portion 212b (in the direction D2 ).

Referring to FIG. 1H, next, the insulating material layer and the fluid material at the first trench 171 are removed. Specifically, parts of the insulating material layer 21 are removed (eg, the second parts 212s and 212b deposited on the sidewalls and the bottom surfaces of the recesses 1710 in this example) are removed, and the first trenches corresponding to the first trenches are removed. The remaining fluid material 191 at 171 exposes the first trench 171, and forms a plurality of insulating blocks 211' and 214' respectively corresponding to the stack structure S1 and the upper part S2 of the second stack structure, such as the 1H as shown in the figure.

In some embodiments, the removal of the insulating material layer and the flowable material 191 is performed by dry etching. It is worth mentioning that, as shown in FIG. 1G, the thickness T _S0 of the first portion 211 of the insulating material layer 21 is much larger than the thickness T _S1 of the second portion 212b, so it is not necessary to use a photomask, but The flowable material 191 can be removed by a self-aligned etch step. As shown in FIG. 1H, the thickness T _S2 of the insulating blocks 211 ′ and 214 ′ formed after etching is smaller than the thickness T _S0 of the first portion 211 deposited before etching, but the height above the stacked structure can be increased. Helps to increase the height of the air gap formed later.

Furthermore, as shown in FIG. 1H, after the self-aligned etching step, the side surfaces 211s of each insulating block 211' are substantially flush with the side surfaces of the first dielectric layer. In the example shown in FIG. 1H, the side surfaces 211s of each insulating block 211' are substantially flush with the side surfaces 162s of the second portion 162 of the first dielectric layer between adjacent stacked structures S1.

Referring to FIG. 1I, then, a dielectric layer 23 is formed over the insulating block 211' (corresponding to the stack structure S1) and the insulating block 214' (corresponding to the stack structure S2), and an air gap 25 is formed, and the dielectric Layer 23 covers air gap 25 and insulating blocks 211' and 214'. Specifically, after the dielectric layer 23 is formed, the bottom surface 23b of the dielectric layer 23 forms an air gap 25 with the space between the first trench 171 and the insulating block 211' above the stacked structure S1.

According to some embodiments of the present disclosure, the formed air gaps 25 at least fill the spaces between the first dielectric layers (eg, the second portions 162 ) on the side surfaces of the adjacent stacked structures S1 . In other words, only the dielectric layer 16 and the air gap 25 exist between the adjacent stacked structures S1 in the direction D1, but no dielectric layer 23 exists.

According to the present disclosure, the material of the dielectric layer 23 and the material of the dielectric layer 16 are different. In this example, the dielectric layer 23 is an oxide layer, and the dielectric layer 16 is a nitride layer. Furthermore, in some embodiments, the material of the dielectric layer 23 and the material of the insulating material layer 21/insulating blocks 211', 214' are the same, for example, contain the same oxide.

As shown in FIG. 1I , due to the insulating blocks 211 ′ and 214 ′, the first trenches 171 between the adjacent stacked structures S1 can extend in the direction D2 , thereby increasing the dielectric for subsequent deposition. The distance between the electrical layer 23 and the substrate 10 increases the height of the air gap 25 (in the direction D2 ) between the adjacent stacked structures S1 . Therefore, in some embodiments, the formed air gap 25 not only fills the space between the first dielectric layers (eg, the second portion 162 ) on the side surface of the adjacent stacked structure S1 , but also fills the adjacent space between the first dielectric layers (eg, the second portion 162 ). The space between the insulating blocks 211 ′ (corresponding to the upper part of the stacked structure S1 ). In other words, only the dielectric layer 16 and the air gap 25 exist between the adjacent stacked structures S1 and the adjacent insulating blocks 211' in the direction D1, but no dielectric layer 23 exists.

As shown in FIG. 1I, the width W1 of the space between the first dielectric layers (eg, the second portion 162 ) on the side surface of the stack structure S1 of D1 in the direction D1 is the same as the width W1 of the air gap in the direction D1 of 25 The width W _Air is equal.

Furthermore, as shown in FIG. 1I , in one example, the air gap 25 exposes at least a portion of the dielectric layer (eg, the second portion 162 ) on all sides of the control gate CG of each stack structure S1 . In this example, the air gaps 25 extending in the direction D2 also directly contact the side surfaces of the insulating blocks 211 ′, so that there are only the dielectric layer 16 and the air gap 25 between the adjacent insulating blocks 211 ′ in the direction D1 the presence of the dielectric layer 23 without the presence of the dielectric layer 23 .

Furthermore, in some embodiments, the top end 25a of the air gap 25 extending in the direction D2 is higher than the top surface 211a of the insulating block 211'.

In addition, the dielectric layer 23 can be deposited by conventional deposition methods or other suitable deposition methods. In some examples, the stacked structures S1 in the _first area A1 (eg, the array area) are arranged closely and have narrow first trenches 171 , so the dielectric layer 23 is not easy to fill in the first trenches 171 .

In some other examples, a tetraethoxysilane (TEOS) material may be selected and deposited by selective means. For example, TEOS deposition is performed under sub-atmospheric pressure (SA) by chemical vapor deposition to form the dielectric layer 23 . The TEOS sub-atmospheric pressure process has different deposition rates on different materials, for example, the deposition rate on the oxide layer is faster, and the deposition rate on the nitride layer is slower, and the deposition rate ratio is, for example, about 2:1. In this example, the insulating block 211 ′ is, for example, an oxide layer, the dielectric layer 16 on the side of the stacked structure S1 is, for example, a nitride layer, and the dielectric layer 23 is not easily filled into the narrow first trench 171 , so After the dielectric layer 23 is deposited, the formed air gap 25, as shown in FIG. 1I, has a top 25a higher than the top surface 211a of the insulating block 211'.

In some embodiments, the ratio of the deposition rate of the dielectric layer 23 on the insulating block 211' to the deposition rate on the dielectric layer 16 is, for example, in the range of about 1.5 to about 2.5, such as about 2.

According to the above-mentioned embodiment, through the disposition of the insulating blocks 211 ′ and 214 ′ ( FIG. 1H ), the first trenches 171 between the adjacent stacked structures S1 can extend in the direction D2 to increase the dielectric for subsequent deposition. The distance between the electrical layer 23 and the substrate 10 (FIG. 1I) increases the height of the air gap 25 (in the direction D2) between the adjacent stacked structures S1. Furthermore, by performing the step of recessing the fluid material 191 with the same depth in each of the first trenches, the insulating blocks 211 ′ and 214 ′ with the same thickness can be subsequently formed, thereby controlling the size of the air gap 25 formed subsequently. Consistency of height and profile, which in turn improves the stability of non-volatile memory structures. In some embodiments, the air gaps 25 have the same height in the direction D2 (eg, the Z direction).

FIGS. 2A-2F are schematic cross-sectional views corresponding to different intermediate stages of manufacturing a non-volatile memory structure according to another embodiment of the present invention, which illustrate another manufacturing process following the step of FIG. 1G. Elements in Figures 2A-2F that are the same or similar to those in Figures 1A-1I are given the same or similar reference numerals for clarity.

The formation steps and configuration of FIG. 2A are the same as those of FIG. 1H, and are not described in detail here for simplicity of description. In addition, in this example, the insulating blocks 211' and 214' respectively formed on the stacked structures S1 and S2 according to the aforementioned manufacturing method are referred to as first insulating layers 211' and 214' in the following description.

Next, referring to FIG. 2B, in one embodiment, another flowable material 29 is deposited on the first insulating layers 211', 214'. The flowable material 29 may have the same material as the flowable material 19 , and the deposition method and material thereof are the same as the aforementioned flowable material 19 , which will not be repeated here.

Next, referring to FIG. 2C , in one embodiment, a portion of the fluid material 29 is removed to expose the first insulating layers 211 ′, 214 ′ and the remaining portion 182 of the oxide layer, so that the portion 182 corresponding to the first insulating layer 211 ′, 214 ′ and the remaining oxide layer is exposed. The flowable material 29 at the grooves 171 is recessed. As shown in FIG. 2C , after removing part of the flowable material 29 , a recess 2710 is formed above the flowable material 291 left in the first groove 171 .

In some embodiments, after removing part of the flowable material 29, the top surface 291a of the flowable material 291 left in the first trench 171 is lower than the top surface 211a of the first insulating layers 211', 214' , 214a. As shown in FIG. 2C, the recessed depth of the flowable material 29 is, for example (but not limited to), to expose the side surfaces of the first insulating layers 211' and 214'.

Next, referring to FIG. 2D , in one embodiment, another insulating material layer 31 is formed over the first insulating layers 211 ′, 214 ′, the remaining portion 182 of the oxide layer, and the remaining fluid material 291 . . In this example, the insulating material layer 31 is deposited by isotropic deposition. The insulating material layer 31 is, for example, an oxide layer. In addition, the insulating material layer 31 and the insulating material layer 21 may have the same or different materials; and the insulating material layer 31 and the insulating material layer 21 may have the same or different thickness, depending on actual application conditions.

As shown in FIG. 2D , in one example, the insulating material layer 31 includes a first portion 311 located on the top surface of the first insulating layer 211 ′, and a second portion deposited on the sidewall and bottom surface of the recessed portion 2710 . Portions 312s and 312b, a third portion 313 over the remaining oxide layer 182, and a fourth portion 314 over the top surface of the first insulating layer 214'.

Next, referring to FIG. 2E , in one embodiment, the insulating material layer and the fluid material at the first trench 171 are removed. Specifically, the second portions 312s and 312b of the insulating material layer 31 (on the sidewalls and the bottom surface of the recess 2710 ) are removed, and the remaining fluid material 291 corresponding to the first trench 171 is removed , so as to expose the first trench 171 , and respectively form second insulating layers 311 ′ and 314 ′ over the first insulating layers 211 ′ and 214 ′. As shown in FIG. 2E , the first insulating layer 211 ′ and the second insulating layer 311 ′ corresponding to the stack structure S1 constitute the insulating block IL ₁ ; and the first insulating layer 214 corresponding to the first stack structure S2 ' and the second insulating layer 314' constitute the insulating block IL ₂ . So far, an insulating block including two insulating layers is constructed above the stacked structure.

Likewise, the insulating material layer and the flowable material 291 at the first trenches 171 can be removed without the use of a photomask. For example, the removal is performed by self-aligned etching, and the sides of each insulating block are substantially flush with the sides of the dielectric layer 16 after removal. As shown in FIG. 2E , the side surfaces 211 s of the first insulating layer 211 ′ and the side surfaces 311 s of the second insulating layer 311 ′ included in the insulating block IL ₁ are substantially flush with the side surfaces 162 s of the dielectric layer 16 .

Then, referring to FIG. 2F , in one embodiment, the dielectric layer 23 is formed over the second insulating layer 311 ′ (corresponding to the stacked structure S1 ) and the second insulating layer 314 ′ (corresponding to the stacked structure S2 ), and formed Air gap 35. The dielectric layer 23 can be deposited by conventional deposition methods or other suitable deposition methods. For example, the dielectric layer 23 may be formed using a sub-atmospheric pressure (SA) selective deposition method, the content of which is described above and will not be repeated here.

In some embodiments, each air gap 35 extending in the direction D2 directly contacts the side surfaces of the first insulating layer 211' and the second insulating layer 311' of each insulating block. As shown in FIG. 2F, according to some embodiments of the present disclosure, the formed air gap 35 not only fills the space between the first dielectric layers (eg, the second portion 162) on the side of the adjacent stacked structure S1, but also and filling the space between the adjacent first insulating layers 211 ′ (corresponding to the upper side of the stack structure S1 ), and further filling the space between the adjacent second insulating layers 311 ′ (corresponding to the upper side of the stack structure S1 ). In other words, only the dielectric layer 16 and the air gap 25 exist between the adjacent stacked structures S1 , between the adjacent first insulating layers 211 ′ and between the adjacent second insulating layers 311 ′ in the direction D1 , without the presence of the dielectric layer 23 .

According to the above-mentioned embodiment, as shown in Figs. 2A to 2E, an insulating block having a multi-layer structure (such as the insulating blocks IL ₁ and IL ₂ shown in Fig. 2E ) can be fabricated, wherein each insulating block includes a plurality of insulator blocks in the direction of Vertically stacked insulating layers on D2. Furthermore, depending on the requirements of the actual process, the steps such as steps 2A-2E can be repeated to manufacture an insulating block containing three or more insulating material layers.

Furthermore, comparing the air gap 25 in Fig. 1I with the air gap 35 in Fig. 2F, the height H2 of the air gap 35 in the direction D2 is greater than the height H1 of the air gap 25 in the direction D2 (H2>H1). Therefore, the thicker the thickness of the insulating block, or the greater the number of insulating layers included, the higher the height of the air gap in the direction D2.

In summary, the non-volatile memory structures and fabrication methods proposed according to some embodiments of the present disclosure have many advantages. For example, a single-layer or multi-layer structure of insulating blocks can be provided in a simple manner without increasing additional manufacturing costs, thereby increasing the air gap 25/35 formed between the stacked structures (eg, word line gate structures) subsequently. The height of the insulating block and/or the number of insulating layers included depend on the height of the air gap to be formed. In the embodiment, the grooves (such as the first grooves) between the stacked structures are filled with the fluid material to perform a recessing step with a uniform depth, and subsequently an insulating block with uniform thickness is formed, thereby controlling each The uniformity in height and profile of the air gap 25/35 improves the stability of the non-volatile memory structure. Furthermore, according to the manufacturing method of the embodiment, it is possible to completely remove the fluid material located in the first trench by self-aligned etching without using a mask, so as to form after depositing the dielectric layer 23 The air gaps 25/35 are wide enough so that only the dielectric layer 16 (such as a nitride layer) and the air gaps 25/35 exist between adjacent stacked structures (such as word line gate structures), but no dielectric The presence of the electrical layer 23 (eg oxide layer), even between adjacent insulating blocks, there is only an air gap 25/35 without the presence of the dielectric layer 23, thus enhancing the adjacent stack structures (eg word line gates) The degree of electrical isolation between the polar structures), the leakage current and the coupling capacitance are reduced, so that the non-volatile memory structure has stable electrical performance, thereby improving the yield and reliability of the final product.

Although the present invention has been disclosed above with several preferred embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make any changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the appended patent application.

10: substrate 12: tunnel dielectric layer 14: gate structure 141: floating gate 142: inter-gate dielectric layer 144: polysilicon gate 144a, 145a, 182a, 191a, 211a, 214a, 291a: top surface 145: metal gate 16, 23: dielectric layer 161, 211, 311: first part 162, 212s, 212b, 312s, 312b: second part 162s, 211s, 311s: side surface 163, 213, 313: first part Three parts 164, 214, 314: Fourth part 171: First trench 1710, 2710: Recess 172: Second trench 18, 182: Oxide layer 19, 191, 29, 291: Fluid material 21, 31: insulating material layer 211', 214': insulating block (first insulating layer) 311', 314': _second insulating layer 23b: bottom surface 25, 35: air gap 25a: top end A1: _first region A2 : second region CG: control gate D1, D2, D3: direction H1, H2: height IL ₁ , IL ₂ : insulating block S1 , S2 : stacked structure T _S0 , T _S1 , T _S2 : thickness W1 , W _Air :width

1A-1I are schematic cross-sectional views corresponding to different intermediate stages of fabricating a non-volatile memory structure according to some embodiments of the present disclosure. FIGS. 2A-2F are schematic cross-sectional views corresponding to different intermediate stages of manufacturing a non-volatile memory structure according to another embodiment of the present invention, which illustrate another manufacturing process following the step of FIG. 1G.

10: Base

12: Tunneling Dielectric Layer

14: Gate structure

141: floating gate

142: Dielectric layer between gates

144: polysilicon gate

145: Metal gate

16, 23: Dielectric layer

161: Part One

162: Part II

162s, 211s: side

163: Part Three

164: Part Four

182: oxide layer

211', 214': insulating block

211a: Top surface

23b: Underside

25: Air Gap

25a: top

A ₁ : The first area

A ₂ : The second area

CG: Control Gate

D1, D2, D3: Direction

H1: height

W1, W _Air : width

Claims (15)

A non-volatile memory structure comprising: a substrate, including an array area; a tunneling dielectric layer on the substrate; A plurality of gate structures are located above the substrate and in the array region, and the gate structures are spaced apart from each other, each of the gate structures includes a floating gate on the tunnel dielectric layer and a floating gate on the tunnel dielectric layer a control gate above the floating gate; A first dielectric layer is located above the substrate and covers the top surface of the tunnel dielectric layer, the first dielectric layer covers the side surfaces and the top surface of each gate structure, wherein the adjacent ones the spaces between the first dielectric layers on the sides of the gate structure are filled with air gaps; a plurality of insulating blocks located on the first dielectric layer and corresponding to the gate structures respectively; and A second dielectric layer is located on the insulating blocks and covers the insulating blocks and the air gaps. The non-volatile memory structure of claim 1, wherein tops of the air gaps are higher than top surfaces of the insulating blocks. The non-volatile memory structure of claim 1, wherein the air gaps expose at least portions of the first dielectric layer on all sides of the control gate of each of the aforementioned gate structures. The non-volatile memory structure of claim 1, wherein the air gaps more directly contact the sides of the insulating blocks. The non-volatile memory structure of claim 1, wherein the air gaps have the same height in a direction perpendicular to the substrate. The non-volatile memory structure of claim 1, wherein each of the insulating blocks and the control gate of each of the gate structures are separated by the first dielectric layer. The non-volatile memory structure of claim 1, wherein the side surfaces of each of the insulating blocks are flush with the side surfaces of the first dielectric layer. The non-volatile memory structure of claim 1, wherein in each of the gate structures, the control gate comprises a polysilicon gate and a metal gate on the polysilicon gate, wherein each of the insulating blocks and the aforementioned The metal gates of each gate structure are separated by the first dielectric layer. A method of manufacturing a non-volatile memory structure, comprising: providing a substrate, the substrate includes a first region and a second region; forming a tunnel dielectric layer on the substrate; A plurality of first stack structures and a plurality of second stack structures are formed on the tunnel dielectric layer spaced apart from each other, and the first stack structures and the second stack structures are respectively located in the first region and the second stack in the area; forming a first dielectric layer over the substrate and covering the top surface of the tunnel dielectric layer and covering the top and side surfaces of the first stack structures and the second stack structures; forming a plurality of insulating blocks on the first dielectric layer, and the insulating blocks respectively correspond to the top surfaces of the first stack structures and the second stack structures; and A second dielectric layer is formed over the first stack structures and the second stack structures to form air gaps, and the second dielectric layer covers the insulating blocks and the air gaps, wherein the Air gaps fill the spaces between the first dielectric layers on the sides of the adjacent first stack structures. The method for manufacturing a non-volatile memory structure as claimed in claim 9, wherein the air gaps are further filled with the spaces between the insulating blocks on the adjacent first stacked structures, the The tops of the air gaps are higher than the top surfaces of the insulating blocks. The method for manufacturing a non-volatile memory structure as claimed in claim 9, wherein after the first dielectric layer is formed, there are first trenches between the first stack structures, and adjacent first stack structures have first trenches. There is a second trench between the structure and the second stacked structure, wherein the width of the second trench in the first direction is greater than the width of the first trenches in the first direction. The method for manufacturing a non-volatile memory structure as claimed in claim 11, wherein after forming the first dielectric layer and before forming the insulating blocks, further comprising: depositing an oxide layer on the first dielectric layer, wherein the oxide layer is above the first trenches but fills the second trenches; removing a portion of the oxide layer to expose the first dielectric layer and the first trenches, and the remaining oxide layer fills the second trenches; depositing a flowable material on the first dielectric layer and the remaining oxide layer, the flowable material filling the first trenches; and A portion of the flowable material is removed to concave the flowable material corresponding to the first grooves. The method for manufacturing a non-volatile memory structure as claimed in claim 12, wherein after removing part of the flowable material, a concave portion is formed above the flowable material left in the first grooves, Wherein the recesses expose at least a portion of the first dielectric layer covering the sides of the first stack structures, and the top surface of the flowable material left in the first trenches is lower than the the top surfaces of some of the first stacked structures. The method for fabricating a non-volatile memory structure as claimed in claim 12, wherein each of the first stacked structures includes a floating gate on the tunnel dielectric layer and a control on the floating gate gate, and the control gate includes a polysilicon gate and a metal gate on the polysilicon gate, and after removing part of the flowable material, the flowability left in the first trenches The top surface of the material is not lower than the top surface of the polysilicon gates of the first stacked structures. The method for manufacturing a non-volatile memory structure according to claim 12, after removing part of the flowable material, further comprising: forming a layer of insulating material on the first dielectric layer, the remaining oxide layer and the remaining fluid material; removing portions of the insulating material layer corresponding to the first trenches and the remaining fluid material, exposing the first trenches and forming the insulating blocks corresponding to the first stacks structure and above the second stacked structures; and The second dielectric layer is deposited.

Images