TW202145393A - Testing system and testing method of chip package - Google Patents

Abstract

A testing system of a chip package includes a transport module, an image capturing module and a processor. The transport module is configured to transport a plurality of chip package along a transport path, so that the plurality of chip packages pass through a picturing region and a testing region. The image capturing module is disposed at the picturing region and configured to move within the picturing region to capture a plurality of images of at least adjacent two of the chip packages located in the picturing region. The testing module is disposed at the testing region to perform chip testing on the plurality of chip packages. The processor is coupled to the image capturing module and the testing module to decide whether to perform the chip testing on at least the adjacent two of the chip packages simultaneously. A testing method is also provided.

Description

Chip package inspection system and chip package inspection method

The present invention relates to an inspection system and an inspection method, and in particular, to a chip package inspection system and a chip package inspection method.

In the semiconductor process, tiny particles or defects are often generated due to some unavoidable reasons. With the continuous reduction of component size and the continuous improvement of circuit density in the semiconductor process, these tiny defects or particles are very important to the integrated body. The influence of circuit quality is also becoming more and more serious. Therefore, in order to maintain the stability of product quality, it is usually necessary to carry out defect inspections for the semiconductor components produced while carrying out various semiconductor processes, so as to analyze the root causes of these defects according to the inspection results. The reason is that the generation of defects can be avoided or reduced by further adjusting the process parameters, so as to achieve the purpose of improving the yield and reliability of the semiconductor process.

The present invention provides a chip package inspection system and a chip package inspection method, which can improve the yield and efficiency of chip inspection.

A chip package inspection system of the present invention includes a conveying module, an image capturing module, a detection module and a processor. The conveying module is used for conveying a plurality of chip packages along the conveying path, so that the plurality of chip packages pass through the camera area and the inspection area on the conveying path in sequence. The image capturing module is disposed in the camera area and moves in the camera area to capture a plurality of images of at least two adjacent chip packages of the plurality of chip packages located in the camera area. The inspection module is disposed in the inspection area to perform chip inspection on the plurality of chip packages. The processor is coupled to the image capturing module and the inspection module to determine whether to package the at least two adjacent chips for parallel chip inspection according to the plurality of images.

In an embodiment of the present invention, the chip package inspection system further includes a fixing base disposed below the image capture module for fixing the plurality of sensors transported below the image capture module chip package.

In an embodiment of the present invention, the fixed base is a vacuum suction base, and is transported to the plurality of chip packages under the image capture module by vacuum suction.

In an embodiment of the present invention, the imaging area is located between the starting point of the conveying path and the detection area.

In an embodiment of the present invention, the chip package inspection system further includes a slide rail disposed in the camera area, and the image capture module is disposed on the slide rail to move along the slide rail rail moves.

In an embodiment of the present invention, the plurality of chip packages are connected to each other to form a package tape-and-reel structure, and each of the plurality of chip packages includes a film, a chip disposed on the film, and a chip disposed on the film. The thin film is electrically connected to the circuit pattern of the chip.

In an embodiment of the present invention, the plurality of imaging points correspond to the junction of the at least two adjacent chip packages, the top of the chip and/or two opposite outer edges of the circuit pattern.

A method for detecting a chip package of the present invention includes the following steps. A plurality of chip packages are conveyed along the conveying path, so that the plurality of wafer packages pass through the imaging area and the inspection area on the conveying path in sequence. A plurality of images are captured for at least two adjacent chip packages of the plurality of chip packages positioned in the imaging region. Whether or not to package the at least two adjacent chips for parallel chip inspection is determined according to the plurality of images.

In an embodiment of the present invention, the processor obtains measurement information of the at least two adjacent chip packages according to the plurality of images.

In an embodiment of the present invention, the measurement information includes the shortest distance between the outer leads of the at least two adjacent chip packages, and when the measurement information is greater than a predetermined value, the processor A decision is made to perform wafer inspection on one of the at least two adjacent wafer packages.

In an embodiment of the present invention, the measurement information includes the shortest distance between the outer leads of the at least two adjacent chip packages, and when the measurement information is less than or equal to a preset value, the The processor determines to package parallel wafer inspections for the at least two adjacent wafers.

In an embodiment of the present invention, the measurement information includes the width of the wiring area of the outer leads of each of the at least two adjacent chip packages, and the detection method further includes storing and/or displaying the measurement information measurement information.

In an embodiment of the present invention, the processor obtains whether each of the at least two adjacent chip packages has a chip according to the plurality of images, and when both the at least two adjacent chip packages have a chip, the The processor determines to package parallel wafer inspections for the at least two adjacent wafers.

In an embodiment of the present invention, the processor obtains whether each of the at least two adjacent chip packages has a chip according to the plurality of images, when one of the at least two adjacent chip packages has a chip , the processor decides to perform wafer inspection on the one wafer package.

Based on the above, the inspection system and inspection method of the present embodiment utilize a movable image capture device to capture multiple images of at least two adjacent chip packages positioned in the camera area, and determine whether to simultaneously or not according to the multiple images The chip inspection is performed on the at least two adjacent chip packages. In this way, the inspection system and inspection method of the present embodiment can effectively improve the inspection efficiency per unit time, and can also avoid simultaneous inspection of multiple chips in the case of serious process errors. The inspection of the chip package can lead to erroneous results, thereby improving the inspection yield of the chip package.

The foregoing and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of each embodiment with reference to the drawings. The directional terms mentioned in the following embodiments, such as "up", "down", "front", "rear", "left", "right", etc., only refer to the directions of the attached drawings. Accordingly, the directional terms used are intended to illustrate rather than limit the present invention. Also, in the following embodiments, the same or similar elements will be given the same or similar reference numerals.

FIG. 1 is a schematic diagram of a chip package inspection system according to an embodiment of the present invention. FIG. 2 is a schematic diagram of an image capture module according to an embodiment of the present invention. Referring to FIG. 1 and FIG. 2 simultaneously, in some embodiments, the inspection system 100 of the chip package is used to perform chip inspection on a plurality of chip packages 210 in sequence. The chip package inspection system 100 may include a transport module 110 , an image capture module 120 , an inspection module 130 and a processor 140 . In this embodiment, a plurality of chip packages 210 can be connected to each other to form the package tape and reel structure 200 as shown in FIG. 2 . That is, in this embodiment, a tape-and-reel packaging technology can be used to package a plurality of chips on a flexible film substrate to form a package tape-and-reel structure 200 having a plurality of chip packages 210 connected to each other. Tape and reel automatic bonding packaging technology can include Chip On Film (COF) packaging, Tape Carrier Package (TCP) and so on. In this embodiment, the chip package 210 may be a chip on film package, but it is not limited thereto. So configured, the transport module 110 may include a plurality of rollers 112 for transporting a plurality of wafer packages 210 using the rollers 112 . In other words, the conveying module 110 can use the rollers 112 disposed on the conveying path TP to convey the package tape and reel structure 200 along the conveying path TP, so that the plurality of chip packages 210 on the package tape and reel structure 200 can be conveyed in sequence through the conveying path TP. The imaging area R1 and the detection area R2 on the path TP. The inspection module 130 is disposed in the inspection area R2 to perform chip inspection on the plurality of chip packages 210 in sequence. In some embodiments, the imaging area R1 is located between the starting point of the transport path TP and the detection area R2, that is, the plurality of chip packages 210 will pass through the imaging area R1 for imaging in sequence, and then pass through the detection area R2 for imaging. Perform wafer inspection.

In some embodiments, the image capture module 120 is disposed in the camera area R1 of the conveying path TP, and is configured to move to a plurality of camera points in the camera area R1 (eg, the camera points P1 and P2 shown in FIG. 3 ). , P3 ) to capture a plurality of images of at least two adjacent chip packages (eg, chip packages 210 a and 210 b ) of the plurality of chip packages 210 located in the camera region R1 . In some embodiments, the inspection system 100 may further include a fixing base 160 disposed below the image capturing module 120 to fix the plurality of chip packages 210 conveyed under the image capturing module 120 .

For example, the fixed base 160 may be a vacuum suction base configured to be vacuum suctioned and transported to the plurality of chip packages 210a, 210b below the image capture module 120 . In some embodiments, the fixed base 160 can utilize suction to attract the chip packages 210a, 210b thereon. Specifically, the top of the fixed base 160 can be attached with a plastic pad, and the bottom of the fixed base 160 can be provided with a ventilation groove, which can be connected with the suction device. The upper surface of the fixing base 124 can be arranged with small air suction holes connected with the ventilation grooves, so when the air suction device is activated, the suction holes can generate suction, and the suction holes located below the image capturing module 120 can be generated. The chip packages 210 a and 210 b are adsorbed on the fixed base 160 . However, this embodiment is not limited thereto, and in other embodiments, the fixing base 160 can temporarily fix the chip packages 210a and 210b in any suitable manner.

In some embodiments, the detection system 100 further includes a moving mechanism 150 disposed in the camera region R1. The image capturing module 120 is disposed on the moving mechanism 150 and can be moved between the plurality of camera points to capture at least two adjacent chip packages 210a and 210b of the chip packages 210 located in the camera region R1. multiple images. For example, the moving mechanism 150 may include a slide rail, and the image capturing module 120 is disposed on the slide rail to move among the plurality of camera points along the slide rail. Specifically, the moving mechanism 150 can be a three-axis slide rail, so that the image capturing module 120 can freely slide along the moving mechanism 150 in three axes including the X-axis, the Y-axis, and the Z-axis. In this embodiment, except for the slide rails that control the movement in the Z-axis direction (moving in the direction away from or close to the fixed base 160 ), other slide rails (X-axis and Y-axis slide rails) can be, for example, parallel to the fixed base The upper surface of the 160 (or the upper surface of the chip packages 210a and 210b ) is arranged so that the image capture module 120 can move along a plane parallel to the upper surface of the fixed base 160 to capture the position on the camera. Multiple images of two adjacent chip packages 210a, 210b in region R1.

3 is a schematic top view of a chip package according to an embodiment of the present invention. 4 is a schematic diagram of a chip package captured by an image capturing module at an imaging point according to an embodiment of the present invention. 3 and 4, in some embodiments, the package tape and reel structure 200 may include a plurality of chip packages (FIG. 3 only shows the chip packages 210a, 210b, 210c, but not limited thereto), wherein each The chip package may include a chip 214, which is electrically connected to the flexible film substrate 212 having circuit patterns formed on the surface thereof. The chip 214 can be, for example, a driving chip of a display panel, but the embodiment is not limited thereto. In some embodiments, the circuit pattern includes inner leads and outer leads, and inner ends of these leads are electrically connected to electrical terminals (eg, bumps) of the chip 214 . In this embodiment, the bumps on the wafer 214 can be bonded to the inner pins on the flexible film substrate, for example, by thermocompression bonding. In this embodiment, outer pins (eg, outer pins 216a and 216b shown in FIG. 4 ) are provided on the flexible film substrate of the packaging tape-and-reel structure 200 , wherein one end of the outer pins (eg, 216b ) It can be bonded with the glass substrate of the display panel, and the other end of the outer pin (eg, 216a ) can be bonded with the printed circuit board (PCB) of the control signal.

Under such a configuration, when the chip packages 210a, 210b are transported along the conveying path TP to below the image capture module 120, the image capture module 120 can align the chip packages 210a, 210b in the camera region R1. 210b captures multiple images. The processor 140 is coupled to the image capture module 120 and the inspection module 130 to determine whether to perform parallel chip inspection on the chip packages 210 a and 210 b according to a plurality of images captured by the image capture module 120 , that is, the chip packages 210 a and 210 b are inspected simultaneously. 210b performs wafer inspection. Further, the processor 140 can obtain at least one measurement information of the chip packages 210a and 210b according to the images captured by the image capturing module 120, and can determine whether the inspection module 130 needs to package two adjacent chips accordingly. 210a, 210b parallel wafer inspection.

FIG. 5 is a schematic flowchart of a method for inspecting a chip package according to an embodiment of the present invention. Referring to FIGS. 3 to 5 simultaneously, in some embodiments, the inspection method for wafer inspection using the inspection system 100 described above may include the following steps. Step S110 is executed to sequentially transport a plurality of chip packages 210 along the transport path TP. Next, step S120 is executed to capture a plurality of images of the two adjacent chip packages 210a and 210b transported into the imaging area R1. For example, in this embodiment, the image capturing module 120 can capture the chip packages 210a and 210b at the camera points P1 and P2 respectively, so as to capture the images M1 and M2 as shown in FIG. 4 . In some embodiments, the positions of the camera points P1 and P2 can be set before the detection process starts. In this embodiment, the imaging points P1 and P2 may correspond to the boundary L1 of two adjacent chip packages 210a and 210b. That is to say, the image capturing module 120 can take pictures at opposite ends of the boundary L1 of the two adjacent chip packages 210a and 210b respectively, so as to obtain the images M1 and M2 as shown in FIG. 4 .

It should be noted here that the moving and photographing sequences of the image capturing module 120 for different groups of chip packages can be different (reverse), so as to save the moving stroke of the chip packages. For example, when capturing images of the chip packages 210a and 210b, the image capturing module 120 may first move to the camera point P1 to capture the image M1, and then move to the camera point P2 to capture the image Image M2. Next, the conveying module 110 continues to convey the next group of two adjacent chip packages (for example, the two adjacent chip packages following the chip packages 210a and 210b) to the camera area R1, and the image capturing module 120 is still at the camera area R1 at this time. Because of the position of the camera point P2, it is possible to shoot at the camera point P2 first, and then move to the camera point P1 for shooting.

Next, step S130 is executed, and the processor 140 obtains at least one measurement information of the two adjacent chip packages 210a and 210b according to the images M1 and M2. In some embodiments, the processor 140 may include an image processing unit to analyze the images M1 and M2 to obtain desired measurement information. In this embodiment, the measurement information may include the shortest distance D1 between the outer leads 216a, 216b of two adjacent chip packages 210a, 210b.

Next, step S130 is executed, and the processor 140 determines whether the measurement information (eg, the shortest distance D1 ) is greater than a predetermined value. In some embodiments, the preset value can be set before the detection process starts, and compared with the preset value after the measurement information is obtained.

Generally speaking, in order to improve the efficiency per unit time and achieve the effect of low input and high output, the inspection module 130 usually adopts a multi-site parallel test method to package multiple chips 210 at a time. Wafer inspection is performed in parallel. That is, the inspection module 130 can simultaneously perform wafer inspection on at least two adjacent chip packages (eg, the chip packages 210 a and 210 b ) transported to the inspection area R2 . However, during the manufacturing process of the chip package, process errors or omissions may occur more or less, for example, the chip and its circuit pattern (including the outer pins) of one of the two adjacent chip packages are offset, thus causing the inspection module 130 In parallel wafer inspection of multiple wafer packages 210a, 210b, erroneous results may be generated.

In view of this, this embodiment obtains the shortest distance D1 between the outer leads 216a and 216b of the two adjacent chip packages 210a and 210b according to the images M1 and M2. If the outer leads of the two adjacent chip packages 210a and 210b are If the shortest distance D1 between 216a and 216b is greater than the preset value, it means that the chip of one of the chip packages 210a and 210b and its circuit pattern (including the outer pins) are too offset. In this case, step S160 is executed to process The controller 140 determines and controls the inspection module 130 to perform wafer inspection on one of the two adjacent chip packages 210a, 210b. Specifically, the processor 140 controls the inspection module 130 to perform single wafer inspection, that is, to perform wafer inspection only on one wafer package (210a or 210b) at a time. For example, the chip package 210a is inspected first, and then the chip package 210b is inspected, so as to avoid an erroneous result caused by inspecting multiple chip packages at the same time when there is a serious process error.

If the shortest distance D1 between the outer leads 216a, 216b of the two adjacent chip packages 210a, 210b is not greater than (ie, less than or equal to) the preset value, that is to say, the chip packages 210a, 210b have no process error or If the process error is within an acceptable range, step S150 is executed, and the processor 140 determines and controls the inspection module 130 to inspect the two adjacent chip packages 210a and 210b in parallel. That is, the processor 140 can control the inspection module 130 to perform multi-site inspection on the chip packages 210 a and 210 b simultaneously according to a preset method, so as to improve the inspection efficiency per unit time.

After the two adjacent chip packages 210a, 210b are both transported to the inspection module 130 in the inspection area R2 for chip inspection (parallel/simultaneous inspection or one-by-one inspection), step S170 is executed, and the processor 140 determines the chip packages 210a, 210b Whether it is the last group of chip packages, and if so, the inspection process can be ended. If not, step S180 is executed, the processor 140 controls the conveying module 110 to continue conveying the package tape and reel structure 200 to move the next group of chip packages (two adjacent chip packages following the chip packages 210a and 210b ) to In the imaging area R1, steps S120 to S170 are repeated for the next group of chip packages until the last group of chip packages completes the chip inspection.

With this configuration, the inspection system and inspection method of the present embodiment can effectively improve the inspection efficiency per unit time, and can also avoid erroneous results caused by inspecting multiple chip packages at the same time under the condition of serious process errors. Inspection yield of chip packaging.

FIG. 6 is a schematic flowchart of a method for inspecting a chip package according to an embodiment of the present invention. It must be noted here that the chip package inspection method and the inspection system 100 used in this embodiment are similar to the chip package inspection method and the inspection system 100 used in FIG. 5 . Therefore, this embodiment follows the previous embodiment. The same or similar elements are represented by the same reference numerals, and the description of the same technical content is omitted. For the description of the omitted part, reference may be made to the foregoing embodiments, which will not be repeated in this embodiment. The difference between the detection method of the chip package of this embodiment and the detection method of the chip package of FIG. 5 will be described below.

Please refer to FIG. 3 , FIG. 4 and FIG. 6 at the same time, the first two steps ( S210 , S220 ) and the last three steps ( S250 , S260 , S270 ) of the detection method for wafer inspection of this embodiment are respectively the same as the detection method in FIG. 5 . The first two steps ( S110 , S120 ) and the last three steps ( S170 , S180 , S190 ) are roughly the same. However, in this embodiment, the image capturing module 120 can take pictures of the chip packages 210a, 210b, and 210c at the camera points P1, P2, P3, and P4, respectively. In this embodiment, the camera points P1 and P2 may correspond to opposite ends of the boundary L1 of the two adjacent chip packages 210a and 210b, while the camera points P3 and P4 may correspond to the two adjacent chip packages 210b and 210c. The opposite ends of the junction, therefore, the image capture module 120 can capture four images corresponding to the camera points P1, P2, P3, and P4 (the images at the camera points P1 and P2 are the images M1, M2). .

Next, step S230 is executed, and the processor 140 obtains the measurement information of the chip packages 210a and 210b according to the above image. In this embodiment, the measurement information may include the width D2 of the wiring area of the outer leads 216a, 216b of the chip packages 210a, 210b. Specifically, according to the images M1 and M2 shown in FIG. 4 captured at the camera points P1 and P2, the processor 140 can obtain the width D2 of the wiring area of the outer lead 216a of the chip package 210a. Similarly, it can be seen that , according to the images captured at the camera points P3 and P4, the processor 140 can obtain the width of the wiring area of the outer pins of the chip package 210b.

Next, step S240 is executed to store and/or display the above measurement information. In some embodiments, the inspection system 100 can also use the image capture module 120 to obtain certain measurement information of each chip package, so as to provide information to subsequent users. For example, the inspection system 100 can also use the image capturing module 120 to obtain the width of the wiring area of the outer leads of each chip package, so that the technicians who perform the outer lead bonding process will know. In this embodiment, the inspection system 100 may include a storage device to store the above-mentioned measurement information (eg, the width of the wiring area of the outer pins of each chip package). In addition, in some embodiments, the inspection system 100 may further include a display device to display the above-mentioned measurement information (eg, the width of the wiring area of the external pins of each chip package), for example, through a human-machine display interface. In some embodiments, if the above-mentioned measurement information is larger or smaller than a specific preset value, the detection system 100 can also issue a warning accordingly.

FIG. 7 is a schematic flowchart of a method for inspecting a chip package according to an embodiment of the present invention. It must be noted here that the chip package inspection method and the inspection system 100 used in this embodiment are similar to the chip package inspection method and the inspection system 100 used in FIGS. 5 and 6 . Therefore, this embodiment uses the same In the component numbers and part of the content of the foregoing embodiments, the same reference numbers are used to represent the same or similar components, and the description of the same technical content is omitted. For the description of the omitted part, reference may be made to the foregoing embodiments, which will not be repeated in this embodiment. The difference between the detection method of the chip package of this embodiment and the detection method of the chip package of FIG. 5 and FIG. 6 will be described below.

The detection method of this embodiment can be said to be the integration of the detection methods of FIG. 5 and FIG. 6 , wherein the first two steps ( S310 , S320 ) and the last three steps ( S380 , S390 ) of the detection method of the wafer inspection of this embodiment , S400 ) are substantially the same as the first two steps ( S110 , S120 ) and the last three steps ( S170 , S180 , S190 ) of the detection method in FIG. 5 , respectively. However, in this embodiment, the image capturing module 120 can take pictures of the chip packages 210a, 210b, and 210c at the camera points P1, P2, P3, P4, P5, and P6, respectively. In this embodiment, the camera points P1 and P2 may correspond to opposite ends of the boundary L1 of two adjacent chip packages 210a and 210b, so as to photograph the boundary of the chip packages 210a and 210b; the camera points P3 and P4 may correspond to The opposite ends of the junction of the two adjacent chip packages 210b and 210c are used to photograph the junction of the chip packages 210b and 210c; the camera points P5 and P6 can be respectively located above the chips (right) of the two adjacent chip packages 210a and 210b. , to photograph the chips of the chip packages 210a and 210b. Therefore, the image capturing module 120 can capture multiple (eg, six) images corresponding to the camera points P1 , P2 , P3 , P4 , P5 , and P6 .

Next, step S330 is executed, and the processor 140 obtains the measurement information of the two adjacent chip packages 210a and 210b according to the above image. In this embodiment, the measurement information obtained according to the images captured by the camera points P1 and P2 may include the shortest distance D1 between the outer leads 216a and 216b of the two adjacent chip packages 210a and 210b and the respective chip packages 210a / The width D2 of the wiring area of the outer pins 216a and 216b of 210b. The measurement information obtained according to the images captured by the camera points P3 and P4 may include the shortest distance between the outer pins of the two adjacent chip packages 210b and 210c and the wiring area of the outer pins of each chip package 210b/210c. width. The measurement information obtained according to the images captured by the camera points P5 and P6 may include whether the two adjacent chip packages 210a and 210b have chips.

Next, step S340 is executed to store and/or display the above measurement information. In some embodiments, the inspection system 100 may utilize a storage device to store the above-mentioned measurement information (eg, the width of the wiring area of the outer pins of each chip package). In addition, in some embodiments, the inspection system 100 can also use a display device to display the above-mentioned measurement information (eg, the width of the wiring area of the external pins of each chip package), for example, through a human-machine display interface. In some embodiments, if the above-mentioned measurement information is larger or smaller than a specific preset value, the detection system 100 can also issue a warning accordingly.

In this embodiment, the image captured by the camera point P6 can obtain the information that the chip package 210b does not have a chip. Therefore, the processor 140 can accordingly decide not to perform chip inspection on the chip package 210b, but only for the chip package 214a. The wafer package 210a performs wafer inspection. When two adjacent chip packages located in the camera region R1 both have chips, the processor 140 may determine and control the inspection module 130 (simultaneously) to perform parallel chip inspection on the two adjacent chip packages.

If the two adjacent chip packages 210a and 210b both have chips, step S350 may be executed continuously, and the processor 140 determines the measurement information (eg, the distance between the outer leads 216a and 216b of the two adjacent chip packages 210a and 210b ). Whether the shortest distance D1 and the shortest distance between the outer leads of the two adjacent chip packages 210b, 210c) are greater than a preset value. If the above-mentioned measurement information is greater than the preset value, it means that the deviation of the chip and its circuit pattern (including the outer pins) in one of the chip packages is too large. At this time, step S370 is executed, and the processor 140 determines and controls the detection The module 130 performs die inspection on one of the two adjacent die packages. Specifically, the processor 140 controls the inspection module 130 to perform single wafer inspection, that is, to perform wafer inspection only on one wafer package (210a or 210b) at a time. For example, the chip package 210a is inspected first, and then the chip package 210b is inspected, so as to avoid an erroneous result caused by inspecting multiple chip packages at the same time when there is a serious process error.

If the shortest distance D1 between the outer leads 216a, 216b of the two adjacent chip packages 210a, 210b is not greater than (ie, less than or equal to) the preset value, that is to say, the chip packages 210a, 210b have no process error or If the process error is within an acceptable range, step S360 is executed, and the processor 140 determines and controls the inspection module 130 to inspect the two adjacent chip packages 210a and 210b in parallel. That is, the processor 140 can control the inspection module 130 to perform multi-site inspection on the chip packages 210 a and 210 b simultaneously according to a preset method, so as to improve the inspection efficiency per unit time.

To sum up, the inspection system and the inspection method of the present embodiment utilize a movable image capture device to capture multiple images of at least two adjacent chip packages positioned in the camera area, and determine according to the multiple images Whether to perform chip inspection on the at least two adjacent chip packages at the same time, in this way, the inspection system and inspection method of the present embodiment can effectively improve the inspection efficiency per unit time, and can avoid the simultaneous detection of multiple chips in the case of serious process errors. Inspection of individual chip packages may result in erroneous results, thereby improving the inspection yield of the chip packages.

Although the present invention has been disclosed above by the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the scope of the appended patent application.

100: Detection System 110: Conveying module 112: Roller 120: Image Capture Module 130: Detection module 140: Processor 160: Fixed base 150: Moving Mechanisms 200: Package Tape and Reel Structure 210, 210a, 210b, 210c: Chip packages 212: Flexible Film Substrates 214, 214a, 214c: Wafers 216a, 216b: Outer pins D1: shortest distance D2: width L1: Junction M1, M2: Image P1, P2, P3, P4, P5, P6: camera points R1: Camera area R2: Detection area TP: transport path

FIG. 1 is a schematic diagram of a chip package inspection system according to an embodiment of the present invention. FIG. 2 is a schematic diagram of an image capture module according to an embodiment of the present invention. 3 is a schematic top view of a chip package according to an embodiment of the present invention. 4 is a schematic diagram of a chip package captured by an image capturing module at an imaging point according to an embodiment of the present invention. FIG. 5 is a schematic flowchart of a method for inspecting a chip package according to an embodiment of the present invention. FIG. 6 is a schematic flowchart of a method for inspecting a chip package according to an embodiment of the present invention. FIG. 7 is a schematic flowchart of a method for inspecting a chip package according to an embodiment of the present invention.

100: Detection System

110: Conveying module

112: Roller

120: Image Capture Module

130: Detection module

140: Processor

160: Fixed base

200: Package Tape and Reel Structure

R1: Camera area

R2: Detection area

TP: transport path

Claims (14)

A chip package inspection system, comprising: a conveying module for conveying a plurality of chip packages along a conveying path, so that the plurality of chip packages pass through the camera area and the detection area on the conveying path in sequence; an image capture module, disposed in the camera area and configured to move between a plurality of camera points in the camera area, to capture images in the plurality of chip packages located in the camera area a plurality of images of at least two adjacent chip packages; an inspection module, disposed in the inspection area, to perform chip inspection on the plurality of chip packages; and The processor, coupled to the image capturing module and the inspection module, is configured to determine whether to package the at least two adjacent chips for parallel chip inspection according to the plurality of images. The inspection system for chip packages according to claim 1, further comprising a fixing base disposed below the image capturing module to fix the plurality of chip packages conveyed under the image capturing module. The inspection system for chip packages according to claim 2, wherein the fixed base is a vacuum suction base, and is transported to the plurality of chip packages under the image capture module by vacuum suction. The inspection system for a wafer package according to claim 1, wherein the imaging area is located between the start point of the conveying path and the inspection area. The chip package inspection system according to claim 1, further comprising a moving mechanism disposed in the camera area, and the image capture module is disposed on the moving mechanism to move between the plurality of camera points between. The inspection system for chip packages according to claim 1, wherein the plurality of chip packages are connected to each other to form a package tape and reel structure, and each of the plurality of chip packages includes a flexible film substrate, disposed on a The chip on the flexible film substrate and the circuit pattern disposed on the flexible film substrate to electrically connect the chip. The chip package inspection system according to claim 6, wherein the plurality of camera points correspond to the junction of the at least two adjacent chip packages and/or above the chip. A detection method for chip packaging, comprising: conveying a plurality of chip packages along the conveying path, so that the multiple chip packages pass through the camera area and the inspection area on the conveying path in sequence; capturing a plurality of images for at least two adjacent chip packages of the plurality of chip packages positioned in the camera region; Whether or not to package the at least two adjacent chips for parallel chip inspection is determined according to the plurality of images. The chip package inspection method according to claim 8, wherein the processor obtains measurement information of the at least two adjacent chip packages according to the plurality of images. The detection method of a chip package according to claim 9, wherein the measurement information includes the shortest distance between the outer leads of the at least two adjacent chip packages, and when the measurement information is greater than a preset value, The processor determines to perform die inspection on one of the at least two adjacent die packages. The inspection method of a chip package according to claim 9, wherein the measurement information includes the shortest distance between the outer leads of the at least two adjacent chip packages, when the measurement information is less than or equal to a predetermined value , the processor decides to package the at least two adjacent wafers for parallel wafer inspection. The detection method of a chip package according to claim 9, wherein the measurement information includes the width of the wiring area of the outer leads of each of the at least two adjacent chip packages, and the detection method further comprises storing and/or The measurement information is displayed. The chip package inspection method according to claim 8, wherein the processor obtains whether each of the at least two adjacent chip packages has a chip according to the plurality of images, and when both the at least two adjacent chip packages have a chip , the processor decides to package the at least two adjacent wafers for parallel wafer inspection. The chip package inspection method according to claim 8, wherein the processor obtains whether each of the at least two adjacent chip packages has a chip according to the plurality of images, and when one of the at least two adjacent chip packages has a chip When the wafer package has wafers, the processor decides to perform wafer inspection on the one wafer package.

Images