TW202143419A - Wafer level chip scale package structure and method for manufacturing the same - Google Patents

Abstract

A wafer level chip scale package structure includes a first chip, a redistribution layer, a plurality of under-ball metallization(UBM) layers, a plurality of conductive pillars, a second chip, an encapsulant, and a plurality of connection portions. The redistribution layer is located on the first chip and is electrically connected to the bonding pad. The UBM layers are located on the redistribution layer. The conductive pillars are located on a part of the UBM layers. The second chip is on another part of the UBM layers. The second chip has an active surface facing the UBM layers. The conductive pillars surround the second chip. The encapsulant encapsulates at least part of the sidewall of the second chip and the conductive pillars. The top surface of the encapsulant is lower than the top surface of the conductive pillars. The connection portions are located on the conductive pillars and are electrically connected to the redistribution layer through the conductive pillars and the UBM layers. The connecting portions extend to the top surface of the encapsulant. A manufacturing method of a wafer level chip scale package structure is also provided.

Description

Wafer-level chip size packaging structure and manufacturing method thereof

The present invention relates to a packaging structure and a manufacturing method thereof, and particularly relates to a wafer-level chip size packaging structure and a manufacturing method thereof.

Wafer level packaging technology (Wafer Level Packaging) is a packaging technology that performs chip size on the entire wafer, that is, most of the packaging work is completed at the wafer stage. Therefore, wafer level chip size packaging can shrink packaging Body size, and has considerable advantages in manufacturing process and material costs.

Generally speaking, there are many factors that affect the reliability of wafer-level chip size packaging. For example, if the components on the wafer have poor bonding strength or damage during the manufacturing process, it will have an adverse effect on the wafer-level chip-scale packaging, thereby reducing the reliability of the wafer-level chip-scale packaging. Therefore, how to reduce the occurrence of adverse effects on wafer-level chip-scale packaging, thereby improving the reliability of wafer-level chip-scale packaging, has become a major challenge for researchers in the field.

The invention provides a wafer-level chip size packaging structure and a manufacturing method thereof, which can reduce the occurrence of adverse effects on the wafer-level chip size packaging structure, thereby improving the reliability of the wafer-level chip size packaging structure.

A wafer-level chip size packaging structure of the present invention includes a first chip, a redistributed circuit layer, a plurality of ball bottom metal layers, a plurality of conductive pillars, a second chip, a packaging glue and a plurality of connecting parts. The first chip has a plurality of bonding pads. The redistributed circuit layer is located on the first chip and electrically connected to the bonding pads. The metal layer at the bottom of the ball is located on the redistributed circuit layer. The conductive pillar is located on a part of the bottom metal layer of the ball. The second chip is located on another part of the bottom metal layer, and the second chip has an active surface facing the bottom metal layer. The conductive pillar surrounds the second wafer. The packaging glue at least encapsulates the second chip and part of the sidewalls of the conductive pillars. The top surface of the encapsulant is lower than the top surface of the plurality of conductive pillars. The connection part is located on the conductive post. The connecting portion is electrically connected to the redistributed circuit layer through the conductive pillar and the ball bottom metal layer, and the connecting portion extends to the top surface of the packaging compound.

The manufacturing method of a wafer-level chip size packaging structure of the present invention includes providing a wafer. The wafer includes a plurality of first chips, and each first chip has a plurality of bonding pads. A redistributed circuit layer is formed on the wafer and electrically connected to a plurality of bonding pads. A plurality of ball bottom metal layers are formed on the redistributed circuit layer. A plurality of conductive pillars are formed on the plurality of ball bottom metal layers, and two adjacent conductive pillars have an opening. The second chip is arranged in the opening, wherein the second chip has an active surface facing the plurality of bottom metal layers and is electrically connected to the plurality of bottom metal layers. A packaging glue is formed to encapsulate at least a part of the sidewalls of the second chip and the plurality of conductive pillars. A plurality of connecting portions are formed on the conductive pillars. The connection part is electrically connected to the redistributed circuit layer through the conductive pillar and the ball bottom metal layer.

Based on the above, the present invention can reduce the adverse effects on the wafer-level chip size packaging structure through the arrangement of the ball bottom metal layer and the packaging compound (such as the second chip on the wafer and the conductive pillars having poor bonding strength). Or the second chip is damaged during the manufacturing process), thereby improving the reliability of the wafer-level chip size packaging structure. On the other hand, since the connecting portion can extend to the top surface of the packaging compound, the connecting portion can have better bonding strength to further improve the reliability of the wafer-level chip size packaging structure.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

The directional terms used herein (for example, up, down, right, left, front, back, top, bottom) are only used as a reference drawing and are not intended to imply absolute orientation.

Unless expressly stated otherwise, any method described herein is in no way intended to be construed as requiring its steps to be performed in a specific order.

Hereinafter, the present invention will be explained more fully with reference to the drawings of this embodiment. However, the present invention can also be embodied in various different forms and should not be limited to the embodiments described herein. The same or similar reference numerals indicate the same or similar elements, and the following paragraphs will not repeat them one by one.

FIGS. 1A to 6A and FIGS. 1B to 6B are respectively a partial top view and a partial cross-sectional view of a wafer-level chip scale package structure in different stages of the manufacturing process according to an embodiment of the present invention. 6C to 6D are partial cross-sectional views following FIG. 6B. 7A to 7D are partial cross-sectional views of the forming method of FIGS. 3B to 4B.

In this embodiment, the manufacturing method of the wafer-level chip size package structure 100 may include the following steps.

1A and 1B at the same time, a wafer 110 is provided, wherein the wafer 110 includes a plurality of first chips 112, and the first chip 112 has a plurality of bonding pads 1121. As shown in FIG. 1A, the plurality of first chips 112 may be arranged on the wafer 110 in an array. In an embodiment, the solder pad 1121 may be an aluminum pad, but the invention is not limited thereto. The bonding pad 1121 can be any suitable conductive pad.

Please refer to FIG. 2A and FIG. 2B at the same time to form a redistributed circuit layer 120 on the wafer 110. For example, the redistributed circuit layer 120 may be formed on the first chip 112 of the wafer 110 and electrically connected to the bonding pad 1121. In this embodiment, the redistributed wiring layer 120 may include a conductive layer 122 and a dielectric layer 124. The steps of forming the redistributed wiring layer 120 may be as follows. First, a conductive material (not shown) is formed on the wafer 110. Next, a patterning process is performed on the conductive material to form a conductive layer 122, wherein the conductive layer 122 is electrically connected to the bonding pad 1121. Then, a dielectric material (not shown) is formed on the conductive layer 122. After that, a plurality of through holes 1241 are formed in the dielectric material to form the dielectric layer 124 and expose a part of the conductive layer 122. Therefore, subsequent components located in the through hole 1241 can be electrically connected to the bonding pad 1121 through the conductive layer 122.

Furthermore, as shown in FIG. 2A, the plurality of through holes 1241 in the dielectric layer 124 may have different sizes. For example, the through hole 1241 near the edge of the first wafer 112 may have a larger size, and the through hole 1241 near the center of the first wafer 112 may have a smaller size, but the present invention is not limited thereto.

In addition, it should be noted that although FIG. 2B only depicts a conductive layer 122 and a dielectric layer 124, however, the present invention does not limit the number of conductive layers 122 and dielectric layers 124, which can be based on actual design requirements. Certainly. In addition, the conductive layer 122 and the dielectric layer 124 can also be formed by suitable materials and forming methods.

Referring to FIGS. 3A and 3B at the same time, a plurality of ball bottom metal layers 130 are formed on the redistributed circuit layer 120. The ball bottom metal layer 130 can improve the bonding strength of subsequent components on the wafer 110 and reduce the lack of bonding strength. It is preferable that adverse effects on the wafer-level chip-scale packaging structure 100 occur, and the reliability of the wafer-level chip-scale packaging structure 100 can be improved.

In this embodiment, the ball bottom metal layer 130 may include a first ball bottom metal layer 132 and a second ball bottom metal layer 134, wherein the first ball bottom metal layer 132 on each first wafer 112 may surround the second ball Bottom metal layer 134. In other words, the first ball bottom metal layer 132 on each first wafer 112 is located on both sides of the second ball bottom metal layer 134. Furthermore, different components can be respectively arranged on the first spherical bottom metal layer 132 and the second spherical bottom metal layer 134 in the subsequent manufacturing process.

Referring to FIGS. 4A and 4B at the same time, a plurality of conductive pillars 140 are formed on the plurality of bottom metal layers 130, wherein the conductive pillars 140 can be electrically connected to the first chip 112. For example, a plurality of conductive pillars 140 may be formed on a part of the bottom metal layer 130 (such as the first bottom metal layer 132), and a part of the bottom metal layer 130 (such as the first bottom metal layer 132) ) And the conductive layer 122 of the redistributed circuit layer 120 is electrically connected to the first chip 112. On the other hand, there may be an opening OP between two adjacent conductive pillars 140. For example, the opening OP may expose another part of the bottom metal layer 130 (such as the second bottom metal layer 134). In other words, the conductive pillar 140 may not be formed on another part of the bottom metal layer 130 (such as the second bottom metal layer 134).

Referring to FIGS. 5A and 5B at the same time, the second chip 150 is disposed on the bottom metal layer 130 of the ball. For example, the second chip 150 may be disposed on another part of the bottom metal layer 130 (such as the second bottom metal layer 134). Furthermore, the second chip 150 may be disposed in the opening OP between two adjacent conductive pillars 140, so the conductive pillar 140 may surround the second chip 150. Here, the first chip 112 and the second chip 150 can be any suitable chips, such as active or passive chips.

In this embodiment, the second wafer 150 has an active surface 150 a facing the bottom metal layer 130. In other words, the back surface 150b of the second chip 150 relative to the active surface 150a can be far away from the bottom metal layer 130. The second chip 150 may be electrically connected to the bottom metal layer 130 in a flip-chip manner. For example, the second chip 150 may also have a plurality of conductive portions 152 on the active surface 150a, and the plurality of conductive portions 152 are bonded to the ball bottom metal layer 130 (such as the second ball bottom metal layer 134). In this way, an electrical connection between the second chip 150 and the bottom metal layer 130 (such as the second bottom metal layer 134) can be achieved.

6A and 6B at the same time, the encapsulant 160 is formed to encapsulate at least part of the sidewalls 140s1 of the second chip 150 and the conductive pillar 140 to effectively protect the second chip 150 and reduce damage to the second chip 150 during the manufacturing process. The adverse effects of the wafer-level chip-scale packaging structure 100 occur, and the reliability of the wafer-level chip-scale packaging structure 100 can be improved. The material of the encapsulant 160 is, for example, Epoxy Molding Compound (EMC), and is formed by, for example, a mold, but the present invention is not limited thereto.

In this embodiment, the height of the conductive pillar 140 relative to the conductive layer 122 may be higher than the height of the second chip 150 relative to the conductive layer 122 and the height of the encapsulant 160 relative to the conductive layer 122. Furthermore, in descending order relative to the height of the conductive layer 122 are the conductive pillar 140, the encapsulant 160, and the second chip 150. In other words, the back surface 150b of the second chip 150 may be lower than the top surface 160a of the encapsulant 160, and the top surface 160a of the encapsulant 160 may be lower than the top surface 140a of the conductive pillar 140 to expose another part of the sidewall of the conductive pillar 140 140s2. However, the present invention is not limited to this. In an unillustrated embodiment, the top surface 160a of the encapsulant 160 may be substantially coplanar with the top surface 140a of the conductive pillar 140. In other words, the encapsulant 160 can completely cover the sidewall 140s2 of the conductive pillar 140. It should be noted that, for clarity of description, the packaging glue 160 is omitted in FIG. 6A.

Referring to FIGS. 6C and 6D at the same time, after the packaging compound 160 is formed, a plurality of solder layers 172 may be formed on the conductive pillar 140. The material of the solder layer 172 is tin, for example. The formation method of the plurality of solder layers 172 may include screen printing, electroplating, or coating. Then, the solder layer 172 may be subjected to a reflow process to form the connecting portion 170 on the conductive pillar 140, wherein the connecting portion 170 may be electrically connected to the redistributed circuit layer 120 through the conductive pillar 140 and the ball bottom metal layer 130. In some embodiments, the connecting portion 170 may be a block, hemispherical, or spherical solder. It should be noted that the connecting portion 170 of the present invention is not limited to be formed by the foregoing method, and may be determined according to actual design requirements.

Furthermore, the connecting portion 170 may extend to the top surface 160a of the encapsulant 160, and the plurality of connecting portions 170 may cover another part of the sidewall 140s2 of the conductive pillar 140, which relatively increases the contact area between the connecting portion 170 and the conductive pillar 140 In other words, since the top surface of the conductive pillar 140 and the sidewall 140s2 are completely covered in the connecting portion 170, the connecting portion 170 can have better bonding strength and a larger conductive area, and at the same time, the encapsulant 160 is also sealed Housing the sidewalls 140s1 of the plurality of conductive pillars 140 relatively increases the stability and structural strength of the plurality of conductive pillars 140, so as to further improve the reliability of the wafer-level chip size packaging structure 100.

After that, in order to further reduce the volume of the wafer-level wafer-scale package structure 100, the wafer 110 may be selectively subjected to a back grinding process to thin the thickness of the wafer 110. Then, a dicing process can be performed on the wafer 110 to form a single-separated wafer-level chip size package structure 100. The cutting process includes, for example, cutting with a rotating blade or a laser beam.

After the above-mentioned manufacturing process, the fabrication of the wafer-level chip size package structure 100 of this embodiment can be substantially completed. The configuration of the ball bottom metal layer 130 and the packaging compound 160 can reduce the adverse effects on the wafer-level chip size packaging structure 100 (for example, the second chip 150 on the wafer and the conductive pillar 140 have poor bonding strength. Or the second wafer 150 is damaged during the manufacturing process). On the other hand, since the connecting portion 170 can extend to the top surface 160a of the packaging compound 160, the connecting portion 170 can have a better bonding strength, which further improves the reliability of the wafer-level chip size packaging structure 100.

In an embodiment, the forming method of FIGS. 3B to 4B may include at least the following steps. Specifically, the following is only an exemplary description that FIGS. 3B to 4B can be formed by the method of FIGS. 7A to 7D, but the present invention is not limited to this, and FIGS. 3B to 4B can be formed by a suitable method.

Please refer to FIGS. 7A and 7B at the same time. First, a plurality of first mask layers 10 may be formed on the redistributed circuit layer 120. The first mask layer 10 may have a plurality of openings corresponding to the through holes 1241 to define the formation position of the ball bottom metal layer 130. In this embodiment, the first mask layer 10 may expose a part of the dielectric layer 124 and a part of the conductive layer 124 exposed by the through hole 1241. Then, an electroplating process can be performed to form the ball bottom metal layer 130 between the first mask layer 10. After that, the first mask layer 10 (not shown) is removed.

7C and 7D at the same time, after the bottom metal layer 130 is formed, a second mask layer 20 is formed on a part of the bottom metal layer 130 (such as the second bottom metal layer 134) and exposes another part of the bottom The metal layer 130 (such as the first ball bottom metal layer 132). Next, an electroplating process is performed to form conductive pillars 140 on the exposed portion of the bottom metal layer 130 (for example, the first bottom metal layer 132). After that, the second mask layer 20 is removed to form the opening OP. Here, the first mask layer 10 and the second mask layer 20 can be formed by suitable materials and forming methods.

To sum up, the present invention can reduce the adverse effects on the wafer-level chip size packaging structure through the configuration of the ball bottom metal layer and the packaging compound (such as the second chip on the wafer and the conductive pillars have bonding strength Poor or the second chip is damaged during the manufacturing process), which can improve the reliability of the wafer-level chip size packaging structure. On the other hand, since the connecting portion can extend to the top surface of the packaging compound, the connecting portion can have better bonding strength to further improve the reliability of the wafer-level chip size packaging structure.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to those defined by the attached patent scope.

10: The first mask layer 20: The second mask layer 100: Wafer-level chip size package structure 110: Wafer 112: The first chip 1121: Solder pad 120: Relay line layer 122: conductive layer 124: Dielectric layer 1241: Through hole 130, 132, 134: metal layer at the bottom of the ball 140: Conductive column 140a, 160a: top surface 140s, 140s1, 140s2: side wall 150: second chip 150a: active side 150b: back 152: Conductive part 160: Encapsulation colloid 170: Connection 172: Solder layer OP: opening

FIGS. 1A to 6A and FIGS. 1B to 6B are respectively a partial top view and a partial cross-sectional view of a wafer-level chip scale package structure in different stages of the manufacturing process according to an embodiment of the present invention. In these figures, a partial top view will be presented first, and then a partial cross-sectional view along the line A-A' in the partial top view will be presented. For example, FIG. 1A is a partial top view of a wafer-level chip-scale package structure in a stage of the manufacturing process. Fig. 1B is a partial cross-sectional view taken along the line A-A' in Fig. 1A. 6C to 6D are partial cross-sectional views following FIG. 6B. 7A to 7D are partial cross-sectional views of the forming method of FIGS. 3B to 4B.

100: Wafer-level chip size package structure

110: Wafer

112: The first chip

1121: Solder pad

120: Relay line layer

122: conductive layer

124: Dielectric layer

130, 132, 134: ball bottom metal layer

140: Conductive column

140s1, 140s2: side wall

150: second chip

150b: back

160: Encapsulation colloid

160a: top surface

170: Connection

Claims (10)

A wafer-level chip size packaging structure, including: The first chip has a plurality of bonding pads; The redistributed circuit layer is located on the first chip and electrically connected to the plurality of bonding pads; A plurality of ball bottom metal layers located on the re-distributed circuit layer; A plurality of conductive pillars located on a part of the plurality of ball bottom metal layers; The second wafer is located on another part of the plurality of ball bottom metal layers, and the second wafer has an active surface facing the plurality of ball bottom metal layers, wherein the plurality of conductive pillars surround the second Chip The packaging glue at least encapsulates the second chip and part of the sidewalls of the plurality of conductive pillars, wherein the top surface of the packaging glue is lower than the top surface of the plurality of conductive pillars; and A plurality of connecting portions located on the plurality of conductive pillars, wherein the plurality of connecting portions are electrically connected to the redistributed circuit layer through the plurality of conductive pillars and the plurality of ball bottom metal layers, and The plurality of connecting portions extend to the top surface of the packaging glue. The wafer-level chip-scale package structure according to claim 1, wherein the plurality of connecting portions are solders in a block shape, a hemisphere shape, or a ball shape. The wafer-level chip-scale package structure according to claim 2, wherein the plurality of connection portions cover the other part of the side wall of the plurality of conductive pillars. A manufacturing method of a wafer-level chip size packaging structure includes: Providing a wafer, wherein the wafer includes a plurality of first chips, and each of the plurality of first chips has a plurality of bonding pads; Forming a redistributed circuit layer on the wafer and electrically connected to the plurality of bonding pads; Forming a plurality of ball bottom metal layers on the redistributed circuit layer; Forming a plurality of conductive pillars on the plurality of bottom metal layers, wherein there is an opening between two adjacent conductive pillars; Disposing a second chip in the opening, wherein the second chip has an active surface facing the plurality of ball bottom metal layers and is electrically connected to the plurality of ball bottom metal layers; Forming an encapsulant to encapsulate at least part of the sidewalls of the second chip and the plurality of conductive pillars; and A plurality of connecting portions are formed on the plurality of conductive pillars, wherein the plurality of connecting portions are electrically connected to the redistributed circuit layer through the plurality of conductive pillars and the plurality of ball bottom metal layers. The manufacturing method of the wafer-level chip size package structure as described in claim 4 further includes: Forming a plurality of first mask layers on the redistributed circuit layer; An electroplating process is performed to form the plurality of ball bottom metal layers between the plurality of first mask layers. The manufacturing method of the wafer-level chip size package structure as described in claim 4 further includes: Forming a plurality of second mask layers on part of the plurality of bottom metal layers and exposing another part of the plurality of bottom metal layers; Performing an electroplating process to form the plurality of conductive pillars on the plurality of bottom metal layers of the other portion that is exposed; and The plurality of second mask layers are removed to form the opening. According to claim 4, the method for manufacturing a wafer-level chip size packaging structure further includes: The backside grinding process is performed on the wafer to thin the thickness of the wafer. According to claim 4, the method for manufacturing a wafer-level chip size packaging structure further includes: A dicing process is performed on the wafer to form an isolated wafer-level chip size package structure. According to the method for manufacturing a wafer-level chip-scale package structure according to claim 8, the step of forming the plurality of connecting portions includes: A plurality of solder layers are formed on the plurality of conductive pillars, wherein the method for forming the plurality of solder layers includes screen printing, electroplating or coating. The method for manufacturing a wafer-level chip size package structure according to claim 9, wherein forming the plurality of solder layers after the plurality of conductive pillars further includes: A reflow process is performed on the plurality of solder layers.

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