TW202119500A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

A semiconductor device includes a semiconductor substrate, a field-effect transistor arranged on the semiconductor substrate and used in an analog circuit, and having a P-type gate electrode, an interlayer insulating film arranged on the field-effect transistor, and a hydrogen shielding metal film arranged on the interlayer insulting film and covering the P-type gate electrode and configured to shield hydrogen.

Description

Semiconductor device and semiconductor device manufacturing method

The present invention relates to a semiconductor device and a manufacturing method of the semiconductor device.

In semiconductor devices in which micro devices are formed on semiconductor substrates such as silicon, there are Metal-Insulator-Semiconductor Field-Effect Transistor (MISFET), resistance elements, fuse elements, etc. An analog semiconductor device made up of a combination of semiconductor elements.

Examples of analog semiconductor devices include a voltage regulator, a voltage detector, and a switching regulator. Among these analog semiconductor devices, with the development of wearable devices (wearable devices) or the Internet of the Things (IoT), development can be extended with low voltage and low current consumption by secondary batteries. Time-driven analog semiconductor devices. Especially when a reference voltage generating circuit is included in a power management (power management) integrated circuit (IC) such as a voltage regulator, it is important to reduce the deviation of the reference voltage or long-term stability.

However, in the MISFET used in such a reference voltage generating circuit, hydrogen generated from a passivation film or the like is bonded to a dangling bond (non-bonding bond) at the interface between the gate oxide film and the silicon substrate. , And there are cases where the threshold voltage varies during manufacturing or changes over time.

Therefore, for example, a semiconductor device is proposed in which a silicon nitride film for shielding hydrogen is formed on an N-channel Metal-Oxide-Semiconductor (MOS) transistor, etc., so that hydrogen does not diffuse into the N-channel MOS. Transistor (for example, refer to Patent Document 1). [Prior Art Literature] [Patent Literature]

[Patent Document 1] Japanese Patent Laid-Open No. 2003-152100

[The problem to be solved by the invention]

In one aspect of the present invention, an object is to provide a semiconductor device that can suppress the occurrence of defects caused by hydrogen without increasing the film formed. [Means to solve the problem]

A semiconductor device according to an embodiment of the present invention includes: Semiconductor substrate A field effect transistor, which is arranged on the semiconductor substrate and used in an analog circuit, and includes a P-type gate electrode; An interlayer insulating film disposed on the field effect transistor; and A hydrogen barrier metal film is disposed on the interlayer insulating film and is near the upper side of the P-type gate electrode, and blocks hydrogen. [Effects of the invention]

According to an aspect of the present invention, it is possible to provide a semiconductor device that can suppress the occurrence of problems caused by hydrogen without increasing the formed film.

A semiconductor device according to an embodiment of the present invention includes: a semiconductor substrate; a field-effect transistor, which is arranged on the semiconductor substrate and used in an analog circuit, and includes a P-type gate electrode; an interlayer insulating film, which is arranged on the field-effect transistor On; and a hydrogen barrier metal film, disposed on the interlayer insulating film and near the upper side of the P-type gate electrode, blocking hydrogen.

The semiconductor device of one embodiment of the present invention was completed based on the following knowledge.

The characteristics required for analog semiconductor devices are quite different from logic semiconductor devices that process binary signals. For example, in the charge and discharge control circuit of secondary batteries such as lithium ion batteries, in order to minimize the discharge of secondary batteries used in mobile devices, etc., the specification of μV units has been mostly pursued for several years. . The reference voltage generating circuit used in the charge and discharge control circuit also pursues reliability in μV units. Therefore, it is necessary to reduce the deviation of the threshold voltage of the field effect transistor (hereinafter referred to as "MOS transistor") included in the reference voltage generating circuit, or the change over time that can be shown by long-term reliability tests. .

When forming the MOS transistor, impurities such as boron, phosphorus, and arsenic are usually injected into the polysilicon film to form a gate electrode. Boron implanted as an impurity is easier to diffuse into the polysilicon film than phosphorus or arsenic, and to the gate oxide film under the polysilicon film. If so, it is considered that the gate oxide film is more likely to be degraded in quality than the case where phosphorus or arsenic is implanted, and it is easier to pass minute atoms such as hydrogen. At this time, if even a trace amount of hydrogen generated from the passivation film is bonded to the dangling bond (non-bonding bond) at the interface between the gate oxide film and the silicon substrate, it will be used in an analog semiconductor device that needs to be adjusted in units of μV. , There are also cases where the threshold voltage varies during manufacturing or changes over time.

In this regard, in the semiconductor device described in Patent Document 1, a silicon nitride film for shielding hydrogen is arranged above the P-type gate electrode, but this not only increases the number of steps for forming the silicon nitride film, but also In addition, the threshold voltage may change due to the stress of the silicon nitride film arranged in the vicinity of the P-type gate electrode.

Therefore, the semiconductor device according to an embodiment of the present invention uses an enlarged area of the metal wiring layer arranged on the MOS transistor to be used as a hydrogen barrier metal film. That is, the semiconductor device can block hydrogen generated from the passivation film and the like by disposing a hydrogen barrier metal film that doubles as a metal wiring layer in the vicinity of the P-type gate electrode where the threshold voltage is easily changed. Without increasing the film formed, the occurrence of defects caused by hydrogen is suppressed.

Next, as an example of a semiconductor device according to an embodiment of the present invention, an embodiment in which the analog circuit is an enhancement/depletion (ED) type reference voltage generating circuit will be described with reference to the drawings.

In addition, the drawing is a schematic drawing, and the relationship between the film thickness and the plane size, the ratio of each film thickness, etc. are not as shown in the drawing. In addition, in a semiconductor substrate, the surface on the side where other films or layers are laminated using a semiconductor manufacturing process is called the "upper surface", and the surface on the side facing the upper surface is called the "lower surface". Furthermore, in the following, the number, position, shape, structure, size, etc. of the plurality of films or the semiconductor elements obtained by structurally combining the plurality of films are not limited to the embodiments shown below, and can be set The preferred number, position, shape, structure, size, etc. are used to implement the present invention.

[First Embodiment] Fig. 1 is a circuit diagram showing an analog circuit of a semiconductor device according to a first embodiment of the present invention. As shown in FIG. 1, the semiconductor device 100 of this embodiment includes an ED-type reference voltage generating circuit that is an analog circuit, and has a depletion-type N-channel field-effect transistor 110 and an enhancement-type N-channel field-effect transistor.晶120。 Crystal 120.

Furthermore, hereinafter, sometimes the "depletion-mode N-channel field effect transistor" is referred to as the "D-type NMOS transistor", and sometimes the "enhanced N-channel field effect transistor" is referred to as the "E-type NMOS transistor". Crystal".

The D-type NMOS transistor 110 functions as a constant current source. When the power supply voltage VDD is applied to the drain connected to the power supply terminal 100a, a constant current that does not depend on the power supply voltage VDD is supplied from the source to the E-type NMOS transistor 120. _{The E-type NMOS transistor 120 generates a reference voltage Vref} based on the constant current supplied from the D-type NMOS transistor 110 to the reference voltage terminal 100c. In this way, the ED-type reference voltage generating circuit is formed by combining the D-type NMOS transistor 110 and the E-type NMOS transistor 120.

To the source of the D-type NMOS transistor 110, the gate of the D-type NMOS transistor 110, the back gate, the reference voltage terminal 100c, and the gate and drain of the E-type NMOS transistor 120 are connected, and these The parts are set to the same potential. In addition, a back gate and a ground terminal 100b are connected to the source of the E-type NMOS transistor 120, and these components are set to the same potential.

Here, when the drain current I _{d1 of the} D-type NMOS transistor 110 is obtained, if the transconductance during the unsaturated operation or the saturation operation is set to gmD, the following formula (1) Generally shown. Furthermore, as described above, since the gate of the D-type NMOS transistor 110 is connected to the source, in the following formula (1), the gate-source voltage V _g1 is 0 V. Therefore, the output current of the D-type NMOS transistor 110, that is, the drain current I _d1, depends on the threshold voltage V _td . I _d1 =1/2·gmD·(V _g1 -V _td ) ² =1/2·gmD·(|V _td |) ² ···(1)

Next, when the drain current I _{d2 of the} E-type NMOS transistor 120 is obtained, if the transconductance during saturation operation is set to gmE, it can be expressed as the following equation (2). Furthermore, as described above, since the gate and drain of the E-type NMOS transistor 120 are connected, and these components are connected to the reference voltage terminal 100c, in the following formula (2), the gate-source The time voltage V _g2 becomes the reference voltage V _ref . Therefore, the drain current I _d2 depends on the threshold voltage V _te and the reference voltage V _ref . I _d2 =1/2·gmE·(V _g2 -V _te ) ² =1/2·gmE·(V _ref -V _te ) ² ···(2)

As described above, since I _{d1 in the above-mentioned formula (1) is equal to I d2 in the} above-mentioned formula (2), the reference voltage V _ref becomes the following formula (3). V _ref ≒V _te +(gmD/gmE) ^1/2 ·|V _td | ···（3）

2 is a schematic plan view showing the semiconductor device according to the first embodiment of the present invention, and is a plan view of an ED-type reference voltage generating circuit formed on a semiconductor substrate. In FIG. 2, the N-type gate electrode 6, the P-type gate electrode 7, the hydrogen barrier metal film 10 that also functions as a metal wiring layer, and the connection to the hydrogen barrier metal film 10 in the structure of the semiconductor device 100 are shown. The metal wiring 9a～metal wiring 9f. In addition, the dotted lines in FIG. 2 indicate the active regions of the D-type NMOS transistor 110 and the E-type NMOS transistor 120, respectively.

In addition, the figure in the top view means the figure (plan view) when the upper surface of a semiconductor substrate is seen from the normal direction.

When viewed from above the semiconductor substrate (in the normal direction of the substrate), the hydrogen barrier metal film 10 on the active area indicated by the dotted line on the side of the E-type NMOS transistor 120 is larger than the area of the P-type gate electrode 7 to cover P-type gate electrode 7 is arranged in a manner.

Here, the cross-sections of the D-type NMOS transistor 110 and the E-type NMOS transistor 120 will be described with reference to FIGS. 3 and 4.

Fig. 3 is an explanatory diagram showing a cross section taken along the line A-A in Fig. 2. Fig. 4 is an explanatory diagram showing a cross section taken along the line B-B in Fig. 2.

As shown in FIGS. 3 and 4, the semiconductor device 100 includes a semiconductor substrate 1, a separation oxide film 2, a gate oxide film 3, a P-type well region 4, a source-drain region 5, and an N-type gate electrode 6. , P-type gate electrode 7, phosphorus and boron-added silicon oxide film (hereinafter referred to as "Boro-Phospho Silicate Glass (BPSG) film") 8, metal wiring 9, hydrogen barrier metal film 10, And the passivation film 11. The D-type NMOS transistor 110 and the E-type NMOS transistor 120 have a separation oxide film 2, a gate oxide film 3, a P-type well region 4, a source-drain region 5, and an N-type gate on the semiconductor substrate 1. The pole electrode 6 and the P-type gate electrode 7 are structurally combined and formed.

The semiconductor substrate 1 is a wafer-like P-type silicon semiconductor substrate.

Furthermore, in this embodiment, the semiconductor substrate 1 is a wafer-like P-type silicon semiconductor substrate, but it is not limited to this. The shape, structure, size, material, and polarity of the semiconductor substrate 1 can be changed according to the purpose. Choose appropriately.

The separation oxide film 2 is a local oxidation of silicon (LOCal Oxidation of Silicon, LOCOS) formed on the semiconductor substrate 1. The separation oxide film 2 is provided on the outer edge of each active region in order to separate the D-type NMOS transistor 110 and the E-type NMOS transistor 120.

Furthermore, in this embodiment, LOCOS is formed in order to separate the D-type NMOS transistor 110 and the E-type NMOS transistor 120, but it is not limited to this. For example, shallow trench insulation (Shallow Trench Isolation, STI) may be formed. ) And so on.

The D-type NMOS transistor 110 includes a gate oxide film 3, a P-type well region 4, a source-drain region 5, and an N-type gate electrode 6 in which phosphorus is implanted into a polysilicon film.

In the D-type NMOS transistor 110, the impurity concentration is adjusted so that the difference between the work functions of the P-type well region 4 and the N-type gate electrode 6 becomes larger, and the reverse direction is applied to the surface of the P-type semiconductor substrate 1. The electric field is therefore a low threshold voltage. Furthermore, since the threshold voltage can be lowered by the N-type channel doped region, the impurity injection into the N-type gate electrode 6 and the channel doped region is appropriately controlled in such a way that the D-type NMOS transistor 110 becomes depletion type. However, the threshold voltage V _td can be set below 0 V. Thereby, even if the potential of the gate is 0 V, a drain current can flow through the channel by applying a drain voltage.

In addition, the back gate is connected to the P-type well region 4 via a region (not shown) containing high-concentration P-type impurities, and is also connected to the source.

The E-type NMOS transistor 120 has a P-type gate electrode 7 formed by _{implanting BF 2} and adjusts the impurity concentration of the P-type gate electrode 7 and the channel doped region so that the _{threshold voltage V te becomes 0 V or more.} In addition, a hydrogen barrier metal film 10 is arranged above the P-type gate electrode 7. Otherwise, the E-type NMOS transistor 120 is the same as the D-type NMOS transistor 110.

In addition, the shape, structure, size, material, and type and concentration of impurities of the P-type gate electrode 7 are not particularly limited, and can be appropriately selected according to the purpose.

On the upper surfaces of the D-type NMOS transistor 110 and the E-type NMOS transistor 120, the surfaces are planarized to form a BPSG film 8 as an interlayer insulating film. In the BPSG film 8, the metal wiring 9a to the metal wiring 9d are buried in the contact holes respectively formed so as to penetrate to the source-drain region 5 to form the source-drain regions. 5's conduction path.

Furthermore, in this embodiment, the interlayer insulating film is set as the BPSG film 8, but it is not limited to this. For example, it can also be set as a non-doped silicate glass (NSG) film and a BPSG film. The laminated structure of the film, the laminated structure of the Tetra-Ethyl-Ortho-Silicate (TEOS) film and the BPSG film, etc.

The hydrogen barrier metal film 10 electrically connected to the upper part of the metal wiring 9a to the metal wiring 9d contains AlSiCu. Since the hydrogen barrier metal film 10 is located above the P-type gate electrode 7, it prevents the hydrogen generated from the passivation film 11 or the like from moving from above, and prevents hydrogen from entering the E-type having the P-type gate electrode 7. The NMOS transistor 120 is blocked in the vicinity. That is, the semiconductor device 100 of the present embodiment has the hydrogen barrier metal film 10 that also functions as a metal wiring layer above the P-type gate electrode 7, so that it is possible to suppress the occurrence of damage without increasing the formed film. Undesirable conditions caused by hydrogen.

The material of the hydrogen barrier metal film 10 is not particularly limited and can be appropriately selected according to the purpose. However, in terms of the hydrogen barrier metal film 10 also serving as a metal wiring layer, an aluminum alloy is preferable. As the aluminum alloy, for example, in addition to AlSiCu, AlNd, AlCu, AlSi, etc. can be cited. In addition, it may also be an aspect in which tungsten is formed as a film on the titanium of the base. If tungsten is formed as a film on the titanium of the substrate, it is advantageous in that not only the tungsten prevents hydrogen from entering, but also the titanium of the substrate can absorb hydrogen.

Furthermore, in this embodiment, the hydrogen barrier metal film 10 is set to be larger than the area of the active region of the P-type gate electrode 7. However, as long as it can block the hydrogen diffused to the active region of the P-type gate electrode 7, it is not. Limited to this, the area of the hydrogen barrier metal film 10 can also be equal to or narrower than the active area of the P-type gate electrode 7.

The thickness of the hydrogen barrier metal film 10 is not particularly limited and can be appropriately selected according to the purpose. However, from the viewpoint of ensuring a thickness capable of blocking hydrogen, it is preferably 300 nm or more and 500 nm or less.

The size of the hydrogen barrier metal film 10 is not particularly limited, and can be appropriately selected according to the purpose, and it is preferably larger than the P-type gate electrode 7 in the active region in a plan view.

On the uppermost surface of the semiconductor device 100, a passivation film 11 is provided.

As the passivation film 11, a silicon nitride film is preferable. As a method of forming the silicon nitride film, when chemical vapor deposition (CVD) is used, the metal wiring 9a to the metal wiring 9d may melt, so plasma CVD is preferably used.

In addition, in this embodiment, the passivation film 11 is a single-layer structure of a silicon nitride film, but it is not limited to this. For example, it may be a two-layer structure of a silicon oxide film and a silicon nitride film. In addition, the shape, structure, and size of the passivation film 11 are not particularly limited, and can be appropriately selected according to the purpose.

In this way, the semiconductor device 100 of this embodiment has on the semiconductor substrate 1 an E-type NMOS transistor 120 for use in an ED-type reference voltage generating circuit, and includes a P-type gate electrode 7; a BPSG film 8, which is arranged on E On the NMOS transistor 120; and the hydrogen barrier metal film 10, which is disposed on the BPSG film 8 and near the upper side of the P-type gate electrode 7, to block hydrogen. Thereby, the semiconductor device 100 can suppress the occurrence of defects caused by hydrogen without increasing the film formed.

Next, a method of manufacturing the semiconductor device 100 of this embodiment will be described with reference to FIGS. 5A to 5C.

First, the semiconductor substrate 1 is prepared and subjected to LOCOS formation processing, and the separation oxide film 2 is formed on the semiconductor substrate 1.

Next, as shown in FIG. 5A, the conventional metal-oxide-semiconductor field-effect transistors (Metal-Oxide-Semiconductor transistors) such as gate oxide film formation processing, source-drain region formation processing, polysilicon gate electrode formation processing, etc. Field-Effect Transistor (MOSFET) manufacturing technology to form a gate oxide film 3, a P-type well region 4, a source-drain region 5, an N-type gate electrode 6, and a P-type gate electrode 7 on the semiconductor substrate 1 . Thereby, the D-type NMOS transistor 110 and the E-type NMOS transistor 120 are formed.

Specifically, in order to form the D-type NMOS transistor 110, firstly, boron is implanted into a part of each active region to form a P-type well region 4, and an N-type channel doped region is formed on a part of the surface of the P-type well region 4. Next, after the gate oxide film 3 is formed on the channel doped region, the polysilicon film formed on the gate oxide film 3 is implanted with 5×10 ¹⁶ /cm ³ or more and 1×10 ¹⁸ /cm ³ or less The low concentration of phosphorus forms the N-type gate electrode 6. Then, at a position under the gate oxide film 3 sandwiching the channel doped region, a high-concentration N-type source-drain region 5 of ^{1×10 19} /cm ^{3 or more is formed in the P-type well region 4} s surface.

Furthermore, these components are formed by performing photo mask processing on necessary parts.

In addition, the thickness of the polysilicon film is not particularly limited, and can be appropriately selected according to the purpose, and it is preferably 100 nm or more and 500 nm or less.

Next, as shown in FIG. 5B, the BPSG film 8 is formed on the entire surface area and planarized.

The method of forming the BPSG film 8 is not particularly limited, and can be appropriately selected according to the purpose.

The method for planarizing the BPSG film 8 is not particularly limited, and can be appropriately selected according to the purpose. For example, a reflow method, an etch back method, and a chemical mechanical polishing (CMP) method can be mentioned. Law and so on. Specifically, the reflow method can be flattened by heat treatment at 850°C or higher after forming an oxide film containing phosphorus or boron.

Next, contact holes are formed in the BPSG film 8 by photolithography and dry etching, and tungsten is embedded with titanium as a base, thereby forming metal wirings 9a to 9d. Then, the hydrogen barrier metal film 10 is formed by photolithography and etching. Since the hydrogen barrier metal film 10 also serves as a metal wiring layer, there are locations that are electrically connected to the upper part of the metal wiring 9a to the metal wiring 9d.

Next, after the BPSG film 8 is formed and planarized, the passivation film 11, which is a silicon nitride film, is formed on the BPSG film 8 and the hydrogen barrier metal film 10 by plasma CVD.

In this way, the manufacturing method of the semiconductor device 100 of this embodiment includes the step of forming an E-type NMOS transistor 120 which is disposed on the semiconductor substrate 1 and used in an ED-type reference voltage generating circuit , And including a P-type gate electrode 7; a step of forming a BPSG film 8 on the E-type NMOS transistor 120; and forming a hydrogen barrier metal that blocks hydrogen on the BPSG film 8 and near the upper portion of the P-type gate electrode 7. Film 10 steps. Thereby, the manufactured semiconductor device 100 can suppress the occurrence of defects caused by hydrogen without increasing the formed film.

Furthermore, in this embodiment, as shown in FIG. 6, the source terminal of the E-type NMOS transistor 120 and the hydrogen barrier metal film 10 can be integrated. Thereby, the area of the hydrogen barrier metal film 10 can be enlarged, and no gap is generated between the source terminal and the hydrogen barrier metal film 10, so hydrogen is less likely to diffuse to the E-type NMOS transistor 120 including the P-type gate electrode 7 In this regard, it is better.

[Second Embodiment] Fig. 7 is an explanatory diagram showing a cross section of a semiconductor device according to a second embodiment of the present invention. As shown in FIG. 7, in the second embodiment, in addition to the first embodiment shown in FIG. 3, a wide-area hydrogen barrier metal film 13 is arranged on the hydrogen barrier metal film 10 with a BPSG film 12 interposed therebetween.

The wide-area hydrogen barrier metal film 13 contains AlSiCu like the hydrogen barrier metal film 10. Since the wide-area hydrogen barrier metal film 13 is located above the P-type gate electrode 7 and the hydrogen barrier metal film 10, in addition to the hydrogen barrier metal film 10, the wide-area hydrogen barrier metal film 13 can also be used to block hydrogen from The intrusion of the E-type NMOS transistor 120 with the P-type gate electrode 7 can further suppress the occurrence of defects caused by hydrogen.

In addition, in the semiconductor device 100 of this embodiment, in the case of having a plurality of field effect transistors, the wide-area hydrogen barrier metal film 13 is preferably arranged on the hydrogen barrier in such a way as to cover the entire plurality of field effect transistors. Above the metal film 10.

[Third Embodiment] FIG. 8 is an explanatory diagram showing a cross-section of a semiconductor device according to a third embodiment of the present invention.

As shown in FIG. 8, in addition to the first embodiment shown in FIG. 3, in the third embodiment, a metal silicide of CoSi is formed on the upper part of the P-type gate electrode 7 and the upper part of the source-drain region 5. Film 14, metal silicide film 15. Thus, the semiconductor device 100 of this embodiment not only uses the hydrogen barrier metal film 10, but also uses the metal silicide film 14 and the metal silicide film 15 to block hydrogen from the E-type NMOS transistor 120 having the P-type gate electrode 7. Intrusion in the vicinity of, so it can further suppress the occurrence of problems caused by hydrogen.

Furthermore, in this embodiment, the metal silicide film 14 and the metal silicide film 15 are made of CoSi, but they are not limited to this. For example, they may be made of WSi, TiSi, NiSi, or the like.

As described above, the semiconductor device of one embodiment of the present invention includes: a semiconductor substrate; a field-effect transistor, which is arranged on the semiconductor substrate and used in an analog circuit, and includes a P-type gate electrode; an interlayer insulating film, It is arranged on the field effect transistor; and a hydrogen barrier metal film is arranged on the interlayer insulating film and is near the upper side of the P-type gate electrode to block hydrogen.

Thereby, the semiconductor device of one embodiment of the present invention can suppress the occurrence of defects caused by hydrogen without increasing the film formed.

Furthermore, in each embodiment described above, the D-type NMOS transistor 110 includes an N-type gate electrode 6, and the E-type NMOS transistor 120 includes a P-type gate electrode, but it is not limited to this. The NMOS transistor 110 may also include a P-type gate electrode.

In addition, in this embodiment, both the D-type NMOS transistor 110 and the E-type NMOS transistor 120 are NMOS transistors, but it is not limited to this, and both may be used as P-channel metal oxide semiconductors. (P-channel Metal-Oxide-Semiconductor, PMOS) transistor.

Furthermore, in each of the above-mentioned embodiments, the analog circuit is set as an ED-type reference voltage generating circuit, but it is not limited to this. For example, non-ED-type reference voltage generating circuits and ED-type reference voltage generating circuits may also be cited. The output of the NOR-ED type reference voltage generating circuit is connected to a circuit of at least one of a non-inverting input terminal and an inverting input terminal of a comparator, a current mirror circuit, and the like.

1: Semiconductor substrate 2: Separation oxide film 3: Gate oxide film 4: P-type well region 5: Source-drain region 6: N-type gate electrode 7: P-type gate electrode 8: BPSG film (interlayer Insulating film) 9a to 9f: Metal wiring 10: Hydrogen barrier metal film 11: Passivation film 12: BPSG film (interlayer insulating film) 13: Wide-area hydrogen barrier metal film 14, 15: Metal silicide film 100: Semiconductor device 100a: Power supply terminal 100b: Ground terminal 100c: Reference voltage terminal 110: Depletion NMOS transistor 120: Enhanced NMOS transistor AA: Line BB: Line VDD: Power supply voltage VSS: Ground voltage V _ref : Reference voltage

Fig. 1 is a circuit diagram showing an analog circuit of a semiconductor device according to a first embodiment of the present invention. Fig. 2 is a schematic plan view showing the semiconductor device according to the first embodiment of the present invention. Fig. 3 is an explanatory diagram showing a cross section taken along the line A-A in Fig. 2. Fig. 4 is an explanatory diagram showing a cross section taken along the line B-B in Fig. 2. 5A is an explanatory diagram showing a method of manufacturing the semiconductor device according to the first embodiment of the present invention. 5B is an explanatory diagram showing the method of manufacturing the semiconductor device according to the first embodiment of the present invention. 5C is an explanatory diagram showing the method of manufacturing the semiconductor device according to the first embodiment of the present invention. Fig. 6 is a schematic plan view showing a modification of the first embodiment of the present invention. Fig. 7 is an explanatory diagram showing a cross section of a semiconductor device according to a second embodiment of the present invention. FIG. 8 is an explanatory diagram showing a cross-section of a semiconductor device according to a third embodiment of the present invention.

100: Semiconductor device

100a: power terminal

100b: Ground terminal

100c: Reference voltage terminal

110: Depletion NMOS Transistor

120: Enhanced NMOS transistor

VDD: power supply voltage

VSS: Ground voltage

V _ref : reference voltage

Claims (10)

A semiconductor device characterized by comprising: Semiconductor substrate A field effect transistor, which is arranged on the semiconductor substrate and used in an analog circuit, and includes a P-type gate electrode; An interlayer insulating film disposed on the field effect transistor; and A hydrogen barrier metal film is disposed on the interlayer insulating film and is near the upper side of the P-type gate electrode, and blocks hydrogen. The semiconductor device according to claim 1, wherein with regard to the area of the hydrogen barrier metal film, when the semiconductor substrate is viewed from above, at least in the active region of the field effect transistor is the size of the P-type gate electrode Above area. The semiconductor device according to claim 1, wherein the hydrogen barrier metal film is an aluminum alloy. The semiconductor device according to claim 2, wherein the hydrogen barrier metal film is an aluminum alloy. The semiconductor device according to any one of claim 1 to claim 4, wherein the analog circuit is a reference voltage generating circuit. The semiconductor device according to claim 5, wherein the reference voltage generating circuit includes: a depletion type field effect transistor that generates a constant current; and an enhanced field effect transistor that generates a voltage based on the constant current; At least any one of the depletion mode field effect transistor and the enhanced field effect transistor is a field effect transistor including the P-type gate electrode. The semiconductor device according to any one of claims 1 to 4, which further has a wide-area hydrogen barrier metal film, and when there are a plurality of field-effect transistors, when the semiconductor substrate is overlooked , And arranged above the hydrogen barrier metal film in a manner of covering the whole or part of the plurality of field effect transistors. The semiconductor device according to claim 5, which further has a wide-area hydrogen barrier metal film, and when there are multiple field-effect transistors, when the semiconductor substrate is viewed from above, a plurality of field-effect transistors can be covered. The whole or part of the transistor is arranged above the hydrogen barrier metal film. The semiconductor device according to any one of claims 1 to 4, wherein a metal silicide film is formed on the upper portion of the P-type gate electrode. A method for manufacturing a semiconductor device, which is characterized by comprising the step of forming a field-effect transistor, which is arranged on a semiconductor substrate and used in an analog circuit, and includes a P-type gate electrode; Forming an interlayer insulating film on the field effect transistor; and A step of forming a hydrogen barrier metal film that blocks hydrogen on the interlayer insulating film and in the vicinity of the upper side of the P-type gate electrode.

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