JP2024059850A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

[Problem] To provide a semiconductor device capable of suppressing the occurrence of defects due to hydrogen without increasing the number of films formed. [Solution] A semiconductor device 100 having a semiconductor substrate 1, a field effect transistor 120 disposed on the semiconductor substrate 1 and used in an analog circuit, the field effect transistor 120 having a P-type gate electrode 7, an interlayer insulating film 8 disposed on the field effect transistor 120, and a hydrogen barrier metal film 10 disposed on the interlayer insulating film 8 in the vicinity of the upper part of the P-type gate electrode 7, for blocking hydrogen. [Selected Figure] Figure 1

Description

The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device.

Among the semiconductor devices in which minute elements are formed on a semiconductor substrate such as silicon, there are analog semiconductor devices that combine semiconductor elements such as MISFETs (Metal-Insulator-Semiconductor Field-Effect Transistors), resistor elements, and fuse elements.

Examples of analog semiconductor devices include voltage regulators, voltage detectors, and switching regulators. With the development of wearable devices and the Internet of Things (IoT), these analog semiconductor devices have been developed that can be driven for long periods of time at low voltages and low current consumption using secondary batteries or the like. In particular, when a power management IC such as a voltage regulator is equipped with a reference voltage generation circuit, it is important to reduce the variation in the reference voltage and to ensure long-term stability.
However, in the MISFETs used in such reference voltage generating circuits, dangling bonds (non-bonding hands) present at the interface between the gate oxide film and the silicon substrate can bind to hydrogen generated from the passivation film or the like, causing the threshold voltage to vary during manufacturing or to change over time.

Therefore, for example, a semiconductor device has been proposed in which a silicon nitride film for blocking hydrogen is formed on N-channel MOS transistors, etc., to prevent hydrogen from diffusing into the N-channel MOS transistors, etc. (see, for example, Patent Document 1).

JP 2003-152100 A

One aspect of the present invention aims to provide a semiconductor device that can suppress the occurrence of defects caused by hydrogen without increasing the number of films formed.

The semiconductor device according to an embodiment of the present invention comprises:
A semiconductor substrate;
a field effect transistor disposed on the semiconductor substrate, used in an analog circuit, and having a P-type gate electrode;
an interlayer insulating film disposed on the field effect transistor;
a hydrogen barrier metal film disposed on the interlayer insulating film and in the vicinity above the P-type gate electrode, the hydrogen barrier metal film blocking hydrogen;
has.

According to one aspect of the present invention, it is possible to provide a semiconductor device that can suppress the occurrence of defects caused by hydrogen without increasing the number of films formed.

FIG. 1 is a circuit diagram showing an analog circuit of a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a schematic plan view showing the semiconductor device according to the first embodiment of the present invention. FIG. 3 is an explanatory diagram showing a cross section taken along line AA in FIG. FIG. 4 is an explanatory diagram showing a cross section taken along line BB in FIG. FIG. 5A is an explanatory diagram showing a method for manufacturing a semiconductor device according to the first embodiment of the present invention. FIG. 5B is an explanatory diagram showing a method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 5C is an explanatory diagram showing a method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 6 is a schematic plan view showing a modified example of the first embodiment of the present invention. FIG. 7 is an explanatory diagram showing a cross section of a semiconductor device according to a second embodiment of the present invention. FIG. 8 is an explanatory diagram showing a cross section of a semiconductor device according to a third embodiment of the present invention.

A semiconductor device according to one embodiment of the present invention includes a semiconductor substrate, a field effect transistor disposed on the semiconductor substrate and used in an analog circuit, the field effect transistor having a P-type gate electrode, an interlayer insulating film disposed on the field effect transistor, and a hydrogen barrier metal film disposed on the interlayer insulating film adjacent to and above the P-type gate electrode, for blocking hydrogen.

The semiconductor device according to one embodiment of the present invention is based on the following findings.
The characteristics required for analog semiconductor devices are significantly different from those required for logic semiconductor devices that handle binary signals. For example, in charge/discharge control circuits for secondary batteries such as lithium ion batteries, in recent years, there have been many cases where specifications in μV units are required in order to minimize discharge of secondary batteries used in mobile devices and the like. Reliability in μV units is also required for the reference voltage generation circuits used in these charge/discharge control circuits. For this reason, it is necessary to reduce the variation in threshold voltage of field effect transistors (hereinafter referred to as "MOS transistors") included in the reference voltage generation circuits and the changes over time that may be shown in long-term reliability tests.

When forming this MOS transistor, impurities such as boron, phosphorus, and arsenic are often injected into the polysilicon film to form the gate electrode. Boron, which is injected as an impurity, diffuses more easily into the polysilicon film than phosphorus or arsenic, and can even diffuse into the gate oxide film underneath the polysilicon film. This makes the quality of the gate oxide film more likely to deteriorate than when phosphorus or arsenic is injected, and it is thought that it becomes easier for tiny atoms such as hydrogen to pass through. If even a small amount of hydrogen generated from a passivation film or the like bonds with the dangling bonds (non-bonding hands) that exist at the interface between the gate oxide film and the silicon substrate, in analog semiconductor devices that require adjustment in μV units, the threshold voltage may vary during manufacturing or change over time.

In this regard, in the semiconductor device described in Patent Document 1, a silicon nitride film for blocking hydrogen is placed on the P-type gate electrode. However, not only does this increase the number of steps required to form the silicon nitride film, but the threshold voltage may also change due to the stress of the silicon nitride film placed near the P-type gate electrode.

In one embodiment of the present invention, the semiconductor device uses a hydrogen barrier metal film by expanding the area of the metal wiring layer disposed above the MOS transistor. In other words, this semiconductor device can block hydrogen generated from passivation films and the like by disposing a hydrogen barrier metal film that also serves as a metal wiring layer in the vicinity of the upper part of the P-type gate electrode, where the threshold voltage is easily changed, thereby suppressing the occurrence of defects caused by hydrogen without increasing the number of films formed.

Next, as an example of a semiconductor device according to one embodiment of the present invention, an embodiment in which the analog circuit is an ED-type reference voltage generating circuit will be described with reference to the drawings.

The drawings are schematic, and the relationship between film thickness and planar dimensions, the ratio of each film thickness, etc. are not as shown in the drawings. In addition, in a semiconductor substrate, the surface on which other films or layers are stacked using a semiconductor manufacturing process is referred to as the "top surface," and the surface opposite the top surface is referred to as the "bottom surface." Furthermore, in the following, the number, position, shape, structure, size, etc. of multiple films and semiconductor elements obtained by structurally combining these are not limited to the embodiments shown below, and can be any number, position, shape, structure, size, etc. that is preferable for implementing the present invention.

[First embodiment]
(Semiconductor device)
1 is a circuit diagram showing an analog circuit of a semiconductor device according to a first embodiment of the present invention. As shown in FIG 1, a semiconductor device 100 according to this embodiment is provided with an ED type reference voltage generating circuit, which is an analog circuit, and has a depletion type N-channel field effect transistor 110 and an enhancement type N-channel field effect transistor 120.
In the following, a "depletion type N-channel field effect transistor" may be referred to as a "D-type NMOS transistor", and an "enhancement type N-channel field effect transistor" may be referred to as an "E-type NMOS transistor".

When a power supply voltage VDD is applied to the drain connected to the power supply terminal 100a, the D-type NMOS transistor 110 functions as a constant current source that supplies a constant current independent of the power supply voltage VDD from the source to the E-type NMOS transistor 120. The E-type NMOS transistor 120 generates a reference voltage _Vref at the reference voltage terminal 100c based on the constant current supplied from the D-type NMOS transistor 110. In this manner, the ED-type reference voltage generating circuit is formed by combining the D-type NMOS transistor 110 and the E-type NMOS transistor 120.

The source of the D-type NMOS transistor 110 is connected to the gate, backgate, and reference voltage terminal 100c of the D-type NMOS transistor 110, as well as the gate and drain of the E-type NMOS transistor 120, and these are at the same potential. In addition, the source of the E-type NMOS transistor 120 is connected to the backgate and ground terminal 100b, and these are at the same potential.

Here, if the drain current I _d1 of the D-type NMOS transistor 110 is calculated, and the mutual conductance during non-saturation or saturated operation is gmD, it can be expressed as in the following formula (1). As described above, since the gate and source of the D-type NMOS transistor 110 are connected, the gate-source voltage V _g1 in the following formula (1) is 0 V. Therefore, the drain current I _d1 , which is the output current of the D-type NMOS transistor 110, depends on the threshold voltage V _td .
I _d1 = 1/2 · gmD · (V _g1 - V _td ) ²
= 1/2 · gmD · (| _Vtd |) ² ... (1)

Next, the drain current _Id2 of the E-type NMOS transistor 120 can be expressed by the following formula (2) if the mutual conductance during saturation operation is gmE. As described above, the gate and drain of the E-type NMOS transistor 120 are connected, and further connected to the reference voltage terminal 100c, so that the gate-source voltage _Vg2 in the following formula (2) is the reference voltage _Vref . Therefore, the drain current _Id2 depends on the threshold voltage Vte and the reference voltage _Vref .
I _d2 = 1/2 gmE (V _g2 - V _te ) ²
= 1/2 gmE ( _Vref - _Vte ) ² (2)

From the above, since I _d1 in the above formula (1) is equal to I _d2 in the above formula (2), the reference voltage V _ref is expressed by the following formula (3).
_Vref≈Vte +( _gmD /gmE)1/2·| _Vtd | ... (3)

Fig. 2 is a schematic plan view showing a semiconductor device according to a first embodiment of the present invention, showing an ED type reference voltage generating circuit formed on a semiconductor substrate. Fig. 2 shows, of the structure of the semiconductor device 100, an N-type gate electrode 6, a P-type gate electrode 7, a hydrogen barrier metal film 10 also functioning as a metal wiring layer, and metal wirings 9a to 9f connected to the hydrogen barrier metal film 10. The dashed lines in Fig. 2 indicate the active regions of a D-type NMOS transistor 110 and an E-type NMOS transistor 120, respectively.
Note that a plan view refers to a view (top view) of a semiconductor substrate as viewed from its normal direction.

When viewed from above the semiconductor substrate (in the direction normal to the substrate), the hydrogen barrier metal film 10 on the active region indicated by the dashed line on the E-type NMOS transistor 120 side is wider than the area of the P-type gate electrode 7 and is disposed so as to cover the P-type gate electrode 7.

Here, the cross sections of the D-type NMOS transistor 110 and the E-type NMOS transistor 120 will be described with reference to Figures 3 and 4.

Fig. 3 is an explanatory diagram showing a cross section taken along line AA in Fig. 2. Fig. 4 is an explanatory diagram showing a cross section taken along line BB in Fig. 2.
3 and 4, the semiconductor device includes a semiconductor substrate 1, an isolation oxide film 2, a gate oxide film 3, a P-type well region 4, a source/drain region 5, an N-type gate electrode 6, a P-type gate electrode 7, a silicon oxide film doped with phosphorus and boron (hereinafter referred to as a "BPSG (Boro-Phospho Silicate Glass) film") 8, metal wiring 9, a hydrogen barrier metal film 10, and a passivation film 11. The D-type NMOS transistor 110 and the E-type NMOS transistor 120 are formed on the semiconductor substrate 1 by structurally combining the isolation oxide film 2, the gate oxide film 3, the P-type well region 4, the source/drain region 5, the N-type gate electrode 6, and the P-type gate electrode 7.

The semiconductor substrate 1 is a wafer-shaped P-type silicon semiconductor substrate.
In this embodiment, the semiconductor substrate 1 is a wafer-shaped P-type silicon semiconductor substrate, but this is not limited to this, and the shape, structure, size, material, and polarity of the semiconductor substrate 1 can be appropriately selected depending on the purpose.

The isolation oxide film 2 is a LOCOS (LOCal Oxidation of Silicon) formed on the semiconductor substrate 1. The isolation oxide film 2 is provided on the outer edge of each active region in order to isolate the D-type NMOS transistor 110 and the E-type NMOS transistor 120.
In this embodiment, LOCOS is formed to isolate the D-type NMOS transistor 110 and the E-type NMOS transistor 120. However, this is not limited to this, and isolation may be achieved by forming, for example, STI (Shallow Trench Isolation) or the like.

The D-type NMOS transistor 110 has a gate oxide film 3, a P-type well region 4, source/drain regions 5, and an N-type gate electrode 6 formed by implanting phosphorus into a polysilicon film.

In the D-type NMOS transistor 110, the impurity concentration is adjusted so that the difference in work function between the P-type well region 4 and the N-type gate electrode 6 is large, and therefore an electric field in the inverted direction is applied to the surface of the P-type semiconductor substrate 1, resulting in a low threshold voltage. Furthermore, since the threshold voltage can be lowered by the N-type channel doped region, the impurity implantation into the N-type gate electrode 6 and the channel doped region is appropriately controlled so that the D-type NMOS transistor 110 becomes a depletion type, and the threshold voltage _Vtd can be made 0V or less. As a result, even if the gate potential is 0V, a drain current can be made to flow through the channel by applying a drain voltage.
The back gate is connected to the P-type well region 4 via a region (not shown) containing a high concentration of P-type impurities, and is also connected to the source.

The E-type NMOS transistor 120 has a P-type gate electrode 7 formed by implanting BF2, and the impurity concentrations of the P-type gate electrode 7 and the channel doped region are adjusted so that the threshold voltage Vte is equal to or higher than 0 V. In addition, a hydrogen barrier metal film 10 is disposed above the P-type gate electrode 7. Other than these, the E-type NMOS transistor 120 is similar to the D-type NMOS transistor 110.
The shape, structure, size, material, and type and concentration of impurities of the P-type gate electrode 7 are not particularly limited and can be appropriately selected depending on the purpose.

A BPSG film 8 serving as an interlayer insulating film is formed with its surface planarized on the upper surfaces of the D-type NMOS transistor 110 and the E-type NMOS transistor 120. Metal wirings 9a to 9d are embedded in contact holes formed in the BPSG film 8 so as to penetrate to the source/drain regions 5, respectively, to form conductive paths from the source/drain regions 5.
In this embodiment, the interlayer insulating film is the BPSG film 8, but is not limited to this and may be, for example, a laminated structure of a non-doped silicate glass (NSG) film and a BPSG film, or a laminated structure of a tetra-ethyl-ortho-silicate (TEOS) film and a BPSG film.

The hydrogen barrier metal film 10, which is electrically connected to the upper part of the metal wiring 9a to 9d, is made of AlSiCu. Since this hydrogen barrier metal film 10 exists above the P-type gate electrode 7, it can block the movement of hydrogen from sources such as the passivation film 11 from above, preventing it from entering the vicinity of the E-type NMOS transistor 120 having the P-type gate electrode 7. In other words, the semiconductor device 100 of this embodiment can suppress the occurrence of defects caused by hydrogen without increasing the number of films formed, because the hydrogen barrier metal film 10, which also functions as a metal wiring layer, exists above the P-type gate electrode 7.

The material of the hydrogen barrier metal film 10 is not particularly limited and can be appropriately selected depending on the purpose, but an aluminum alloy is preferable because the hydrogen barrier metal film 10 also serves as a metal wiring layer. Examples of the aluminum alloy include AlSiCu, AlNd, AlCu, and AlSi. In addition, a tungsten film may be formed on the titanium substrate. The tungsten film formed on the titanium substrate is advantageous in that the tungsten prevents hydrogen from penetrating and the titanium substrate can absorb hydrogen.
In this embodiment, the hydrogen barrier metal film 10 is made wider than the area of the active region of the P-type gate electrode 7, but this is not limited to this and the area of the hydrogen barrier metal film 10 may be equal to or narrower than the active region of the P-type gate electrode 7 as long as it can block hydrogen diffusing into the active region of the P-type gate electrode 7.

There are no particular limitations on the thickness of the hydrogen-blocking metal film 10 and it can be selected appropriately depending on the purpose, but a thickness of 300 nm or more and 500 nm or less is preferable in order to ensure a thickness that can block hydrogen.

There is no particular limit to the size of the hydrogen barrier metal film 10 and it can be selected appropriately depending on the purpose, but it is preferable that it is larger than the P-type gate electrode 7 in the active region when viewed in a plan view.

A passivation film 11 is provided on the top surface of the semiconductor device 100 .
A silicon nitride film is preferable as the passivation film 11. When low-pressure CVD (Chemical Vapor Deposition) is used as a method for forming the silicon nitride film, the metal wirings 9a to 9d may melt, so it is preferable to use plasma CVD.
In this embodiment, the passivation film 11 has a single-layer structure of a silicon nitride film, but is not limited thereto, and may have, for example, a two-layer structure of a silicon oxide film and a silicon nitride film. The shape, structure, and size of the passivation film 11 are not particularly limited, and may be appropriately selected according to the purpose.

In this way, the semiconductor device 100 of this embodiment has, on a semiconductor substrate 1, an E-type NMOS transistor 120 used in an ED-type reference voltage generating circuit and equipped with a P-type gate electrode 7, a BPSG film 8 disposed on the E-type NMOS transistor 120, and a hydrogen barrier metal film 10 disposed on the BPSG film 8 and adjacent to the upper portion of the P-type gate electrode 7 to block hydrogen. As a result, the semiconductor device 100 can suppress the occurrence of defects due to hydrogen without increasing the number of films to be formed.

Next, a method for manufacturing the semiconductor device 100 of this embodiment will be described with reference to Figures 5A to 5C.

First, a semiconductor substrate 1 is prepared and subjected to a LOCOS forming process to form an isolation oxide film 2 on the semiconductor substrate 1 .
5A, a gate oxide film 3, a P-type well region 4, a source/drain region 5, an N-type gate electrode 6, and a P-type gate electrode 7 are formed on the semiconductor substrate 1 by conventional MOSFET manufacturing techniques such as a gate oxide film formation process, a source/drain region formation process, and a gate electrode formation process using polysilicon. This forms a D-type NMOS transistor 110 and an E-type NMOS transistor 120.

Specifically, to form the D-type NMOS transistor 110, first, boron is implanted into a part of each active region to form a P-type well region 4, and an N-type channel doped region is formed in a part of the surface of the P-type well region 4. Next, a gate oxide film 3 is formed on this channel doped region, and then phosphorus is implanted at a low concentration of 5×10 ¹⁶ to 1×10 ¹⁸ /cm ³ into the polysilicon film formed on the gate oxide film 3 to form an N-type gate electrode 6. Then, N-type source/drain regions 5 with a high concentration of 1×10 ¹⁹ /cm ³ or more are formed on the surface of the P-type well region 4 at positions sandwiching the channel doped region below the gate oxide film 3.
These are formed by performing a photomask treatment on the necessary parts.
The thickness of the polysilicon film is not particularly limited and can be appropriately selected depending on the purpose, but is preferably 100 nm or more and 500 nm or less.

Next, as shown in FIG. 5B, a BPSG film 8 is formed over the entire surface and then planarized.
The method for forming the BPSG film 8 is not particularly limited and can be appropriately selected depending on the purpose.
The method for planarizing the BPSG film 8 is not particularly limited and may be appropriately selected depending on the purpose, and examples thereof include a reflow method, an etch-back method, a CMP (Chemical Mechanical Polishing) method, etc. Specifically, the reflow method may be performed by forming an oxide film containing phosphorus or boron, and then planarizing the film by heat treatment at 850° C. or higher.

Next, contact holes are opened in the BPSG film 8 by photolithography and dry etching, and tungsten is filled in using titanium as a base to form metal wiring 9a-9d. Then, photolithography and etching are used to form the hydrogen barrier metal film 10. This hydrogen barrier metal film 10 also serves as a metal wiring layer, so there are locations where it is electrically connected to the upper portions of the metal wiring 9a-9d.

Next, a BPSG film 8 is formed and planarized, and then a passivation film 11, which is a silicon nitride film, is formed on the BPSG film 8 and the hydrogen barrier metal film 10 by plasma CVD.

In this way, the semiconductor device 100 of this embodiment includes a process of forming an E-type NMOS transistor 120 that is disposed on a semiconductor substrate 1 and is used in an ED-type reference voltage generating circuit and has a P-type gate electrode 7, a process of forming a BPSG film 8 on the E-type NMOS transistor 120, and a process of forming a hydrogen barrier metal film 10 that blocks hydrogen on the BPSG film 8 and in the vicinity above the P-type gate electrode 7. As a result, the manufactured semiconductor device 100 can suppress the occurrence of defects due to hydrogen without increasing the number of films to be formed.

In this embodiment, the source terminal of the E-type NMOS transistor 120 and the hydrogen barrier metal film 10 may be integrated as shown in FIG. 6. This allows the area of the hydrogen barrier metal film 10 to be increased, and there is no gap between the source terminal and the hydrogen barrier metal film 10, which is preferable in that hydrogen is less likely to diffuse into the E-type NMOS transistor 120 having the P-type gate electrode 7.

Second Embodiment
7 is an explanatory diagram showing a cross section of a semiconductor device according to a second embodiment of the present invention. As shown in Fig. 7, in the second embodiment, in addition to the first embodiment shown in Fig. 3, a global hydrogen barrier metal film 13 is disposed on a hydrogen barrier metal film 10 with a BPSG film 12 interposed therebetween.
The global hydrogen barrier metal film 13 is made of AlSiCu, like the hydrogen barrier metal film 10. Since the global hydrogen barrier metal film 13 exists above the P-type gate electrode 7 and the hydrogen barrier metal film 10, the global hydrogen barrier metal film 13 in addition to the hydrogen barrier metal film 10 can block the intrusion of hydrogen into the E-type NMOS transistor 120 having the P-type gate electrode 7, thereby further suppressing the occurrence of defects due to hydrogen.

In addition, when the semiconductor device 100 of this embodiment has multiple field effect transistors, it is preferable that the wide area hydrogen barrier metal film 13 is disposed above the hydrogen barrier metal film 10 so as to cover the entire multiple field effect transistors.

[Third embodiment]
FIG. 8 is an explanatory diagram showing a cross section of a semiconductor device according to a third embodiment of the present invention.
8, in the third embodiment, in addition to the first embodiment shown in FIG 3, CoSi metal silicide films 14, 15 are formed on the upper part of the P-type gate electrode 7 and on the upper part of the source/drain region 5. As a result, the semiconductor device 100 of this embodiment can block the intrusion of hydrogen in the vicinity of the E-type NMOS transistor 120 having the P-type gate electrode 7 by the metal silicide films 14, 15 in addition to the hydrogen barrier metal film 10, and therefore can further suppress the occurrence of defects due to hydrogen.
In this embodiment, the metal silicide films 14 and 15 are made of CoSi, but the material is not limited to CoSi and may be, for example, WSi, TiSi, NiSi, or the like.

As described above, a semiconductor device in one embodiment of the present invention includes a semiconductor substrate, a field effect transistor disposed on the semiconductor substrate, used in an analog circuit, and having a P-type gate electrode, an interlayer insulating film disposed on the field effect transistor, and a hydrogen barrier metal film disposed on the interlayer insulating film in the vicinity of and above the P-type gate electrode, which blocks hydrogen.
As a result, the semiconductor device according to one embodiment of the present invention can suppress the occurrence of defects due to hydrogen without increasing the number of films to be formed.

In each of the above embodiments, the D-type NMOS transistor 110 has an N-type gate electrode 6, and the E-type NMOS transistor 120 has a P-type gate electrode, but this is not limited to the above, and the D-type NMOS transistor 110 may have a P-type gate electrode.
In addition, in this embodiment, both the D-type NMOS transistor 110 and the E-type NMOS transistor 120 are NMOS transistors, but this is not limiting, and both may be PMOS transistors.

In the above embodiments, the analog circuit is an ED-type reference voltage generating circuit, but this is not limited to this. For example, a non-ED-type reference voltage generating circuit, a circuit in which the output of an ED-type or non-ED-type reference voltage generating circuit is connected to at least one of the non-inverting input terminal and the inverting input terminal of a comparator, a current mirror circuit, etc. can be used.

1. Semiconductor substrate
2. Separation oxide film
3. Gate oxide film
4 P-type well region
5. Source/drain region
6 N-type gate electrode
7 P-type gate electrode
8 BPSG film (interlayer insulating film)
9 Metal wiring 10 Hydrogen barrier metal film 11 Passivation film 12 BPSG film (interlayer insulating film)
13 Wide-area hydrogen barrier metal film 14, 15 Metal silicide film 100 Semiconductor device 110 Depletion-type NMOS transistor 120 Enhancement-type NMOS transistor

Claims (8)

A semiconductor substrate;
a field effect transistor disposed on the semiconductor substrate, used in an analog circuit, and having a P-type gate electrode;
an interlayer insulating film disposed on the field effect transistor;
a hydrogen barrier metal film disposed on the interlayer insulating film and in the vicinity of an upper portion of the P-type gate electrode, the hydrogen barrier metal film also serving as a metal wiring layer and blocking hydrogen with a wide wiring area;
A semiconductor device comprising: The semiconductor device according to claim 1, wherein the area of the hydrogen barrier metal film is equal to or greater than the area of the P-type gate electrode at least in the active region of the field effect transistor when the semiconductor substrate is viewed in plan. The semiconductor device according to claim 1 or 2, wherein the hydrogen barrier metal film is an aluminum alloy. The semiconductor device according to any one of claims 1 to 3, wherein the analog circuit is a reference voltage generating circuit. the reference voltage generating circuit includes a depletion type field effect transistor that generates a constant current, and an enhancement type field effect transistor that generates a voltage based on the constant current,
5. The semiconductor device according to claim 4, wherein at least one of the depletion type field effect transistor and the enhancement type field effect transistor is a field effect transistor having the P-type gate electrode. The semiconductor device according to any one of claims 1 to 5, further comprising a wide-area hydrogen barrier metal film disposed above the hydrogen barrier metal film so as to cover all or part of the field effect transistor when the semiconductor substrate is viewed in plan. The semiconductor device according to any one of claims 1 to 6, wherein a metal silicide film is formed on the upper part of the P-type gate electrode. forming a field effect transistor disposed on a semiconductor substrate and used in an analog circuit, the field effect transistor having a P-type gate electrode;
forming an interlayer insulating film on the field effect transistor;
forming a hydrogen barrier metal film on the interlayer insulating film in the vicinity of an upper portion of the P-type gate electrode, the hydrogen barrier metal film also serving as a metal wiring layer and blocking hydrogen over a wide wiring area;
2. A method for manufacturing a semiconductor device comprising the steps of:

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