TW202115897A - Semiconductor materal substrate, micro light emitting diode panel and method of fabricating the same - Google Patents

Abstract

A method of fabricating a micro light emitting diode panel including forming a semiconductor material substrate, forming a plurality of transistor devices, transferring and bonding the transistor devices to a circuit substrate and transferring a plurality of micro light emitting diode devices from a micro light emitting diode device substrate to the circuit substrate is provided. The semiconductor material substrate has a carrier, a release layer, an inorganic insulation layer and a semiconductor material layer. The release layer is positioned between the carrier and the inorganic insulation layer and the semiconductor material layer is bonded to the release layer via the inorganic insulation layer. The electron mobility of the semiconductor material layer is higher than 20 cm² /V·s. The transistor devices are disposed on the release layer. The transistor devices are electrically connected to the circuit substrate and the micro light emitting diode devices are electrically connected to the transistor devices. A micro light emitting diode panel is also provided.

Description

Semiconductor material substrate, miniature light-emitting diode panel and manufacturing method thereof

The invention relates to a transfer technology of micro-components, and more particularly to a semiconductor material substrate, a micro-light-emitting diode panel and a manufacturing method thereof.

In recent years, when the manufacturing cost of organic light-emitting diode (OLED) display panels is too high and their service life cannot compete with the current mainstream displays, micro LED displays (Micro LED Display) has gradually attracted the investment attention of major technology manufacturers. Miniature light-emitting diode displays have optical performance equivalent to organic light-emitting diode display technology, such as high color saturation, fast response speed and high contrast, and have the advantages of low energy consumption and long material life.

With the gradual increase in display size and resolution, the operating electrical properties of the transistor elements used in the display panel, such as electron mobility, are bound to be improved. Among them, low temperature poly-silicon thin film transistors (LTPS TFTs) are widely used in small-size and high-resolution display panels due to their high electron mobility. However, the channel layer of this type of transistor is usually formed by an excimer laser annealing (ELA) process to form a polysilicon film. Therefore, due to the size limitation of the process equipment and the difficulty of controlling the process uniformity, large-size display panels still cannot use such high-mobility transistors as drive switches. How to solve the above problems has become an important issue for related manufacturers.

The present invention provides a semiconductor material substrate with better driving capability of miniature light-emitting diodes.

The invention provides a method for manufacturing a miniature light emitting diode panel, which has lower production cost and can increase the design margin of the product.

The invention provides a miniature light-emitting diode panel, which has both cost advantages and better operating electrical properties.

The semiconductor material substrate of the present invention includes a carrier, a sacrificial layer, an inorganic insulating layer, and a semiconductor material layer. The sacrificial layer is arranged on the carrier board. The sacrificial layer is located between the carrier board and the inorganic insulating layer. The semiconductor material layer is arranged on the inorganic insulating layer. The semiconductor material layer is connected to the sacrificial layer through the inorganic insulating layer. The electron mobility of the semiconductor material layer is greater than 20 cm ² /V·s.

In an embodiment of the present invention, the carrier of the aforementioned semiconductor material substrate is a sapphire substrate.

In an embodiment of the present invention, the sacrificial layer of the aforementioned semiconductor material substrate is an epitaxial semiconductor layer, and the inorganic insulating layer is a silicon oxide layer.

In an embodiment of the present invention, the semiconductor material layer of the aforementioned semiconductor material substrate is a single crystal silicon material layer.

The manufacturing method of the micro light emitting diode panel of the present invention includes forming a semiconductor material substrate, forming a plurality of transistor elements, transferring and bonding the plurality of transistor elements to a circuit substrate, and self-containing the plurality of micro light emitting diode elements. The micro light emitting diode device substrate is transferred to the circuit substrate. The semiconductor material substrate includes a carrier, a sacrificial layer, an inorganic insulating layer, and a semiconductor material layer. The sacrificial layer is located between the carrier board and the inorganic insulating layer, the semiconductor material layer is joined to the sacrificial layer through the inorganic insulating layer, and the electron mobility of the semiconductor material layer is greater than 20 cm ² /V·s. A plurality of transistor elements are arranged on the sacrificial layer. A plurality of transistor elements are electrically connected to the circuit substrate, and a plurality of micro light emitting diode elements are electrically connected to these transistor elements.

In an embodiment of the present invention, the transfer step of the plurality of transistor elements in the method for manufacturing a micro light emitting diode panel described above includes transferring these transistor elements to a temporary substrate and using the temporary substrate to transfer these transistor elements. And bonded on the circuit board.

In an embodiment of the present invention, the transfer step of the plurality of transistor elements in the manufacturing method of the above-mentioned micro light emitting diode panel includes removing the sacrificial layer to separate the transistor elements from the carrier.

In an embodiment of the present invention, in the above-mentioned method for manufacturing a micro light emitting diode panel, the step of forming a transistor element includes removing a part of the semiconductor material layer to form a semiconductor pattern.

In an embodiment of the present invention, in the above-mentioned method for manufacturing a micro light emitting diode panel, the step of forming a transistor element further includes forming a source electrode and a drain electrode, a gate insulating layer and a gate electrode on the semiconductor pattern. The source electrode and the drain electrode are respectively electrically connected to two different regions of the semiconductor pattern, and the gate insulating layer covers the source electrode, the drain electrode and a part of the semiconductor pattern.

In an embodiment of the present invention, in the above-mentioned method for manufacturing a miniature light emitting diode panel, after the transistor element is bonded to the circuit substrate, the source, drain and gate are located between the semiconductor pattern and the circuit substrate.

In an embodiment of the present invention, in the above-mentioned method for manufacturing a micro light emitting diode panel, the step of forming a transistor element further includes forming a first pad and a second pad. The first pad and the second pad are electrically connected to the source electrode and the drain electrode, respectively, and the transistor element is connected to the circuit substrate through the first pad, the second pad and the gate electrode.

In an embodiment of the present invention, the first pad, the second pad, and the gate of the method for manufacturing a micro light emitting diode panel are formed by patterning the same film layer.

In an embodiment of the present invention, the above-mentioned manufacturing method of the micro light emitting diode panel further includes forming a flat layer to cover the transistor element and the micro light emitting diode element, and forming a conductive layer on the flat layer. The flat layer has an opening exposing the top surface of the micro light emitting diode device, and the conductive layer passes through the opening to electrically connect the micro light emitting diode device.

In an embodiment of the present invention, the manufacturing method of the above-mentioned micro light emitting diode panel further includes forming a plurality of conductive patterns on the circuit substrate after the plurality of transistor elements are transferred to the circuit substrate. A part of these conductive patterns are respectively electrically connected to a plurality of transistor elements, and a plurality of micro light emitting diode elements are respectively bonded and electrically connected to another part of these conductive patterns.

In an embodiment of the present invention, in the above-mentioned method for manufacturing a micro light emitting diode panel, the step of forming a transistor element includes removing part of the inorganic insulating layer to form an insulating pattern. The insulating pattern overlaps the transistor element.

In an embodiment of the present invention, in the above-mentioned method for manufacturing a micro light emitting diode panel, after the transistor element is transferred and bonded to the circuit substrate, the transistor element is located between the circuit substrate and the insulating pattern.

The micro light emitting diode panel of the present invention includes a circuit substrate, a plurality of transistor elements, and a plurality of micro light emitting diode elements. A plurality of transistor elements are arranged on the circuit substrate, and each has a semiconductor pattern, a source electrode, a drain electrode, and a gate electrode. The source electrode and the drain electrode are electrically connected to the semiconductor pattern, and the source electrode, the drain electrode and the gate electrode are located between the semiconductor pattern and the circuit substrate. The electron mobility of the semiconductor pattern is greater than 20 cm ² /V·s. A plurality of miniature light-emitting diode elements are arranged on the circuit substrate, and are electrically connected to a plurality of transistor elements, respectively.

In an embodiment of the present invention, the circuit substrate of the aforementioned micro light emitting diode panel has a plurality of signal lines, and the signal lines are electrically connected to the gates, the sources, and the gates of the transistors. Multiple miniature light-emitting diode elements.

In an embodiment of the present invention, the aforementioned micro light emitting diode panel further includes a flat layer and a conductive layer. The flat layer is arranged on the circuit substrate and covers a plurality of transistor elements and a plurality of micro light emitting diode elements. The conductive layer covers the flat layer, and the flat layer has a plurality of openings overlapping the micro light emitting diode elements. The conductive layer extends into the openings to electrically connect a plurality of miniature light-emitting diode devices.

Based on the above, in the miniature light-emitting diode panel and the manufacturing method thereof according to an embodiment of the present invention, a plurality of transistor elements pre-formed on the carrier are transferred to the circuit substrate through a transfer process, which can reduce production costs and increase The design margin of the product. On the other hand, since the semiconductor material layer of the semiconductor material substrate has higher electron mobility, the miniature light-emitting diode panel has better operating electrical properties.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or Intermediate elements can also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements. As used herein, "connection" can refer to physical and/or electrical connection. Furthermore, "electrical connection" can mean that there are other components between the two components.

Reference will now be made in detail to the exemplary embodiments of the present invention, and examples of the exemplary embodiments are illustrated in the accompanying drawings. Whenever possible, the same component symbols are used in the drawings and descriptions to indicate the same or similar parts.

FIG. 1 is a schematic top view of a micro light emitting diode panel according to an embodiment of the invention. 2A to 2K are cross-sectional views of the manufacturing process of the micro light emitting diode panel of FIG. 1. Fig. 3 is a cross-sectional view of a partial area of the micro light emitting diode panel of Fig. 1. In particular, for the sake of clarity, FIG. 1 omits the illustration of the insulating layer 55, the pad P3, the flat layer PL, and the conductive layer CL in FIG. 3.

1 and 3, the micro light emitting diode panel 10 includes a circuit substrate 50, a plurality of transistor elements 100, and a plurality of micro light emitting diode elements 200. The transistor element 100 and the micro light emitting diode element 200 are disposed on the circuit substrate 50 and are electrically connected to the circuit substrate 50 respectively. The circuit substrate 50 may include a substrate 51 and a plurality of signal lines disposed on the substrate 51. In this embodiment, the plurality of signal lines are, for example, a plurality of first signal lines SL1 and a plurality of second signal lines SL2, and the first signal lines SL1 and the second signal lines SL2 that intersect each other can define a miniature light emitting A plurality of pixel areas PR of the diode panel 10. A plurality of micro light emitting diode elements 200 are respectively arranged in these pixel regions PR. It should be noted that the present invention is not limited to the content disclosed in the drawings. In other embodiments, the number of micro light emitting diode elements 200 located in the pixel region PR can also be adjusted according to actual application requirements. More than one.

For example, the first signal line SL1 and the second signal line SL2 are respectively a scan line and a power line, but the invention is not limited to this. It should be noted that, in this embodiment, the number of transistor elements 100 corresponding to the micro light emitting diode element 200 is exemplified by taking one as an example, but it is not limited thereto. In other embodiments, the number of transistor elements 100 used to drive the micro light-emitting diode element 200 can also be adjusted to two or more than three according to actual circuit design requirements; at the same time, the circuit substrate can also include other A plurality of third signal lines are electrically connected to the transistor element, and the third signal line is, for example, a sensing line or a data line. In this embodiment, the circuit substrate 50 may also optionally include a plurality of conductive patterns CP, and the conductive patterns CP are electrically connected between the transistor device 100 and the micro light emitting diode device 200.

Furthermore, the transistor element 100 has a source SE, a drain DE, a gate GE, and a semiconductor pattern SC. The source SE is electrically connected between the semiconductor pattern SC and the protrusion SL2a of the second signal line SL2. The drain electrode DE is electrically connected between the semiconductor pattern SC and the corresponding conductive pattern CP, and the gate electrode GE is electrically connected to the first signal line SL1. In particular, the source SE, the drain DE, and the gate GE may be located between the semiconductor pattern SC and the circuit substrate 50, but the invention is not limited to this. In this embodiment, the transistor device 100 can also optionally have a pad P1 and a pad P2, and the pad P1 and the pad P2 penetrate the gate insulating layer 105 of the transistor device 100 to be electrically connected to the source SE respectively. And dip pole DE. On the other hand, the circuit substrate 50 can also be selectively provided with a pad P3, and the pad P3 penetrates the insulating layer 55 to be electrically connected to the first signal line SL1. Specifically, the transistor element 100 is bonded to the circuit substrate 50 through the connection relationship between the pad P1, the pad P2, and the gate electrode GE and the protruding portion SL2a, the conductive pattern CP, and the pad P3, respectively. However, the present invention does not Limit this.

In this embodiment, since the material of the semiconductor pattern SC may include single crystalline silicon (single crystalline silicon) material, the transistor device 100 may have higher electron mobility, for example, the electron mobility is higher than 100. The ^{transistor element of cm 2} /V·s helps to improve the operating electrical performance of the miniature light-emitting diode panel 10. However, the present invention is not limited to this. According to other embodiments, the material of the semiconductor pattern SC may also include low temperature polysilicon (LTPS) or metal oxide; that is, the transistor element may also be a low temperature polysilicon thin film transistor (LTPS TFT), micro-Si TFT or Metal Oxide Transistor. More specifically, in one embodiment, the electron mobility of a transistor element containing a metal oxide may be higher than 20 cm ² /V·s. In another embodiment, the electron mobility of a transistor element including low-temperature polysilicon can be higher than 50 cm ² /V·s.

On the other hand, the micro light emitting diode device 200 includes an epitaxial structure 210, a first electrode 201 and a second electrode 202. In this embodiment, the first electrode 201 and the second electrode 202 are respectively disposed on opposite sides of the epitaxial structure 210; that is, the micro light emitting diode device 200 of this embodiment is a vertical type (vertical type) micro Light-emitting elements, but the invention is not limited to this. Furthermore, the epitaxial structure 210 may include a first type semiconductor layer 211, a light emitting layer 212, and a second type semiconductor layer 213, and the first electrode 201 and the second electrode 202 are electrically connected to the first type semiconductor layer 211 and the second type semiconductor layer 211, respectively. Type 2 semiconductor layer 213. In this embodiment, the first-type semiconductor layer 211 and the second-type semiconductor layer 213 may be a P-type semiconductor and an N-type semiconductor, respectively, and the light-emitting layer 212 may be a multiple quantum well (MQW) structure. The invention is not limited to this.

For example, in this embodiment, the first-type semiconductor layer 211 and the second-type semiconductor layer 213 may also have different thicknesses in the normal direction of the substrate 51. For example, the vertical thickness of the second-type semiconductor layer 213 is greater than that of the second-type semiconductor layer 213. The vertical thickness of the first-type semiconductor layer 211. In other words, the light emitting layer 212 of the micro light emitting diode device 200 may be located in a region of the epitaxial structure 210 closer to the first electrode 201 (as shown in FIG. 3), but the present invention is not limited to this. In other embodiments, the first-type semiconductor layer 211 and the second-type semiconductor layer 213 have substantially the same thickness in the normal direction of the substrate 51. That is, the light-emitting layer 212 can be selectively located in the middle region of the epitaxial structure 210.

In this embodiment, the micro light emitting diode panel 10 further includes a flat layer PL and a conductive layer CL. The flat layer PL covers the transistor element 100, the micro light emitting diode element 200 and a part of the circuit substrate 50, and has a plurality of openings PLa overlapping the micro light emitting diode elements 200. The conductive layer CL covers the flat layer PL and extends into the openings PLa to form the second electrode 202 that is in electrical contact with the plurality of micro light emitting diode devices 200. In other words, the second electrode 202 of this embodiment is implemented in the form of a common electrode. For example, when the micro light emitting diode panel 10 is enabled, the first electrode 201 can selectively have a high potential, and the second electrode 202 (or the conductive layer CL) can selectively have a ground potential (Ground ) Or low potential, and through the current generated by the potential difference between the two electrodes, the epitaxial structure 210 is enabled to make the light-emitting layer 212 emit a (visible) light beam, so as to achieve the effect of displaying images.

The manufacturing process of the micro light emitting diode panel 10 will be exemplarily described below. 2A and 2B, first, a semiconductor material substrate 35 is formed. In this embodiment, the semiconductor material substrate 35 includes a carrier plate 31, a sacrificial layer 32, an inorganic insulating layer 42, and a semiconductor material layer 41A. The sacrificial layer 32 is located between the carrier plate 31 and the inorganic insulating layer 42, and the inorganic insulating layer 42 is located Between the sacrificial layer 32 and the semiconductor material layer 41A. For example, the semiconductor material substrate 35 of this embodiment is formed by bonding a silicon wafer 40 to an epitaxial substrate 30.

In detail, the epitaxial substrate 30 includes a carrier plate 31 and a sacrificial layer 32 disposed on the carrier plate 31. The silicon wafer 40 includes, for example, a single crystal silicon material layer 41, a hydrogen-doped crystalline silicon material layer 41d, and an inorganic insulating layer 42; that is, the silicon wafer 40 may be a multilayer stack structure of multiple semiconductor material layers and an inorganic insulating layer 42. In particular, the hydrogen-doped crystalline silicon material layer 41d can be selectively located in a region of the single crystal silicon material layer 41 that is closer to the inorganic insulating layer 42. In other words, the portion of the single crystal silicon material layer 41 between the hydrogen-doped crystalline silicon material layer 41d and the inorganic insulating layer 42 can form a single crystal silicon film.

Furthermore, in the process of forming the semiconductor material substrate 35, the silicon wafer 40 is connected to the epitaxial substrate 30 through the bonding relationship between the inorganic insulating layer 42 and the sacrificial layer 32. After the silicon wafer 40 and the epitaxial substrate 30 are joined, a high temperature process can be performed to blister and peel the hydrogen-doped crystalline silicon material layer 41d so that the single-crystal silicon material layer 41 is located on the hydrogen-doped crystalline silicon. The two parts on opposite sides of the material layer 41d are separated from each other. Then, the part of the single crystal silicon material layer 41 still connected to the inorganic insulating layer 42 can be further subjected to a chemical mechanical polishing (CMP) process to form the semiconductor material layer 41A of the semiconductor material substrate 35. In more detail, controlling the depth position of the hydrogen-doped crystalline silicon material layer 41d can initially control the thickness of the single crystal silicon material layer 41, and then the thickness of the semiconductor material layer 41A can be more accurately controlled by chemical mechanical polishing. However, the present invention is not limited to this. According to other embodiments, the semiconductor material substrate may also form a semiconductor material layer on the epitaxial substrate through an epitaxial film formation method.

In this embodiment, the carrier 31 is, for example, a sapphire substrate, a glass substrate, a silicon wafer substrate, a silicon carbide substrate or a polymer substrate, but the invention is not limited to this. In this embodiment, the material of the sacrificial layer 32 may include gallium nitride (GaN), silicon oxide, or silicon nitride. The material of the inorganic insulating layer 42 includes silicon oxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiOxNy; x>y), silicon oxynitride (SiNxOy; x>y), or other suitable inorganic insulating materials .

Next, a plurality of transistor elements 100 are formed on the semiconductor material substrate 35, as shown in FIG. 2C. 2B, 2C and 3 at the same time, for example, the step of forming the transistor device 100 may include patterning the semiconductor material layer 41A and the inorganic insulating layer 42 to form a plurality of semiconductor patterns SC and a plurality of insulating patterns 42P, forming a source SE and a drain DE, forming a gate insulating layer 105, and forming a gate GE. Based on the consideration of conductivity, the source electrode SE, the drain electrode DE, and the gate electrode GE are generally made of metal materials. However, the present invention is not limited to this. According to other embodiments, the source SE, the drain DE, and the gate GE may also use other conductive materials, such as alloys, nitrides of metallic materials, oxides of metallic materials, and metallic materials. Oxynitride, or other suitable materials, or stacked layers of metal materials and other conductive materials.

In this embodiment, since the insulating pattern 42P and the semiconductor pattern SC are formed in the same lithographic etching process, the insulating pattern 42P can be aligned with the semiconductor pattern SC in the normal direction of the carrier 31. That is, the insulating pattern 42P may completely overlap the semiconductor pattern SC. However, the present invention is not limited to this. According to other embodiments, the inorganic insulating layer 42 and the gate insulating layer 105 may be selectively subjected to a lithographic etching process at the same time to form a plurality of insulating patterns. Furthermore, the step of forming the transistor device 100 may further include forming a plurality of pads, such as pads P1 and P2, wherein the pads P1 and P2 penetrate the gate insulating layer 105 to be electrically connected to the source SE respectively. It is the same as the drain DE, but the present invention is not limited to this, and the pads can also be manufactured in the subsequent transfer process. In this embodiment, the material of the pad P1, the pad P2, and the gate GE can be selectively the same; that is, the pad P1, the pad P2, and the gate GE can belong to the same film layer, but the present invention does not Limit this.

2D to FIG. 2H, after forming the transistor elements 100, the transistor elements 100 can be selectively transferred from the carrier 31 to a temporary substrate, and then the temporary substrate is used to transfer and bond the transistor elements 100 To the circuit substrate 50, but the present invention is not limited to this. In other embodiments, the transistor 100 can also be directly transferred to the circuit substrate 50. In this embodiment, the transistor element 100 is transferred to the circuit substrate 50 after two transfer processes.

In detail, in the first transfer process of the transistor element 100, the carrier structure 70 with the adhesive layer 71 is used to temporarily fix the transistor element 100 to the carrier structure 70. Then use the transfer part 81 of the selectively transferable carrier structure 80 to extract the transistor element 100 on the carrier structure 70, and the transistor element 100 is fixed to the carrier structure through the bonding relationship between the insulating pattern 42P and the transfer part 81 80 on. After the carrier structure 70 is separated from the plurality of transistor elements 100, the carrier structure 80 can be selectively turned over and transpose these transistor elements 100 on the circuit substrate 50. At this time, different from the arrangement of the transistor element 100 and the insulating pattern 42P on the carrier 31 (as shown in FIG. 2C), the transistor element 100 can be selectively located between the circuit substrate 50 and the insulating pattern 42P, but The present invention is not limited to this. It is worth mentioning that since the side of the transistor element 100 away from the circuit substrate 50 is provided with an insulating pattern 42P, there is no need to form an additional insulating layer in the subsequent manufacturing process to prevent other conductive film layers from being electrically short-circuited with the transistor element 100. Help reduce production costs.

For example, the material of the adhesive layer 71 may include an adhesive material. The viscous material is, for example, an organic material (such as benzocyclobutene, phenol formaldehyde resin, epoxy resin, polyisoprene rubber or a combination thereof), inorganic Materials (such as silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof), or thermally degraded materials (such as cold brittle materials, hot melt materials, photoresist materials, or combinations thereof). In particular, the viscosity of the viscous material can change with different temperatures, for example, the higher the temperature, the greater the viscosity of the viscose, but the present invention is not limited to this. In other words, the adhesive layer 71 can transpose (transfer and place) the transistor device 100 through its adhesion relationship with the transistor device 100, but the invention is not limited to this. In other embodiments, the extraction method used in the transposition technology of the micro-components may also include an electrostatic force (Electrostatic force) or a Van Der Waals force (Van Der Waals force). In addition, in this embodiment, the adhesive layer 71 is formed on the carrier structure 70 in its entirety, so that all the transistor elements 100 on the carrier 31 are transposed to the carrier structure 70, but it is not limited thereto. In other embodiments, the adhesive layer 71 can also be a patterned film layer to selectively transpose the transistor element 100 on the carrier plate 31.

In particular, after the adhesive layer 71 of the carrier structure 70 is bonded to the plurality of transistor elements 100, the sacrificial layer 32 can be removed to separate the transistor elements 100 from the carrier 31. For example, a laser lift off (LLO) method may be used to remove the sacrificial layer 32, but the invention is not limited to this. In other embodiments, a fixing structure may also be formed on the carrier board 31, and the fixing structure is suitable for temporarily fixing the plurality of transistor elements 100 on the carrier board 31. During the lifting process after the carrier structure is attached to the transistor element, the fixing structure can be easily broken to cause the transistor element to be separated from the carrier plate 31.

Please refer to FIG. 1, FIG. 2I and FIG. 2J, after the transfer process of the plurality of transistor devices 100 is completed, the plurality of micro light emitting diode devices 200 are transferred from the unshown micro light emitting diode device substrate to the circuit substrate 50 up. For example, the micro light emitting diode device 200 can be transferred to the area between two adjacent transistor devices 100 on the circuit substrate 50 through the transfer portion 81A of the carrier structure 80A. In other words, the plurality of transistor elements 100 and the plurality of micro light emitting diode elements 200 can be alternately arranged on the circuit substrate 50 along the extending direction of the second signal line SL2, but the invention is not limited to this. According to other embodiments, more than two miniature light emitting diode devices 200 may also be provided between two adjacent transistor devices 100. It should be noted that the present invention does not limit the arrangement of the multiple transfer parts on the carrier structure without the disclosure of the figures. In other embodiments, the configuration (for example, the arrangement period or the spacing) of the multiple transfer parts of the carrier structure can also be adjusted according to the actual product design and process requirements.

It is worth mentioning that by transferring the plurality of transistor elements 100 pre-formed on the carrier 31 to the circuit substrate 50 through the above-mentioned transfer process, the production cost can be reduced and the design margin of the product can be increased. From another point of view, the semiconductor pattern SC of the transistor device 100 of this embodiment is a single crystal silicon film. Accordingly, compared with amorphous silicon semiconductor or metal oxide semiconductor material, it has better electron mobility, and through the above-mentioned transfer process, this type of transistor with high electron mobility can be applied to large-size display panels. , Which helps to improve the electrical performance of the large-size display panel.

2K, after a plurality of micro light emitting diode elements 200 are transposed on the circuit substrate 50, a flat layer PL is formed to cover the transistor element 100 and the micro light emitting diode element 200, wherein the flat layer PL has overlapped The plurality of openings PLa of the plurality of micro light emitting diode devices 200. In this embodiment, the material of the flat layer PL may include inorganic materials (for example: silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, or a stacked layer of at least two of the above materials), organic materials, or other materials. Suitable materials, or a combination of the above. Next, a conductive layer CL is formed on the flat layer PL, wherein the conductive layer CL covers the flat layer PL and extends into the openings PLa of the flat layer PL to electrically connect the plurality of micro light emitting diode devices 200. At this point, the micro light emitting diode panel 10 of this embodiment is completed.

In particular, in the manufacturing process of the micro light emitting diode panel 10 of this embodiment, the components using the transfer technology are exemplified by taking the transistor element 100 and the micro light emitting diode element 200 as examples. It means that the present invention is limited by this. According to other embodiments not shown, the micro light emitting diode panel may further include a micro integrated circuit (micro integrated circuit), a micro sensor (micro sensor), a microchip with a circuit, or other devices. It can control micro-semiconductors that perform predetermined electronic functions, and these micro-elements can also be transferred through the aforementioned transposition method.

4 is a cross-sectional view of a micro light emitting diode panel according to another embodiment of the invention. 4, the difference between the micro light emitting diode panel 11 of this embodiment and the micro light emitting diode panel 10 of FIG. 3 lies in: the types of micro light emitting diode elements and the signal line configuration of the circuit substrate are different. In this embodiment, the first electrode 201A and the second electrode 202A of the micro light emitting diode element 200A are arranged on the same side of the epitaxial structure 210A; that is, the micro light emitting diode element 200A is a flip chip -chip type) miniature light-emitting element. In detail, the micro light emitting diode device 200A further includes an insulating layer 205. The first electrode 201A penetrates the insulating layer 205 to electrically connect the first type semiconductor layer 211A, and the second electrode 202A penetrates the first type semiconductor layer 211A to emit light. The layer 212A and the insulating layer 205 are electrically connected to the second type semiconductor layer 213A.

On the other hand, the circuit substrate 50A further includes a third signal line SL3, and the first electrode 201A and the second electrode 202A of the micro light emitting diode device 200A are respectively connected to the conductive pattern CP-1 and the third signal line of the circuit substrate 50A SL3. For example, when the micro light emitting diode panel 11 is enabled, the third signal line SL3 may have a ground potential (Ground) or a low potential. In this embodiment, since the two electrodes of the micro light emitting diode device 200A are located on the same side of the epitaxial structure 210A, after the micro light emitting diode device 200A is transferred and bonded to the circuit substrate 50A, the subsequent manufacturing process can be omitted. The production of the flat layer and the conductive layer helps to further reduce the production cost.

5 is a cross-sectional view of a micro light emitting diode panel according to another embodiment of the invention. Referring to FIG. 5, the main difference between the micro light emitting diode panel 12 of this embodiment and the micro light emitting diode panel 11 of FIG. 4 is that the composition and configuration of the transistor elements are different. In this embodiment, the transistor element 100A is directly transferred from the carrier board to the circuit substrate 50B; that is, the number of transfers of the transistor element 100A in this embodiment is only one. Therefore, the source SE, the drain DE, and the gate GE are arranged on the side of the semiconductor pattern SC away from the circuit substrate 50B. On the other hand, the transistor device 100A of this embodiment does not have pads.

In order to electrically connect the source SE, the drain DE, and the gate GE to the circuit substrate 50B, a flat layer PL-1 needs to be formed to cover the transistor element 100A and part of the circuit substrate 50B in the subsequent manufacturing process. Next, a plurality of conductive patterns, such as conductive pattern CP-2, conductive pattern CP-3, and conductive pattern CP-4, are further formed on the flat layer PL-1. The conductive pattern CP-2 and the conductive pattern CP-3 penetrate the flat layer PL-1 to electrically connect the source SE and the drain DE of the transistor device 100A, respectively. The first electrode 201A and the second electrode 202A of the micro light emitting diode device 200A are respectively bonded to the conductive pattern CP-3 and the conductive pattern CP-4. In particular, the gate electrode GE of the transistor element 100A can also be electrically connected to the circuit substrate 50 through another conductive pattern (not shown), and the end of the conductive pattern CP-2 away from the source electrode SE can penetrate the flat layer PL-1 is electrically connected to the circuit board 50B, but the invention is not limited to this.

In summary, in the micro light emitting diode panel and the manufacturing method thereof according to an embodiment of the present invention, a plurality of transistor elements pre-formed on the carrier board are transferred to the circuit substrate through the transfer process, which can reduce the production cost And increase the design margin of the product. On the other hand, since the semiconductor material layer of the semiconductor material substrate has higher electron mobility, the miniature light-emitting diode panel has better operating electrical properties.

10, 11, 12: Miniature LED panel 30: Epitaxy substrate 31: carrier board 32: Sacrifice layer 35: Semiconductor material substrate 40: Silicon wafer 41: Single crystal silicon material layer 41A: Semiconductor material layer 41d: Hydrogen-doped crystalline silicon material layer 42: Inorganic insulating layer 42P: Insulation pattern 50, 50A, 50B: circuit board 51: substrate 55, 205: insulating layer 70, 80, 80A: carrier board structure 71: Adhesive layer 81, 81A: Transfer Department 100, 100A: Transistor element 105: gate insulation 200, 200A: Miniature light-emitting diode components 201, 201A: first electrode 202, 202A: second electrode 210, 210A: epitaxial structure 211, 211A: first type semiconductor layer 212, 212A: light-emitting layer 213, 213A: Type II semiconductor layer CL: conductive layer CP, CP-1, CP-2, CP-3, CP-4: conductive pattern DE: Dip pole GE: Gate PL, PL-1: Flat layer PLa: opening PR: pixel area P1, P2, P3: pads SC: Semiconductor pattern SE: Source SL1: The first signal line SL2: The second signal line SL3: The third signal line SL2a: protrusion

FIG. 1 is a schematic top view of a micro light emitting diode panel according to an embodiment of the invention. 2A to 2K are cross-sectional views of the manufacturing process of the micro light emitting diode panel of FIG. 1. Fig. 3 is a cross-sectional view of a partial area of the micro light emitting diode panel of Fig. 1. 4 is a cross-sectional view of a micro light emitting diode panel according to another embodiment of the invention. 5 is a cross-sectional view of a micro light emitting diode panel according to another embodiment of the invention.

10: Mini LED panel

42: Inorganic insulating layer

42P: Insulation pattern

50: circuit board

51: substrate

55: Insulation layer

100: Transistor element

105: gate insulation

200: Miniature LED components

201: first electrode

202: second electrode

210: epitaxial structure

211: The first type semiconductor layer

212: light-emitting layer

213: second type semiconductor layer

CL: conductive layer

CP: conductive pattern

DE: Dip pole

GE: Gate

PL: Flat layer

PLa: opening

P1, P2, P3: pads

SC: Semiconductor pattern

SE: Source

SL1: The first signal line

SL2: The second signal line

SL2a: protrusion

Claims (19)

A method for manufacturing a miniature light-emitting diode panel includes: forming a semiconductor material substrate, wherein the semiconductor material substrate includes a carrier, a sacrificial layer, an inorganic insulating layer, and a semiconductor material layer, and the sacrificial layer is located on the carrier Between the inorganic insulating layer and the inorganic insulating layer, the semiconductor material layer is bonded to the sacrificial layer through the inorganic insulating layer, and the electron mobility of the semiconductor material layer is greater than 20 cm ² /V·s; forming a plurality of transistor elements, wherein the The transistor elements are disposed on the sacrificial layer; the transistor elements are transferred and bonded to a circuit substrate, and the transistor elements are electrically connected to the circuit substrate; and the plurality of micro light emitting diode elements are self-contained A micro-light-emitting diode device substrate is transferred to the circuit substrate, and the micro-light-emitting diode devices are electrically connected to the transistor devices. According to the manufacturing method of the miniature light-emitting diode panel described in item 1 of the scope of patent application, the transfer step of the transistor elements includes: Transferring the transistor elements to a temporary substrate; and The temporary substrate is used to transfer and bond the transistor elements to the circuit substrate. According to the manufacturing method of the miniature light-emitting diode panel described in item 1 of the scope of patent application, the transfer step of the transistor elements includes: The sacrificial layer is removed to separate the transistor elements from the carrier board. According to the method for manufacturing a miniature light-emitting diode panel as described in item 1 of the scope of patent application, the step of forming the transistor element includes: Part of the semiconductor material layer is removed to form a semiconductor pattern. According to the manufacturing method of the micro light-emitting diode panel described in item 4 of the scope of patent application, the step of forming the transistor element further includes: A source and a drain, a gate insulating layer, and a gate are formed on the semiconductor pattern, the source and the drain are electrically connected to two different regions of the semiconductor pattern, and the gate insulating layer covers the source Electrode, the drain electrode and part of the semiconductor pattern. According to the method for manufacturing a miniature light emitting diode panel described in claim 5, after the transistor element and the circuit substrate are joined, the source, the drain and the gate are located between the semiconductor pattern and the Between circuit boards. According to the manufacturing method of the micro light-emitting diode panel described in item 5 of the scope of patent application, the step of forming the transistor element further includes: A first pad and a second pad are formed, wherein the first pad and the second pad are electrically connected to the source and the drain, respectively, and the transistor element passes through the first pad, the The second pad and the gate are joined on the circuit substrate. According to the manufacturing method of the miniature light-emitting diode panel described in item 7 of the scope of patent application, the first pad, the second pad and the gate are formed by patterning the same film layer. The manufacturing method of the miniature light-emitting diode panel as described in item 1 of the scope of patent application further includes: Forming a flat layer to cover the transistor element and the miniature light emitting diode element; and A conductive layer is formed on the flat layer, wherein the flat layer has an opening exposing a top surface of the micro light emitting diode device, and the conductive layer passes through the opening to electrically connect the micro light emitting diode device . The manufacturing method of the miniature light-emitting diode panel as described in item 1 of the scope of patent application further includes: After the transistor elements are transferred to the circuit substrate, a plurality of conductive patterns are formed on the circuit substrate, wherein a part of the conductive patterns is electrically connected to the transistor elements, and the micro light emitting diode elements The other parts of the conductive patterns are respectively joined and electrically connected. According to the method for manufacturing a miniature light-emitting diode panel as described in item 1 of the scope of patent application, the step of forming the transistor element includes: Part of the inorganic insulating layer is removed to form an insulating pattern, wherein the insulating pattern overlaps the transistor element. According to the method for manufacturing a miniature light emitting diode panel described in claim 11, after the transistor element is transferred and bonded to the circuit substrate, the transistor element is located between the circuit substrate and the insulating pattern. A semiconductor material substrate includes: a carrier plate; a sacrificial layer disposed on the carrier plate; an inorganic insulating layer, wherein the sacrificial layer is located between the carrier plate and the inorganic insulating layer; and a semiconductor material layer disposed on the carrier plate On the inorganic insulating layer, the semiconductor material layer is connected to the sacrificial layer through the inorganic insulating layer, and the electron mobility of the semiconductor material layer is greater than 20 cm ² /V·s. The semiconductor material substrate according to item 13 of the scope of patent application, wherein the carrier is a sapphire substrate. According to the semiconductor material substrate described in claim 13, wherein the sacrificial layer is an epitaxial semiconductor layer, and the inorganic insulating layer is a silicon oxide layer. The semiconductor material substrate according to item 13 of the scope of patent application, wherein the semiconductor material layer is a single crystal silicon material layer. A miniature light emitting diode panel includes: a circuit substrate; a plurality of transistor elements are arranged on the circuit substrate, and the transistor elements respectively have a semiconductor pattern, a source electrode, a drain electrode and a gate electrode, The source and the drain are electrically connected to the semiconductor pattern, wherein the source, the drain, and the gate are located between the semiconductor pattern and the circuit substrate, and the electron mobility of the semiconductor pattern is greater than 20 cm ² / V·s; and a plurality of miniature light-emitting diode elements are arranged on the circuit substrate and are electrically connected to the transistor elements. The miniature light-emitting diode panel described in claim 17, wherein the circuit substrate has a plurality of signal lines, and the signal lines are respectively electrically connected to the gates and the sources of the transistors Poles and these miniature light-emitting diode elements. The miniature light-emitting diode panel described in item 17 of the scope of patent application further includes: A flat layer disposed on the circuit substrate and covering the transistor elements and the micro light emitting diode elements; and A conductive layer covering the flat layer, wherein the flat layer has a plurality of openings overlapping the micro light emitting diode elements, and the conductive layer extends into the openings to electrically connect the micro light emitting diode elements .

Images