TW202111756A - Method and system of estimating wafer crystalline orientation - Google Patents

Abstract

A method includes: receiving a first wafer; defining a first zone and a second zone on the first wafer and a plurality of first areas; defining a plurality of first areas and second areas for the first and second zones, respectively; projecting first ion beams onto the first areas and receiving first thermal waves in response to the first ion beams; rotating the first wafer by a twist angle; projecting second ion beams onto the second areas and receiving second thermal waves in response to the second ion beams; and estimating a first crystalline orientation angle of the first wafer based on the first and second ion beams and the first and second thermal waves.

Description

Method and system for estimating wafer crystal orientation

The embodiment of the present invention relates to a method and system for estimating the crystal orientation of a wafer.

The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced several generations of ICs, each of which has smaller and more complex circuits than the previous generation. To promote advanced IC devices, ion implantation is widely used to dope impurities into a workpiece (such as a semiconductor wafer) to form N-type or P-type wells. In the case of ion implantation, the amount of impurities in the workpiece is modified in order to introduce conductivity into the wells. A desired impurity material can be ionized and accelerated by an ion source to form an ion beam with a prescribed energy. The ion beam can be guided to a front surface of the workpiece and penetrate into the block of the workpiece. The implanted ions can be distributed around a depth of the wafer area, and the distribution and concentration of the ions are controllable, such as by adjusting the implantation angle and beam energy.

According to an embodiment of the present invention, a method includes: receiving a first wafer; defining a first zone and a second zone on the first wafer; The second zone defines a plurality of first regions and second regions; projecting the first ion beam onto the first regions and receiving the first thermal wave in response to the first ion beams; making the first wafer Rotate to a twist angle; project a second ion beam onto the second areas and receive a second thermal wave in response to the second ion beams; and based on the first ion beams and the second ion beams And the first heat waves and the second heat waves estimate a first crystal orientation angle of the first wafer.

According to an embodiment of the present invention, a method includes: defining a first zone and a second zone on a first wafer; respectively projecting a first ion beam and a second ion beam to the first Zone and the second zone; estimate a first crystal orientation angle of the first wafer based on the first ion beams and the second ion beams; define a third crystal on a second wafer Zone and a fourth zone; the third ion beam and the fourth ion beam are projected onto the third zone and the fourth zone, respectively; based on the estimation of the third ion beam and the fourth ion beam Measuring a second crystal orientation angle of the second wafer; and estimating a third crystal orientation angle of a third wafer based on the first crystal orientation angle and the second crystal orientation angle.

According to an embodiment of the present invention, a method includes: receiving a plurality of wafers; estimating crystal orientation angles of the plurality of wafers; classifying the plurality of wafers into wafer groups according to their equal crystal orientation angles Select at least one wafer from one of the wafer groups; and perform an ion implantation operation on the at least one wafer according to a representative crystal orientation angle of the one of the wafer groups.

The following disclosure provides many different embodiments or examples of different components used to implement the provided subject matter. Specific examples of components and configurations are described below to simplify the disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first member on or on a second member may include an embodiment in which the first member and the second member are formed in direct contact, and may also include an additional member may be formed on the first member. Between the component and the second component, the first component and the second component may not be in direct contact with each other. In addition, the present disclosure may repeat reference numbers and/or letters in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and/or configurations discussed.

In addition, for ease of description, spatially relative terms such as "below", "below", "below", "above", "upper" and the like can be used herein to describe a The relationship between an element or component and another element or component(s) shown in the figure. Spatial relative terms are intended to cover different orientations of devices in use or operation other than those depicted in the figures. The device can be oriented in other ways (rotated by 90 degrees or in other orientations) and therefore the spatial relative descriptors used in this article can also be interpreted.

Although the numerical ranges and parameters described in the broad scope of this disclosure are approximate values, the numerical values described in the specific examples are reported as accurately as possible. However, any value inherently contains specific errors that are necessarily caused by deviations usually found in the respective test measurements. Moreover, as used herein, the terms "about", "substantial" or "substantially" generally mean within 10%, 5%, 1%, or 0.5% of a given value or range. Alternatively, the terms "about", "substantial" or "substantially" mean within an acceptable standard error of the mean when considered by the average technician. Except in the operation/working example, or unless otherwise clearly specified, all numerical ranges, quantities, values and percentages disclosed in this article (such as material quantity, duration, temperature, operating conditions, quantity ratios, etc.) are similar The numerical range, quantity, value and percentage of the above) should be understood as being modified by the terms "about", "substantial" or "substantially" in all examples. Therefore, unless there are instructions to the contrary, the numerical parameters described in the scope of the present disclosure and the accompanying invention application are approximate values that can be changed as required. At the very least, each numerical parameter should be explained at least based on the reported number of significant digits and by applying ordinary rounding techniques. The range can be expressed herein as from one endpoint to the other or between two endpoints. Unless otherwise specified, all ranges disclosed herein include endpoints.

Those familiar with the technology will understand that the embodiments of the present disclosure can be implemented as a system, method, or computer program product. Therefore, the embodiment of the present disclosure can adopt a completely hardware embodiment, a completely software embodiment (including firmware, resident software, microcode, etc.), or a combination thereof, which can be generally referred to as a "circuit", "area" in this text. The form of one embodiment of the software and hardware aspects of "block", "module" or "system". In addition, the embodiments of the present disclosure can be in the form of a computer program product embodied in any tangible medium, which has a program code embodied in the medium and executable by a computer.

A semiconductor wafer is used as a substrate of a semiconductor device, in which doped regions can be formed in the bulk of the semiconductor wafer. A semi-conductive ingot or wafer is formed using a lattice structure with parallel lattice planes. The lattice plane of the semi-conductive ingot determines the crystal orientation (or lattice orientation) angle of the ingot or semiconductor wafer. Generally speaking, a semi-conductive ingot is grown with a substantially equal crystal orientation angle through one of the ingots and the angle difference is usually negligible. However, as the size of semiconductor devices continues to decrease, the manufacturing of semiconductor devices needs to be performed with greater accuracy in operating parameters. Otherwise, manufacturing operations performed with insufficient parameter accuracy will cause quality uniformity problems in the manufactured semiconductor devices.

In this disclosure, a method and a system for estimating the crystal orientation angle of a semiconductor wafer are provided. The estimation method is performed on a single test wafer. Due to the elimination of the influence of the angle variability between different test wafers, the proposed estimation method is more accurate than the alternative estimation method using multiple test wafers. In addition, since only one test wafer is used for each semi-conductive ingot, the cost of the test wafer is also reduced. Manufacturing operations (such as ion implantation) can be performed with accuracy that better matches the larger projection angle of the crystal orientation angle of the semiconductor, and the doped region can be formed by ion implantation with a better profile control. The proposed method also reduces the cost of estimating the crystal orientation angle of a wafer group of the same lot. This is because in some cases at least two test wafers or only one test wafer are required, thereby reducing the number of wafers. The additional cost of quality control and the improvement of the calibration efficiency of the crystal orientation angle.

FIG. 1A is a schematic diagram showing a method 100 of forming a semiconductor wafer according to some embodiments. The method 100 begins with a crystal growth operation 102. Therefore, a semi-conductive ingot 103 is formed. The semi-conductive ingot 103 can be formed using any crystal growth method known in the art, such as the Chukraski (Cz) method. In some embodiments, the semi-conductive ingot 103 is grown to include a single crystal lattice structure. In some embodiments, the semi-conductive ingot 103 is an ingot made of silicon or another suitable semiconductor material. After the silicon ingot 103 is formed, an operation 104 is performed to manufacture a slice of the semiconductor wafer 110 from the semiconductive ingot 103, such as the semiconductor wafer 110a, 110b, or 110c. Operation 104 may include one or more wafer formation procedures, such as cutting the semi-conductive ingot 103 into original wafers, and beveling, grinding, etching, and polishing the original wafers to form the finished semiconductor wafer 110. In some embodiments, if the semiconductor wafers 110 are formed from the same semi-conductive ingot 103, they belong to the same wafer batch. In some embodiments, the finished semiconductor wafer 110 has a diameter between about 1 inch and about 12 inches. In some embodiments, the finished semiconductor wafer 110 has a thickness between about 100 µm and about 500 µm.

In some embodiments, the semiconductor wafer 110 has a similar crystal structure having the same crystal orientation as one associated with a crystal plane (such as (100), (110), or (111) crystal plane). An identical semi-conductive ingot 103 is manufactured. Regarding an ion implantation (also known as an ion beam projection) operation, the penetration depth and distribution of the implantation are determined at least in part by the angle between the incident ion beam and the crystal orientation angle of the lattice structure. Therefore, the electrical behavior of a well region formed in a semiconductor wafer using ion beam projection and a semiconductor device including the well region are affected by the accuracy of the crystal orientation angle control.

In some embodiments, each of the semiconductor wafers (eg, semiconductor wafers 110a, 110b, and 110c) has a respective normal line N1, N2, and N3 perpendicular to one of the surfaces of the semiconductor wafer 110a, 110b, or 110c. Ideally, each semiconductor wafer 110a, 110b, or 110c shares the same crystal orientation direction parallel to one of the longitudinal axes 103L of the semiconductive ingot 103 associated with a certain crystal plane (for example, a (100) plane). However, in most cases, when cutting the semi-conductive ingot 103, the cutting blade may not be exactly perpendicular to the longitudinal axis 103L. Therefore, the normal lines N1, N2, or N3 are not parallel to the directions of the respective crystal orientation lines 110L1, 110L2, and 110L3. _{The angle β 1} , β ₂ or β ₃ between the direction of the crystal orientation line 110L1, 110L2 or 110L3 and the respective normal line N1, N2 or N3 is referred to herein as the crystal orientation angle of the semiconductor wafer 110a, 110b or 110c . In some embodiments, the included angles β ₁ , β ₂ and β ₃ are substantially zero degrees.

In some embodiments, during the crystal growth of the semiconductive ingot 103, the orientation of the crystal plane may rotate about the longitudinal axis 103L as the lattice structure grows upward. In other words, the actual crystal orientation lines 110L1, 110L2, and 110L3 at positions 108a, 108b, and 108c may respectively point to slightly different directions. In addition, the included angles β ₁ , β ₂ and β ₃ may not be equal. In some embodiments, the rotation of the crystal plane during crystal growth is proportional to the growth height of the semiconductive ingot 103. Therefore, the included angles β ₁ , β ₂ and β ₃ or equivalently the crystal orientation angle of the semiconductor wafer 110 are approximately expressed by a linear equation. In some other embodiments, the angle may be from the same semiconductive ingot 103 of two or more of the other semiconductor wafer 110 (e.g., β ₂ and β ₃₎ estimated angle (e.g., β _1), or equivalent The crystal orientation angle of the ground semiconductor wafer 110.

FIG. 1B is a schematic diagram showing an ion beam 120 projected onto a semiconductor wafer 110 according to some embodiments. Referring to the plot (A) of FIG. 1B, the semiconductor wafer 110 is placed with its surface 110S parallel to the xy plane. The plot (A) of FIG. 1B also shows a normal line N extending in the direction of the z-axis and perpendicular to a surface 110S. In some embodiments, a crystal plane of the semiconductor wafer 110 may not be parallel to the surface 110S of the semiconductor wafer 110, as illustrated by a crystal orientation line 110L, which indicates the crystal orientation of the semiconductor wafer 110. A crystal orientation angle β is formed between the normal line N and the crystal orientation line 110L. When the semiconductor wafer 110 rotates around the normal line N perpendicular to the xy plane, the crystal plane and the crystal orientation line 110L also rotate with the rotation of the semiconductor wafer 110. In some embodiments, when the semiconductor wafer 110 rotates around the normal line N, the crystal orientation line 110L rotates around the normal line N. A notch 130N serves as a reference point, and the semiconductor wafer 110 can be rotated from the notch 130 by a rotation angle to a target coordinate (x ₀ , y ₀ ), an angle between a reference line 110T and a target line 110R Or a center angle is referred to herein as a twist angle θ, where the reference line 110R is drawn from the center of the surface 110S to the notch 130N and the target line 110T is drawn from the center of the surface 110S to the target coordinate (x ₀ , y ₀ ). In some embodiments, the twist angle θ represents a change in the orientation of the crystal plane of the semiconductor wafer 110.

The ion beam 120 is projected by an ion implantation source (not shown separately) used in an ion implantation operation, such as an implanter. The ion beam 120 and the normal line N form an included angle α, which is referred to herein as a projection angle of the implanter. The ion beam 120 is projected onto a position (such as the center) of the surface 110S of the semiconductor wafer 110 along a path 120P.

Referring to the plot (B) of FIG. 1B, a top view and a side view of the semiconductor wafer 110 are shown. During an ion beam projection operation, the semiconductor wafer 110 may be tilted with respect to a wafer tilt angle ω of the xy plane. In some embodiments, a wafer stage (not shown separately) that supports and holds the semiconductor wafer 110 is provided, wherein the wafer 110 is tilted by tilting the wafer stage. Assuming that the target coordinates (x ₀ , y ₀ ) are selected as the tilt point, the semiconductor wafer 110 is tilted by tilting the wafer stage, wherein the target line 110T associated with the target _{coordinates (x 0} , y _{0) forms an xy plane} The wafer tilt angle ω. The tilt angle ω may be positive or negative depending on whether the target line 110T is above or below the xy plane. In some embodiments, the direction of the crystal orientation line 110L is changed by the amount of the wafer tilt angle ω. Based on the above, the wafer tilt angle ω, twist angle θ, and projection angle α together determine the angle between the ion beam 120 and the crystal orientation line 110L of the semiconductor wafer 110, thereby determining the difference between the ion beam 120 and the semiconductor wafer 110 Implantation angle.

In some embodiments, the angle difference (α-β) between the projection angle α of the ion beam 120 and the crystal orientation angle β is a factor in determining the contour of the implanted well. In addition, the deviation of the well profile is greater when the implanted well has a reduced spacing (for example, less than about 1 µm). For example, in an advanced CMOS image sensor application, a sensing pixel is formed with a pixel pitch less than 0.8 µm. In these conditions, one or more wells are implanted to form sensing pixels, where the deviation of the illumination angle should be less than 0.05 degrees. As previously discussed, in addition to the implantation angle of the implanter, the actual irradiation angle is also determined by the crystal orientation angle. However, in a mass production process, it is difficult to have different batches of blank semiconductor wafers with equal crystal orientation angles. Even the same batch of semiconductor wafers manufactured from the same semi-conductive ingot 103 (for example, the semiconductor wafer 110 in FIG. 1A) still contains one of the largest crystal orientation angles of about 0.1 degrees across the entire height of the semi-conductive ingot 103 The angular deviation exceeds the accuracy tolerance of advanced CMOS image sensors. Therefore, it is necessary to provide an accurate estimation of the crystal orientation angle to eliminate or reduce the interference of the variability of the crystal orientation angle.

2 is a flowchart of a method 200 for estimating a crystal orientation angle of a semiconductor wafer according to some embodiments. It should be understood that additional steps may be provided before, during, and after the steps shown in FIG. 2, and some of the steps described below may be substituted or eliminated in other embodiments of the method 200. The order of the steps can be interchangeable.

In step 202, a first wafer 110 is received. The first wafer 110 is also shown in FIG. 3. In some embodiments, the first wafer 110 is selected from a wafer lot and serves as one of the test wafers of the wafer lot. In some embodiments, the first wafer 110 is placed on a wafer stage or platform (not shown separately). In some embodiments, a notch 110N is formed or marked on the first wafer. When the first wafer 110 is rotated by the wafer stage, a mark 302 pointing to the notch 110N of the first wafer 110 serves as a reference point of the first wafer 110 with respect to the notch 110N.

In step 204, as shown in the plot (A) of FIG. 3, a first zone 310 and a second zone 320 are defined on the first wafer 110. In addition, a plurality of first regions 312 (e.g., first regions 312a, 312b, 312c, 312d, and 312e) and a plurality of second regions 322 (e.g., second region 322a, 322b, 322c, 322d and 322e). In some embodiments, the first zone 310 and the second zone 320 represent the two halves of the first wafer 110. In some embodiments, the first zone 310 and the second zone 320 are symmetrical with respect to a symmetry line S1. In some embodiments, the first zone 310 and the second zone 320 have substantially the same area, and each of them is equal to half of the total area of the first wafer 110. In some embodiments, the first zone 310 is adjacent to the second zone 320; however, in some other embodiments, the first zone 310 and the second zone 320 are separated by the first zone 310 and the second zone A third zone between 320 is separated, and the first zone 310 and the second zone 320 each have an area smaller than half of the total area of the first wafer 110. In the depicted embodiment, the first zone 310 or the second zone 320 has a semicircular shape; however, other shapes such as a polygonal shape or a circular shape are also feasible. The shapes and areas of the first zone 310 and the second zone 320 shown in the plot (A) of FIG. 3 are for illustration purposes. Other configurations of the first zone 310 and the second zone 320 are also within the expected scope of this disclosure.

A first area 312 is defined in the first zone 310. A second area 322 is defined in the second zone 320. In some embodiments, the first region 312 has a different shape or area. For example, the first area 312a has a semicircular shape, and each of the remaining first areas 312b, 312c, 312d, and 312e has an arc shape; however, other shapes such as a polygonal shape, a circular pie shape, or a circular shape are also available. Department is feasible. In some embodiments, the first region 312a is adjacent to the remaining first regions 312b, 312c, 312d, and 312e. The first area 312a may be laterally surrounded by the first areas 312b, 312c, 312d, and 312e and the second area 322a of the second zone 320. In some embodiments, the first regions 312a to 312e are adjacent to each other. In some embodiments, the first regions 312a to 312e are separated from each other. In the depicted example, the first zone 310 is divided into five first regions 312a to 312e. However, other numbers of first regions 312 are also feasible.

In some embodiments, the second region 322 has a different shape or area. For example, the second area 322a has a semicircular shape, and each of the remaining second areas 322b, 322c, 322d, and 322e has an arc shape; however, other shapes such as a polygonal shape, a round cake shape, or a circular shape are also available. Department is feasible. In some embodiments, the second area 322a is adjacent to the remaining second areas 322b, 322c, 322d, and 322e. The second area 322a may be laterally surrounded by the second areas 322b, 322c, 322d, and 322e and the first area 312a of the first zone 310. In some embodiments, the second regions 322a to 322e are adjacent to each other. In some embodiments, the second regions 322a to 312e are separated from each other. In the depicted example, the second zone 320 is divided into five second regions 322a to 322e. However, other numbers of second regions 322 are also feasible.

In some embodiments, one of the first regions 312 (eg, the first region 312a) and one of the second regions 322 (eg, the second region 322a) are paired. In some embodiments, the paired first region 312a and the second region 322a are symmetrical with respect to the symmetry line S1. In some embodiments, the paired first region 312a and the second region 322a have the same area and shape. Similarly, the first area 312b (312c, 312d, or 312e) is paired with the second area 322b (322c, 322d, or 322e), and the first area 312b (312c, 312d, or 312e) and the second area 322b (322c, 322d, or 322e) is symmetrical with respect to the line of symmetry S1.

In step 206, a first ion beam projection is performed, in which the first ion beam 402 is projected onto the first area 312, as shown in the plot (A) of FIG. 4. The first thermal wave 404 is received in response to the first ion beam 402. In some embodiments, the implanter is configured to project one individual first ion beam 402 onto the individual first region 312 at a time, wherein the first ion beam is projected at different times with the same energy and the same implant angle α Each of 402 and each of the individual first regions 312 receive individual first ion beams 402 at a respective wafer tilt angle ω. In some embodiments, the implanter repeatedly projects the first ion beam 402 at different tilt angles ω, where the tilt angle ω has an angle difference K ₁ . For example, the angle difference K ₁ is 0.2°, and the implanter is configured to tilt the wafer at -0.4°, -0.2°, 0°, 0.2°, and 0.4° for each of the first regions 311a to 311e five times A first ion beam 402 is projected. In some embodiments, the second zone 320 is prevented from receiving the first ion beam 402 during the projection of the first ion beam.

When the first ion beam 402 is projected onto the surface 110S of the first wafer 110, the ionized particles in the first ion beam 402 are accelerated by the implanter and penetrate into the internal lattice structure of the first wafer 110. A part of the ionized particles of the first ion beam 402 collides with atoms in the lattice structure and generates a first thermal wave 404 propagating outward. A heat wave detector (such as a thermometer) is used to receive the first heat wave 404 caused by the collision of the first ion beam 402 and the lattice structure. The intensity or temperature of the first thermal wave 404 is determined by the degree of collision, which is related to the actual irradiation angle of the first ion beam 402. Since the first ion beam 402 is projected onto the individual first regions 312 at different wafer tilt angles ω, the first thermal waves 404 of different examples of the wafer tilt angle ω have different wave intensities.

In some embodiments, the first ion beam 402 is irradiated onto the respective first regions 312 at an irradiation angle expressed as an angular difference (α-β) (assuming a zero-degree wafer tilt angle ω). By tuning the wafer tilt angle ω, the actual irradiation angle can be made smaller than (α-β) in order to achieve greater ion penetration and less collisions between ionized particles and lattice atoms, and thus cause respective first thermal waves 404 has reduced wave intensity. In some embodiments, when the wafer tilt angle ω is tuned to compensate for the angle (α-β) between the implantation angle α and the crystal orientation angle β, the first ion beam 402 uses a minimum irradiation angle (substantially zero degrees) Hit the crystal plane, resulting in one of the minimum wave strengths of the first thermal wave 404.

In step 208, referring also to the plot (B) of FIG. 3, the first wafer 110 is rotated by a twist angle θ using the wafer stage. In some embodiments, the torsion angle θ is set to 180 degrees; however, other values of the torsion angle θ are also feasible. In the embodiment in which the twist angle θ is set to 180 degrees, the first wafer 110 is rotated by 180 degrees, thereby causing the notch 110N to deviate from the mark 302, and the first regions 312a to 312e and the second regions 322a to 322e The relative positions are interchanged with respect to the line of symmetry S1.

In step 210, referring back to the plot (B) of FIG. 4, a second ion beam projection is performed, in which the second ion beam 412 is projected onto the second area 322. The second thermal wave 414 is received in response to the second ion beam 412. In some embodiments, the implanter is configured to project one individual second ion beam 412 onto the individual second region 322 at a time, wherein the second ion beam is projected at different times with the same energy and the same implant angle α Each of 412 and each of the individual second regions 322 receive individual second ion beams 412 at a respective wafer tilt angle ω. In some embodiments, the first ion beam 402 and the second ion beam 412 have the same implant energy and implant angle α. In some embodiments, the wafer tilt angle ω has an angle difference K ₂ . For example, the angle difference K ₂ is 0.2°, and the implanter is configured to project the five second ion beams 422 at the respective wafer tilt angles of -0.4°, -0.2°, 0°, 0.2°, and 0.4° On the second areas 322a to 322e. In some embodiments, the angle difference K _{1 is the} same or different from the angle difference K ₂ . In some embodiments, the first zone 310 is prevented from receiving the ion beam 422 during the projection of the second ion beam.

When the second ion beam 412 is projected onto the surface 110S of the first wafer 110, the ionized particles in the second ion beam 412 are accelerated by the implanter and penetrate into the internal lattice structure of the first wafer 110. A part of the ionized particles of the second ion beam 412 collides with atoms in the lattice structure and generates a second thermal wave 414 propagating outward. A heat wave detector (such as a thermometer) is used to receive the second heat wave 414 caused by the collision of the second ion beam 412 and the lattice structure. The intensity or temperature of the second thermal wave 414 is determined by the degree of collision, which is related to the actual irradiation angle of the second ion beam 412. Since the second ion beam 412 is projected onto the individual second regions 322 at different wafer tilt angles ω, the second thermal waves 414 with different wafer tilt angles ω have different wave intensities.

Referring to the plots (A) and (B) of FIG. 4, due to the rotation of the first wafer 110 by a torsion angle θ of 180 degrees, the crystal orientation angles β and -β are distinguished by a sign. In some embodiments, assuming a wafer tilt angle ω of zero degrees, the second ion beam 412 is irradiated onto the second region 322 at an irradiation angle of (α+β). By tuning the wafer tilt angle ω, the actual irradiation angle can be made smaller than (α+β) to achieve greater ion penetration and less collisions between ionized particles and lattice atoms, thus reducing the respective second thermal waves 414 The intensity of the wave. In some embodiments, when the wafer tilt angle ω is tuned to compensate for the included angle (α+β), the second ion beam 404 hits the crystal plane with a minimum irradiation angle (substantially zero degrees), which results in the second thermal wave 414 A minimum wave intensity.

In step 212, a first crystal orientation angle β of the first wafer 110 is estimated based on the first ion beam 402, the second ion beam 412, the first thermal wave 404, and the second thermal wave 414. In some embodiments, the implantation angle of the implanter is also estimated based on the first ion beam 402, the second ion beam 412, the first thermal wave 404, and the second thermal wave 414. Referring to FIG. 5, a schematic diagram 500 illustrates the intensity of the heat wave versus the wafer tilt angle ω according to some embodiments. The intensities of the first heat wave 404 and the second heat wave 414 are plotted on the graph 500. The diamond mark indicates the intensity of the first heat wave 404 at different wafer tilt angles ω and the square mark indicates the intensity of the second heat wave 414 at different wafer tilt angles ω.

A curve fitting operation is performed to generate a curve that best fits the measurement of the first heat wave 404, as shown by the dashed line. Similarly, another curve fitting operation is performed to generate a curve that best fits the measurement of the second heat wave 414, as shown by the solid line. Subsequently, a wafer tilt angle ω _{1 is} determined, which obtains one of the smallest intensities of the first heat wave 404. Similarly, another wafer tilt angle ω _{2 is} determined, which obtains one of the smallest intensities of the second heat wave 414. In some embodiments, the value of the _{wafer tilt angle ω 1} or ω ₂ is determined by solving an equation describing the curve of the first heat wave 404 or the second heat wave 414.

_{As previously discussed, the wafer tilt angle ω 1} that causes the minimum wave intensity of the first heat wave 404 corresponds to the angle difference (α-β) and the wafer tilt angle ω ₂ that causes the minimum wave intensity of the second heat wave 414 corresponds to Angle difference (α+β). Therefore, the values of the implantation angle α and the crystal orientation angle β can be estimated through linear algebra and can be expressed as follows.

α=(ω ₁ +ω ₂ )/2

β=(ω ₂ -ω ₁ )/2

FIG. 6 is a flowchart of a method 600 of manufacturing a semiconductor device according to some embodiments. It should be understood that additional steps may be provided before, during, and after the steps shown in FIG. 6, and some of the steps described below may be substituted or eliminated in other embodiments of the method 600. The order of the steps can be interchangeable.

In step 602, a first wafer is received. In some embodiments, the first wafer is the wafer 110a in FIG. 1A and the wafer 110 in FIGS. 3 and 4. In step 604, a first zone and a second zone are defined on the first wafer. In some embodiments, the first zone and the second zone are the first zone 310 and the second zone 320 in FIG. 3. In some embodiments, the first area 312 is defined in the first zone 310 and the second area 322 is defined in the second zone 320.

In step 606, a first ion beam projection and a second ion beam projection are performed, wherein the first ion beam and the second ion beam are respectively projected to the first crystal by the respective first ion beam projection and the second ion beam projection. On the first zone and the second zone of the circle. In some embodiments, the first ion beam and the second ion beam are the first ion beam 402 and the second ion beam 412, respectively. In some embodiments, the first area and the second area receive the first ion beam projection and the second ion beam projection at respective implanter tilt angles. In some embodiments, the first heat wave and the second heat wave are received in response to the first ion beam projection and the second ion beam projection, respectively. In some embodiments, the first ion beam projection or the second ion beam projection in step 606 is performed in a manner similar to steps 206, 208, and 210.

In step 608, a first crystal orientation angle of a first wafer is estimated based on the first ion beam and the second ion beam. In some embodiments, the first crystal orientation angle of the first wafer is further estimated based on the first heat wave and the second heat wave. In some embodiments, in step 608, the implantation angle of the implanter is also estimated based on the first ion beam, the second ion beam, the first thermal wave, and the second thermal wave. In some embodiments, the estimation of the first crystal orientation angle of the first wafer and the implantation angle of the implanter in step 608 is performed in a manner similar to that of step 212.

In step 610, a second wafer is received. In some embodiments, the second wafer is the wafer 110b in FIG. 1A and the wafer 110 in FIGS. 3 and 4. In some embodiments, the first wafer and the second wafer are test wafers. In some embodiments, the first wafer and the second wafer are manufactured from the same semi-conductive ingot and separated by one or more other wafers in the semi-conductive ingot. In some embodiments, the first wafer and the second wafer belong to the same wafer lot and are separated by one or more other wafers.

In step 612, a third zone and a fourth zone are defined on the second wafer. In some embodiments, the third zone and the fourth zone are the first zone 310 and the second zone 320 in FIG. 3. In some embodiments, the first area 312 is defined in the first zone 310 and the second area 322 is defined in the second zone 320.

In step 614, a third ion beam projection and a fourth ion beam projection are performed, wherein the third ion beam and the fourth ion beam are respectively projected to the second crystal by the respective third ion beam projection and the fourth ion beam projection. On the third and fourth zones of the circle. In some embodiments, the third ion beam and the fourth ion beam are the first ion beam 402 and the second ion beam 412, respectively. In some embodiments, the first area 312 and the second area 322 of the second wafer receive the third ion beam projection and the fourth ion beam projection at respective implanter tilt angles. In some embodiments, the third heat wave and the fourth heat wave are received in response to the third ion beam projection and the fourth ion beam projection, respectively. In some embodiments, the third ion beam projection or the fourth ion beam projection in step 614 is performed in a manner similar to that in steps 206, 208, and 210.

In step 616, a second crystal orientation angle of a second wafer is estimated based on the third ion beam and the fourth ion beam. In some embodiments, the second crystal orientation angle of the second wafer is further estimated based on the third heat wave and the fourth heat wave. In some embodiments, in step 616, the implantation angle of the implanter is also estimated based on the third ion beam, the fourth ion beam, the third thermal wave, and the fourth thermal wave. In some embodiments, the estimation of the second crystal orientation angle of the second wafer and the implantation angle of the implanter performed in step 616 is performed in a manner similar to that of step 212.

In step 618, a third wafer is received. In some embodiments, the third wafer is a wafer prepared for manufacturing a semiconductor device. In some embodiments, the third wafer is manufactured by manufacturing a semiconductive ingot of the first wafer and the second wafer. In some embodiments, the third wafer belongs to a wafer lot that is the same as the first wafer and the second wafer. In some embodiments, the third wafer is in one of the semi-conductive ingots between the first wafer and the second wafer.

In step 620, a third crystal orientation angle of the third wafer is determined based on the first crystal orientation angle and the second crystal orientation angle. In some embodiments, the determination is determined by interpolating or extrapolating the first crystal orientation angle and the second crystal orientation angle based on the distance between the first wafer, the second wafer, and the third wafer in the semiconductive ingot The third crystal orientation angle of the third wafer. In some embodiments, the third crystal orientation angle of the third wafer is an arithmetic mean value of the first wafer crystal orientation angle and the second wafer crystal orientation angle. In some embodiments, a fourth crystal orientation angle of a fourth wafer in the same semiconductive ingot is received, and the fourth crystal orientation angle is based on the first crystal orientation angle, the second crystal orientation angle, and the fourth crystal orientation angle (for example, through A suitable approximation method, such as curve fitting or linear regression, determines the third crystal orientation angle of the third wafer.

In some embodiments, the implanters used to perform ion beam projection in steps 606 and 614 are the same implanters, and the implantation is determined based on the estimated results of the implant angle of the implanters performed in steps 608 and 616. The final implantation angle of the implanter. In some embodiments, the final implantation angle is determined by averaging the estimated results of the implantation angles of the first wafer and the second wafer performed in steps 608 and 616.

In step 622, an ion implantation is performed on the third wafer according to the third crystal orientation angle. In some embodiments, the third wafer is not a test wafer and ion implantation is performed to create a well in the third wafer for manufacturing a semiconductor device. In some embodiments, ion implantation is performed on the third wafer according to the implantation angle of the implanter.

FIG. 7 is a flowchart of a method 700 of manufacturing a semiconductor device according to some embodiments. It should be understood that additional steps may be provided before, during, and after the steps shown in FIG. 7, and some of the steps described below may be substituted or eliminated in other embodiments of the method 700. The order of the steps can be interchangeable.

In step 702, a plurality of wafers are received. In some embodiments, the plurality of wafers belong to the same wafer lot or different wafer lots. In some embodiments, a plurality of wafers are manufactured from the same semi-conductive ingot or manufactured from different semi-conductive ingots. In step 704, the crystal orientation angles of a plurality of wafers are estimated. In some embodiments, method 200 (in which the crystal orientation angle is estimated in step 212) or method 600 (in which the crystal orientation angle is estimated in step 602) is used to determine each of the plurality of wafers based on the crystal orientation angles of other wafers. Orientation angle of the crystal. In some embodiments, the crystal orientation angle is estimated by another suitable method. In some embodiments, an implantation angle of an implanter is also estimated in step 704. In some embodiments, the plurality of wafers includes one or more test wafers, and the crystal orientation angle of the test wafers is estimated. Determine the crystal orientation angles of the rest of the plurality of wafers based on the estimated crystal orientation angles of the test wafers.

In step 706, a plurality of wafers (excluding test wafers, if present) are classified into more than one wafer group according to their equal crystal orientation angles. In some embodiments, each wafer group is identified by a representative crystal orientation angle. In some embodiments, the number of wafer groups is determined based on the granularity of the classified crystal orientation angles. A smaller standard deviation of the crystal orientation angle of the wafers in a wafer group may require more wafer groups, which results in a more accurate representative crystal orientation angle of each wafer group. The wafers in each wafer group can be from the same or different semi-conductive ingots.

In step 708, at least one wafer from a certain wafer group is selected. In step 710, an ion implantation operation is performed on at least one selected wafer. In some embodiments, the implanter is used to perform the ion implantation operation based on the estimated tilt angle of the implanter and the representative crystal orientation angle of the wafer group from which at least one wafer is selected. Since the selected wafers share a common representative crystal orientation angle, it can be compared to one of these wafers by minimizing or eliminating the variability of the crystal orientation angle between different wafers in a mass production process. Perform ion implantation with a more precise tilt angle.

FIG. 8 is a schematic diagram of a system 800 for implementing a method for estimating crystal orientation angles according to some embodiments. The system 800 includes one or more processors 801, a network interface 803, an input and output (I/O) device 805, a storage 807, a memory 809, and a bus 808. The bus 808 couples the network interface 803, the I/O device 805, the storage 807, the storage 809, and the processor 801 with each other.

The processor 801 is configured to execute program instructions, and the program instructions include a tool configured to execute the method described and illustrated with reference to the figures of this disclosure. Therefore, the tool is configured to perform steps such as estimating and providing crystal orientation angles and tuning parameters of one or more semiconductor processing devices (e.g., the tilt angle of an implanter).

The network interface 803 is configured to access program instructions and remotely stored data accessed by program instructions via a network (not shown).

The I/O device 805 includes an input device and an output device configured to interact with the user of the system 800. In some embodiments, the input device includes, for example, a keyboard, a mouse, and other devices. The output device includes, for example, a display, a printer, and other devices.

The storage device 807 is configured to store program instructions and data accessed by the program instructions. In some embodiments, the storage device 807 includes a non-transitory computer-readable storage medium, such as a magnetic disk and an optical disk.

The memory 809 is configured to store program instructions to be executed by the processor 801 and data accessed by the program instructions. In some embodiments, the memory 809 includes any combination of a random access memory (RAM), some other volatile storage device, a read-only memory (ROM), and some other non-volatile storage device.

According to an embodiment, a method includes: receiving a first wafer; defining a first zone and a second zone on the first wafer; defining the first zone and the second zone respectively A plurality of first regions and second regions; projecting a first ion beam onto the first regions and receiving a first thermal wave in response to the first ion beams; rotating the first wafer to a twist angle ; Projecting the second ion beam onto the second areas and receiving the second heat wave in response to the second ion beams; and based on the first ion beams and the second ion beams and the first The heat wave and the second heat waves estimate a first crystal orientation angle of the first wafer.

According to an embodiment, a method includes: defining a first zone and a second zone on a first wafer; and projecting a first ion beam and a second ion beam to the first zone and the second zone, respectively On the second zone; estimate a first crystal orientation angle of the first wafer based on the first ion beams and the second ion beams; define a third zone and a first on a second wafer Four zones; the third ion beam and the fourth ion beam are projected onto the third zone and the fourth zone respectively; the second crystal is estimated based on the third ion beams and the fourth ion beams Circle a second crystal orientation angle; and estimate a third crystal orientation angle of a third wafer based on the first crystal orientation angle and the second crystal orientation angle.

According to an embodiment, a method includes: receiving a plurality of wafers; estimating crystal orientation angles of the plurality of wafers; classifying the plurality of wafers into wafer groups according to their equal crystal orientation angles; One of the circle groups selects at least one wafer; and an ion implantation operation is performed on the at least one wafer according to a representative crystal orientation angle of the one of the wafer groups.

The foregoing summarizes the features of several embodiments, so that those familiar with the art can better understand the aspect of the present disclosure. Those familiar with the technology should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purpose and/or achieving the same advantages of the embodiments described herein. Those familiar with this technology should also recognize that these equivalent structures do not deviate from the spirit and scope of the disclosure, and that various changes, substitutions and alterations can be made in this article without departing from the spirit and scope of the disclosure.

100: Method 102: Crystal growth operation 103: Semi-conductive ingot 103L: Longitudinal axis 104: Operation 108a: Position 108b: Position 108c: Position 110: Semiconductor wafer 110a: Semiconductor wafer 110b: Semiconductor wafer 110c: Semiconductor wafer 110L: Crystal Orientation Line 110L1: Crystal Orientation Line 110L2: Crystal Orientation Line 110L3: Crystal Orientation Line 110N: Notch 110R: Target Line/Reference Line 110S: Surface 110T: Target Line/Reference Line 120: Ion Beam 120P: Path 130: Notch 200: Method 202: Step 204: Step 206: Step 208: Step 210: Step 212: Step 302: Mark 310: First Zones 312a to 312e: First Zone 320: Second Zones 322a to 322e: First Second area 402: first ion beam 404: first thermal wave 412: second ion beam 414: second thermal wave 500: schematic/chart 600: method 602: step 604: step 606: step 608: step 610: step 612 : Step 614: Step 616: Step 618: Step 620: Step 622: Step 700: Method 702: Step 704: Step 706: Step 708: Step 710: Step 800: System 801: Processor 803: Network interface 805: Input And output (I/O) device 807: storage 808: bus 809: memory N: normal line N1: normal line N2: normal line N3: normal line S1: line of symmetry α: included angle β: crystal orientation angle β ₁ : Included angle β ₂ : included angle β ₃ : included angle θ: twist angle ω: wafer tilt angle ω ₁ : wafer tilt angle ω ₂ : wafer tilt angle

When read in conjunction with the accompanying drawings, the aspect of the present disclosure can be better understood from the following embodiments. It should be noted that according to standard practice in the industry, various components are not drawn to scale. In fact, for clarity of discussion, the size of various components can be increased or decreased arbitrarily.

FIG. 1A is a schematic diagram showing a method of forming a semiconductor wafer according to some embodiments.

FIG. 1B is a schematic diagram showing an ion beam projected onto a semiconductor wafer according to some embodiments.

2 is a flowchart of a method for estimating a crystal orientation angle of a semiconductor wafer according to some embodiments.

FIG. 3 is a schematic diagram showing a surface of a semiconductor wafer with divided zones according to some embodiments.

FIG. 4 is a schematic diagram showing ion beam projection according to some embodiments.

FIG. 5 is a schematic diagram showing the intensity of the heat wave versus the tilt angle of the wafer according to some embodiments.

6 is a flowchart of a method of estimating a crystal orientation angle of a semiconductor wafer according to some embodiments.

FIG. 7 is a flowchart of a method of manufacturing a semiconductor device according to some embodiments.

FIG. 8 is a schematic diagram of a system for implementing a crystal orientation angle estimation method according to some embodiments.

200: method

202: Step

204: Step

206: Step

208: Step

210: Step

212: Step

Claims (20)

A method including: Receiving a first wafer; Defining a first zone and a second zone on the first wafer; Defining a plurality of first areas and second areas for the first zone and the second zone respectively; Projecting first ion beams onto the first regions and receiving first heat waves in response to the first ion beams; Rotating the first wafer to a twist angle; Projecting second ion beams onto the second areas and receiving second heat waves in response to the second ion beams; and Estimating a first crystal orientation angle of the first wafer based on the first ion beams and the second ion beams, the first heat waves and the second heat waves. The method of claim 1, wherein projecting the first ion beams onto the first regions includes projecting each of the first ion beams onto each of the first regions at different times and using The first wafer is tilted up to respective first tilt angles, wherein the first tilt angles have an angle difference. The method of claim 1, wherein projecting the second ion beams onto the second regions includes projecting each of the second ion beams onto each of the second regions at different times and using The first wafer is tilted up to respective second tilt angles, wherein the second tilt angles are separated by a second difference. Such as the method of claim 1, wherein the twist angle is substantially 180 degrees. The method of claim 1, wherein estimating a crystal orientation angle of the first wafer includes measuring the first intensity and the second intensity of the first heat waves and the second heat waves, respectively. Such as the method of claim 1, which further includes: Receiving a second wafer and defining a third zone and a fourth zone on the second wafer, wherein the first wafer and the second wafer are manufactured from a same ingot; Project a third ion beam and a fourth ion beam onto the third zone and the fourth zone respectively; and Estimating a second crystal orientation angle of the second wafer based on the third ion beams and the fourth ion beams. Such as the method of claim 6, which further includes: Receiving a third wafer from the ingot; and A crystal orientation angle of the third wafer is estimated based on the first crystal orientation angle and the second crystal orientation angle. The method of claim 7, wherein the crystal orientation angle of the third wafer includes an arithmetic mean value of the first wafer crystal orientation angle and the second wafer crystal orientation angle. Such as the method of claim 1, further comprising projecting the first ion beams and the first ion beams based on the first ion beams and the second ion beams and the first heat waves and the second heat waves. One of two ion beam implanters and one implant angle. According to the method of claim 9, further comprising performing ion implantation on the third wafer according to the third crystal orientation angle and the implantation angle. The method of claim 1, wherein the first zone and the second zone have a semicircular shape. Such as the method of claim 1, wherein the first regions include a first central region laterally surrounded by the remaining first regions and the second zone. A method including: Defining a first zone and a second zone on a first wafer; Projecting a first ion beam and a second ion beam onto the first zone and the second zone respectively; Estimating a first crystal orientation angle of the first wafer based on the first ion beams and the second ion beams; Defining a third zone and a fourth zone on a second wafer; Project a third ion beam and a fourth ion beam onto the third zone and the fourth zone respectively; Estimating a second crystal orientation angle of the second wafer based on the third ion beams and the fourth ion beams; and A third crystal orientation angle of a third wafer is estimated based on the first crystal orientation angle and the second crystal orientation angle. The method of claim 13, further comprising forming a semi-conductive ingot and cutting the semi-conductive ingot to form the first wafer, the second wafer, and the third wafer. The method of claim 13, wherein projecting a first ion beam and a second ion beam onto the first zone and the second zone further comprises projecting one of the first ion beams onto the first zone On a first area and project one of the second ion beams onto a second area of the second zone, wherein the one of the first ion beams and the second ion beams The one has the same energy and implant angle. The method of claim 15, wherein the first area and the second area are symmetrical with respect to a symmetry line of the first wafer. A method including: Receive multiple wafers; Estimate the crystal orientation angle of the plurality of wafers; Classify the plurality of wafers into wafer groups according to their equal crystal orientation angles; Select at least one wafer from one of the wafer groups; and An ion implantation operation is performed on the at least one wafer according to a representative crystal orientation angle of the one of the wafer groups. The method of claim 17, further comprising estimating an implantation angle of an implanter that performs the ion implantation operation, wherein the ion implantation operation is performed according to the implantation angle. The method of claim 17, wherein the plurality of wafers includes a test wafer, wherein the estimation of the crystal orientation angles of the plurality of wafers includes estimating the crystal orientation angles of the remaining wafers Measure the crystal orientation angle of one of the test wafers. The method of claim 19, wherein the estimation of the crystal orientation angle of the test wafer includes projecting ion beams onto different areas of the test wafer at different wafer inclination angles.

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