TW202110300A - Electronic component embedded substrate - Google Patents

Abstract

There is provided an electronic component embedded substrate with a structure in which an electronic component is embedded in a position overlapped with a ground plane for ensuring high heat dissipation while preventing delamination in a moisture absorption sensitivity level test. The electronic component embedded substrate 1 comprises: a wiring layer L3 embedded between insulation layers 13 and 14, and an electronic component 40 embedded between insulation layers 12 and 13. The wiring layer L3 comprises a ground plane G overlapped with the electronic component 40, and further comprises a region A1 which, as observed in a top view, is surrounded by a circle with a center point overlapped with a corner of the electronic component 40 and a radius of 1/3 a short side of the electronic component 40, and a region A2 which, as observed in a top view, is overlapped with the electronic component 40 while not duplicated with the region A1. The region A1 is formed with opening parts H. Thereby, moisture contained in the insulation layers 12 and 13 can be easily discharged, and high heat dissipation can be ensured.

Description

Built-in substrate for electronic parts

The present invention relates to an electronic component built-in substrate, and more particularly to an electronic component built-in substrate having a structure in which electronic components are embedded in a position overlapping with a large-area ground reference plane.

As described in Patent Documents 1 and 2, in an electronic component built-in substrate, electronic components such as semiconductor ICs are embedded so as to overlap with a large-area ground reference plane. If the electronic components overlap with the ground reference plane when viewed from above, the signal quality of the signal transmitted in the substrate of the electronic component can be improved, and the heat generated by the operation of the electronic component can be effectively dissipated . [Prior Technical Literature] [Patent Literature]

Patent Document 1: Japanese Patent Laid-Open No. 2008-91471 Patent Document 2: Japanese Patent Laid-Open No. 2012-209527

(The problem to be solved by the invention)

However, in the electronic component built-in substrate described in Patent Document 1, since a plurality of openings are formed on the ground reference surface, and the openings are provided at positions overlapping with the electronic components, there is a problem due to the openings. There is a problem of reduced heat dissipation. On the other hand, in the electronic component built-in substrate described in Patent Document 2, since the electronic component is covered by the ground reference surface without openings, although high heat dissipation can be obtained, it is due to the suction performed before shipment. In the moisture sensitivity test (MSL test), there is a problem that peeling occurs easily at the interface between the electronic component and the insulating layer.

Therefore, the object of the present invention is to prevent peeling during moisture absorption sensitivity tests while ensuring high heat dissipation in an electronic component built-in substrate having a structure in which electronic components are embedded in a position overlapping with the ground reference plane. . (Technical means to solve the problem)

The electronic component built-in substrate of the present invention is characterized in that it includes: first, second, and third insulating layers; a first wiring layer, which is buried between the first insulating layer and the second insulating layer; and Electronic components, which are buried between the second insulating layer and the third insulating layer; the first wiring layer includes a ground reference plane, the electronic components are arranged at a position that overlaps the ground reference plane when viewed from above, and the first wiring layer includes There is a first area. The first area is the area surrounded by a circle with the point overlapping with the corner of the electronic component as the center and 1/3 of the short side of the electronic component as the radius when viewed from above. An opening is formed on the ground reference plane in one area.

According to the present invention, since an opening is formed in the ground reference plane in the first region overlapping with the vicinity of the corner of the electronic component, the moisture contained in the second and third insulating layers is easily discharged. Thereby, it is possible to improve the adhesiveness near the corners of the electronic component where peeling is most likely to occur.

In the present invention, the electronic component has first and second edges. The corners are formed by the terminal portions of the first and second edges. At least one of the first and second edges can also be connected to ground. The section where the reference plane overlaps is longer than the section where it does not overlap with the ground reference plane. Even with the above structure, since peeling is likely to occur near the corners of the electronic component, it is also possible to prevent peeling by providing an opening on the ground reference surface. In this case, at least one of the first and second edges may overlap with the ground reference plane in the entire section. In the case of this structure, although peeling is more likely to occur near the corners of the electronic component, it is possible to prevent peeling by providing an opening on the ground reference surface.

In the present invention, the first wiring layer is also provided with a second area, which overlaps with the electronic component when viewed from above and does not overlap with the first area, and is within the ground reference plane in the first area The pattern formation density can also be lower than the pattern formation density of the ground reference plane in the second region. Although this structure is a structure that does not easily drain the water contained in the second and third insulating layers, the water is easily drained due to the opening of the ground reference surface. Moreover, since the patterning density of the ground reference plane is high in the second area overlapping with the electronic component, sufficient heat dissipation can also be ensured.

In the present invention, a ground reference plane may also exist in the entire second area. In this way, higher heat dissipation can be obtained.

In the present invention, when a rectangular area including the first and second areas is defined in the first wiring layer, the first wiring layer further includes a third area, and the third area is included in the rectangular area In addition, a region that does not overlap with the first and second regions, and the pattern formation density of the ground reference plane in the first region can also be lower than the pattern formation density of the ground reference plane in the third region. In this way, since a larger area of the ground reference plane is used, the signal quality of the signal transmitted in the built-in substrate of the electronic component can be further improved, and higher heat dissipation can be obtained.

In the present invention, a ground reference plane may also exist in the entire third area. In this way, the signal quality of the signal transmitted in the internal substrate of the electronic component can be further improved, and higher heat dissipation can be obtained.

The electronic component built-in substrate of the present invention preferably also has a second wiring layer, the second wiring layer is located on the opposite side of the first wiring layer via the first insulating layer; the second wiring layer is provided with a ground The reference plane, the second wiring layer is provided with a fourth region overlapping the first region of the first wiring layer, and an opening is formed in the ground reference plane located in the fourth region. Thereby, the drainage path of moisture will not be blocked by the ground reference plane formed on the second wiring layer. In this case, it is preferable that the opening formed in the first area and the opening formed in the fourth area have an overlapping portion when viewed in a plan view. This makes it easier to drain water.

In the present invention, the electronic component may be a semiconductor IC, and it may be buried in between the second insulating layer and the third insulating layer so that the back surface opposite to the main surface on which the terminal electrode is formed faces the ground reference. between. In this way, the ground reference plane can cover substantially the entire back surface of the semiconductor IC. (Compared with the effect of previous technology)

As described above, according to the present invention, in an electronic component built-in substrate having a structure in which electronic components are embedded in a position overlapping with the ground reference plane, it is possible to prevent peeling during the moisture absorption sensitivity test while ensuring high heat dissipation.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the drawings.

1 is a schematic cross-sectional view for explaining the structure of an electronic component built-in substrate 1 according to a preferred embodiment of the present invention.

As shown in FIG. 1, the electronic component built-in substrate 1 of this embodiment includes four insulating layers 11 to 14, wiring layers L1 to L4 formed on the surfaces of the insulating layers 11 to 14, and buried in The electronic component 40 between the wiring layer L2 and the wiring layer L3. Although not particularly limited, the insulating layer 11 located at the uppermost layer and the insulating layer 14 located at the lowermost layer may also be core layers in which a core material such as glass fiber is impregnated with a resin material such as glass epoxy. In contrast, the insulating layers 12 and 13 may be made of a resin material that does not include a core material such as glass cloth. In particular, it is preferable that the thermal expansion coefficient of the insulating layers 11 and 14 is smaller than the thermal expansion coefficient of the insulating layers 12 and 13. Although the type of the electronic component 40 is not particularly limited, for example, it may be a semiconductor IC. In the example shown in FIG. 1, the electronic component 40 is embedded in a front type manner so that the main surface on which the terminal electrode 41 is formed faces the upper side.

The wiring layer L1 is the uppermost wiring layer, and most of it is covered by the solder resist 21. The area not covered by the solder resist 21 in the wiring layer L1 constitutes an external terminal E1 on which a chip component or the like is mounted. The wiring layer L4 is the wiring layer located in the lowermost layer, and most of it is covered by the solder resist 22. The area not covered by the solder resist 22 in the wiring layer L4 constitutes the external terminal E2 connected to the mother board via solder. In contrast, the wiring layers L2 and L3 are located in the inner layer. Among them, the wiring layer L2 is located between the insulating layer 11 and the insulating layer 12, and the wiring layer L3 is located between the insulating layer 13 and the insulating layer 14. In addition, the wiring layer L1 and the wiring layer L2 are connected via via-hole conductors 31, the wiring layer L2 and the terminal electrodes 41 of the electronic component 40 are connected via via-hole conductors 32, and the wiring layer L2 and the wiring layer L3 are via via-hole conductors. 33 is connected, and the wiring layer L3 and the wiring layer L4 are connected via the via-hole conductor 34.

As shown in FIG. 1, a ground reference plane G is provided on the wiring layer L3. The ground reference plane G is a large-area solid pattern supplied with a ground potential, and is provided at a position overlapping with the electronic component 40 when viewed from above. The ground reference plane G can perform the following functions: improve the signal quality of the signal transmitted to the signal wiring formed on the other wiring layers L1, L2, L4, and effectively dissipate the heat generated by the operation of the electronic component 40 .

However, if the ground reference plane G is a completely solid pattern, the release path of the moisture contained in the insulating layers 12 and 13 is blocked by the ground reference plane G, and there is a possibility of moisture remaining near the electronic component 40 . If moisture remains in the vicinity of the electronic component 40, there is a possibility that the expansion of moisture occurs during the solder reflow step, thereby causing peeling at the interface between the electronic component 40 and the insulating layer 13. In view of this, in the electronic component built-in substrate 1 of this embodiment, an opening H is provided in a part of the ground reference plane G, so that moisture can be released from the opening.

FIG. 2 is a schematic diagram for explaining the positional relationship between the electronic component 40 and the opening H. As shown in FIG. The electronic component 40 is in contact with the insulating layer 13 on the back side. Although the electronic component 40 is less likely to be peeled from the insulating layer 13 in the region 42 located at the center of the back surface, peeling is likely to occur at the edge. In particular, in the edge portion of the back surface, the area 44 which is farther from the corner portion and closer to the corner portion is more likely to be peeled off. In this embodiment, the length of the regions 43 and 44 is defined as 1/3 of the length of one side of the electronic component 40. Here, the reason why peeling easily occurs in the region 44 is because when the insulating layer 13 containing moisture is thermally expanded, the stress caused by the difference in the coefficient of thermal expansion is concentrated on the corners of the electronic component 40. Therefore, in order to prevent peeling of the electronic component 40, it is necessary to effectively release the moisture remaining near the corner portion before the solder reflow. To achieve this, an opening H is provided near the corner portion of the electronic component 40 when viewed from above. As a result, in the preheating step performed before the solder reflow, since the moisture contained in the insulating layers 12 and 13 is discharged through the opening H, at least the amount of moisture in the vicinity of the corners of the electronic component 40 is greatly increased. Therefore, even if the solder reflow is performed, it is difficult to cause peeling of the electronic component 40.

FIG. 3 is a schematic diagram for explaining the position of the opening H formed in the ground reference plane G in more detail. As mentioned above, peeling of the electronic component 40 is likely to occur at the edge of the back, especially in the area 44 near the corner. Therefore, in order to effectively release the moisture remaining around the area 44, the position of the opening H needs to be determined. In view of this, in the electronic component built-in substrate 1 of the present embodiment, the area A1 is defined in the wiring layer L3, and the opening H is arranged in the area A1, wherein the area A1 is viewed in a plan view with the electrons The area surrounded by a circle with the overlapping point C of the corners of the part 40 as the center and one-third of one side of the electronic part 40 as the radius. Preferably, when there is a ground reference plane G at a position overlapping with the electronic component 40 in the wiring layer L4, a region A4 that coincides with the region A1 in a plan view is defined in the wiring layer L4 and in the region A4 An opening is arranged inside. This is because when the wiring layer L4 has a ground reference plane G with a solid pattern, only the opening H is provided in the wiring layer L3, and moisture cannot be effectively released. In this case, as shown in FIG. 1, it is preferable that the opening H provided in the wiring layer L3 and the opening H4 provided in the wiring layer L4 have an overlapping portion D in a plan view.

In the first example shown in FIG. 3, one opening H is respectively arranged at a position in the area A1 that does not overlap with the electronic component 40 when viewed from above. In the wiring layer L3, the area that overlaps the electronic component 40 when viewed from above and does not overlap with the area A1 is defined as the area A2, and is included in the rectangular area A including the areas A1 and A2. When any area that does not overlap is defined as the area A3, the ground reference plane G exists in the entire areas A2 and A3. Thereby, not only the moisture remaining near the corners of the electronic component 40 can be discharged in the preheating step, but also the heat generated by the operation of the electronic component 40 can be effectively dissipated through the ground reference plane G. That is, the water discharge characteristics and heat dissipation characteristics can be realized at the same time.

In the second example shown in FIG. 4, one opening H is respectively arranged at a position overlapping with the electronic component 40 in the area A1 when viewed from above. For the areas A2 and A3, a ground reference plane G exists in the entire area. In this way, the opening H may be provided at a position overlapping with the electronic component 40.

In the third example shown in FIG. 5, an opening H is respectively arranged at a position overlapping with the electronic component 40 and a position not overlapping in the area A1 when viewed from above. For the areas A2 and A3, a ground reference plane G exists in the entire area. In this way, the opening H may be provided at both a position overlapping with the electronic component 40 and a position not overlapping.

In the fourth example shown in FIG. 6, one opening H is respectively arranged at a position overlapping with the corner of the electronic component 40 in the area A1 when viewed from above. For the areas A2 and A3, a ground reference plane G exists in the entire area. In this way, the opening H may be provided at a position overlapping with the corner of the electronic component 40.

In the fifth example shown in FIG. 7, three openings H are respectively arranged along the edge at a position in the area A1 that does not overlap with the electronic component 40 when viewed from above. For the areas A2 and A3, a ground reference plane G exists in the entire area. In this way, a plurality of openings H may also be provided along the edge of the electronic component 40.

In the sixth example shown in FIG. 8, a plurality of openings H are regularly arranged along the edge of the electronic component 40 so as not to overlap with the electronic component 40. Most of the openings H are located in the area A1, but some of the openings H are located in the area A3. For the area A2, a ground reference plane G exists in the entire area. In this way, a part of the opening H may also be located in the area A3. Even in this case, as long as the openings H are laid out in such a way that the patterning density of the ground reference plane G in the area A1 is lower than that of the ground reference plane G in the area A3, the water can still be discharged at the same time. Characteristics and heat dissipation characteristics.

In the seventh example shown in FIG. 9, a plurality of openings H are regularly arranged along the edge of the electronic component 40 so as to overlap with the edge of the electronic component 40. Most of the openings H are located in the area A1, but some of the openings H are located in the areas A2 and A3. In this way, a part of the opening H may also be located in the areas A2 and A3. Even in this case, if the patterning density of the ground reference plane G in the area A1 is lower than that of the ground reference plane G in the area A2, the openings H can be laid out at the same time, and water can be discharged at the same time. Characteristics and heat dissipation characteristics.

In the eighth example shown in FIG. 10, most of the electronic components 40 do not overlap the ground reference plane G of the wiring layer L3, but the entire section of the edges 51 and 52 of the electronic component 40 overlaps the ground reference plane G of the wiring layer L3 . Regarding the edges 53 and 54 of the electronic component 40, only a part of it overlaps with the ground reference plane G. The corner portion of the electronic component 40 is formed by the terminal portion of the edge 51 or 52 and the terminal portion of the edge 53 or 54. Even in this case, if the ground reference plane G overlapping the edges 51 and 52 is a solid pattern, peeling may occur near the corners. Therefore, as shown in FIG. 10, by providing the opening H in the area A1, peeling near the corner can be prevented. As mentioned above, even if most of the electronic component 40 does not overlap the ground reference plane G of the wiring layer L3, when an edge of the electronic component 40 overlaps the ground reference plane G of the wiring layer L3, if there is no opening H, it is still easy to peel off at the corners. This phenomenon is particularly noticeable when the entire section of an edge of the electronic component 40 overlaps with the ground reference plane G, but even if the entire section does not overlap with the ground reference plane G, the section overlapping with the ground reference plane G is better than the ground reference plane. If there is a longer edge in the area where the surface G does not overlap, it may still be a problem. Therefore, as shown in FIG. 10, an opening H can be provided in the area A1 to prevent peeling.

In the ninth example shown in FIG. 11, most of the edges 51, 52 of the electronic component 40 overlap the ground reference plane G of the wiring layer L3, but unlike the eighth example shown in FIG. 10, the edges 51, 52 The corner formed by 54 and the corner formed by the edges 52 and 53 do not overlap with the ground reference plane G of the wiring layer L3. In this case, since it is not easy to peel off at the above-mentioned corners, it only needs to be in the area A1 corresponding to the corners formed by the edges 51 and 53 and between the corners formed by the edges 52 and 54. The opening H may be provided in the corresponding area A1. As described above, in the present invention, it is not necessary to provide the opening H corresponding to all corners.

In addition, in the tenth example shown in FIG. 12, when the planar shape of the electronic component 40 is rectangular, the radius of the circle defining the area A1 can be set to 1/3 of the short side of the electronic component 40.

As described above, the electronic component built-in substrate 1 of the present embodiment has a large-area ground reference plane G at a position overlapping with the electronic component 40, so that heat dissipation characteristics and signal quality can be improved. Furthermore, since the ground reference plane G located near the corner of the electronic component 40 is provided with the opening H, it is possible to effectively discharge moisture from the insulating layers 12 and 13 after moisture absorption.

Although the preferred embodiments of the present invention have been described above, the present invention is not limited to the above-mentioned embodiments. Various changes can be made without departing from the essence of the present invention, and of course the contents are also included in the present invention. Within the scope of invention.

1: Built-in substrate for electronic parts 11~14: Insulation layer 21, 22: Solder resist 31~34: Through hole conductor 40: electronic parts 41: Terminal electrode 42~44: area 51~54: Edge A: Rectangular area A1: The first area A2: The second area A3: The third area C: point D: Overlap E1, E2: external terminals G: Ground reference plane H, H4: opening L1~L4: Wiring layer

1 is a schematic cross-sectional view for explaining the structure of an electronic component built-in substrate 1 according to a preferred embodiment of the present invention. FIG. 2 is a schematic diagram for explaining the positional relationship between the electronic component 40 and the opening H. As shown in FIG. Fig. 3 is a schematic diagram for explaining the position of the opening H in the first example. Fig. 4 is a schematic diagram for explaining the position of the opening H in the second example. Fig. 5 is a schematic diagram for explaining the position of the opening H in the third example. Fig. 6 is a schematic diagram for explaining the position of the opening H in the fourth example. Fig. 7 is a schematic diagram for explaining the position of the opening H in the fifth example. Fig. 8 is a schematic diagram for explaining the position of the opening H in the sixth example. Fig. 9 is a schematic diagram for explaining the position of the opening H in the seventh example. Fig. 10 is a schematic diagram for explaining the position of the opening H in the eighth example. Fig. 11 is a schematic diagram for explaining the position of the opening H in the ninth example. FIG. 12 is a schematic diagram for explaining the planar shape of the electronic component 40 of the tenth example.

1: Built-in substrate for electronic parts

11~14: Insulation layer

21, 22: Solder resist

31~34: Through hole conductor

40: electronic parts

41: Terminal electrode

D: Overlap

E1, E2: external terminals

G: Ground reference plane

H, H4: opening

L1~L4: Wiring layer

Claims (10)

An electronic component built-in substrate, which is characterized in that it has: The first, second and third insulating layers; A first wiring layer, which is buried between the first insulating layer and the second insulating layer; and Electronic components, which are buried between the second insulating layer and the third insulating layer; The above-mentioned first wiring layer includes a ground reference plane, The electronic component is arranged at a position overlapping the ground reference plane when viewed from above, The first wiring layer includes a first region, which is surrounded by a circle centered on a point overlapping with the corner of the electronic component and 1/3 of the short side of the electronic component as a radius when viewed from above. Area, and An opening is formed in the ground reference plane located in the first region. For example, the electronic component of claim 1 has a built-in substrate, of which, The above electronic component has first and second edges, The corner portion is formed by the terminal portions of the first and second edges, and At least one of the first and second edges has a section overlapping with the ground reference plane longer than a section not overlapping the ground reference plane. For example, the electronic component built-in substrate of claim 2, wherein at least one of the first and second edges, the entire section overlaps the ground reference plane. Such as the electronic component built-in substrate of any one of claims 1 to 3, wherein: The first wiring layer is also provided with a second region which is connected to the electrical The area where the sub-part overlaps and does not overlap with the above-mentioned first area, and, The pattern formation density of the ground reference plane in the first region is lower than the pattern formation density of the ground reference plane in the second region. For example, the electronic component built-in substrate of claim 4, wherein the ground reference plane exists in the entire second area. Such as the built-in substrate of the electronic component of claim 4 or 5, of which, When a rectangular area including the first and second areas is defined in the first wiring layer In other cases, the first wiring layer is further provided with a third region, which is included in the rectangular region and does not overlap with the first and second regions, and The patterning density of the ground reference plane in the first region is lower than the patterning density of the ground reference plane in the third region. For example, the electronic component built-in substrate of claim 6, wherein the ground reference plane exists in the entire third area. For example, the electronic component built-in substrate of any one of claims 1 to 7, which also has: The second wiring layer, the second wiring layer is located in the first distribution via the first insulating layer The opposite side of the line layer; The second wiring layer is provided with a ground reference plane, The second wiring layer is provided with a fourth region overlapping with the first region of the first wiring layer, An opening is formed in the ground reference plane located in the fourth region. The electronic component built-in substrate of claim 8, wherein the opening formed in the first area and the opening formed in the fourth area have an overlapping portion when viewed from above. The electronic component built-in substrate according to any one of claims 1 to 9, wherein the electronic component is a semiconductor IC, and the back surface opposite to the main surface on which the terminal electrode is formed is the surface facing the ground reference The method is buried between the second insulating layer and the third insulating layer.

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