TW202046329A - Memory apparatus - Google Patents

Abstract

A memory apparatus is provided. A data read-write circuit is configured to access data in a memory cell array. A parity-data read-write circuit is configured to access a parity data in a parity memory cell array. A syndrome operation circuit generates an error decoding signal according to the data received from the data read-write circuit and the parity data received from the parity-data read-write circuit. During a same read period as reading the data, the data read-write circuit corrects an error bit of the data to output a corrected data and a correction bit signal based on the error decoding signal. The syndrome operation circuit further generates a parity data write signal to the parity-data read-write circuit to update the parity data in the parity data memory cell array according to the correction bit signal. The data read-write circuit also writes the corrected data back to the memory cell array.

Description

Memory device

The present invention relates to a memory device, and more particularly to a memory device with error checking and error correction functions.

With the advancement of technology, consumer demand for storage media has also increased rapidly. Among them, Dynamic Random Access Memory (DRAM) has the advantages of simple structure, high density, and low cost, so it is widely used Various electronic devices. In order to improve the data reliability of DRAM, some DRAMs are equipped with error-correcting code memory (ECC memory) to detect the error bit in the stored data and correct the error bit. At present, DRAM mainly uses single error correction (Single Error Correcting) technology, but the single error correction technology can only correct one-bit errors at a time. If the stored data has an error of more than 2 bits at the same time, the error correction function of the ECC circuit will fail. However, during DRAM operation, soft errors may occur due to factors such as high temperature, refresh, etc., resulting in error bits. If the error bit cannot be corrected in time, the stored data may accumulate two error bits and reduce the data reliability of the memory. Therefore, how to correct the stored data in time to avoid the accumulation of more than 2 error bits and maintain the accuracy of the DRAM data becomes a problem to be overcome.

The present invention provides a memory device that can correct error bits in real time and update stored data and correction data for error checking and correction during data reading cycles.

A memory device of the present invention includes: a data reading and writing circuit, a correction data reading and writing circuit, and a syndrome operation circuit. The data read-write circuit is coupled to the memory cell array for accessing data in the memory cell array. The calibration data read-write circuit is coupled to the calibration data memory cell array for accessing calibration data of the calibration data memory cell array. The syndrome calculation circuit generates an error decoding signal based on the data received from the data read and write circuit and the correction data received from the correction data read and write circuit. In the same read cycle when the data is read, the data read and write circuit The decoded signal corrects the error bits in the data and outputs the correct data and correction bit signals. The data read and write circuit writes the corrected data back to the memory cell array, and the syndrome calculation circuit also outputs corrections based on the correction bit signal The data write signal is sent to the calibration data read-write circuit to update the calibration data in the calibration data memory cell array.

Based on the above, the memory device of the present invention can read data from the memory cell array and complete inspection and calibration in one read cycle. When an error bit is found in the data, the memory device of the present invention can instantly correct the error in the same read cycle to output the correct data, and correspondingly write back the corrected data in a continuous period The memory cell array and the updated calibration data are written back to the calibration data memory cell array. Therefore, the memory device of the present invention can improve the reliability of data.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

FIG. 1 is a block diagram of a memory device according to an embodiment of the invention. 1, the memory device 100 includes a memory cell array 110, a calibration data memory cell array 120, a data reading and writing circuit 130, a calibration data reading and writing circuit 140, and a syndrome operation circuit 170, wherein the syndrome operation circuit 170 includes The syndrome generating circuit 150 and the syndrome decoding circuit 160. The data read/write circuit 130 is coupled to the memory cell array 110 to access the data MD of the memory cell array 110. The calibration data read-write circuit 140 is coupled to the calibration data memory cell array 120 to access the calibration data PM of the calibration data memory cell array 120. The correction data PM is an error checking and correction code used to check and correct the data MD, for example, the data MD is generated by ECC encoding procedures such as Hamming code (Hamming code). The number of bits of the correction data PM depends on the number of bits of the data MD. In this embodiment, the size of the data MD is 64 bits as an example, and the size of the correction data PM is correspondingly set to 7 bits, but the present invention does not limit the size of the data MD and the correction data PM.

The syndrome calculation circuit 170 is based on the data MD received from the data read/write circuit 130 (the data read/write circuit 130 reads the data MD and then outputs the read bit signal RD) and the correction data PM received from the correction data read/write circuit 140 ( The correction data reading and writing circuit 140 reads the correction data PM and outputs a correction read signal PS) to generate an error decoding signal SD, wherein, in the same reading cycle of reading the data MD, the data reading and writing circuit 130 decodes the signal SD according to the error Correct the error bit in the data MD and output the correct data (ie the data output signal RWB) and the correction bit signal CS. The data read and write circuit 130 writes the corrected data back to the memory cell array 110, and the syndrome calculation circuit 170 also outputs a correction data write signal NS according to the correction bit signal CS to the correction data read and write circuit 140 to update the correction data The correction data PM in the memory cell array 120.

In other words, in this embodiment, after reading the data MD and the correction data PM, the data can be checked through the syndrome encoding and syndrome decoding of the syndrome calculation circuit 170. Whether there is an error bit in MD. If there is an error bit, the data reading and writing circuit 130 can instantly correct the error bit according to the error decoding signal SD in the same read cycle to output the correct data output signal RWB, and can also output the correction bit signal CS to The syndrome calculation circuit 170 causes the correction data read/write circuit 140 to update the correction data PM. In particular, between reading the data MD and outputting the correct data output signal RWB, the memory device 100 does not need to select the memory cells of the memory cell array 110 again, and can complete the above actions in the same read cycle. And can also update the correction data PM.

The circuit structure and implementation of this embodiment are further described below. FIG. 2 is a circuit block diagram of a data reading and writing circuit according to an embodiment of the invention. Please refer to FIG. 2, the data reading and writing circuit 130 includes a data reading circuit 210, a data correction circuit 220 and a data writing circuit 230. The data reading circuit 210 is coupled to the memory cell array 110 for reading the data MD from the memory cell array 110 to generate the read data AD and the corresponding read bit signal RD. The data correction circuit 220 is coupled to the data reading circuit 210 and the syndrome decoding circuit 160 of the syndrome operation circuit 170, and is used to latch the read data AD during the read cycle and correct the read data according to the error decoding signal SD The error bit of AD is used to generate the correct data output signal RWB and correction bit signal CS. The data output signal RWB is the output result of the data read and write circuit 130 reading and correcting the data MD. The data writing circuit 230 is coupled to the data correction circuit 220 and the memory cell array 110 for replacing the data output signal RWB corresponding to the error bit with the correction bit signal CS to write the correct data MD back to the memory cell array 110.

1 again, the syndrome calculation circuit 170 includes a syndrome generation circuit 150 and a syndrome decoding circuit 160. The syndrome generating circuit 150 is coupled to the data read/write circuit 130 and the correction data read/write circuit 140, and according to the read operation or the write operation, selects to receive the output signal of the data read circuit 210 or the data correction circuit 220 to generate correction data write Signal NS. More specifically, when the data read/write circuit 130 performs a read operation, the syndrome generation circuit 150 generates a correction data write signal NS according to the read bit signal RD, and when the data read/write circuit 130 performs a write operation, The syndrome generating circuit 150 generates a correction data write signal NS according to the correction bit signal CS or the data output signal RWB.

The syndrome generation circuit 150 compares the correction data write signal NS with the corresponding correction data PM (the correction data read-write circuit 140 reads the correction data PM to provide the correction read signal PS to the syndrome generation circuit 150) to generate a check Sub signal SY. The syndrome decoding circuit 160 is coupled to the syndrome generating circuit 150 to decode the syndrome signal SY to generate an error decoding signal SD. The data reading and writing circuit 130 corrects the error bits in the data MD according to the error decoding signal SD.

Next, a specific implementation of the data reading and writing circuit 130 is described. 3A is a schematic circuit diagram of a data reading circuit according to an embodiment of the present invention, and FIG. 3B is a schematic diagram of waveforms of a reading operation of a memory device according to an embodiment of the present invention. 4 is a schematic circuit diagram of a data correction circuit according to an embodiment of the present invention, FIG. 5A is a schematic circuit diagram of a data writing circuit according to an embodiment of the present invention, and FIG. 5B is a data writing circuit according to an embodiment of the present invention The circuit diagram of the control signal generating circuit of the input circuit. Please refer to FIGS. 3A to 5B in conjunction with FIGS. 1 and 2 to specifically describe the implementation details of the data reading and writing circuit 130.

In FIG. 3A, the data reading circuit 210 includes a reading switch 310, a precharge circuit 320, and an amplifier circuit 330. The input terminal of the read switch 310 receives the data MD from the memory cell array 110 and is turned on or off under the control of the read enable signal DE. The precharge circuit 320 is coupled to the input terminal of the read switch 310 and is controlled by the precharge signal PB to perform a precharge action on the input terminal of the read switch 310. The input terminal of the amplifying circuit 330 is coupled to the output terminal of the read switch 310 and is controlled by the read enable signal DE to generate the read data AD and generate the corresponding read bit signal RD.

Specifically, the sense amplifier in the memory cell array 110 outputs the data MD stored in the memory cell in the form of a differential signal, so the data MD includes the differential signal of the data signal MDiT and the inverted data signal MDiN , The data MD takes 64 bits as an example. In this manual, MDi represents one of the bits of the data MD, i is an integer from 0 to 63 (i=0, 1, 2..., 63), such as MD0, MD1 ,...MD63. Similarly, the read data AD is also a differential signal including the read data signal ADiT and the inverted read data signal ADiN. In this specification, i refers to the corresponding bit. For example, read bit signal RDi, data output signal RWBi and correction bit signal CSi means read bit signal RD, data output signal RWB and correction bit signal CS Corresponding bits in, please analogize.

In the read switch 310, the transmission gate TG1 is coupled to the bit line BL to receive the data signal MDiT, the transmission gate TG2 is coupled to the complementary bit line BLN to receive the inverted data signal MDiN, and both the transmission gate TG1 and the transmission gate TG2 are Controlled to read the enable signal DE. The input terminal of the inverter INV1 in FIG. 3A receives the read enable signal DE, and its output terminal is commonly coupled to one of the control terminals of the transmission gate TG1 and the transmission gate TG2 (for example, the N-type in the transmission gate TG1 and the transmission gate TG2) The control end of the transistor). The input terminal of the inverter INV2 is coupled to the output terminal of the inverter INV1, and its output terminal is commonly coupled to the transmission gate TG1 and the other control terminal of the transmission gate TG2 (for example, the P-type transistor in the transmission gate TG1 and the transmission gate TG2) Control end).

In the precharge circuit 320, the inverter INV3 receives the precharge signal PB. The first terminal of the P-type transistor TP1 is coupled to the power supply voltage VDD, the control terminal thereof is coupled to the output terminal of the inverter INV3, and the second terminal thereof is coupled to the bit line BL. The first end of the P-type transistor TP2 is coupled to the power supply voltage VDD, the control end is coupled to the output end of the inverter INV3, and the second end is coupled to the complementary bit line BLN. The P-type transistor TP3 is coupled between the second terminal of the P-type transistor TP1 and the second terminal of the P-type transistor TP2, and its control terminal is coupled to the output terminal of the inverter INV3.

In the amplifying circuit 330, the amplifier 332 is coupled to the read switch 310 to receive the data signal MDiT and the inverted data signal MDiN, and correspondingly output the read data signal ADiT and the inverted read data signal ADiN. The inverter INV4 receives the inverted read data signal ADiN to output the read bit signal RDi.

In this embodiment, the amplifier 332 includes P-type transistors T31 to T32 and N-type transistors T33 to T35. The P-type transistor T31 and the N-type transistor T33 are connected in series between the voltage power supply VDD and the first terminal of the N-type transistor T35. The P-type transistor T32 and the N-type transistor T34 are also connected in series with the voltage power supply VDD and N. Between the first ends of the P-type transistor T35, the control ends of the P-type transistor T31 and the N-type transistor T33 are commonly coupled to the first end of the N-type transistor T34, the P-type transistor T32 and the N-type transistor T34 The control terminals of are commonly coupled to the first terminal of the N-type transistor T33. The second terminal of the N-type transistor T35 is coupled to the ground voltage GND, and the control terminal thereof is coupled to the read enable signal DE.

In FIG. 3B, before the read operation, the precharge signal PB turns on the read switch 310 to perform a precharge operation on the bit line BL and the complementary bit line BLN. When the reading operation is about to start, the precharging signal PB turns off the reading switch 310 to end the precharging operation. At the same time, the selection signal CSL used to select the memory cells of the memory cell array 110 changes from a low logic level (Low) to a high logic level (High) to read the data MD of the selected memory cell. Then, the read enable signal DE is switched to a high logic level (High) to turn on the read switch 310 and the enable amplifier 332 to amplify the data signal MDiT and the inverted data signal MDiN to output the read data signal ADiT, and inverted read The data signal ADiN and the read bit signal RDi. The low voltage VSS in FIG. 3B uses the ground voltage GND as an example.

4, the data correction circuit 220 includes a correction switch 410, a read bit latch 420, a correction circuit 430, and an output circuit 440. The input terminal of the calibration switch 410 receives the read data ADi from the data read circuit 210, and is turned on or off under the control of the read latch signal LAR. The read bit latch 420 is coupled to the calibration switch 410 for latching the read data ADi. The correction circuit 430 is coupled to the read bit latch 420 and receives the corresponding error decoding signal SDi, for correcting the bit stored in the read bit latch 420 according to the error decoding signal SDi. The output circuit 440 is coupled to the correction circuit 430 and the read bit latch 420, and is controlled by the output enable signal OE to output the bits stored in the read bit latch 420 as the data output signal RWBi.

In the calibration switch 410 of FIG. 4, the transmission gate TG3 receives the read data signal ADiT from the data reading circuit 210, the transmission gate TG4 receives the inverted read data signal ADiN from the data reading circuit 210, and the transmission gate TG3 and the transmission gate TG4 is controlled by the read latch signal LAR. The input terminal of the inverter INV5 receives the read latch signal LAR, and its output terminal is commonly coupled to one of the control terminals of the transmission gate TG3 and the transmission gate TG4 to provide an inverted signal of the read latch signal LAR.

The read bit latch 420 includes an inverter INV6 and an inverter INV7. The input terminal of the inverter INV6 is coupled to the output terminal of the inverter INV7 and receives the read data signal ADiT through the transmission gate TG3. The input terminal of the inverter INV7 is coupled to the output terminal of the inverter INV6 and receives the inverted read data signal ADiN through the transmission gate TG4.

In the correction circuit 430, the inverter INV8 receives the error decoding signal SDi, and the inverter INV9 is coupled to the output terminal of the inverter INV6 to output the correction bit signal CSi. The first terminal of the P-type transistor TP4 is coupled to the power supply voltage VDD, the second terminal thereof is coupled to the first terminal of the P-type transistor TP5, and the control terminal thereof is coupled to the output terminal of the inverter INV8. The second terminal of the P-type transistor TP5 is coupled to the input terminal of the inverter INV6, and its control terminal receives the read data signal ADiT. The first terminal of the P-type transistor TP6 is also coupled to the power supply voltage VDD, the second terminal thereof is coupled to the first terminal of the P-type transistor TP7, and the control terminal thereof is coupled to the output terminal of the inverter INV8. The second terminal of the P-type transistor TP7 is coupled to the output terminal of the inverter INV6, and its control terminal receives the inverted read data signal ADiN.

In the output circuit 440, the input terminal of the inverter INV10 is coupled to the output enable signal OE. The first input terminal of the NAND gate NAND1 is coupled to the second terminal of the P-type transistor TP5, and the second input terminal thereof receives the output enable signal OE. The first input terminal of the NOR gate NOR1 is coupled to the second terminal of the P-type transistor TP5, and the second input terminal thereof is coupled to the output terminal of the inverter INV10. The first terminal of the P-type transistor TP8 is coupled to the power supply voltage VDD, the control terminal is coupled to the output terminal of the inverter NAND1, and the first terminal of the N-type transistor TN1 is coupled to the second terminal of the P-type transistor TP8. The corrected data output signal RWBi is provided, the control terminal of which is coupled to the output terminal of the NOR1, and the second terminal of which is coupled to the ground voltage GND. The output circuit 440 may further include a latch 442 coupled to the first terminal of the N-type transistor TN1. The circuit structure of the latch 442 is the same as that of the read bit latch 420 and is formed by two inverters INV interconnected.

Please refer to FIG. 3B again, when the read latch signal LAR switches to a high logic level, the read bit latch 420 receives the read data ADi to latch its bit value, and generates a corresponding positive latch bit signal EiT and anti-latch bit signal EiN. In FIG. 3B, during the period when the high logic level of the latch signal LAR is read, the positive latch bit signal EiT changes to a low logic level, and the anti-latched bit signal EiN changes to a high logic level. After the read latch signal LAR is switched to a low logic level, if the i-th bit of the data MD is an error bit, the error decoding signal SDi from the syndrome decoding circuit 160 will be switched to a high logic level. In the same read cycle, the correction circuit 430 reads the wrong bit value latched by the bit latch 420 according to the error decoding signal SDi, so the bit signal EiT is positively latched and the bit is negatively latched. The signal EiN is inverted to correct the error. Finally, the output circuit 440 outputs the correct data output signal RWBi according to the output enable signal OE.

5A, the data writing circuit 230 includes an inverter INV11, a writing switch 510, a writing switch 520, a writing bit latch 530, and an output circuit 540. The input terminal of the inverter INV11 receives the corresponding data output signal RWBi. The input terminal of the write switch 510 is coupled to the output terminal of the inverter INV11 and is controlled by the first write latch signal LAWm to be turned on or off. The input terminal of the write switch 520 receives the corresponding correction bit signal CSi and is controlled by the second write latch signal LDWm to be turned on or off. Here m is an integer from 0 to 7, which represents the corresponding mask bit. The write bit latch 530 is coupled to the output terminal of the write switch 510 and the output terminal of the write switch 520, and the output circuit 540 is coupled to the output terminal of the write switch 520 and the write bit latch 530. The output circuit 540 is controlled by the write enable signal WE and writes the data output signal RWBi or the correction bit signal CSi into the memory cell array 110.

Here, the data signal MDiT and the inverted data signal MDiN output by the output circuit 540 can be respectively sent back to the bit line and the complementary bit line of the memory cell array 110 to rewrite the data MDi.

In FIG. 5A, the write switch 510 is implemented in the manner of the transfer gate TG5, and the write switch 520 is implemented in the manner of the transfer gate TG6. The two control terminals of the transmission gate TG5 respectively receive the corresponding first write latch signal LAWm and the inverted signal of the first write latch signal LAWm (referred to as the inverted first write latch signal) LAWmB, the transmission gate TG6 The two control terminals of, respectively receive the second write latch signal LDWm and the inverted signal of the second write latch signal LDWm (referred to as the inverted second write latch signal) LDWmB.

The write bit latch 530 includes an inverter INV12 and an inverter INV13. The input terminal of the inverter INV12 is coupled to the output terminal of the inverter INV13, the input terminal of the inverter INV13 is coupled to the output terminal of the inverter INV12, and the input terminal of the inverter INV12 is commonly coupled to the transmission gate TG5 and the transmission Gate the output of TG6.

In the output circuit 540, the inverter INV14 is connected in series to the inverter INV15, and the inverter INV14 receives the write enable signal WE. The first input terminal of the inverter gate NAND2 is coupled to the output terminal of the inverter INV12, the second input terminal thereof is coupled to the output terminal of the inverter INV15, and the first input terminal of the inverter gate NOR2 is coupled to the output terminal of the inverter INV12 The output terminal, the second input terminal of which is coupled to the output terminal of the inverter INV14. The first terminal of the P-type transistor TP9 is coupled to the power supply voltage VDD, its control terminal is coupled to the output terminal of the inverter NAND2, and the first terminal of the N-type transistor TN2 is coupled to the second terminal of the P-type transistor TP9. A corresponding data signal MDiT is provided, the control terminal of which is coupled to the output terminal of the NOR gate NOR2, and the second terminal of which is coupled to the ground voltage GND. The first input terminal of the inverter NAND3 is coupled to the output terminal of the inverter INV13, and the second input terminal thereof is coupled to the output terminal of the inverter INV15. The first input terminal of the NOR gate NOR3 is coupled to the output terminal of the inverter INV13, and the second input terminal thereof is coupled to the output terminal of the inverter INV14. The first terminal of the P-type transistor TP10 is coupled to the power supply voltage VDD, the control terminal is coupled to the output terminal of the inverter NAND3, and the first terminal of the N-type transistor TN3 is coupled to the second terminal of the P-type transistor TP10. A corresponding inverted data signal MDiN is provided, the control terminal of which is coupled to the output terminal of the NOR3, and the second terminal of which is coupled to the ground voltage GND.

Referring to FIG. 5B, the data writing circuit 230 further includes a control signal generating circuit 550. The control signal generating circuit 550 generates a first write latch signal LAWm and a second write latch signal LAWm according to the initial write latch signal LAW and the write mask signal DM Write the latch signal LDWm. In this embodiment, the write mask signal DM is an 8-bit signal, so the write mask signal DMm is a signal corresponding to the m-th bit, and m is an integer from 0 to 7.

The control signal generating circuit 550 provides the verification write latch signal LAWPT and the inverse verification write latch signal LAWPB to the correction data read-write circuit 140, and provides corresponding first write latch signal LAWm and second write The latch signal LDWm and its inverted signal are sent to the data writing circuit 230.

The control signal generating circuit 550 includes an inverter INV16, an inverter INV17, an inverter INV18, and a signal generating circuit 610. The inverter INV16 and the inverter INV17 are connected in series and the input terminal of the inverter INV16 receives the initial write latch signal LAW, and the inverter INV17 outputs the verify write latch signal LAWPT to the correction data read-write circuit 140, wherein The inverter INV18 receives the initial write latch signal LAW to output an inverted verify write latch signal LAWPB.

It is supplemented that during the read operation, the write enable signal WE and the initial write latch signal LAW will remain at a low logic level.

In the signal generating circuit 610 of FIG. 5B, the output terminal of the inverter INV19 receives the corresponding write mask signal DMm. The first input terminal of the inverter NAND4 receives the initial write latch signal LAW, the second input terminal thereof is coupled to the output terminal of the inverter INV19, and the output terminal thereof outputs the corresponding inverted first write latch signal LAWmB. The input terminal of the inverter INV20 is coupled to the output terminal of the inverter NAND4 to output the corresponding first write latch signal LAWm. The first input terminal of the inverter NAND5 receives the initial write latch signal LAW, the second input terminal receives the corresponding write mask signal DMm, and the output terminal outputs the corresponding inverted second write latch signal LDWmB. The input terminal of the inverter INV21 is coupled to the output terminal of the inverter NAND5 to output the corresponding second write latch signal LDWm.

6A is a waveform diagram of a write operation of a memory device according to an embodiment of the present invention when no error bit is found, and FIG. 6B is a waveform diagram of a memory device according to an embodiment of the present invention when an error bit is corrected The waveform diagram of the write operation. Please refer to FIGS. 6A and 6B in conjunction with the above embodiments.

In FIG. 6A, when the memory device 100 wants to write data MD and the bit to be written does not need to be corrected, the enable time of the select signal CSL used to select the memory cell (for example, the time to maintain the high logic level) ) Is called the normal writing time. During the normal writing time, the correction bit signal CS and the writing mask signal DM will always maintain a low logic level, the writing switch 510 is turned on and the writing switch 520 is turned off, and the data writing circuit 230 selects the data output signal RWBi is written into the memory cell array 110.

In FIG. 6B, after the memory device 100 finds an error bit in the data MD and the data writing circuit 230 wants to write back the correct data, the enabling time of the selection signal CSL is called the correction writing time. In the correction writing time, after the read latch signal LAR is switched to a low logic level, the logic level of the error decoding signal SDi corresponding to the error bit position is changed to a high level. Correspondingly, the output of the data correction circuit 220 The correction bit signal CSi is also switched to a high logic level. It is supplemented that the syndrome generating circuit 150 also correspondingly outputs the correction data write signal NS to the correction data read-write circuit 140 to update the correction data PM.

Then the data write circuit 230 performs a write operation, the corresponding first write latch signal LAWm will turn off the write switch 510 and the corresponding second write latch signal LDWm will turn on the write switch 520 to correct the bit signal CSi replaces the data output signal RWBi and is input to the output circuit 540 to write the correct bit value in the enable time of the write enable signal WE.

In short, when the bit to be written is originally correct, the data writing circuit 230 writes the data output signal RWBi into the memory cell array 110. When the bit to be written is the position of the wrong bit, the data writing circuit 230 The input circuit 230 writes the correction bit signal CSi into the memory cell array 110.

In particular, in this embodiment, the enabling time of the selection signal CSL can be changed, and the correction writing time will be longer than the normal writing time. When the memory device 100 finds an error bit, the data read/write circuit 130 and the correction data read/write circuit 140 can write back the correct data during the same period of correction by extending the enable time of the selection signal CSL Memory cell array 110 and update calibration data PM. In other words, the selection signal CSL only needs to be enabled once to complete the check, correction and update actions.

Next, the circuit structure details of the syndrome generating circuit 150 will be described. FIG. 7A is a schematic circuit diagram of a syndrome generating circuit according to an embodiment of the present invention, FIG. 7B is a schematic circuit diagram of an internal arithmetic circuit of the syndrome generating circuit according to an embodiment of the present invention, and FIG. 7C is a schematic diagram according to the present invention A schematic circuit diagram of the syndrome control signal generating circuit of the syndrome generating circuit of an embodiment.

7A, the syndrome generation circuit 150 includes an internal arithmetic circuit 710 and a plurality of mutually exclusive OR gates XOR2, wherein the internal arithmetic circuit 710 includes a plurality of transmission gates TG (transmission gates TG7~TG9 in FIG. 7B) and Multiple mutually exclusive or gate XOR1.

In FIG. 7B, the internal arithmetic circuit 710 controls a plurality of transmission gates TG to selectively provide a data output signal RWB, a correction bit signal CS, or a read bit signal RD to a plurality of mutually exclusive or gates XOR1 to output a correction data write signal. NS. Specifically, the internal arithmetic circuit 710 has a plurality of input circuits 720. In addition to receiving the corresponding data output signal RWBi, each input circuit 720 can also receive the corresponding read bit signal RDi from the data reading circuit 210 and the corresponding correction bit signal CSi from the data correction circuit 220. The internal arithmetic circuit 710 controls the multiple transmission gates TG7 to TG9 in the input circuit 720 to select and input one of the read bit signal RD, the data output signal RWB and the correction bit signal CS to the corresponding mutual exclusion or gate XOR1 .

In detail, the transmission gate TG7 receives the corresponding read bit signal RDi and is controlled by the write data control signal WED and the inverted signal WEDB of the write data control signal WED, and the transmission gate TG8 receives the data output signal RWBi and is controlled In the write data selection signal WEm and the inverted signal WEmB of the write data selection signal WEm, the transmission gate TG9 receives the correction bit signal CSi and is controlled by the write mask selection signal DWm and the inverse of the write mask selection signal DWm Phase signal DWmB.

When the memory device 100 performs a read operation, the input circuit 720 selects to receive the read bit signal RDi, turns on the transmission gate TG7 and closes the transmission gate TG8 and the transmission gate TG9; when the memory device 100 performs a write operation, the input circuit 720 closes the transmission gate TG7, and turns on the transmission gate TG8 or the transmission gate TG9 according to the write mask signal DM to select to receive the data output signal RWBi or the correction bit signal CSi.

After multiple levels of mutual exclusion or gate XOR1 operations, the internal arithmetic circuit 710 finally outputs the correction data write signal NSj. Because the parity bit in this embodiment is 7 bits, j is an integer from 0 to 6, and the correction The data write signal NSj represents the signal corresponding to the jth bit in the corrected data write signal NS.

In FIG. 7A, a plurality of mutually exclusive OR gates XOR2 receive the corresponding correction data write signal NSj from the internal arithmetic circuit 710 and the corresponding correction read signal PSj from the correction data read-write circuit 140. The syndrome generating circuit 150 compares the corrected read signal PS with the corrected data write signal NS to output a syndrome signal SY. The syndrome decoding circuit 160 receives the syndrome signal SY and the decoding control signal SDE and performs a decoding operation on the syndrome signal SY to output an error decoding signal SD to the data correction circuit 220 of the data reading and writing circuit 130.

The syndrome generating circuit 150 also includes a syndrome control signal generating circuit 730 for generating the control signal of the transmission gate TG. The circuit structure of the syndrome control signal generating circuit 730 in FIG. 7C is similar to the control signal generating circuit 550 in FIG. 5B, so the details of the operation of the syndrome control signal generating circuit 730 will not be repeated here.

Next, the specific circuit structure of the correction data reading and writing circuit 140 is described. 8 is a schematic circuit diagram of a correction data reading and writing circuit according to an embodiment of the present invention, and FIG. 9 is a circuit schematic diagram of a correction data writing circuit according to an embodiment of the present invention.

Referring to FIG. 8, the correction data reading and writing circuit 140 includes a correction data reading circuit 810 and a correction data writing circuit 820. The calibration data reading circuit 810 is coupled to the calibration data memory cell array 120 and the syndrome operation circuit 170 for reading the calibration data PM from the calibration data memory cell array 120 to output the calibration read signal PS to the syndrome operation circuit 170 The syndrome generating circuit 150. The correction data writing circuit 820 is coupled to the correction data memory cell array 120 and the syndrome generation circuit 150 of the syndrome operation circuit 170, and is used for writing the corrected correction data PM into the correction data memory cell array 120.

When the memory device 100 performs a reading operation, the calibration data reading circuit 810 can read the calibration data PM from the calibration data memory cell array 120 to output a calibration read signal PS to the syndrome generating circuit 150. The syndrome generating circuit 150 checks whether the read bit signal RD has an error bit according to the corrected read signal PS. If there is an error bit, the corresponding error decoding signal SDi will change the logic level. In this embodiment, if the i-th bit of the data MD is wrong, the error decoding signal SDi will change to a high logic level, as shown in FIG. 3B.

For the circuit details of the calibration data reading circuit 810, refer to FIG. 3A. Those skilled in the art can obtain sufficient suggestions, teachings, and implementations from the data reading circuit 210, which will not be repeated here.

9 shows the circuit details of the correction data writing circuit 820, and its circuit structure is similar to the data writing circuit 230 of FIG. 5A. Those skilled in the art can obtain sufficient suggestions, teachings and implementations from the data writing circuit 230 , I will not repeat them here.

Please refer to FIG. 6B again. When the syndrome generating circuit 150 detects that the read bit signal RD has an error bit, the data writing circuit 230 performs error correction on the read bit signal RD, and the syndrome generating circuit 150 will A new correction data write signal NS is output according to the correction bit signal CS for recording the error bit position. The calibration data writing circuit 820 writes a new calibration data writing signal NS to the calibration data memory cell array 120 to update the calibration data PM. The correction data PM in FIG. 9 includes a differential signal composed of a correction data signal PMjT and an inverted correction data signal PMjN, j is an integer from 0 to 6, representing the corresponding parity bit.

In summary, the memory device of the present invention can read data from the memory cell array and check it in one read cycle. When an error bit in the data is found, the memory device of the present invention can be Correct the error instantly and output the correct data in one reading cycle. In addition, the memory device of the present invention can also simultaneously output correction bit signals to the data writing circuit and the syndrome generating circuit. By extending the enable period of the selection signal, the data writing circuit can write the corrected data back to the memory cell array and the syndrome generating circuit can provide a new correction data writing signal to the correction data writing circuit to update the correction data . In this way, the selection signal only needs to provide an enabling period for the memory cell to be written once to complete the data correction and update, achieving the effect of real-time checking and correcting errors.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

100: Memory device 110: Memory cell array 120: Calibration data memory cell array 130: data read and write circuit 140: Calibration data read and write circuit 150: Syndrome generation circuit 160: Syndrome Decoding Circuit 170: syndrome calculation circuit 210: Data reading circuit 220: data correction circuit 230: Data writing circuit 310: Read switch 320: pre-charging circuit 330: amplifier circuit 332: Amplifier 410: Calibration switch 420: read bit latch 430: correction circuit 440, 540: output circuit 442: Latch 510, 520: write switch 530: Write bit latch 550: Control signal generating circuit 610: signal generating circuit 710: Syndrome Operation Circuit 720: input circuit 730: Syndrome control signal generating circuit 810: Calibration data reading circuit 820: Calibration data writing circuit AD, ADi: read data ADiT: read data signal ADiN: Inverted read data signal BL: bit line BLN: complementary bit line CS: Correction bit signal DE: Read enable signal DM: write mask signal DWm: Write mask selection signal DWmB: Inverted write mask selection signal EiT: Positive latch bit signal EiN: Anti-latching bit signal GND: Ground voltage LAR: read latch signal LAWIN: Initial write latch signal LAWm: first write latch signal LAWmB: inverted first write latch signal LDWm: The second write latch signal LDWmB: Inverted second write latch signal LAWPT: Verify write latch signal LAWPB: Inverted verification write latch signal MD: Information MDiT: data signal MDiN: Inverted data signal NAND1～NAND5: reverse and gate NOR1～NOR3: reverse or gate NS: Correction data write signal INV, INV1～INV21: inverter OE: output enable signal PB: Precharge signal PM: Calibration data PS: Correct reading signal RWB, RWBi: data output signal RD, RDi: read bit signal SY: syndrome signal SD, SDi: Error decoded signal SDE decode control signal TG, TG1～TG9: Transmission gate T31, T32, TP1～TP10: P-type transistor T33, T34, T35, TN1~TN3: N-type transistor VDD: voltage supply VSS: Low voltage WE: Write enable signal WED: write data control signal WEDB: Inverted write data control signal WEm: write data selection signal WEmB: Inverted write data selection signal

FIG. 1 is a block diagram of a memory device according to an embodiment of the invention. FIG. 2 is a circuit block diagram of a data reading and writing circuit according to an embodiment of the invention. 3A is a schematic circuit diagram of a data reading circuit according to an embodiment of the invention. 3B is a schematic diagram of waveforms of a read operation of the memory device according to an embodiment of the invention. FIG. 4 is a circuit diagram of a data correction circuit according to an embodiment of the invention. 5A is a circuit diagram of a data writing circuit according to an embodiment of the invention. 5B is a schematic circuit diagram of a control signal generating circuit of a data writing circuit according to an embodiment of the invention. 6A is a schematic diagram of a write operation of a memory device according to an embodiment of the present invention when no error bit is found. 6B is a schematic diagram of waveforms of a write operation in the case of correcting error bits in the memory device according to an embodiment of the present invention. FIG. 7A is a schematic circuit diagram of a syndrome generating circuit according to an embodiment of the invention. FIG. 7B is a circuit diagram of the internal arithmetic circuit of the syndrome generating circuit according to an embodiment of the present invention. 7C is a schematic circuit diagram of the syndrome control signal generating circuit of the syndrome generating circuit according to an embodiment of the present invention. FIG. 8 is a circuit diagram of a correction data reading and writing circuit according to an embodiment of the present invention. FIG. 9 is a circuit diagram of a correction data writing circuit according to an embodiment of the invention.

100: Memory device

110: Memory cell array

120: Calibration data memory cell array

130: data read and write circuit

140: Calibration data read and write circuit

150: Syndrome generation circuit

160: Syndrome Decoding Circuit

170: syndrome calculation circuit

CS: Correction bit signal

MD: Information

NS: Correction data write signal

PM: Calibration data

PS: Correct reading signal

RD: read bit signal

RWB: Data output signal

SY: syndrome signal

SD: Error decoded signal

Claims (17)

A memory device includes: A data read and write circuit, coupled to the memory cell array, for accessing data in the memory cell array; The correction data read-write circuit is coupled to the correction data memory cell array for accessing the correction data of the correction data memory cell array; A syndrome operation circuit for generating an error decoding signal based on the data received from the data reading and writing circuit and the correction data received from the correction data reading and writing circuit, Wherein, in the same read cycle when the data is read, the data read-write circuit corrects the error bit in the data according to the error decoding signal and outputs the correct data and correction bit signal, The data read-write circuit writes the corrected data back to the memory cell array, and the syndrome operation circuit also outputs a correction data write signal to the correction data read based on the correction bit signal The writing circuit updates the correction data in the correction data memory cell array. The memory device described in item 1 of the scope of patent application, wherein when the corrected data is to be written into the memory cell array, the enable time of the selection signal used to select the memory cell is called correction writing When the data without the error bit is to be written into the memory cell array, the enable time of the selection signal is called the normal writing time, and the correction writing time Greater than the normal writing time. The memory device described in item 1 of the scope of patent application, wherein the data reading and writing circuit includes: A data reading circuit, coupled to the memory cell array, for reading the data from the memory cell array to generate read data and corresponding read bit signals; A data correction circuit, coupled to the data reading circuit and the syndrome operation circuit, is used for latching the read data during the read period and correcting the read according to the error decoding signal Error bits of data to generate a data output signal and the correction bit signal, wherein the data output signal is the output result of the data read and write circuit after reading and correcting the data; and A data writing circuit, coupled to the data correction circuit and the memory cell array, for replacing the data output signal corresponding to the error bit with the correction bit signal to write back the correct data The memory cell array. The memory device described in item 3 of the scope of patent application, wherein the data reading circuit includes: A read switch, the input terminal of which receives the data from the memory cell array, and is turned on or off under the control of a read enable signal; A pre-charging circuit, coupled to the input terminal of the read switch, is controlled by a pre-charge signal to perform a pre-charging action on the input terminal of the read switch, An amplifying circuit, the input terminal of which is coupled to the output terminal of the read switch, is controlled by the read enable signal to generate the read data and generate the corresponding read bit signal. The memory device described in item 4 of the scope of patent application, wherein: The read switch includes: The first transmission gate and the second transmission gate, wherein the first transmission gate is coupled to a bit line to receive a data signal, the second transmission gate is coupled to a complementary bit line to receive an inverted data signal, and the first transmission gate is Both a transmission gate and the second transmission gate are controlled by the read enable signal, wherein the data is a differential signal including the data signal and the inverted data signal; and A first inverter and a second inverter, wherein the input terminal of the first inverter receives the read enable signal, and the output terminal is commonly coupled to the first transmission gate and the second transmission One of the control terminals of the gate, the input terminal of the second inverter is coupled to the output terminal of the first inverter, and the output terminal is commonly coupled to the first transmission gate and the second transmission gate. The other control end The pre-charging path includes: A third inverter, which receives the precharge signal; A first P-type transistor, the first terminal of which is coupled to the power supply voltage, the control terminal of which is coupled to the output terminal of the third inverter, and the second terminal of which is coupled to the bit line; A second P-type transistor, the first terminal of which is coupled to the power supply voltage, the control terminal of which is coupled to the output terminal of the third inverter, and the second terminal of which is coupled to the complementary bit line; and The third P-type transistor is coupled between the second terminal of the first P-type transistor and the second terminal of the second P-type transistor, and its control terminal is coupled to the third inverter The output terminal; and The amplifying circuit includes: Amplifier, coupled to the read switch to receive the data signal and the inverted data signal, and correspondingly output the read data signal and the inverted read data signal, wherein the read data includes the read Obtaining a difference signal between the data signal and the inverted read data signal; and The fourth inverter receives the inverted read data signal to output the read bit signal. The memory device according to the third item of the scope of patent application, wherein the data correction circuit includes: A calibration switch, the input terminal of which receives the read data from the data read circuit, and is turned on or off under the control of a read latch signal; A read bit latch, coupled to the correction switch, for latching the read data; A correction circuit, coupled to the read bit latch and receives the error decoding signal, for correcting the bits stored in the read bit latch according to the error decoding signal; and A first output circuit, coupled to the correction circuit and the read bit latch, is controlled by an output enable signal to output the bits stored in the read bit latch as the data output signal. The memory device described in item 6 of the scope of patent application, wherein: The calibration switch includes: The third transmission gate and the fourth transmission gate, wherein the third transmission gate receives a read data signal from the data reading circuit, and the fourth transmission gate receives an inverted read data signal from the data reading circuit , And the third transmission gate and the fourth transmission gate are both controlled by the read latch signal, wherein the read data includes the read data signal and the inverted read data signal Differential signal; and A fifth inverter, the input terminal of which receives the read latch signal, and the output terminal of which is commonly coupled to one of the control terminals of the third transmission gate and the fourth transmission gate; and The read bit latch includes: A sixth inverter and a seventh inverter, wherein the input terminal of the sixth inverter is coupled to the output terminal of the seventh inverter and receives the read data signal through the third transmission gate , And the input terminal of the seventh inverter is coupled to the output terminal of the sixth inverter and receives the inverted read data signal through the fourth transmission gate. The memory device according to item 7 of the scope of patent application, wherein the correction circuit includes: An eighth inverter, which receives the error decoding signal; A ninth inverter, coupled to the output terminal of the sixth inverter to output the correction bit signal; A fourth P-type transistor and a fifth P-type transistor, wherein the first end of the fourth P-type transistor is coupled to the power supply voltage, and the second end is coupled to the first end of the fifth P-type transistor , Its control terminal is coupled to the output terminal of the eighth inverter, and the second terminal of the fifth P-type transistor is coupled to the input terminal of the sixth inverter, and its control terminal receives the read Get data signals; and The sixth P-type transistor and the seventh P-type transistor, wherein the first end of the sixth P-type transistor is coupled to the power supply voltage, and the second end thereof is coupled to the second end of the seventh P-type transistor One end, its control end is coupled to the output end of the eighth inverter, and the second end of the seventh P-type transistor is coupled to the output end of the sixth inverter, and its control end receives the output end of the sixth inverter. The inversion reads the data signal. The memory device according to item 8 of the scope of patent application, wherein the first output circuit includes: A tenth inverter, the input terminal of which is coupled to the output enable signal; The first inverter, the first input terminal of which is coupled to the second terminal of the fifth P-type transistor, and the second input terminal of which receives the output enable signal; A first inverter, whose first input terminal is coupled to the second terminal of the fifth P-type transistor, and its second input terminal is coupled to the output terminal of the tenth inverter; An eighth P-type transistor, the first terminal of which is coupled to the power supply voltage, and the control terminal of which is coupled to the output terminal of the first inverter; A first N-type transistor, the first terminal of which is coupled to the second terminal of the eighth P-type transistor and provides the corrected data output signal, and its control terminal is coupled to the output of the first inverter The second terminal is coupled to a ground voltage. The memory device described in item 3 of the scope of patent application, wherein the data writing circuit includes: An eleventh inverter, the input terminal of which receives the corresponding data output signal; A first write switch, the input terminal of which is coupled to the output terminal of the eleventh inverter, and is controlled by the first write latch signal to be turned on or off; A second write switch, the input terminal of which receives the corresponding correction bit signal and is controlled by the second write latch signal to be turned on or off; Write bit latch, coupled to the output terminal of the first write switch and the output terminal of the second write switch; A second output circuit, coupled to the output terminal of the second write switch and the write bit latch, is controlled by a write enable signal and outputs the data signal or the correction bit signal Write the memory cell array. The memory device described in item 10 of the scope of patent application, wherein: The first write switch is a fifth transmission gate, and the second write switch is a sixth transmission gate; and The write bit latch includes: The twelfth inverter and the thirteenth inverter, wherein the input end of the twelfth inverter is coupled to the output end of the thirteenth inverter, and the input of the thirteenth inverter The terminal is coupled to the output terminal of the twelfth inverter, wherein the input terminal of the twelfth inverter is commonly coupled to the output terminals of the fifth transmission gate and the sixth transmission gate. The memory device according to claim 11, wherein the second output circuit includes: A fourteenth inverter and a fifteenth inverter, the fourteenth inverter is serially connected to the fifteenth inverter, and the fourteenth inverter receives the write enable signal ； A second inverter, the first input terminal of which is coupled to the output terminal of the twelfth inverter, and the second input terminal of which is coupled to the output terminal of the fifteenth inverter; A second inverter, whose first input terminal is coupled to the output terminal of the twelfth inverter, and its second input terminal is coupled to the output terminal of the fourteenth inverter; A ninth P-type transistor, the first terminal of which is coupled to the power supply voltage, and the control terminal of which is coupled to the output terminal of the second inverter; The first end of the second N-type transistor is coupled to the second end of the ninth P-type transistor and provides a corresponding data signal. The control end is coupled to the output end of the second inverter. The two ends are coupled to the ground voltage; The third inverter, the first input terminal of which is coupled to the output terminal of the thirteenth inverter, and the second input terminal of which is coupled to the output terminal of the fifteenth inverter; A third inverter, whose first input terminal is coupled to the output terminal of the thirteenth inverter, and its second input terminal is coupled to the output terminal of the fourteenth inverter; A tenth P-type transistor, the first terminal of which is coupled to the power supply voltage, and the control terminal of which is coupled to the output terminal of the third inverter; and A third N-type transistor, the first terminal of which is coupled to the second terminal of the tenth P-type transistor and provides a corresponding inverted data signal, and its control terminal is coupled to the output terminal of the third inverter, The second terminal is coupled to the ground voltage, wherein the data is a differential signal including the data signal and the inverted data signal. The memory device according to the 12th patent application, wherein the data writing circuit further includes a control signal generating circuit, and the control signal generating circuit generates the data according to the initial write latch signal and the write mask signal The first write latch signal and the second write latch signal include: The sixteenth inverter, the seventeenth inverter and the eighteenth inverter, wherein the sixteenth inverter and the seventeenth inverter are connected in series and the sixteenth inverter The input terminal of the inverter receives the initial write latch signal, the seventeenth inverter outputs a verify write latch signal to the correction data read-write circuit, and the eighteenth inverter receives the An initial write latch signal to output an inverted verification write latch signal to the correction data read-write circuit; and The signal generating circuit includes: A nineteenth inverter, the output terminal of which receives the corresponding write mask signal; The fourth inverter, its first input terminal receives the initial write latch signal, its second input terminal is coupled to the output terminal of the nineteenth inverter, and its output terminal outputs the corresponding first Write the inverted signal of the latch signal; A twentieth inverter, the input terminal of which is coupled to the output terminal of the fourth inverter to output the corresponding first write latch signal; The fifth inverter, its first input terminal receives the initial write latch signal, its second input terminal receives the corresponding write mask signal, and its output terminal outputs the corresponding second write lock The inverted signal of the stored signal; and The input terminal of the twenty-first inverter is coupled to the output terminal of the fifth inverter to output the corresponding second write latch signal. The memory device described in item 3 of the scope of patent application, wherein the syndrome operation circuit includes: The syndrome generating circuit is coupled to the data reading and writing circuit and the correction data reading and writing circuit, and according to the reading operation or the writing operation, it selects and receives the output signal of the data reading circuit or the data correction circuit to Generating the correction data write signal, and compare the correction data write signal with the corresponding correction data to generate a syndrome signal; A syndrome decoding circuit, coupled to the syndrome generating circuit, decodes the syndrome signal to generate the error decoded signal. The memory device according to claim 14, wherein, when the data read-write circuit performs the read operation, the syndrome generation circuit generates the correction according to the read bit signal Data write signal, and when the data read/write circuit performs the write operation, the syndrome generation circuit generates the correction data write signal according to the correction bit signal or the data output signal. The memory device according to item 14 of the scope of patent application, wherein the correction data read-write circuit reads the correction data to output a correction read signal to the syndrome generation circuit, and the syndrome The generating circuit includes: The internal arithmetic circuit includes a plurality of transmission gates and a plurality of first mutually exclusive or gates, and the data output signal, the correction bit signal or the read bit data are selectively provided by controlling the plurality of transmission gates To the plurality of first mutually exclusive OR gates to output the correction data write signal; and A plurality of second mutually exclusive OR gates receive the correction data write signal from the internal arithmetic circuit and receive the corresponding correction read signal from the correction data read-write circuit to output the syndrome signal. The memory device according to item 1 of the scope of patent application, wherein the correction data read-write circuit includes: A calibration data reading circuit, coupled to the calibration data memory cell array and the syndrome operation circuit, is used to read the calibration data from the calibration data memory cell array to output a calibration read signal to the calibration Empirical calculation circuit; A correction data writing circuit is coupled to the correction data memory cell array and the syndrome operation circuit, and is used for writing the corrected correction data into the correction data memory cell array.

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