CN114664338A - Dual port memory, read data output control method, read data output control device and read data output control medium - Google Patents

Abstract

A dual port memory and a read data output control method, device and medium thereof, the method comprises: tracking successive read operations as they are performed on the memory cells based on an external clock signal; when each read operation in the continuous read operations is finished, corresponding latch control signals are respectively generated, so that the output data latch latches and outputs the data read by executing the read operation when receiving the latch control signals. The scheme can improve the performance of the dual-port static random access memory.

Description

Dual port memory, read data output control method, read data output control device and read data output control medium

Technical Field

The present invention relates to the field of semiconductor integrated circuits, and in particular, to a dual port memory, and a read data output control method, apparatus, and medium thereof.

Background

A single-port static random access memory (SP-SRAM) is a static random access memory having only one access port. With only one port, a single port sram can only provide one memory access operation at a time.

Dual port static random access memory (DP-SRAM) provides more bandwidth than single port static random access memory (SP-SRAM), since dual port static random access memory (DP-SRAM) dual port memories typically include two ports operated with an array of memory cells that can be accessed simultaneously from both ports. With more bandwidth, the demand for DP-SRAM is increasing relative to the demand for SP-SRAM.

However, the performance of the conventional dual-port sram still needs to be improved.

Disclosure of Invention

The invention solves the technical problem of improving the performance of the dual-port static random access memory.

In order to solve the above problems, the present invention provides a read data output control method for a dual port memory, the dual port memory including a memory array, a bit line detection unit, and an output data latch; the memory array comprises a plurality of rows and a plurality of columns of memory cells; the memory cells in the same row and the same read word line, and the memory cells in the same column and the same read bit line; the input end of the bit line detection unit is coupled to the read bit line of the corresponding column through the corresponding read column multiplexer, the output end of the bit line detection unit is coupled to the input end of the output data latch, and the read data output control method includes:

tracking successive read operations as they are performed on the memory cells based on an external clock signal;

when each read operation in the continuous read operations is finished, corresponding latch control signals are respectively generated, so that the output data latch latches and outputs the data read by executing the read operation when receiving the latch control signals.

Optionally, the tracking the consecutive read operations comprises:

and monitoring a read word line and a read bit line of a memory cell corresponding to the read operation so as to track the read operation.

Optionally, the determining that the read operation is finished comprises:

the read operation is determined to be ended when the voltage signal on the read word line of the memory cell transitions from a high level to a low level and the read bit line is precharged to a high level.

Optionally, the memory cells read by the consecutive read operations are the same memory cell or different memory cells.

Correspondingly, the embodiment of the invention also provides a read data output control device of the dual-port memory, wherein the dual-port memory comprises a memory array, a bit line detection unit and an output data latch; the memory array comprises a plurality of rows and a plurality of columns of memory cells; the memory cells in the same row and the same read word line, and the memory cells in the same column and the same read bit line; the input of the bit line detection unit is coupled to the read bit lines of the corresponding column through the corresponding read column multiplexer, respectively, and the output of the bit line detection unit is coupled to the input of the output data latch, the apparatus comprising:

a tracking unit adapted to track successive read operations when the successive read operations are performed on the memory cell based on an external clock signal;

and the latch control unit is suitable for respectively generating corresponding latch control signals when each read operation in the continuous read operations is finished, so that the output data latch latches and outputs the data read by executing the read operation when receiving the latch control signals.

Optionally, the tracking unit is adapted to monitor a read word line and a read bit line of a memory cell corresponding to the read operation, so as to track the consecutive read operation.

Optionally, the tracking cell is adapted to determine that the read operation is ended when a voltage signal on a read word line of the memory cell transitions from a high level to a low level and a read bit line is precharged to a high level.

Optionally, the memory cells read by the consecutive read operations are the same memory cell or different memory cells.

Correspondingly, the embodiment of the invention also provides a computer-readable storage medium, and the storage medium stores one or more computer instructions, and the one or more computer instructions are used for implementing the read data output control method.

Accordingly, an embodiment of the present invention further provides a dual port memory, which is characterized by including any one of the read data output control apparatuses described above.

Compared with the prior art, the technical scheme of the invention has the following advantages:

in the read data output control method provided by the embodiment of the present invention, when a continuous read operation is performed on the memory cell based on an external clock signal, the continuous read operation is tracked; when each read operation in the continuous read operations is finished, corresponding latch control signals are respectively generated, so that the data read by the read operation is latched and output by the output data latch when the latch control signals are received, and the situation that the output node of the output data latch is changed from a low level to a high level and then back to the low level in the continuous read data execution period can be avoided when the read operation is finished, so that the dynamic power loss can be saved, and the performance of the dual-port memory can be improved.

Drawings

FIG. 1 is a schematic diagram of a memory cell in a dual port SRAM;

FIG. 2 is a pulse timing diagram of one of the relevant signals in the dual port SRAM of FIG. 1;

FIG. 3 is a schematic diagram of a pseudo-dual port memory according to an embodiment of the invention;

fig. 4 is a flow chart illustrating a read data output control method of a dual port memory according to an embodiment of the present invention;

FIG. 5 shows a pulse timing diagram of related signals of a dual port memory in an embodiment of the invention;

fig. 6 is a schematic structural diagram of a read data output control apparatus of a dual port memory according to an embodiment of the present invention.

Detailed Description

As is known in the art, a dual port sram has two ports, a memory cell in a memory array can be read by two different ports at the same time, and two different memory cells in a row in the memory array can be written with different data at the same time.

Fig. 1 shows a structure of a memory cell in a dual port static random access memory. Referring to fig. 1, a memory cell includes: includes a first inverter (not shown) and a second inverter (not shown), a first access NMOS transistor NM3 and a second access NMOS transistor NM4, a third access NMOS transistor NM4 and a fourth access NMOS transistor NM 5.

The first inverter comprises a first PMOS transistor PM1 and a first NMOS transistor NM 1; the second inverter includes a second PMOS transistor PM2 and a second NMOS transistor NM 2.

The gate end of the first PMOS transistor PM1 is coupled to the gate end of the first NMOS transistor NM1 and the second latch node QB of the latch, the source end of the first PMOS transistor PM1 is coupled to the power supply voltage VDD, the drain end of the first PMOS transistor PM1 is coupled to the drain end of the first NMOS transistor NM1 and serves as the first latch node Q of the latch, and the source end of the first NMOS transistor NM1 is coupled to the ground voltage VSS.

A gate terminal of the second PMOS transistor PM2 is coupled to a gate terminal of the second NMOS transistor NM2 and a first latch node Q of the latch, a source terminal of the second PMOS transistor PM2 is coupled to a power supply voltage VDD, a drain terminal of the second PMOS transistor PM1 is coupled to a drain terminal of the second NMOS transistor NM1 and serves as a second latch node QB of the latch, and a source terminal of the second NMOS transistor NM2 is coupled to a ground voltage VSS;

the gate terminal of the first access NMOS transistor NM3 and the gate terminal of the second access NMOS transistor NM4 are both coupled to a write word line WWL, the source terminal of the first access NMOS transistor NM3 is coupled to the first latch node Q, and the drain terminal of the first access NMOS transistor NM3 is coupled to a corresponding first write bit line WBL; the source terminal of the second access NMOS transistor NM4 is coupled to the second latch node QB, and the drain terminal of the second access NMOS transistor NM4 is coupled to the corresponding second write bit line WBLB.

A gate terminal of the third access NMOS transistor NM4 is coupled to the read word line RWL, a source terminal of the third access NMOS transistor NM4 is coupled to the read bit line RBL, and a drain terminal of the third access NMOS transistor NM4 is coupled to a source terminal of the fourth access NMOS transistor NM 5; a gate terminal of the fourth access NMOS transistor NM5 is coupled to the second latch node QB of the latch, and a source terminal of the fourth access NMOS transistor NM5 is coupled to a ground voltage VSS.

In reading data in memory cells in the dual port static random access memory, a bit line precharge circuit (not shown) first precharges a read bit line RBL of a column in which a target memory cell is located to a power supply voltage VDD.

When the storage data in the target memory cell is 0, the first latch node Q is low and the second latch node QB is high, and the fourth access NMOS transistor NM5 is turned on. When the read word line RWL of the target memory cell receives a high level signal, the third access NMOS transistor NM4 is turned on, so that the read bit line RBL is pulled down from the power supply voltage VDD to the ground voltage VSS through the third access NMOS transistor NM4 and the fourth access NMOS transistor NM 5.

On the contrary, when the storage data in the target memory cell is 1, the first latch node Q is at a high level and the second latch node QB is at a low level, and the fourth access NMOS transistor NM5 is turned off. When the read word line RWL of the target memory cell receives a high level signal, the third access NMOS transistor NM4 is turned on, and the second latch node QB is at a high level, thereby maintaining the read bit line RBL at the power supply voltage VDD.

The bit line detection unit detects the voltage change on the read bit line RBL of the target memory cell, so that the data in the target memory cell is read out and sent to the output data latch for latching and outputting.

Referring to fig. 2, the latch clock signal of the output data latch is obtained by delaying the external clock signal CLK. In other words, the latch clock signal of the output data latch is controlled by the external clock signal CLK. When the latch clock signal is at a high level, the output of the output node Q of the output data latch changes with the change of the input node Q of the output data latch, that is, the output data latch is transparent when the latch clock signal LCLK is at a high level.

With continued reference to fig. 2, consecutive read operations are performed on the memory cells in the memory array, and the read data corresponding to the consecutive read operations are all 0. When the previous read operation is performed, the bit line sensing unit sends the read data 0 to the output data latch. When the high level of the output data latch clock signal arrives, the output data latch latches and outputs the data 0 acquired from the bit line sensing unit as shown at a time point t1, that is, the output node Q of the output data latch outputs the low level.

When the previous read operation is finished, as described above, the bit line precharge circuit precharges the read bit line RBL of the column in which the target memory cell is located to the power supply voltage VDD, and if a high level of the latch clock signal arrives at this time, the power supply voltage VDD on the read bit line RBL is transmitted to the output data latch Q through the bit line detection unit, so that the output of the output node Q of the output data latch changes from a low level to the power supply voltage VDD at time t 2.

When the next read data operation is performed, as indicated by a dotted line box 20 in fig. 2, the voltage of the target memory cell RBL is pulled down from the power supply voltage VDD to the low level VSS, and at a time point t3, the voltage is transmitted to the output node Q of the output data latch through the bit line sensing unit, so that the output node Q of the output data latch is changed back to the low level VSS from the power supply voltage VDD.

It can be seen that during two read operations of data 0, the latch clock signal controlled by the external clock signal CLK causes the output node Q of the output data latch to briefly change from low to high and back to low during two consecutive read 0 operations, resulting in a so-called glitch (glitch).

The presence of this fault consumes a significant amount of dynamic power, since during two read data 0 operations the output of the output node Q of the data latch briefly goes from low to the supply voltage and back from the supply voltage to low, which consumes a significant amount of dynamic power.

The invention provides a read data output control method of a dual-port memory, when continuous read operation is executed on a memory unit based on an external clock signal, the continuous read operation is tracked; when each reading operation in the continuous reading operation is finished, corresponding latch control signals are respectively generated, so that the data read by the reading operation is latched and output by the output data latch when the latch control signals are received, and the output node of the output data latch is prevented from changing from a low level to a high level and then changing back to the low level during the continuous reading data operation, so that the dynamic power can be saved, and the performance of the dual-port memory can be improved.

For ease of understanding, the structure of a dual port memory in the embodiment of the present invention will be described first.

Fig. 3 is a schematic diagram of a pseudo-dual port memory according to an embodiment of the invention. Referring to fig. 3, a pseudo-dual port memory in an embodiment of the invention may include a memory array 310, a timing control circuit 320, a word line decoding and driving circuit 330, a bit line decoding circuit 340, and an input-output control circuit 350. The memory array 310 is coupled to a word line decoding and driving circuit 330 and the input/output control circuit 350, respectively, the word line decoding and driving circuit 330 and the bit line decoding circuit 340 are further coupled to the timing control circuit 320, respectively, and the bit line decoding circuit 340 is further coupled to the input/output control circuit 350.

With continued reference to FIG. 3, the memory array includes M N memory cells, write word lines WWL 0-WWLm, read word lines RWL 0-RWLM, pairs of write bit lines (WBL0/WBLB0) - (WBLm/WBLBm), and read bit lines RWL 0-RWLM, arranged in one-to-one correspondence with rows of memory cells. Wherein M, N are all positive integers greater than 1, M is (M-1) and is a positive integer, and N is (N-1) and is a positive integer.

In the memory array 319, memory cells in the same row are coupled to the same write word line WWLi (i is a positive integer greater than or equal to 0 and less than or equal to m) and read bit line RWLi, and memory cells in the same column are coupled to the same pair of write bit lines RWj (j is a positive integer greater than or equal to 0 and less than or equal to n). Specifically, the memory cells of the first row are coupled to a first write word line WWL0 and a first read word line RWL0, respectively, and the memory cells of the second row are coupled … to the memory cells of the mth row and are coupled to an mth write word line WWLm and an mth read word line RWLm, respectively, to a second write word line WWL1 and a first read word line RWL1, respectively; the memory cells of the first row are coupled to the first pair of write bit lines WBL0, WBLB0 and first read bit line RBL0, respectively, and the memory cells of the second row are coupled to the second pair of write bit lines WBL1, WBLB1 and second read bit line RBL1, respectively, and … … the memory cells of the nth row are coupled to the nth pair of write bit lines WBLn, WBLBn and nth read bit line RBLn, respectively.

The timing control circuit 320 may receive an external clock signal and control an access operation of the memory array according to the external clock signal. Specifically, the timing control circuit 320 may generate control signals related to a read operation, including a read clock signal, a bit line decoding control signal, a bit line detection enable control signal, and an output data latch control signal; control signals associated with write operations may also be generated, including write clock control signals, write data latch control signals, and the like. In addition, the timing control circuit 320 can generate a bit line precharge control signal to precharge the bit lines of the corresponding columns in the memory array to a high level in preparation for the read operation.

In some embodiments, the word line decoding and word line driving circuit 330 may include a write word line decoder (not shown) and a write word line driver (not shown), a read word line decoder (not shown) and a read word line driver (not shown).

When a write operation is performed, the write word line decoder may parse information of a row address where a write target memory cell is located from the received write address and transmit the parsed information to the write word line driver circuit. The write word line driving circuit may receive information of a row address where the write target memory cell is located, and precharge the write word line of the row where the write target memory cell is located to a high level.

Similarly, when a read operation is performed, the read word line decoder may parse information of a row address where a read target memory cell is located from the received read address and transmit the parsed information to the read word line driver circuit. The read word line driving circuit may receive information of a row address where the read target memory cell is located, and precharge a write word line of the row where the target memory cell is located to a high level.

In a read operation, the bit line decoding circuit 340 may perform column address decoding on a read address sent by a peripheral device, generate a corresponding read selection signal, and send the read selection signal to the input/output control circuit 350, so that the input/output control circuit 350 reads data stored in a corresponding read target memory cell through the read selection signal.

When a write operation is performed, the bit line decoding circuit 340 may perform column address decoding on a write address sent by a peripheral device, generate a corresponding write selection signal, and send the write selection signal to the input/output control circuit 350, so that the input/output control circuit 350 writes input data sent by the peripheral device into a corresponding write target memory cell through the write selection signal.

With continued reference to fig. 3, in some embodiments, the input/output control circuit 350 may include a read multiplexer (not shown), a bit line detection unit (not shown), an output data latch (not shown), an input data latch (not shown), a write driver (not shown), and a bit line precharge circuit (not shown).

When a read operation is performed, the read multiplexer may receive a read selection signal transmitted by the bit line decoding circuit 340, and couple the bit line detection unit to a read bit line of a read target memory cell corresponding to the read selection signal; the bit line detection unit can read the data in the read target storage unit through a signal on a coupled read bit line and send the data to the output data latch; the output data latch may latch data in the read target memory cell read by the bit line sensing unit and output the latched data to a peripheral device.

When a write operation is performed, the input data latch may latch write data transmitted from a peripheral device and provide the latched write data to the write driver; the write column multiplexer may receive a write selection signal transmitted by the bit line decoding circuit 340, and couple the output terminal of the write driver to the write bit line pair of the corresponding column in the memory array according to the write selection signal; the write driver may then drive the write data into a write bit line pair coupled to a corresponding column in the memory array through a write column multiplexer, thereby writing the received write data into a corresponding write target memory cell.

The bit line precharge circuit may precharge all read bit lines in the memory array to a preset supply voltage prior to a read operation in preparation for the read operation.

Only the components of the dual port memory involved in the embodiments of the present invention have been described above. Those skilled in the art will appreciate that the pseudo-dual port memory may include other functional components associated with memory operations to implement functions associated with memory operations, and is not limited herein.

A read data output control method of the dual port memory in the embodiment of the present invention will be described below.

Fig. 4 is a flowchart illustrating a read data output control method for a dual port memory according to an embodiment of the present invention. Referring to fig. 4, a read data output control method for a dual port memory, which is used for controlling an output data latch in an input/output control circuit by a timing control circuit, may specifically include the following steps:

step S401: when successive read operations are performed on the memory cells based on an external clock signal, the successive read operations are tracked.

In a specific implementation, the consecutive read operations are tracked, i.e. the end point in time of each of the consecutive read operations is monitored.

In the embodiment of the present invention, the end time point of each of the consecutive read operations is detected by a change in the voltage signals on the read word line and the read bit line corresponding to the read operation. Specifically, when it is determined that the corresponding read word line transitions from a high level to a low level and the voltage signal on the read bit line transitions from a high level to a low level, it may be determined that the corresponding read operation is ended; otherwise, the corresponding read operation is not yet finished.

Step S402: when each read operation in the continuous read operations is finished, corresponding latch control signals are respectively generated, so that the output data latch latches and outputs the data read by executing the read operation when receiving the latch control signals.

In particular implementations, when each of the successive read operations is determined to be complete, a corresponding latch control signal may be generated to be sent to the output data. The output data latch may latch the read data acquired from the bit line detection unit and output the latched read data to a peripheral device when receiving the latch control signal.

In other words, the output latch clock signal for controlling the output data latch is high only in the corresponding time period before the current read operation is finished and the next read operation is reached, that is, the output data latch clock signal in the embodiment of the present invention is controlled by the timing control circuit according to the end time of the read operation, not by the external clock signal.

Referring to fig. 5, the output data latch clock control signal generated in the implementation of the present invention can prevent the occurrence of a fail (glitch) caused by the read bit line voltage signal precharged by the bit line precharge circuit being read out while the output data output latch controlled by the external clock signal becomes transparent during the execution of the consecutive read "0" operation.

In a specific implementation, the duration of the high level pulse of the output latch clock signal for controlling the output data latch may be set according to actual needs, as long as the set duration of time is such that the output data latch outputs the data read from the read-target memory cell to a peripheral device.

Correspondingly, the embodiment of the invention also provides a read data output control device of the dual-port memory.

Fig. 6 shows a read data output control apparatus of a dual port memory in an embodiment of the present invention. Referring to fig. 6, the read data output control apparatus 60 in the embodiment of the present invention may include a tracking unit 601 and a latch control unit 602, wherein:

the tracking unit 601 is adapted to track successive read operations performed on the memory cell based on an external clock signal.

In an implementation, the tracking unit 601 is adapted to monitor the read word line and the read bit line of the memory cell corresponding to the read operation, so as to track the consecutive read operations. Specifically, the tracking unit 601 is adapted to determine that the corresponding read operation is finished when the voltage signal on the read word line of the memory cell is converted from a high level to a low level and the signal on the read bit line is converted from a high level to a low level.

The latch control unit 602 is adapted to generate corresponding latch control signals when each of the consecutive read operations ends, so that the output data latch latches and outputs the data read by performing the read operation when receiving the latch control signals.

It will be understood by those skilled in the art that the data reading operation control device in the embodiment of the present invention may be disposed in the aforementioned timing control circuit, that is, the timing control circuit executes the above-mentioned operations. Of course, the functional module may also be disposed in other functional modules of the dual port memory, or the corresponding functional module may be disposed separately, which is not limited herein.

Correspondingly, the embodiment of the invention also provides a computer-readable storage medium, and one or more computer instructions are stored in the storage medium and used for realizing the read data output control method. For the read data output control method, reference is made to the detailed description of the foregoing sections, which are not repeated.

Correspondingly, the embodiment of the invention also provides a dual-port memory, which comprises the read data output control device. For the read data output control device, please refer to the detailed description of the previous section, which is not repeated.

By adopting the scheme provided by the embodiment of the invention, when continuous reading operation is executed on the storage unit based on an external clock signal, the continuous reading operation is tracked; when each read operation in the continuous read operations is finished, corresponding latch control signals are respectively generated, so that the data read by the read operation is latched and output by the output data latch when the latch control signals are received, and the situation that the output node Q of the output data latch is changed from a low level to a high level and then back to the low level in the continuous read data execution period can be avoided when the read operation is finished, so that the dynamic power loss can be saved, and the performance of the dual-port memory can be improved.

The embodiments of the present invention described above are combinations of elements and features of the present invention. Unless otherwise mentioned, the elements or features may be considered optional. Each element or feature may be practiced without being combined with other elements or features. In addition, the embodiments of the present invention may be configured by combining some elements and/or features. The order of operations described in the embodiments of the present invention may be rearranged. Some configurations of any embodiment may be included in another embodiment, and may be replaced with corresponding configurations of the other embodiment. It will be apparent to those skilled in the art that claims that are not explicitly cited in each other in the appended claims may be incorporated into the embodiments of the present invention or may be incorporated as new claims in modifications subsequent to the filing of this application.

Embodiments of the invention may be implemented by various means, such as hardware, firmware, software, or a combination thereof. In a hardware configuration, the method according to the exemplary embodiment of the present invention may be implemented by one or more Application Specific Integrated Circuits (ASICs), Digital Signal Processors (DSPs), Digital Signal Processing Devices (DSPDs), Programmable Logic Devices (PLDs), Field Programmable Gate Arrays (FPGAs), processors, controllers, micro-controllers, microprocessors, and the like.

In a firmware or software configuration, embodiments of the present invention may be implemented in the form of modules, procedures, functions, and the like. The software codes may be stored in memory units and executed by processors. The memory unit is located inside or outside the processor, and may transmit and receive data to and from the processor via various known means.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (10)

1. A read data output control method of a dual-port memory comprises a memory array, a bit line detection unit and an output data latch; the memory array comprises a plurality of rows and a plurality of columns of memory cells; the memory cells in the same row and the same read word line, and the memory cells in the same column and the same read bit line; the input of the bit line detection unit is coupled to the read bit lines of the corresponding column through corresponding read column multiplexers, respectively, and the output of the bit line detection unit is coupled to the input of the output data latch, wherein the method comprises:

tracking successive read operations as they are performed on the memory cells based on an external clock signal;

when each read operation in the continuous read operations is finished, corresponding latch control signals are respectively generated, so that the output data latch latches and outputs the data read by executing the read operation when receiving the latch control signals.

2. The method of claim 1, wherein tracking the consecutive read operations comprises:

and monitoring a read word line and a read bit line of a memory cell corresponding to the read operation so as to track the read operation.

3. The method of claim 2, wherein the determining that the read operation is complete comprises:

the read operation is determined to be ended when the voltage signal on the read word line of the memory cell transitions from a high level to a low level and the read bit line is precharged to a high level.

4. The method as claimed in claim 1, wherein the memory cells read by the consecutive read operations are the same memory cells or different memory cells.

5. A read data output control device of a dual port memory comprises a memory array, a bit line detection unit and an output data latch; the memory array comprises a plurality of rows and a plurality of columns of memory cells; the memory cells in the same row and the same read word line, and the memory cells in the same column and the same read bit line; the input of the bit line detection unit is coupled to the read bit lines of the corresponding column through corresponding read column multiplexers, respectively, and the output of the bit line detection unit is coupled to the input of the output data latch, wherein the apparatus comprises:

a tracking unit adapted to track successive read operations when the successive read operations are performed on the memory cell based on an external clock signal;

and the latch control unit is suitable for respectively generating corresponding latch control signals when each read operation in the continuous read operations is finished, so that the output data latch latches and outputs the data read by executing the read operation when receiving the latch control signals.

6. The apparatus as claimed in claim 5, wherein the tracking unit is adapted to monitor the read word line and the read bit line of the memory cell corresponding to the read operation for tracking the consecutive read operations.

7. The read data output control apparatus of the dual port memory according to claim 6, wherein the tracking unit is adapted to determine that the read operation is ended when the voltage signal on the read word line of the memory cell is converted from a high level to a low level and the read bit line is precharged to a high level.

8. The read data output control device of the dual port memory according to claim 5, wherein the memory cells read by the consecutive read operations are the same memory cell or different memory cells.

9. A computer-readable storage medium, wherein the storage medium stores one or more computer instructions for implementing the read data output control method of any one of claims 1-4.

10. A dual port memory comprising the read data output control means as claimed in any one of claims 5 to 8.

Images