CN112131037B

CN112131037B - memory device

Info

Publication number: CN112131037B
Application number: CN201910547971.0A
Authority: CN
Inventors: 中冈裕司
Original assignee: Winbond Electronics Corp
Current assignee: Winbond Electronics Corp
Priority date: 2019-06-24
Filing date: 2019-06-24
Publication date: 2023-11-14
Anticipated expiration: 2039-06-24
Also published as: CN112131037A

Abstract

The invention provides a memory device. The data read-write circuit is used for accessing the data of the memory cell array. The correction data read-write circuit is used for accessing correction data of the correction data storage unit array. The syndrome arithmetic circuit generates an error decoding signal based on the data received from the data read/write circuit and the correction data received from the correction data read/write circuit. In the same reading period of the read data, the data read-write circuit corrects the error bit in the data according to the error decoding signal and outputs the correct data and the correction bit signal. The syndrome arithmetic circuit also outputs a correction data write signal to the correction data read/write circuit according to the correction bit signal to update the correction data in the correction data memory cell array. The data read-write circuit also writes the corrected data back to the memory cell array.

Description

Memory device

Technical Field

The present invention relates to a memory device, and more particularly, to a memory device having error checking and correcting functions.

Background

With the advancement of technology, the demand of consumers for storage media has also increased rapidly, and the dynamic random access memory (Dynamic Random Access Memory, DRAM) has the advantages of simple structure, high density and low cost, and is thus widely used in various electronic devices. To improve the data reliability of DRAMs, some DRAMs are provided with Error-correction memory (ECC memory) to detect Error bits in stored data and correct the Error bits. At present, the DRAM mainly adopts a single error correction (Single Error Correcting) technology, but the single error correction technology can only correct one-bit error at a time. If the stored data has errors of more than 2 bits at the same time, the error correction function of the ECC circuit fails. However, the DRAM may be operated with Soft error (Soft error) due to high temperature, refresh, etc. to generate error bits. If the error bits cannot be corrected in time, the stored data may accumulate two error bits to reduce the data reliability of the memory. Therefore, how to correct the stored data in time to avoid accumulating more than 2 error bits to maintain the data correctness of the DRAM is a problem to be overcome.

Disclosure of Invention

The invention provides a memory device, which can correct error bits in real time in a data reading period and update stored data and correction data for error checking and correction.

A memory device of the present invention includes: the correction circuit comprises a data read-write circuit, a correction data read-write circuit and a syndrome operation circuit. The data read-write circuit is coupled with the memory cell array and used for accessing the data of the memory cell array. The correction data read-write circuit is coupled with the correction data storage unit array and used for accessing correction data of the correction data storage unit array. The data read/write circuit corrects error bits in the data according to the error decoding signals and outputs correct data and correction bit signals in the same reading period of the read data, wherein the data read/write circuit writes the corrected data back to the memory cell array, and the syndrome operation circuit outputs correction data writing signals to the correction data read/write circuit according to the correction bit signals to update the correction data in the correction data memory cell array.

Based on the above, the memory device of the present invention can read data from the memory cell array and complete checking and correction in one read cycle. When an error bit is found in the data, the memory device of the invention can correct the error in the same reading period to output correct data, and correspondingly write the corrected data back to the memory cell array and the updated correction data back to the correction data memory cell array in a continuous period. Therefore, the memory device can improve the reliability of data.

In order to make the above features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

FIG. 1 is a block diagram of a memory device according to an embodiment of the invention;

FIG. 2 is a schematic circuit diagram of a data read/write circuit according to an embodiment of the invention;

FIG. 3A is a schematic circuit diagram of a data reading circuit according to an embodiment of the invention;

FIG. 3B is a waveform diagram illustrating a read operation of a memory device according to an embodiment of the invention;

FIG. 4 is a circuit diagram of a data correction circuit according to an embodiment of the invention;

FIG. 5A is a schematic diagram of a data write circuit according to an embodiment of the invention;

FIG. 5B is a schematic circuit diagram of a control signal generation circuit of the data write circuit according to an embodiment of the present invention;

FIG. 6A is a waveform diagram of a write operation of a memory device without finding an error bit according to an embodiment of the present invention;

FIG. 6B is a waveform diagram of a write operation of the memory device with correction of erroneous bits according to an embodiment of the present invention;

FIG. 7A is a schematic diagram of a syndrome generating circuit according to an embodiment of the invention;

FIG. 7B is a schematic diagram of an internal operation circuit of the syndrome generating circuit according to an embodiment of the present invention;

FIG. 7C is a schematic diagram of a syndrome control signal generating circuit of a syndrome generating circuit according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of a correction data read/write circuit according to an embodiment of the invention;

FIG. 9 is a circuit diagram of a correction data write circuit according to an embodiment of the present invention.

Description of the reference numerals

100: memory device

110: memory cell array

120: correction data memory cell array

130: data read-write circuit

140: correction data read-write circuit

150: syndrome generating circuit

160: syndrome decoding circuit

170: syndrome arithmetic circuit

210: data reading circuit

220: data correction circuit

230: data writing circuit

310: reading switch

320: pre-charging circuit

330: amplifying circuit

332: amplifier

410: correction switch

420: read bit latch

430: correction circuit

440. 540: output circuit

442: latch device

510. 520: write switch

530: write bit latch

550: control signal generating circuit

610: signal generating circuit

710: internal arithmetic circuit

720: input circuit

730: syndrome control signal generating circuit

810: correction data reading circuit

820: correction data writing circuit

AD. ADi: reading data

ADiT: reading data signals

ADiN: inverting read data signals

BL: bit line

BLN: complementary bit line

CS: correcting bit signals

DE: read enable signal

DM: write mask signal

DWm: write mask select signal

DWmB: inverted write mask select signal

EiT: positive latch bit signal

EiN: inverse latching bit signals

GND: ground voltage

LAR: reading latch signals

Law: initial write latch signal

LAWm: first write latch signal

LAWmB: inverting a first write latch signal

LDWm: second write latch signal

LDWmB: inverting the second write latch signal

LAWPT: verifying a write latch signal

LAWPB: inverse verification write latch signal

MD: data

MDiT: data signal

MDiN: inverted data signal

NAND1 to NAND5: inverse gate

NOR1 to NOR3: OR gate

NS: correcting data write signals

INV, INV1 to INV21: inverter with a high-speed circuit

OE: output enable signal

PB: prefilled signal

PM: correction data

PS: correcting read signals

RWB, RWBi: data output signal

RD, RDi: reading a bit signal

SY: syndrome signal

SD, SDi: error decoding signal

SDE: decoding control signals

TG, TG1 to TG9: transmission gate

T31, T32, TP1 to TP10: p-type transistor

T33, T34, T35, TN1 to TN3: n-type transistor

VDD: voltage power supply

VSS: low voltage

WE: write enable signal

WED: write data control signal

WEDB: inverted write data control signal

WEm: write data select signal

WEmB: inverted write data select signal

Detailed Description

FIG. 1 is a block diagram of a memory device according to an embodiment of the invention. Referring to fig. 1, the memory device 100 includes a memory cell array 110, a correction data memory cell array 120, a data read/write circuit 130, a correction data read/write circuit 140, and a syndrome operation circuit 170, wherein the syndrome operation circuit 170 includes a syndrome generating circuit 150 and a syndrome decoding circuit 160. The data read/write circuit 130 is coupled to the memory cell array 110 to access the data MD of the memory cell array 110. The correction data read/write circuit 140 is coupled to the correction data memory cell array 120 to access the correction data PM of the correction data memory cell array 120. The correction data PM is an error checking and correcting code for checking and correcting the data MD, for example, an ECC encoding process such as Hamming code (Hamming code) is performed on the data MD. The number of bits of the correction data PM depends on the number of bits of the data MD. In the present embodiment, the size of the data MD is 64 bits, and the size of the correction data PM is set to 7 bits, but the sizes of the data MD and the correction data PM are not limited in the present invention.

The syndrome arithmetic circuit 170 generates an error decoding signal SD based on the data MD received from the data read/write circuit 130 (the data read/write circuit 130 outputs the read bit signal RD after reading the data MD) and the correction data PM received from the correction data read/write circuit 140 (the correction data read/write circuit 140 outputs the correction read signal PS after reading the correction data PM), wherein the data read/write circuit 130 corrects the error bit in the data MD and outputs the correct data (i.e., the data output signal RWB) and the correction bit signal CS based on the error decoding signal SD in the same read cycle of the read data MD. The data read/write circuit 130 writes the corrected data back to the memory cell array 110, and the syndrome operation circuit 170 outputs a corrected data write signal NS to the corrected data read/write circuit 140 according to the corrected bit signal CS to update the corrected data PM in the corrected data memory cell array 120.

In other words, in the present embodiment, after the data MD and the correction data PM are read, whether there is an error bit in the data MD can be checked by the syndrome encoding (Syndrome encoding) and the syndrome decoding (Syndrome decoding) of the syndrome arithmetic circuit 170. If there is an error bit, the data read/write circuit 130 may correct the error bit based on the error decoding signal SD in real time in the same reading period to output a correct data output signal RWB, and may output a corrected bit signal CS to the syndrome arithmetic circuit 170 together to cause the corrected data read/write circuit 140 to update the corrected data PM. It is particularly mentioned that the memory device 100 does not need to select the memory cells of the memory cell array 110 again between reading the data MD and outputting the correct data output signal RWB, the above-mentioned operations can be completed in the same reading period, and the correction data PM can also be updated.

The circuit configuration and implementation of the present embodiment are further described below. FIG. 2 is a schematic circuit diagram of a data read/write circuit according to an embodiment of the invention. Referring to fig. 2, the data read/write circuit 130 includes a data read circuit 210, a data correction circuit 220 and a data write circuit 230. The data reading circuit 210 is coupled to the memory cell array 110 for reading data MD from the memory cell array 110 to generate read data AD and a corresponding read bit signal RD. The data correction circuit 220 is coupled to the data reading circuit 210 and the syndrome decoding circuit 160 of the syndrome computing circuit 170, and is used for latching the read data AD in a read cycle, and correcting the error bit of the read data AD according to the error decoding signal SD to generate a correct data output signal RWB and a corrected bit signal CS, wherein the data output signal RWB is an output result of the data reading and writing circuit 130 after reading and correcting the data MD. The data writing circuit 230 is coupled to the data correction circuit 220 and the memory cell array 110, and is configured to replace the data output signal RWB corresponding to the error bit with the correction bit signal CS to write the correct data MD back to the memory cell array 110.

Referring to fig. 1 again, the syndrome operation circuit 170 includes a syndrome generating circuit 150 and a syndrome decoding circuit 160. The syndrome generating circuit 150 is coupled to the data read/write circuit 130 and the correction data read/write circuit 140, and selectively receives the output signal of the data read circuit 210 or the data correction circuit 220 to generate the correction data write signal NS according to the read operation or the write operation. More specifically, the syndrome generating circuit 150 generates the correction data writing signal NS according to the read bit signal RD when the data read/write circuit 130 performs a read operation, and the syndrome generating circuit 150 generates the correction data writing signal NS according to the correction bit signal CS or the data output signal RWB when the data read/write circuit 130 performs a write operation.

The syndrome generating circuit 150 compares the correction data write signal NS with the corresponding correction data PM (the correction data read/write circuit 140 reads the correction data PM to provide the correction read signal PS to the syndrome generating circuit 150) to generate the syndrome signal SY. The syndrome decoder 160 is coupled to the syndrome generator 150 for decoding the syndrome signal SY to generate the error decoding signal SD. The data read/write circuit 130 corrects the error bits in the data MD according to the error decoding signal SD.

Next, a specific embodiment of the data read/write circuit 130 will be described. Fig. 3A is a circuit diagram of a data reading circuit according to an embodiment of the invention, and fig. 3B is a waveform diagram of a reading operation of a memory device according to an embodiment of the invention. Fig. 4 is a circuit diagram of a data correction circuit according to an embodiment of the present invention, fig. 5A is a circuit diagram of a data write circuit according to an embodiment of the present invention, and fig. 5B is a circuit diagram of a control signal generation circuit of a data write circuit according to an embodiment of the present invention. Please refer to fig. 3A-5B in conjunction with fig. 1 and fig. 2 to specifically illustrate the implementation details of the data read/write circuit 130.

In fig. 3A, the data reading circuit 210 includes a reading switch 310, a precharge circuit 320, and an amplifying circuit 330. The input terminal of the read switch 310 receives the data MD from the memory cell array 110 and is turned on or off by the read enable signal DE. The precharge circuit 320 is coupled to the input terminal of the read switch 310 and is controlled by the precharge signal PB to perform a precharge operation on the input terminal of the read switch 310. The input end of the amplifying circuit 330 is coupled to the output end of the read switch 310, and is controlled by the read enable signal DE to generate the read data AD and generate the corresponding read bit signal RD.

Specifically, the sense amplifier in the memory cell array 110 outputs the data MD stored in the memory cells in the form of a differential signal (Differential signal), so the data MD includes a differential signal of a data signal MDiT and an inverted data signal MDiN, where the data MD is exemplified by 64 bits, and in this specification, MDi represents one of the bits of the data MD, i is an integer from 0 to 63 (i=0, 1,2, …, 63), such as MD0, MD1, …, MD63. Similarly, the read data AD is a differential signal including the read data signal ADiT and the inverted read data signal ADiN. In the present specification, i refers to a corresponding bit, for example, the read bit signal RDi, the data output signal RWBi and the correction bit signal CSi represent a corresponding bit of the read bit signal RD, the data output signal RWB and the correction bit signal CS, and so on.

In the read switch 310, the transmission gate TG1 is coupled to the bit line BL to receive the data signal MDiT, the transmission gate TG2 is coupled to the complementary bit line BLN to receive the inverted data signal MDiN, and both the transmission gate TG1 and the transmission gate TG2 are controlled by the read enable signal DE. The input end of the inverter INV1 in fig. 3A receives the read enable signal DE, and the output end thereof is commonly coupled to one of the control ends of the transmission gates TG1 and TG2 (e.g., the control ends of the N-type transistors in the transmission gates TG1 and TG 2). The input end of the inverter INV2 is coupled to the output end of the inverter INV1, and the output ends thereof are commonly coupled to the other control ends of the transmission gates TG1 and TG2 (e.g., the control ends of the P-type transistors in the transmission gates TG1 and TG 2).

In the precharge circuit 320, the inverter INV3 receives the precharge signal PB. The P-type transistor TP1 has a first terminal coupled to the power voltage VDD, a control terminal coupled to the output terminal of the inverter INV3, and a second terminal coupled to the bit line BL. The P-type transistor TP2 has a first terminal coupled to the power voltage VDD, a control terminal coupled to the output terminal of the inverter INV3, and a second terminal coupled to the complementary bit line BLN. The P-type transistor TP3 is coupled between the second terminal of the P-type transistor TP1 and the second terminal of the P-type transistor TP2, and the control terminal thereof is coupled to the output terminal of the inverter INV 3.

In the amplifying circuit 330, the amplifier 332 is coupled to the read switch 310 to receive the data signal MDiT and the inverted data signal MDiN, and output the read data signal ADiT and the inverted read data signal ADiN, respectively. The inverter INV4 receives the inverted read data signal ADiN to output the read bit signal RDi.

In the present embodiment, the amplifier 332 includes P-type transistors T31 to T32 and N-type transistors T33 to T35. The P-type transistor T31 and the N-type transistor T33 are connected in series between the voltage source VDD and the first end of the N-type transistor T35, the P-type transistor T32 and the N-type transistor T34 are also connected in series between the voltage source VDD and the first end of the N-type transistor T35, wherein the control ends of the P-type transistor T31 and the N-type transistor T33 are commonly coupled to the first end of the N-type transistor T34, and the control ends of the P-type transistor T32 and the N-type transistor T34 are commonly coupled to the first end of the N-type transistor T33. The second terminal of the N-type transistor T35 is coupled to the ground voltage GND, and the control terminal thereof is coupled to the read enable signal DE.

In FIG. 3B, before a read operation, the precharge signal PB turns on the read switch 310 to precharge the bit line BL and the complementary bit line BLN. When the read operation is to be started, the precharge signal PB turns off the read switch 310 to end the precharge operation. Meanwhile, the selection signal CSL for selecting a memory cell of the memory cell array 110 changes from a Low logic level (Low) to a High logic level (High) to read the data MD of the selected memory cell. Then, the read enable signal DE is switched to a High logic level (High) to turn on the read switch 310 and the start amplifier 332 to amplify the data signal MDiT and the inverted data signal MDiN to output the read data signal ADiT, the inverted read data signal ADiN and the read bit signal RDi. The low voltage VSS in fig. 3B is exemplified as the ground voltage GND.

Referring to fig. 4, the data correction circuit 220 includes a correction switch 410, a read bit latch 420, a correction circuit 430 and an output circuit 440. The input terminal of the correction switch 410 receives the read data ADi from the data read circuit 210 and is turned on or off by the read latch signal LAR. The read bit latch 420 is coupled to the correction switch 410 for latching the read data ADi. The correction circuit 430 is coupled to the read bit latch 420 and receives the corresponding error decoding signal SDi, and is configured to correct the bits stored in the read bit latch 420 according to the error decoding signal SDi. The output circuit 440 is coupled to the correction circuit 430 and the read bit latch 420, and outputs the bit stored in the read bit latch 420 as a data output signal RWBi under the control of an output enable signal OE.

In the correction switch 410 of fig. 4, the transmission gate TG3 receives the read data signal ADiT from the data read circuit 210, the transmission gate TG4 receives the inverted read data signal ADiN from the data read circuit 210, and both the transmission gate TG3 and the transmission gate TG4 are controlled by the read latch signal LAR. The input end of the inverter INV5 receives the read latch signal LAR, and the output end thereof is commonly coupled to one of the control ends of the transmission gate TG3 and the transmission gate TG4 to provide an inverted signal of the read latch signal LAR.

The read bit latch 420 includes an inverter INV6 and an inverter INV7. An input terminal of the inverter INV6 is coupled to an output terminal of the inverter INV7 and receives the read data signal ADiT through the transmission gate TG 3. An input terminal of the inverter INV7 is coupled to an output terminal of the inverter INV6 and receives the inverted read data signal ADiN through the transmission gate TG 4.

In the correction circuit 430, the inverter INV8 receives the error decoding signal SDi, and the inverter INV9 is coupled to the output end of the inverter INV6 to output the correction bit signal CSi. The first terminal of the P-type transistor TP4 is coupled to the power voltage VDD, the second terminal thereof is coupled to the first terminal of the P-type transistor TP5, and the control terminal thereof is coupled to the output terminal of the inverter INV 8. The second terminal of the P-type transistor TP5 is coupled to the input terminal of the inverter INV6, and the control terminal thereof receives the read data signal ADiT. The first terminal of the P-type transistor TP6 is also coupled to the power voltage VDD, the second terminal thereof is coupled to the first terminal of the P-type transistor TP7, and the control terminal thereof is coupled to the output terminal of the inverter INV 8. The second terminal of the P-type transistor TP7 is coupled to the output terminal of the inverter INV6, and the control terminal thereof receives the inverted read data signal ADiN.

In the output circuit 440, an input terminal of the inverter INV10 is coupled to the output enable signal OE. The first input terminal of the NAND gate NAND1 is coupled to the second terminal of the P-type transistor TP5, and the second input terminal thereof receives the output enable signal OE. The first input terminal of the NOR gate NOR1 is coupled to the second terminal of the P-type transistor TP5, and the second input terminal thereof is coupled to the output terminal of the inverter INV 10. The first terminal of the P-type transistor TP8 is coupled to the power voltage VDD, the control terminal thereof is coupled to the output terminal of the NAND gate NAND1, and the first terminal of the N-type transistor TN1 is coupled to the second terminal of the P-type transistor TP8 and provides the corrected data output signal RWBi, the control terminal thereof is coupled to the output terminal of the NOR gate NOR1, and the second terminal thereof is coupled to the ground voltage GND. The output circuit 440 may also include a latch 442 coupled to the first terminal of the N-type transistor TN 1. The circuit architecture of latch 442 is identical to that of read bit latch 420, and is formed by the interconnection of two inverters INV.

Referring again to FIG. 3B, when the read latch signal LAR is switched to a high logic level, the read bit latch 420 receives the read data ADi to latch its bit value and generates the corresponding positive latch bit signal EiT and the corresponding negative latch bit signal EiN. In fig. 3B, during the high logic level period of the read latch signal LAR, the positive latch bit signal EiT changes to a low logic level and the negative latch bit signal EiN changes to a high logic level. After the read latch signal LAR is switched to the low logic level, if the ith bit of the data MD is an error bit, the error decoding signal SDi from the syndrome decoding circuit 160 is switched to the high logic level. In the same reading period, the correction circuit 430 inverts the error bit value latched by the read bit latch 420 according to the error decoding signal SDi, so that the positive latch bit signal EiT and the negative latch bit signal EiN are inverted to correct the error. Finally, the output circuit 440 outputs the correct data output signal RWBi according to the output enable signal OE.

Referring to fig. 5A, the data writing circuit 230 includes an inverter INV11, a writing switch 510, a writing switch 520, a writing bit latch 530 and an output circuit 540. An input end of the inverter INV11 receives the corresponding data output signal RWBi. The input end of the write switch 510 is coupled to the output end of the inverter INV11 and is controlled by the first write latch signal law to be turned on or off. The input terminal of the write switch 520 receives the corresponding correction bit signal CSi and is controlled by the second write latch signal LDWm to be turned on or off. Where m is an integer from 0 to 7, representing the corresponding Mask (Mask) bits. The write bit latch 530 is coupled to the output of the write switch 510 and the output of the write switch 520, and the output circuit 540 is coupled to the output of the write switch 520 and the write bit latch 530. The output circuit 540 is controlled by the write enable signal WE and writes the data output signal RWBi or the correction bit signal CSi to the memory cell array 110.

Here, the data signal MDiT and the inverted data signal MDiN outputted by the output circuit 540 can be respectively transmitted back to the bit line and the complementary bit line of the memory cell array 110 to rewrite the data MDi.

In fig. 5A, the write switch 510 is implemented as a transmission gate TG5, and the write switch 520 is implemented as a transmission gate TG 6. The two control ends of the transmission gate TG5 respectively receive the corresponding first write latch signal law and an inverted signal of the first write latch signal law (abbreviated as an inverted first write latch signal) law, and the two control ends of the transmission gate TG6 respectively receive the second write latch signal law and an inverted signal of the second write latch signal law (abbreviated as an inverted second write latch signal) LDWmB.

The write bit latch 530 includes an inverter INV12 and an inverter INV13. The input end of the inverter INV12 is coupled to the output end of the inverter INV13, and the input end of the inverter INV13 is coupled to the output end of the inverter INV12, wherein the input end of the inverter INV12 is commonly coupled to the output ends of the transmission gate TG5 and the transmission gate TG 6.

In the output circuit 540, the inverter INV14 is connected in series with the inverter INV15, and the inverter INV14 receives the write enable signal WE. The first input end of the NOR gate NAND2 is coupled to the output end of the inverter INV12, the second input end thereof is coupled to the output end of the inverter INV15, the first input end of the NOR gate NOR2 is coupled to the output end of the inverter INV12, and the second input end thereof is coupled to the output end of the inverter INV 14. The first terminal of the P-type transistor TP9 is coupled to the power voltage VDD, the control terminal thereof is coupled to the output terminal of the NAND gate NAND2, and the first terminal of the N-type transistor TN2 is coupled to the second terminal of the P-type transistor TP9 and provides the corresponding data signal MDiT, the control terminal thereof is coupled to the output terminal of the NOR gate NOR2, and the second terminal thereof is coupled to the ground voltage GND. The first input terminal of the NAND gate NAND3 is coupled to the output terminal of the inverter INV13, and the second input terminal thereof is coupled to the output terminal of the inverter INV 15. The first input terminal of the NOR gate NOR3 is coupled to the output terminal of the inverter INV13, and the second input terminal thereof is coupled to the output terminal of the inverter INV 14. The first terminal of the P-type transistor TP10 is coupled to the power voltage VDD, the control terminal thereof is coupled to the output terminal of the NAND gate NAND3, and the first terminal of the N-type transistor TN3 is coupled to the second terminal of the P-type transistor TP10 and provides a corresponding inverted data signal MDiN, the control terminal thereof is coupled to the output terminal of the NOR gate NOR3, and the second terminal thereof is coupled to the ground voltage GND.

Referring to fig. 5B, the data writing circuit 230 further includes a control signal generating circuit 550, and the control signal generating circuit 550 generates a first writing latch signal LAW and a second writing latch signal LDWm according to the initial writing latch signal LAW and the writing mask signal DM. In the present embodiment, the write mask signal DM is an 8-bit signal, and thus the write mask signal DMm is a signal representing the corresponding mth bit, m being an integer of 0 to 7. The control signal generating circuit 550 provides the verify write latch signal LAWPT and the inverse verify write latch signal LAWPB to the correction data read/write circuit 140, and provides the corresponding first write latch signal LAWm and the second write latch signal LDWm, and their inverse signals to the data write circuit 230.

The control signal generating circuit 550 includes an inverter INV16, an inverter INV17, an inverter INV18, and a signal generating circuit 610. The inverter INV16 is connected in series with the inverter INV17, and an input end of the inverter INV16 receives the initial write latch signal LAW, the inverter INV17 outputs the verify write latch signal LAW to the correction data read-write circuit 140, wherein the inverter INV18 receives the initial write latch signal LAW to output the inverse verify write latch signal LAW.

It is added that the write enable signal WE and the initial write latch signal LAW remain at the low logic level during the read operation.

In the signal generating circuit 610 of fig. 5B, the output end of the inverter INV19 receives the corresponding write mask signal DMm. The first input terminal of the NAND gate NAND4 receives the initial write latch signal LAW, the second input terminal thereof is coupled to the output terminal of the inverter INV19, and the output terminal thereof outputs the corresponding inverted first write latch signal LAW. An input terminal of the inverter INV20 is coupled to the output terminal of the NAND gate NAND4 to output the corresponding first write latch signal law. The NAND gate NAND5 has a first input terminal receiving the initial write latch signal LAW, a second input terminal receiving the corresponding write mask signal DMm, and an output terminal outputting the corresponding inverted second write latch signal LDWmB. An input terminal of the inverter INV21 is coupled to the output terminal of the NAND gate NAND5 to output the corresponding second write latch signal LDWm.

FIG. 6A is a waveform diagram of a write operation of a memory device without finding an error bit according to an embodiment of the present invention, and FIG. 6B is a waveform diagram of a write operation of a memory device with correcting an error bit according to an embodiment of the present invention. Please simultaneously implement the above embodiments with reference to fig. 6A and 6B.

In fig. 6A, when the memory device 100 is to write data MD and the bits to be written do not need correction, the enable time (e.g., the time kept at the high logic level) of the selection signal CSL to select the memory cell is referred to as the normal write time. During the normal write time, the correction bit signal CS and the write mask signal DM keep at low logic levels, the write switch 510 is turned on and the write switch 520 is turned off, and the data write circuit 230 selectively writes the data output signal RWBi into the memory cell array 110.

In fig. 6B, after the memory device 100 finds the error bit in the data MD, and when the data write circuit 230 is to write back the correct data, the enabling time of the selection signal CSL is called the corrected write time. In the correction write time, after the read latch signal LAR is switched to the low logic level, the logic level of the error decoding signal SDi corresponding to the error bit position is shifted to the high level, and correspondingly, the correction bit signal CSi outputted from the data correction circuit 220 is also switched to the high logic level. It should be noted that, the syndrome generating circuit 150 also correspondingly outputs the correction data writing signal NS to the correction data reading/writing circuit 140 to update the correction data PM.

Then, the data writing circuit 230 performs a writing operation, the corresponding first writing latch signal law turns off the writing switch 510 and the corresponding second writing latch signal LDWm turns on the writing switch 520, so that the correction bit signal CSi is input to the output circuit 540 instead of the data output signal RWBi to write a correct bit value in the enabling time of the writing enabling signal WE.

In short, the data write circuit 230 writes the data output signal RWBi to the memory cell array 110 when the bit to be written is originally correct, and the data write circuit 230 writes the correction bit signal CSi to the memory cell array 110 when the bit to be written is the position of the error bit.

Specifically, in the present embodiment, the enable time of the selection signal CSL may be changed, and the corrected write time may be longer than the normal write time. When the memory device 100 finds the error bit, the data read/write circuit 130 and the correction data read/write circuit 140 can write the correct data back to the memory cell array 110 and update the correction data PM in the same period of correction by extending the enable time of the selection signal CSL. That is, the selection signal CSL is enabled only once to complete the checking, correcting and updating operations.

Details of the circuit architecture of the syndrome generating circuit 150 are described next. Fig. 7A is a circuit diagram of a syndrome generating circuit according to an embodiment of the present invention, fig. 7B is a circuit diagram of an internal operation circuit of the syndrome generating circuit according to an embodiment of the present invention, and fig. 7C is a circuit diagram of a syndrome control signal generating circuit of the syndrome generating circuit according to an embodiment of the present invention.

Referring to fig. 7A, the syndrome generating circuit 150 includes an internal operation circuit 710 and a plurality of exclusive or gates XOR2, wherein the internal operation circuit 710 includes a plurality of transmission gates TG (e.g. TG 7-TG 9 in fig. 7B) and a plurality of exclusive or gates XOR1.

In fig. 7B, the internal operation circuit 710 outputs the correction data write signal NS by controlling the plurality of transmission gates TG to selectively provide the data output signal RWB, the correction bit signal CS, or the read bit signal RD to the plurality of exclusive or gates XOR1. Specifically, the internal operation circuit 710 has a plurality of input circuits 720. Each input circuit 720 may receive a corresponding read bit signal RDi from the data read circuit 210 and a corresponding correction bit signal CSi from the data correction circuit 220 in addition to the corresponding data output signal RWBi. The internal operation circuit 710 selectively inputs one of the read bit signal RD, the data output signal RWB and the correction bit signal CS to the corresponding exclusive OR gate XOR1 by controlling the plurality of transmission gates TG 7-TG 9 in the input circuit 720.

In detail, the transmission gate TG7 receives the corresponding read bit signal RDi and is controlled by the write data control signal WED and the inverted signal WEDB of the write data control signal WED, the transmission gate TG8 receives the data output signal RWBi and is controlled by the inverted signal WEmB of the write data selection signal WEm and the write data selection signal WEm, and the transmission gate TG9 receives the correction bit signal CSi and is controlled by the inverted signal DWmB of the write mask selection signal DWm and the write mask selection signal DWm.

When the memory device 100 performs a read operation, the input circuit 720 selects the read bit signal RDi, turns on the transmission gate TG7 and turns off the transmission gates TG8 and TG9; when the memory device 100 performs a write operation, the input circuit 720 turns off the transmission gate TG7 and turns on the transmission gate TG8 or the transmission gate TG9 according to the write mask signal DM to select the received data output signal RWBi or the correction bit signal CSi.

The internal operation circuit 710 finally outputs the correction data write signal NSj through the exclusive or gate XOR1 operation of the plurality of stages, wherein j is an integer from 0 to 6 because the check bit of the present embodiment is 7 bits, and the correction data write signal NSj represents a signal corresponding to the j-th bit in the correction data write signal NS.

In fig. 7A, a plurality of exclusive or gates XOR2 receive the corresponding correction data write signal NSj from the internal arithmetic circuit 710 and the corresponding correction read signal PSj from the correction data read-write circuit 140. The syndrome generating circuit 150 compares the correction read signal PS with the correction data write signal NS to output a syndrome signal SY. The syndrome decoding circuit 160 receives the syndrome signal SY and the decoding control signal SDE and performs a decoding operation on the syndrome signal SY to output an error decoding signal SD to the data correction circuit 220 of the data read/write circuit 130.

The syndrome generating circuit 150 further includes a syndrome control signal generating circuit 730 for generating the control signal of the transmission gate TG. The circuit architecture of the syndrome control signal generating circuit 730 in fig. 7C is similar to that of the control signal generating circuit 550 in fig. 5B, and thus the details of the operation of the syndrome control signal generating circuit 730 are not described herein.

Next, a specific circuit architecture of the correction data read/write circuit 140 is described. Fig. 8 is a circuit diagram of a correction data read/write circuit according to an embodiment of the present invention, and fig. 9 is a circuit diagram of a correction data write circuit according to an embodiment of the present invention.

Referring to fig. 8, the correction data read/write circuit 140 includes a correction data read circuit 810 and a correction data write circuit 820. The correction data reading circuit 810 is coupled to the correction data memory cell array 120 and the syndrome operation circuit 170, and is configured to read the correction data PM from the correction data memory cell array 120 to output a correction read signal PS to the syndrome generation circuit 150 of the syndrome operation circuit 170. The correction data writing circuit 820 is coupled to the correction data memory cell array 120 and the syndrome generating circuit 150 of the syndrome computing circuit 170, and is used for writing the corrected correction data PM into the correction data memory cell array 120.

When the memory device 100 performs a read operation, the correction data read circuit 810 may read the correction data PM from the correction data storage unit array 120 to output the correction read signal PS to the syndrome generating circuit 150. The syndrome generating circuit 150 checks whether the read bit signal RD has an erroneous bit according to the corrected read signal PS. If there are erroneous bits, the corresponding erroneous decoding signal SDi changes logic level. In this embodiment, if the ith bit of the data MD is erroneous, the error decoding signal SDi changes to a high logic level, as shown in fig. 3B.

The circuit details of the calibration data reading circuit 810 can be referred to fig. 3A, and those skilled in the art can obtain enough suggestions, teachings and embodiments from the data reading circuit 210, which are not described herein.

Fig. 9 shows a circuit detail of the correction data writing circuit 820, which has a circuit architecture similar to that of the data writing circuit 230 of fig. 5A, and those skilled in the art can obtain sufficient suggestions, teachings and embodiments from the data writing circuit 230, and are not described herein.

Referring to fig. 6B again, when the syndrome generating circuit 150 checks that the read bit signal RD has an error bit, the data writing circuit 230 corrects the error of the read bit signal RD, and the syndrome generating circuit 150 outputs a new corrected data writing signal NS according to the corrected bit signal CS recording the error bit position. The correction data write circuit 820 writes a new correction data write signal NS to the correction data memory cell array 120 to update the correction data PM. The correction data PM in fig. 9 is a differential signal including a correction data signal PMjT and an inverse correction data signal PMjN, j being an integer of 0 to 6, representing a corresponding parity bit.

In summary, the memory device of the present invention can read data from the memory cell array and check the data in one read cycle, wherein when an error bit is found in the data, the memory device of the present invention can correct the error in real time and output the correct data in the same read cycle. In addition, the memory device of the invention can also output correction bit signals to the data writing circuit and the syndrome generating circuit at the same time. By extending the enable period of the select signal, the data write circuit can write the corrected data back to the memory cell array and the syndrome generating circuit can provide a new correction data write signal to the correction data write circuit to update the correction data. Therefore, the selection signal can complete the correction and updating of the data only by providing an enabling period for the memory cell to be written in, thereby achieving the effects of checking and correcting errors in real time.

Although the invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, but rather may be modified or altered somewhat by persons skilled in the art without departing from the spirit and scope of the invention.

Claims

1. A memory device, comprising:

the data read-write circuit is coupled with the memory cell array and used for accessing the data of the memory cell array;

the correction data read-write circuit is coupled with the correction data storage unit array and used for accessing correction data of the correction data storage unit array; and

a syndrome arithmetic circuit for generating an error decoding signal based on the data received from the data read/write circuit and the correction data received from the correction data read/write circuit,

wherein in the same reading period for reading the data, the data read-write circuit corrects the error bit in the data according to the error decoding signal and outputs the correct data and correction bit signal, wherein the data read-write circuit writes the corrected data back to the memory cell array, wherein the syndrome arithmetic circuit also outputs correction data write signal to the correction data read-write circuit according to the correction bit signal to update the correction data in the correction data memory cell array,

The data read-write circuit includes:

a data reading circuit coupled to the memory cell array for reading the data from the memory cell array to generate read data and a corresponding read bit signal;

the data correction circuit is coupled with the data reading circuit and the syndrome operation circuit and used for latching the read data in the reading period and correcting error bits of the read data according to the error decoding signal to generate a data output signal and the correction bit signal, wherein the data output signal is an output result of the data reading and writing circuit after the data is read and corrected; and

a data writing circuit coupled to the data correction circuit and the memory cell array for replacing the data output signal corresponding to the error bit with the correction bit signal to write the correct data back to the memory cell array,

the data correction circuit includes:

the input end of the correction switch receives the read data from the data reading circuit and is controlled by a read latch signal to be turned on or turned off;

a read bit latch coupled to the correction switch for latching the read data;

A correction circuit coupled to the read bit latch and receiving the error decoding signal for correcting the bits stored in the read bit latch according to the error decoding signal; and

the first output circuit is coupled with the correction circuit and the read bit latch and is controlled by an output enabling signal to output the bit stored in the read bit latch as the data output signal.

2. The memory device according to claim 1, wherein when the data after correction is to be written to the memory cell array, an enable time of a selection signal for selecting a memory cell is referred to as a correction write time, and when the data of the error bit is not found to be written to the memory cell array, the enable time of the selection signal is referred to as a normal write time, wherein the correction write time is longer than the normal write time.

3. The memory device of claim 1, wherein the data read circuit comprises:

the input end of the read switch receives the data from the memory cell array and is controlled by a read enabling signal to be turned on or turned off;

The precharge circuit is coupled with the input end of the reading switch and is controlled by a precharge signal to execute precharge action on the input end of the reading switch; and

the input end of the amplifying circuit is coupled with the output end of the reading switch, is controlled by the reading enabling signal to generate the reading data, and generates the corresponding reading bit signal.

4. The memory device of claim 3, wherein,

the read switch includes:

a first transmission gate and a second transmission gate, wherein the first transmission gate is coupled to a bit line to receive a data signal, the second transmission gate is coupled to a complementary bit line to receive an inverted data signal, and the first transmission gate and the second transmission gate are both controlled by the read enable signal, wherein the data is a differential signal comprising the data signal and the inverted data signal; and

the input end of the first inverter receives the reading enabling signal, the output end of the first inverter is commonly coupled with one control end of the first transmission gate and the second transmission gate, the input end of the second inverter is coupled with the output end of the first inverter, and the output end of the second inverter is commonly coupled with the other control ends of the first transmission gate and the second transmission gate;

The precharge circuit includes:

a third inverter receiving the precharge signal;

a first P-type transistor having a first end coupled to a power voltage, a control end coupled to an output end of the third inverter, and a second end coupled to the bit line;

a second P-type transistor having a first terminal coupled to the power voltage, a control terminal coupled to the output terminal of the third inverter, and a second terminal coupled to the complementary bit line; and

a third P-type transistor coupled between the second end of the first P-type transistor and the second end of the second P-type transistor, and having a control end coupled to the output end of the third inverter; and

the amplifying circuit includes:

an amplifier coupled to the read switch to receive the data signal and the inverted data signal and to output a read data signal and an inverted read data signal, respectively, wherein the read data signal is a differential signal comprising the read data signal and the inverted read data signal; and

and a fourth inverter receiving the inverted read data signal to output the read bit signal.

5. The memory device of claim 1, wherein,

the correction switch includes:

A third transfer gate and a fourth transfer gate, wherein the third transfer gate receives a read data signal from the data read circuit, the fourth transfer gate receives an inverted read data signal from the data read circuit, and both the third transfer gate and the fourth transfer gate are controlled by the read latch signal, wherein the read data is a differential signal comprising the read data signal and the inverted read data signal; and

the input end of the fifth inverter receives the reading latch signal, and the output end of the fifth inverter is commonly coupled with one control end of the third transmission gate and the fourth transmission gate; and

the read bit latch includes:

a sixth inverter and a seventh inverter, wherein an input terminal of the sixth inverter is coupled to an output terminal of the seventh inverter and receives the read data signal through the third transmission gate, and an input terminal of the seventh inverter is coupled to an output terminal of the sixth inverter and receives the inverted read data signal through the fourth transmission gate.

6. The memory device of claim 5, wherein the correction circuit comprises:

an eighth inverter receiving the error decoding signal;

A ninth inverter coupled to an output terminal of the sixth inverter to output the correction bit signal;

a fourth P-type transistor and a fifth P-type transistor, wherein a first terminal of the fourth P-type transistor is coupled to a power supply voltage, a second terminal of the fourth P-type transistor is coupled to a first terminal of the fifth P-type transistor, a control terminal of the fourth P-type transistor is coupled to an output terminal of the eighth inverter, and a second terminal of the fifth P-type transistor is coupled to an input terminal of the sixth inverter, and a control terminal of the fifth P-type transistor receives the read data signal; and

a sixth P-type transistor and a seventh P-type transistor, wherein a first terminal of the sixth P-type transistor is coupled to the power voltage, a second terminal of the sixth P-type transistor is coupled to the first terminal of the seventh P-type transistor, a control terminal of the seventh P-type transistor is coupled to the output terminal of the eighth inverter, and a second terminal of the seventh P-type transistor is coupled to the output terminal of the sixth inverter, and a control terminal of the seventh P-type transistor receives the inverted read data signal.

7. The memory device of claim 6, wherein the first output circuit comprises:

a tenth inverter having an input coupled to the output enable signal;

a first inverse AND gate, a first input end of which is coupled with the second end of the fifth P-type transistor, and a second input end of which receives the output enabling signal;

A first inverse OR gate, a first input end of which is coupled with the second end of the fifth P-type transistor, and a second input end of which is coupled with the output end of the tenth inverter;

an eighth P-type transistor having a first terminal coupled to the power voltage and a control terminal coupled to the output terminal of the first nand gate; and

the first N-type transistor has a first end coupled to the second end of the eighth P-type transistor and provides the corrected data output signal, a control end coupled to the output end of the first OR gate, and a second end coupled to a ground voltage.

8. The memory device of claim 1, wherein the data write circuit comprises:

an eleventh inverter whose input terminal receives the corresponding data output signal;

the input end of the first write-in switch is coupled with the output end of the eleventh inverter and is controlled by a first write-in latch signal to be turned on or turned off;

the input end of the second write-in switch receives the corresponding correction bit signal and is controlled by a second write-in latch signal to be turned on or turned off;

a write bit latch coupled to the output of the first write switch and the output of the second write switch; and

And the second output circuit is coupled with the output end of the second write switch and the write bit latch, is controlled by a write enabling signal and writes the data output signal or the correction bit signal into the memory cell array.

9. The memory device of claim 8, wherein,

the first write-in switch is a fifth transmission gate, and the second write-in switch is a sixth transmission gate; and

the write bit latch includes:

a twelfth inverter and a thirteenth inverter, wherein an input terminal of the twelfth inverter is coupled to an output terminal of the thirteenth inverter, an input terminal of the thirteenth inverter is coupled to an output terminal of the twelfth inverter, and an input terminal of the twelfth inverter is commonly coupled to the output terminals of the fifth transmission gate and the sixth transmission gate.

10. The memory device of claim 9, wherein the second output circuit comprises:

a fourteenth inverter and a fifteenth inverter, the fourteenth inverter being connected in series with the fifteenth inverter, and the fourteenth inverter receiving the write enable signal;

a second inverse AND gate, the first input end of which is coupled with the output end of the twelfth inverter, and the second input end of which is coupled with the output end of the fifteenth inverter;

A second inverse OR gate, the first input end of which is coupled with the output end of the twelfth inverter, and the second input end of which is coupled with the output end of the fourteenth inverter;

a ninth P-type transistor having a first terminal coupled to a power voltage and a control terminal coupled to an output terminal of the second nand gate;

a second N-type transistor having a first terminal coupled to the second terminal of the ninth P-type transistor and providing a corresponding data signal, a control terminal coupled to the output terminal of the second nor gate, and a second terminal coupled to the ground voltage;

a third inverse AND gate, the first input end of which is coupled with the output end of the thirteenth inverter, and the second input end of which is coupled with the output end of the fifteenth inverter;

a third or gate having a first input coupled to the output of the thirteenth inverter and a second input coupled to the output of the fourteenth inverter;

a tenth P-type transistor having a first terminal coupled to the power voltage and a control terminal coupled to the output terminal of the third inverting AND gate; and

and a third N-type transistor, a first end of which is coupled with a second end of the tenth P-type transistor and provides a corresponding inverted data signal, a control end of which is coupled with an output end of the third inverse OR gate, and a second end of which is coupled with the grounding voltage, wherein the data is a differential signal comprising the data signal and the inverted data signal.

11. The memory device according to claim 10, wherein the data writing circuit further includes a control signal generating circuit that generates the first write latch signal and the second write latch signal based on an initial write latch signal and a write mask signal, comprising:

a sixteenth inverter, a seventeenth inverter and an eighteenth inverter, wherein the sixteenth inverter is connected in series with the seventeenth inverter, the input end of the sixteenth inverter receives the initial writing latch signal, the seventeenth inverter outputs a verification writing latch signal to the correction data read-write circuit, and the eighteenth inverter receives the initial writing latch signal to output an inverse verification writing latch signal to the correction data read-write circuit; and

a signal generating circuit comprising:

a nineteenth inverter whose output receives the corresponding write mask signal;

a fourth nand gate, a first input terminal of which receives the initial write latch signal, a second input terminal of which is coupled to an output terminal of the nineteenth inverter, and an output terminal of which outputs an inverted signal of the corresponding first write latch signal;

A twentieth inverter having an input coupled to the output of the fourth nand gate for outputting the corresponding first write latch signal;

a fifth inverse AND gate, wherein a first input end of the fifth inverse AND gate receives the initial writing latch signal, a second input end of the fifth inverse AND gate receives the corresponding writing mask signal, and an output end of the fifth inverse AND gate outputs an inverse signal of the corresponding second writing latch signal; and

and a twenty-first inverter having an input coupled to the output of the fifth nand gate for outputting the corresponding second write latch signal.

12. The memory device of claim 1, wherein the syndrome operation circuit comprises:

a syndrome generating circuit coupled to the data read/write circuit and the correction data read/write circuit, selectively receiving an output signal of the data read circuit or the data correction circuit according to a read operation or a write operation to generate the correction data write signal, and comparing the correction data write signal with the corresponding correction data to generate a syndrome signal; and

and the syndrome decoding circuit is coupled with the syndrome generating circuit and decodes the syndrome signal to generate the error decoding signal.

13. The memory device according to claim 12, wherein the syndrome generating circuit generates the correction data write signal according to the read bit signal when the data read/write circuit performs the read operation, and wherein the syndrome generating circuit generates the correction data write signal according to the correction bit signal or the data output signal when the data read/write circuit performs the write operation.

14. The memory device according to claim 12, wherein the correction data read-write circuit reads the correction data to output a correction read signal to the syndrome generating circuit, and wherein the syndrome generating circuit includes:

an internal operation circuit including a plurality of transmission gates and a plurality of first exclusive OR gates, wherein the plurality of transmission gates are controlled to selectively provide the data output signal, the correction bit signal or the read bit data to the plurality of first exclusive OR gates so as to output the correction data write signal; and

and a plurality of second exclusive OR gates for receiving the correction data write signal from the internal operation circuit and the corresponding correction read signal from the correction data read/write circuit to output the syndrome signal.

15. The memory device according to claim 1, wherein the correction data read-write circuit includes:

the correction data reading circuit is coupled with the correction data storage unit array and the syndrome operation circuit and is used for reading the correction data from the correction data storage unit array to output a correction reading signal to the syndrome operation circuit; and

and the correction data writing circuit is coupled with the correction data storage unit array and the syndrome operation circuit and is used for writing the corrected correction data into the correction data storage unit array.