JP6907265B2 - Memory device - Google Patents

Description

The present invention relates to a memory device, and more particularly to a memory device having an error inspection and error correction function.

With advances in science and technology, consumers are also rapidly increasing their demand for storage media, of which dynamic random access memory (Dynamic Random Access Memory, DRAM) has a simple structure, high density, and so on. It has the advantage of low cost and is therefore widely applied in various electronic devices. In order to improve the data reliability of the DRAM, some DRAMs include an ECC memory (Error-correcting code memory, ECC memory) to detect an error bit in the stored data and correct the error bit. Currently, DRAM mainly employs single error correction (Single Error Correcting) technology, but the single error correction technology can correct only one bit of an error at a time. If the stored data has an error of 2 bits or more at the same time, the error correction function of the ECC circuit is invalidated. However, during DRAM operation, a soft error may occur due to factors such as high temperature and refresh, and an error bit may be generated. If the error bits cannot be corrected in a timely manner, two error bits may be accumulated in the stored data to reduce the reliability of the data in the memory. Therefore, how to correct the stored data in a timely manner, avoid accumulating two or more error bits, and maintain the accuracy of the DRAM data is one issue to be overcome. ..

The present invention provides a memory device capable of immediately correcting error bits and updating stored data and parity data for error inspection correction in a data read cycle.

The memory device of the present invention includes a data read / write circuit, a parity data read / write circuit, and a syndrome arithmetic circuit. The data read / write circuit is coupled to the memory cell array and is used to access the data in the memory cell array. The parity data read / write circuit is coupled to the parity data memory cell array and is used to access the parity data of the parity data memory cell array. The syndrome arithmetic circuit generates an error decode signal based on the data received from the data read / write circuit and the parity data received from the parity data read / write circuit, and in the same read cycle as reading the data, the data read / write circuit is , Corrects the error bits in the data based on the error decode signal, outputs the correct data and the corrected bit signal, the data read / write circuit writes the corrected data back to the memory cell array, and the syndrome arithmetic circuit further The parity data write signal is output to the parity data read / write circuit based on the correction bit signal, and the parity data in the parity data memory cell array is updated.

Based on the above, the memory device of the present invention can read data from the memory cell array in one read cycle to complete inspection and correction. When it detects that there is one error bit in the data, the memory device of the present invention immediately corrects the error in the same one read cycle, outputs the correct data, and correspondingly corrects it in one consecutive cycle. Later data can be written back to the memory cell array and updated parity data can be written back to the parity data memory cell array. Thereby, the memory device of the present invention can improve the reliability of data.

It is a block diagram of the memory device according to one Example of this invention. It is a circuit block diagram of the data read / write circuit according to one Example of this invention. It is a circuit explanatory drawing of the data read circuit according to one Example of this invention. It is a waveform explanatory drawing of the read operation of the memory apparatus by one Example of this invention. It is a circuit explanatory drawing of the data correction circuit according to one Example of this invention. It is a circuit explanatory drawing of the data light circuit according to one Example of this invention. It is a circuit explanatory drawing of the control signal generation circuit of the data light circuit by one Embodiment of this invention. It is a waveform explanatory diagram of the write operation when the error bit of the memory device by one Embodiment of this invention is not found. It is a waveform explanatory drawing of the write operation at the time of correcting the error bit of the memory apparatus by one Embodiment of this invention. It is a circuit explanatory drawing of the syndrome generation circuit by one Example of this invention. It is a circuit explanatory drawing of the internal arithmetic circuit of the syndrome generation circuit by one Example of this invention. It is a circuit explanatory drawing of the syndrome control signal generation circuit of the syndrome generation circuit by one Embodiment of this invention. It is a circuit explanatory drawing of the parity data read / write circuit according to one Example of this invention. It is a circuit explanatory drawing of the parity data write circuit according to one Example of this invention.

In order to make the above-mentioned features and advantages of the present invention easy to understand, examples will be given and the details will be described below together with the drawings.

FIG. 1 is a block diagram of a memory device according to an embodiment of the present invention. With reference to FIG. 1, the memory device 100 includes a memory cell array 110, a parity data memory cell array 120, a data read / write circuit 130, a parity data read / write circuit 140, and a syndrome calculation circuit 170. The syndrome calculation circuit 170 includes a syndrome generation circuit 150 and a syndrome decoding circuit 160. The data read / write circuit 130 is coupled to the memory cell array 110 and accesses the data MD of the memory cell array 110. The parity data read / write circuit 140 is coupled to the parity data memory cell array 120 to access the parity data PM of the parity data memory cell array 120. The parity data PM is an error inspection and correction code used for inspecting and correcting the data MD, and is generated by executing an ECC decoding program such as a Hamming code for the data MD, for example. Will be done. The number of bits of the parity data PM is determined by the number of bits of the data MD. In the present embodiment, the size of the data MD is 64 bits as an example, and the size of the parity data PM is set to 7 bits correspondingly, but the present invention limits the sizes of the data MD and the parity data PM. It's not something to do.

The syndrome calculation circuit 170 is a data MD received from the data read / write circuit 130 (the data read / write circuit 130 outputs a read bit signal RD after reading the data MD) and a parity data PM (parity) received from the parity data read / write circuit 140. The data read / write circuit 140 outputs the parity read signal PS after reading the parity data PM) to generate an error decode signal SD, and in the same one read cycle of the read data MD, the data read / write circuit 130 performs error decoding. The error bit in the data MD is corrected based on the signal SD, and the correct data (that is, the data output signal RWB) and the corrected bit signal CS are output. The data read / write circuit 130 writes the corrected data back to the memory cell array 110, and the syndrome arithmetic circuit 170 further outputs the parity data write signal NS to the parity data read / write circuit 140 based on the correction bit signal CS, and the parity data memory cell array. The parity data PM in 120 is updated.

In other words, in this embodiment, after reading the data MD and the parity data PM, whether or not there is an error bit in the data MD is determined by the syndrome encoding (Syndrome encoding) and the syndrome decoding (Syndrome decoding) of the syndrome arithmetic circuit 170. Can be inspected. If there is an error bit, the data read / write circuit 130 can immediately correct the error bit based on the error decode signal SD and output the correct data output signal RWB in the same one read cycle, and can output the corrected bit signal CS. It is also possible to output the signal in conjunction with the syndrome calculation circuit 170 and have the parity data read / write circuit 140 update the parity data PM. In particular, between reading the data MD and outputting the correct data output signal RWB, the memory device 100 does not need to reselect the memory cell of the memory cell array 110, and can complete the above operation in the same one read cycle. Further, the parity data PM can be updated.
Hereinafter, the circuit structure and the implementation method of this embodiment will be further described.

FIG. 2 is a circuit block diagram of a data read / write circuit according to an embodiment of the present invention. With reference to FIG. 2, the data read / write circuit 130 includes a data read circuit 210, a data correction circuit 220, and a data write circuit 230. The data read circuit 210 is coupled to the memory cell array 110 to read the data MD from the memory cell array 110 to generate the read data AD and the corresponding read bit signal RD. The data correction circuit 220 is coupled to the data read circuit 210 and the syndrome decoding circuit 160 of the syndrome arithmetic circuit 170 to latch the read data AD during the read cycle, and the error bit of the read data AD based on the error decoding signal SD. Is used to generate the correct data output signal RWB and correction bit signal CS, where the data output signal RWB is the output result after the data read / write circuit 130 reads and corrects the data MD. The data write circuit 230 is coupled to the data correction circuit 220 and the memory cell array 110, and is used to replace the data output signal RWB corresponding to the error bit using the correction bit signal CS and write the correct data MD back to the memory cell array 110. Be done.

With reference to FIG. 1 again, the syndrome arithmetic circuit 170 includes a syndrome generation circuit 150 and a syndrome decoding circuit 160. The syndrome generation circuit 150 is coupled to the data read / write circuit 130 and the parity data read / write circuit 140, and selectively receives the output signal of the data read circuit 210 or the data correction circuit 220 based on the read operation or the write operation to receive the parity data write. Generate signal NS. More specifically, when the data read / write circuit 130 executes the read operation, the syndrome generation circuit 150 generates the parity data write signal NS based on the read bit signal RD, and the data read / write circuit 130 executes the write operation. At this time, the syndrome generation circuit 150 generates a parity data write signal NS based on the correction bit signal CS or the data output signal RWB.

The syndrome generation circuit 150 compares the parity data write signal NS and the corresponding parity data PM (the parity data read / write circuit 140 reads the parity data PM and provides the parity read signal PS to the syndrome generation circuit 150), and the syndrome signal. Generate SY. The syndrome decoding circuit 160 is coupled to the syndrome generating circuit 150 to decode the syndrome signal SY and generate an error decoding signal SD. The data read / write circuit 130 corrects the error bits in the data MD based on the error decoding signal SD.
Next, a specific implementation method of the data read / write circuit 130 will be described.

FIG. 3A is a circuit explanatory diagram of a data read circuit according to an embodiment of the present invention, and FIG. 3B is a waveform explanatory diagram of a read operation of a memory device according to an embodiment of the present invention. FIG. 4 is a circuit explanatory diagram of a data correction circuit according to an embodiment of the present invention, FIG. 5A is a circuit explanatory diagram of a data light circuit according to an embodiment of the present invention, and FIG. 5B is an explanatory diagram of a data light circuit according to an embodiment of the present invention. It is a circuit explanatory drawing of the control signal generation circuit of the data light circuit by an Example. The details of the implementation of the data read / write circuit 130 will be specifically described with reference to FIGS. 3A to 5B together with FIGS. 1 and 2.

In FIG. 3A, the data read circuit 210 includes a reed switch 310, a precharge circuit 320, and an amplifier circuit 330. The input end of the reed switch 310 receives the data MD from the memory cell array 110 and is controlled to be turned on or off by the read enable signal DE. The precharge circuit 320 is coupled to the input end of the reed switch 310 and is controlled by the precharge signal PB to execute a precharge operation on the input end of the reed switch 310. The input end of the amplifier circuit 330 is coupled to the output end of the reed switch 310 and is controlled by the read enable signal DE to generate read data AD and generate the corresponding read bit signal RD.

Specifically, since the sense amplifier in the memory cell array 110 outputs the data MD stored in the memory cell by the differential signal (Differential Signal) method, the data MD is the difference between the data signal MDiT and the reverse phase data signal MDiN. The data MD includes a dynamic signal, of which 64 bits are taken as an example, and in the present specification, MDi represents one bit of the data MD, and i is an integer of 0 to 63 (i = 0, 1, 2, ..., 63), for example, MD0, MD1, ..., MD63. Similarly, the read data AD is also a differential signal including the read data signal ADiT and the reverse phase read data signal ADiN. In the present specification, i refers to the corresponding bit, for example, the read bit signal RDi, the data output signal RWBi, and the correction bit signal CSi correspond to the corresponding bits in the read bit signal RD, the data output signal RWB, and the correction bit signal CS. It represents a bit and is inferred by this.

In the read switch 310, the transmission gate TG1 is coupled to the bit line BL to receive the data signal MDiT, the transmission gate TG2 is coupled to the complementary bit line BLN to receive the reversed-phase data signal MDiN, and the transmission gate TG1 and The transmission gate TG2 is controlled by the read enable signal DE. The input end of the inverter INV1 in FIG. 3A receives the read enable signal DE, and its output end is commonly coupled to one control end of the transmission gate TG1 and one control end of the transmission gate TG2 (eg,). The control end of the N-type transistor of the transmission gate TG1 and the transmission gate TG2). The input end of the inverter INV2 is coupled to the output end of the inverter INV1, and the output ends are within the other control end of the transmission gate TG1 and the other control end of the transmission gate TG2 (eg, in the transmission gate TG1 and the transmission gate TG2). It is commonly coupled to the control end of the P-type transistor).

In the precharge circuit 320, the inverter INV3 receives the precharge signal PB. The first end of the P-type transistor TP1 is coupled to the power supply voltage VDD, its control end is coupled to the output end of the inverter INV3, and its second end is coupled to the bit line BL. The first end of the P-type transistor TP2 is coupled to the power supply voltage VDD, its control end is coupled to the output end of the inverter INV3, and its second end is coupled to the complementary bit line BLN. The P-type transistor TP3 is coupled between the second end of the P-type transistor TP1 and the second end of the P-type transistor TP2, and its control end is coupled to the output end of the inverter INV3.

In the amplifier circuit 330, the amplifier 332 is coupled to the reed switch 310 to receive the data signal MDiT and the negative phase data signal MDiN, and correspondingly outputs the read data signal ADiT and the negative phase read data signal ADiN. The inverter INV4 receives the reverse phase read data signal ADiN and outputs the read bit signal RDi.

In this embodiment, the amplifier 332 is a P-type transistor T31, T32 and an N-type transistor T33 to T35. The P-type transistor T31 and the N-type transistor T33 are coupled in series between the voltage power supply VDD and the first end of the N-type transistor T35, and the P-type transistor T32 and the N-type transistor T34 are similarly supplied with the power supply voltages VDD and N-type. It is coupled in series between the first ends of the transistor T33, and the control ends of the P-type transistor T31 and the N-type transistor T33 are commonly coupled to the first end of the N-type transistor T34, and the P-type transistor T32 and the N-type transistor are coupled. The control end of the T34 is commonly coupled to the first end of the N-type transistor T33. The second end of the N-type transistor T35 is coupled to the ground voltage GND, and its control end is coupled to the read enable signal DE.

In FIG. 3B, prior to the lead operation, the precharge signal PB turns on the reed switch 310 to perform a precharge operation on the bit line BL and the complementary bit line BLN. When the lead operation is started, the precharge signal PB turns off the reed switch 310 and ends the precharge operation. At the same time, the selection signal CSL for selecting the memory cell of the memory cell array 110 changes from the low logic level (Low) to the high logic level (High), and reads the data MD of the selected memory cell. Next, the read enable signal DE is switched to a high logic level (High), the read switch 310 is turned on, the amplifier 332 is activated to amplify the data signal MDiT and the reverse phase data signal MDiN, and the read data signal ADiT, reverse. The phase read data signal ADiN and the read bit signal RDi are output. The low voltage VSS of FIG. 3B uses the ground voltage GND as an example here.

With reference to FIG. 4, the data correction circuit 220 includes a correction switch 410, a read bit latch 420, a correction circuit 430 and an output circuit 440. The input end of the correction switch 410 receives read data ADi from the data read circuit 210 and is controlled on or off by the read latch signal LAR. The read bit latch 420 is coupled to the correction switch 410 and is used to latch the read data ADi. The correction circuit 430 is coupled to the read bit latch 420, receives the corresponding error decode signal SDI, and is used to correct the bits stored in the read bit latch 420 based on the error decode signal SDI. The output circuit 440 is coupled to the correction circuit 430 and the read bit latch 420, and outputs the bit stored in the read bit latch 420 as the data output signal RWBi, which is controlled by the output enable signal OE.

In the correction switch 410 of FIG. 4, the transmission gate TG3 receives the read data signal ADiT from the data read circuit 210, the transmission gate TG4 receives the reverse phase read data signal ADiN from the data read circuit 210, and the transmission gate TG3 and The transmission gate TG4 is controlled by the read latch signal LAR. The inverter INV5 input end receives the read latch signal LAR, and its output end is commonly coupled to one of the control ends of the transmission gate TG3 and one of the control ends of the transmission gate TG4 to transmit the read latch signal LAR reverse phase signal. offer.

The read bit latch 420 includes an inverter INV6 and an inverter INV7. The input end of the inverter INV6 is coupled to the output end of the inverter INV7, and receives the read data signal ADiT via the transmission gate TG3. The input end of the inverter INV7 is coupled to the output end of the inverter INV6, and receives the reverse phase read data signal ADiN via the transmission gate TG4.

In the correction circuit 430, the inverter INV8 receives the error decoding signal SDi, and the inverter INV9 is coupled to the output end of the inverter INV6 to output the correction bit signal CSi. The first end of the P-type transistor TP4 is coupled to the power supply voltage VDD, the second end thereof is coupled to the first end of the P-type transistor TP5, and the control end thereof is coupled to the output end of the inverter INV8. The second end of the P-type transistor TP5 is coupled to the input end of the inverter INV6, and its control end receives the read data signal ADiT. The first end of the P-type transistor TP6 is similarly coupled to the power supply voltage VDD, the second end is coupled to the first end of the P-type transistor TP7, and its control end is coupled to the output end of the inverter INV8. .. The second end of the P-type transistor TP7 is coupled to the output end of the inverter INV6, and the control end receives the reverse phase read data signal ADiN.

In the output circuit 440, the input end of the inverter INV10 is coupled to the output enable signal OE. The first input end of the NAND gate NAND1 is coupled to the second end of the P-type transistor TP5, and the second input end receives the output enable signal OE. The first input end of the NOR gate NOR1 is coupled to the second end of the P-type transistor TP5, and the second input end is coupled to the output end of the inverter INV10. The first end of the P-type transistor TP8 is coupled to the power supply voltage VDD, its control end is coupled to the output end of the NAND gate NAND1, and the first end of the N-type transistor TN1 is the second end of the P-type transistor TP8. Provides a corrected data output signal RWBi, the control end of which is coupled to the output end of the NOR gate NOR1, and the second end of which is coupled to the ground voltage NAND. The output circuit 440 can further include a latch 442 coupled to the first end of the N-type transistor TN1. The circuit structure of the latch 442 is the same as that of the lead bit latch 420, and the two inverter INVs are formed by coupling with each other.

With reference to FIG. 3B again, when the read latch signal LAR switches to a high logic level, the read bit latch 420 receives the read data ADi, latches its bit value, and corresponds to the forward latch bit signal EiT and the reverse latch bit. Generate the signal EiN. In FIG. 3B, during the high logic level period of the read latch signal LAR, the forward latch bit signal EiT changes to the low logic level and the reverse latch bit signal EiN changes to the high logic level. After the read latch signal LAR is switched to the low logic level, if the i-th bit of the data MD is the error bit, the error decoding signal SDi from the syndrome decoding circuit 160 is switched to the high logic level. In the same read cycle, the correction circuit 430 inverts the bit value of the error latched by the read bit latch 420 based on the error decode signal SDi, so that the forward latch bit signal EiT and the reverse latch bit signal EiN are inverted. And correct the error. Finally, the output circuit 440 outputs the correct data output signal RWBi based on the output enable signal OE.

With reference to FIG. 5A, the data write circuit 230 includes an inverter INV11, a light switch 510, a light switch 520, a write bit latch 530 and an output circuit 540. The input end of the inverter INV11 receives the corresponding data output signal RWBi. The input end of the light switch 510 is coupled to the output end of the inverter INV11 and is controlled on or off by the first light latch signal LAWm. The input end of the light switch 520 receives the corresponding correction bit signal CSi and is controlled on or off by the second light latch signal LDWm. Here, m is an integer from 0 to 7 and indicates the corresponding mask bit. The light bit latch 530 is coupled to the output end of the light switch 510 and the output end of the light switch 520, and the output circuit 540 is coupled to the output end of the light switch 520 and the output end of the light bit latch 530. The output circuit 540 is controlled by the write enable signal WE, and writes the data output signal RWBi or the correction bit signal CSi to the memory cell array 110.

Here, the data signal MDiT and the reverse phase data signal MDiN output by the output circuit 540 are sent back to the bit line and the complementary bit line of the memory cell array 110, respectively, in order to newly write the data MDi.

In FIG. 5A, the light switch 510 is implemented by the transmission gate TG5 system, and the light switch 520 is implemented by the transmission gate TG6 system. The two control ends of the transmission gate TG5 receive the opposite phase signal (abbreviated as the reverse phase first light latch signal) LAWmB of the corresponding first light latch signal LAWm and the first light latch signal LAWm, respectively, and the transmission gate TG6 The two control ends receive the opposite phase signal (abbreviated as the reverse phase second light latch signal) LDWmB of the second light latch signal LDWm and the second light latch signal LDWm, respectively.

The write bit latch 530 includes an inverter INV12 and an inverter INV13. The input end of the inverter INV12 is coupled to the output end of the inverter INV13, the input end of the inverter INV13 is coupled to the output end of the inverter INV12, and the input end of the inverter INV12 is connected to the output ends of the transmission gate TG5 and the transmission gate TG6. Commonly combined.

In the output circuit 540, the inverter INV14 is coupled in series with the inverter INV15, and the inverter INV14 is received by the write enable signal WE. The first input end of the NAND gate NAND2 is coupled to the output end of the inverter INV12, the second input end is coupled to the output end of the inverter INV15, and the first input end of the NOR gate NOR2 is coupled to the output end of the inverter INV12. Then, the second input end is coupled to the output end of the inverter INV14. The first end of the P-type transistor TP9 is coupled to the power supply voltage VDD, the control end is coupled to the output end of the NAND gate NAND2, and the first end of the N-type transistor TN2 is coupled to the second end of the P-type transistor TP9. The corresponding data signal MDiT is provided, the control end is coupled to the output end of the NOR gate NOR2, and the second end is coupled to the ground voltage NAND. The first input end of the NAND gate NAND3 is coupled to the output end of the inverter INV13, and the second input end is coupled to the output end of the inverter INV15. The first input end of the NOR gate NOR3 is coupled to the output end of the inverter INV13, and the second input end is coupled to the output end of the inverter INV14. The first end of the P-type transistor TP10 is coupled to the power supply voltage VDD, the control end is coupled to the output end of the NAND gate NAND3, and the first end of the N-type transistor TN3 is coupled to the second end of the P-type transistor TP10. The corresponding reversed-phase data signal MDiN is provided, the control end is coupled to the output end of the NOR gate NOR3, the second end of which is coupled to the ground voltage NAND.

With reference to FIG. 5B, the data write circuit 230 further includes a control signal generation circuit 550, which includes a first light latch signal LAWm and a second light latch signal LAWm based on the initial light latch signal LAW and the light mask signal DM. Generates a light latch signal LDWm. In this embodiment, since the light mask signal DM is an 8-bit signal, the light mask signal DMm represents the signal corresponding to the m-th bit, and m is an integer of 0 to 7.

The control signal generation circuit 550 provides the parity write latch signal LAWPT and the reverse phase parity write latch signal LAWPB to the parity data read / write circuit 140, and corresponds to the first write latch signal LAWm and the second write latch signal LDWm, and their reverse phases. The signal is provided to the data light circuit 230.

The control signal generation circuit 550 includes an inverter INV16, an inverter INV17, an inverter INV18, and a signal production circuit 610. The inverter INV16 and the inverter INV17 are coupled in series, the input end of the inverter INV16 receives the initial write latch signal LAW, and the inverter INV17 output outputs the parity write latch signal LAWPT to the parity data read / write circuit 140, and the inverter INV18 Receives the initial write latch signal LAW and outputs the reverse phase parity write latch signal LAWPB.

As a supplementary explanation, when the read operation is executed, the write enable signal WE and the initial write latch signal LAW are maintained at the low logic level.

In the signal production circuit 610 of FIG. 5B, the output end of the inverter INV19 receives the corresponding light mask signal DMm. The first input end of the NAND gate NAND4 receives the initial write latch signal LAW, its second input end is coupled to the output end of the inverter INV19, and its output end is the corresponding reversed phase first write latch signal LAWmb. Is output. The input end of the inverter INV20 is coupled to the output end of the NAND gate NAND4, and the output end outputs the corresponding first write latch signal LAWm. The first input end of the NAND gate NAND5 receives the initial write latch signal LAW, the second input end receives the corresponding light mask signal DMm, and its output end is the corresponding reverse phase second write latch signal LDWmb. Is output. The input end of the inverter INV21 is coupled to the output end of the NAND gate NAND5, and the output end outputs the corresponding second write latch signal LDWm.

FIG. 6A is an explanatory diagram of the waveform of the write operation when the error bit of the memory device according to the embodiment of the present invention is not found, and FIG. 6B is a correction of the error bit of the memory device according to the embodiment of the present invention. It is a waveform explanatory diagram of the light operation in the case of. See FIGS. 6A and 6B with the above examples.

In FIG. 6A, when the memory device 100 writes the data MD and the bits to be written do not need to be corrected, the enable time for selecting the selection signal CSL of the memory cell (for example, the time for maintaining the high logic level) is normally written. Called time. In the normal write time, the correction bit signal CS and the write mask signal DM continue to maintain the low logic level, the write switch 510 is turned on, the write switch 520 is turned off, and the data write circuit 230 is the data output signal RWBi. Is selectively written to the memory cell array 110.

In FIG. 6B, when the memory device 100 finds an error bit in the data MD and the data write circuit 230 writes back the correct data, the enable time of the selection signal CSL is referred to as a correction write time. After the read latch signal LAR is switched to the low logic level in the correction writing time, the logic level of the error decoding signal SDi corresponding to the error bit position becomes high level, and the correction bit signal output by the data correction circuit 220 correspondingly becomes high. CSi also switches to a high logic level. As a supplementary explanation, the syndrome generation circuit 150 also outputs the parity data write signal NS to the parity data read / write circuit 140 to update the parity data PM.

Next, the data write circuit 230 performs a ride operation, the corresponding first light latch signal LAWm turns off the light switch 510, the corresponding second light latch signal LDWm turns on the light switch 520, and the correction bit signal CSi. The data output signal RWBi is replaced and input to the output circuit 540, and the correct bit value is written at the enable time of the write enable signal WE.

In other words, when the bit to be written is originally correct, the data write circuit 230 writes the data output signal RWBi to the memory cell array 110, and when the bit to be written is an error bit, the data write circuit 230 writes the correction bit signal CSi. Write to memory cell array 110.

In particular, in this embodiment, the enable time of the selection signal CSL can be changed, and the correction write time becomes longer than the normal write time. When the memory device 100 finds an error bit, by extending the enable time of the selection signal CSL, the data write circuit 130 and the parity data read / write circuit 140 transfer the correct data to the memory cell array 110 in the same one cycle of correction. It can be written back and the parity data PM can be updated. That is, the selection signal CSL can complete the inspection correction and update operations only by enabling it once.
Next, the details of the circuit structure of the syndrome generation circuit 150 will be described.

FIG. 7A is a circuit explanatory diagram of a syndrome generating circuit according to an embodiment of the present invention, FIG. 7B is a circuit explanatory diagram of an internal arithmetic circuit of a syndrome generating circuit according to an embodiment of the present invention, and FIG. 7C is a circuit explanatory diagram. It is a circuit explanatory drawing of the syndrome control signal generation circuit of the syndrome generation circuit by one Embodiment of this invention.

First, referring to FIG. 7A, the syndrome generation circuit 150 includes an internal arithmetic circuit 710 and a plurality of XOR gates XOR2, and the internal operation circuit 710 includes a plurality of transmission gates TG (transmission gates TG7 to TG9 in FIG. 7B) and a plurality of transmission gates TG9. Includes a first XOR gate XOR1.

In FIG. 7B, the internal arithmetic circuit 710 controls a plurality of transmission gates TGs to selectively provide a data output signal RWB, a correction bit signal CS, or a read bit signal RD to the plurality of XOR gates XOR1, and provides a parity data write signal. Output NS. Specifically, the internal arithmetic circuit 710 has a plurality of input circuits 720. In addition to receiving the corresponding data output signal RWBi, each input circuit 720 further receives the corresponding read bit signal RDi from the data read circuit 210 and the corresponding correction bit signal CSi from the data correction circuit 220. Can be done. The internal arithmetic circuit 710 controls a plurality of transmission gates TG7 to TG9 in the input circuit 720 to convert one of the read bit signal RD, the data output signal RWB, and the correction bit signal CS into the corresponding XOR gate XOR1. Enter selectively.

Specifically, the transmission gate TG7 receives the corresponding read bit signal RDi and is controlled by the reverse phase signal WEDB of the write data control signal WED and the write data control signal WED, and the transmission gate TG8 receives the data output signal RWBi. Received and controlled by the reverse phase signal WEm of the write data selection signal WEm and the write data selection signal WEm, the transmission gate TG9 receives the correction bit signal CSi, and the reverse phase of the light mask selection signal DWm and the light mask selection signal DWm. It is controlled by the signal DWmb.

When the memory device 100 performs a read operation, the input circuit 720 selectively receives the read bit signal RDi, turns on the transmission gate TG7, and turns off the transmission gate TG8 and the transmission gate TG9. When the memory device 100 executes the write operation, the input circuit 720 turns off the transmission gate TG7 and turns on the transmission gate TG8 or the transmission gate TG9 based on the write mask signal DM to turn on the data output signal RWBi or the correction bit signal CSi. Is selectively received.

After the calculation of the multi-stage XOR gate XOR1, the internal operating circuit 710 finally outputs the parity data write signal NSj, and since the parity bit of this embodiment is 7 bits, j is an integer of 0 to 6. Yes, the parity data write signal NSj represents a signal corresponding to the jth bit of the parity data write signal NS.

In FIG. 7A, the plurality of XOR gates XOR2 receive the corresponding parity data write signal NSj from the internal arithmetic circuit 710 and the corresponding parity read signal PSj from the parity data read / write circuit 140. The syndrome generation circuit 150 compares the parity read signal PS and the parity data write signal NS and outputs the syndrome signal SY. The syndrome decoding circuit 160 receives the syndrome signal SY and the decoding control signal SDE, executes a decoding operation on the syndrome signal SY, and outputs the error decoding signal SD to the data correction circuit 220 of the data reading / writing circuit 130.

The syndrome generation circuit 150 further includes a syndrome control signal generation circuit 730 used for generating the control signal of the transmission gate TG. Since the circuit structure of the syndrome control signal generation circuit 730 of FIG. 7C is similar to that of the control signal generation circuit 550 of FIG. 5B, the details of the operation of the syndrome control signal generation circuit 730 will not be described again here.

Next, a specific circuit structure of the parity data read / write circuit 140 will be described.
FIG. 8 is a circuit explanatory diagram of a parity data read / write circuit according to an embodiment of the present invention, and FIG. 9 is a circuit explanatory diagram of a parity data write circuit according to an embodiment of the present invention.

First, referring to FIG. 8, the parity data read / write circuit 140 includes a parity data read circuit 810 and a parity data write circuit 820. The parity data read circuit 810 is coupled to the parity data memory cell array 120 and the syndrome calculation circuit 170, reads the parity data PM from the parity data memory cell array 120, and outputs the parity read signal PS to the syndrome generation circuit 150 of the syndrome calculation circuit 170. Used for. The parity data write circuit 820 is coupled to the parity data memory cell array 120 and the syndrome generation circuit 150 of the syndrome calculation circuit 170, and is used to write the corrected parity data PM to the parity data memory cell array 120.

When the memory device 100 executes the read operation, the parity data read circuit 810 can read the parity data PM from the parity data memory cell array 120 and output the parity read signal PS to the syndrome generation circuit 150. The syndrome generation circuit 150 checks whether or not the read bit signal RD has an error bit based on the parity read signal PS. If an error bit is present, the corresponding error decode signal SDi changes the logic level. In this embodiment, if the i-th bit of the data MD is an error, the error decode signal SDi changes to a high logic level, as shown in FIG. 3B.

The details of the circuit of the parity data read circuit 810 can be referred to in FIG. 3A, and those skilled in the art can obtain sufficient proposals, teachings and implementation methods from the data read circuit 210, which will not be described again here.

FIG. 9 shows the circuit details of the parity data write circuit 820, the circuit structure of which is similar to the data write circuit 230 of FIG. 5A, and those skilled in the art will fully propose, teach and implement from the data write circuit 230. A method can be obtained and will not be described again here.

With reference to FIG. 6B, when the syndrome generating circuit 150 detects that the read bit signal RD has an error bit, the data write circuit 230 corrects the read bit signal RD, and the syndrome generating circuit 150 determines the error bit position. A new parity data write signal NS is output based on the correction bit signal CS. The parity data write circuit 820 writes a new parity data write signal NS to the parity data memory cell array 120 and updates the parity data PM. The parity data PM of FIG. 9 includes a differential signal composed of a parity data data signal PMjT and a reverse phase parity data signal PMjN, where j is an integer of 0 to 6 and represents a corresponding parity bit.

Summarizing the above, the memory device of the present invention can read data from the memory cell array and perform inspection in one read cycle, and when it is discovered that there is one error bit in the data, the memory of the present invention. The device can correct the error and output the correct data in the same one read cycle. Further, the memory device of the present invention can further output the correction bit signal to the data write circuit and the syndrome generation circuit at the same time. By extending the enable time of the selection signal, the data write circuit can write the corrected data back to the memory cell array, and the syndrome generation circuit outputs a new parity data write signal to the parity data write circuit. , Parity data can be updated. In this way, the selection signal can complete the correction and update of the data by providing only one enable time for the memory cell to be written, achieving the effect of immediately inspecting and correcting the error.

The present invention discloses examples as described above, but it is not intended to limit the present invention, and those skilled in the art will make some modifications and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention is based on what is defined by the scope of claims described later.

100 Memory device 110 Memory cell array 120 Parity data Memory cell array 130 Data read / write circuit 140 Parity data read / write circuit 150 Syndrome generation circuit 160 Syndrome decode circuit 170 Syndrome arithmetic circuit 210 Data read circuit 220 Data correction circuit 230 Data write circuit 310 Read switch 320 Precharge Circuit 330 Amplification circuit 332 Amplifier 410 Correction switch 420 Read bit latch 430 Correction circuit 440, 540 Output circuit 442 Latch 510, 520 Light switch 530 Light bit latch 550 Control signal generation circuit 610 Signal production circuit 710 Syndrome calculation circuit 720 Input circuit 730 Syndrome Control signal generation circuit 810 Parity data read circuit 820 Parity data write circuit AD, ADi read data ADiT read data signal ADiN reverse phase read data signal BL bit line BLN complementary bit line CS correction bit signal DE read enable signal DM light mask signal DWm write Mask selection signal DWmb Reverse phase write Mask selection signal EiT Positive latch bit signal EiN Reverse latch bit signal GND Ground voltage LAR Read latch signal LAWIN Initial light latch signal LAWm 1st write latch signal LAWmB Reverse phase 1st write latch signal LDWm 2nd write Latch signal LDWmb Reverse phase 2nd write latch signal LAWPT Parity write Latch signal LAWPB Reverse phase parity write latch signal MD data MDiT Data signal MDiN Reverse phase data signal NAND1 to NAND5 NAND gate NOR1 to NOR3 NOR gate NS parity data write signal INV, INV1 ~ INV21 Inverter OE output enable signal PB Precharge signal PM Parity data PS Parity read signal RWB, RWBi data output signal RD, RDi read bit signal SY syndrome signal SD, SDi error decode signal SDE decode control signal TG, TG1 to TG9 transmission gate T31, T32, TP1-TP10 P-type transistor T33, T34, T35, TN1-TN3 N-type transistor VDD voltage power supply VSS low voltage WE light enable signal WED light data control signal WEDB reverse phase light data control signal WEm light day Data selection signal WEB Reverse phase light data selection signal

Claims (15)

A data read / write circuit that is coupled to a memory cell array and used to access the data in the memory cell array.
A parity data read / write circuit that is coupled to the parity data memory cell array and used to access the parity data of the parity data memory cell array.
A syndrome arithmetic circuit used to generate an error decoding signal based on the data received from the data read / write circuit and the parity data received from the parity data read / write circuit.
Including
In the same read cycle as reading the data, the data read / write circuit corrects the error bits of the data based on the error decode signal, outputs the correct data and the corrected bit signal, and outputs the correct data and the corrected bit signal. Writes the corrected data back to the memory cell array, the syndrome arithmetic circuit outputs a parity data write signal to the parity data read / write circuit based on the correction bit signal, and the syndrome data memory cell array in the parity data memory cell array. Update the parity data
The data read / write circuit
A data read circuit coupled to the memory cell array and used to read the data from the memory cell array to generate read data and a corresponding read bit signal.
The data output signal and the correction bit are coupled to the data read circuit and the syndrome calculation circuit to latch the read data in the read cycle, and correct the error bit of the read data based on the error decode signal. The data output signal is used to generate a signal, and the data output signal includes a data correction circuit which is an output result after the data read / write circuit reads and corrects the data.
A data write circuit coupled to the data correction circuit and the memory cell array and used to replace the correction bit signal with the data output signal corresponding to the error bit and write the correct data back to the memory cell array.
Including
The data correction circuit
A correction switch whose input end receives the read data from the data read circuit and is turned on or off by a read latch signal.
A read bit latch coupled to the correction switch and used to latch the read data,
A correction circuit coupled to the read bit latch, receiving the error decoding signal, and correcting a bit stored in the read bit latch based on the error decoding signal.
A first output circuit coupled to the correction circuit and the read bit latch, controlled by an output enable signal, and outputting a bit stored in the read bit latch as the data output signal.
Including memory devices. When the corrected data is written to the memory cell array, the enable time of the selection signal for selecting the memory cell is referred to as the correction write time, and the data for which the error bit has not been found is transferred to the memory cell array. The memory device according to claim 1, wherein the enable time of the selection signal at the time of writing is referred to as a normal write time, and the correction write time is longer than the normal write time. The data read circuit is
A reed switch whose input end receives the data from the memory cell array and is controlled on or off by a read enable signal.
A precharge circuit coupled to the input end of the reed switch and controlled by a precharge signal to execute a precharge operation on the input end of the reed switch.
An amplifier circuit in which an input end is coupled to an output end of the reed switch, controlled by the read enable signal to generate the read data, and a corresponding read bit signal.
The memory device according to claim 1. The reed switch includes a first transmission gate, a second transmission gate, a first inverter and a second inverter.
The first transmission gate is coupled to a bit line and receives a data signal, the second transmission gate is coupled to a complementary bit line and receives a reverse phase data signal, the first transmission gate and the second transmission gate. The transmission gates are all controlled by the read enable signal, and the data includes a differential signal of the data signal and the reverse phase data signal.
The input end of the first inverter receives the read enable signal, and the output end of the first inverter is common to one control end of the first transmission gate and one control end of the second transmission gate. Combined, the input end of the second inverter is coupled to the output end of the first inverter, and the output end of the second inverter is the other control end of the first transmission gate and the other of the second transmission gate. Commonly coupled to the control end of
The precharge circuit is
The third inverter that receives the precharge signal and
A first P-type transistor whose first end is coupled to the power supply voltage, whose control end is coupled to the output end of the third inverter, and whose second end is coupled to the bit line.
A second P-type transistor whose first end is coupled to the power supply voltage, whose control end is coupled to the output end of the third inverter, and whose second end is coupled to the complementary bit line.
A third P-type transistor coupled between the second end of the first P-type transistor and the second end of the second P-type transistor, and a control end coupled to the output end of the third inverter.
Including
The amplifier circuit
The data signal and the reverse phase data signal are received by being coupled to the lead switch, and the read data signal and the reverse phase read data signal are output correspondingly, and the read data is the read data signal and the reverse phase read. An amplifier that contains a differential signal of the data signal and
A fourth inverter that receives the reverse phase read data signal and outputs the read bit signal, and
The memory device according to claim 3. The correction switch includes a third transmission gate, a fourth transmission gate, and a fifth inverter.
The third transmission gate receives a read data signal from the data read circuit, the fourth transmission gate receives a reverse phase read data signal from the data read circuit, and the third transmission gate and the fourth transmission gate Is controlled by the read latch signal, and the read data includes a differential signal of the read data signal and the reverse phase read data signal.
The input end of the fifth inverter receives the read latch signal, and the output end of the fifth inverter is common to one control end of the third transmission gate and one control end of the fourth transmission gate. Combined,
The read bit latch includes a sixth inverter and a seventh inverter.
The input end of the 6th inverter is coupled to the output end of the 7th inverter, receives the read data signal via the 3rd transmission gate, and the input end of the 7th inverter is the output of the 6th inverter. The memory device according to claim 1, which is coupled to an end and receives the reversed-phase read data signal via the fourth transmission gate. The correction circuit
The eighth inverter that receives the error decoding signal and
A ninth inverter that is coupled to the output end of the sixth inverter and outputs the correction bit signal,
4th P type transistor and 5th P type transistor,
6th P type transistor and 7th P type transistor,
Including
The first end of the 4P type transistor is coupled to the power supply voltage, the second end of the 4P type transistor is coupled to the first end of the 5P type transistor, and the control end of the 4P type transistor is , The second end of the 5th P-type transistor is coupled to the output end of the 8th inverter, the second end of the 5th P-type transistor is coupled to the input end of the 6th inverter, and the control end of the 5th P-type transistor receives the read data signal. death,
The first end of the 6P type transistor is coupled to the power supply voltage, the second end of the 6P type transistor is coupled to the first end of the 7P type transistor, and the control end of the 6P type transistor is coupled. Is coupled to the output end of the 8th inverter, the 2nd end of the 7P type transistor is coupled to the output end of the 6th inverter, and the control end of the 7th P type transistor is the reverse phase read data. The memory device according to claim 5, which receives a signal. The first output circuit is
The 10th inverter whose input end is coupled to the output enable signal,
A first NAND gate in which the first input end is coupled to the second end of the fifth P-type transistor and the second input end receives the output enable signal.
First input coupled to the second end of the second 5P-type transistor, a first 1NOR gate second input terminal is coupled to the output of the tenth inverter,
An eighth P-type transistor whose first end is coupled to the power supply voltage and whose control end is coupled to the output end of the first NAND gate.
The first end is coupled to the second end of the 8P transistor to provide the corrected data output signal, the control end is coupled to the output end of the first NOR gate, and the second end is coupled to the ground voltage. 1st N type transistor to be
The memory device according to claim 6, which includes. The data light circuit is
An eleventh inverter whose input end receives the corresponding data output signal, and
A first light switch whose input end is coupled to the output end of the eleventh inverter and is controlled to be turned on or off by a first light latch signal.
A second write switch whose input end receives the corresponding correction bit signal and is controlled on or off by a second write latch signal.
A light bit latch coupled to the output end of the first light switch and the output end of the second light switch,
A second output circuit coupled to the output end of the second write switch and the output end of the write bit latch, controlled by a write enable signal, and writing the data output signal or the correction bit signal to the memory cell array.
The memory device according to claim 1. The first light switch is a fifth transmission gate, and the second light switch is a sixth transmission gate.
The write bit latch includes a twelfth inverter and a thirteenth inverter.
The input end of the twelfth inverter is coupled to the output end of the thirteenth inverter, the input end of the thirteenth inverter is coupled to the output end of the twelfth inverter, and the input end of the twelfth inverter is the twelfth. 5. The memory device according to claim 8, which is commonly coupled to the output end of the transmission gate and the output end of the sixth transmission gate. The second output circuit is
The 14th inverter that receives the write enable signal and
The 15th inverter coupled in series with the 14th inverter and
A second NAND gate in which the first input end is coupled to the output end of the twelfth inverter and the second input end is coupled to the output end of the fifteenth inverter.
A second NOR gate whose first input end is coupled to the output end of the 12th inverter and whose second input end is coupled to the output end of the 14th inverter.
A ninth P-type transistor whose first end is coupled to the power supply voltage and whose control end is coupled to the output end of the second NAND gate.
The first end is coupled to the second end of the 9P transistor to provide the corresponding data signal, the control end is coupled to the output end of the second NOR gate, and the second end is coupled to the ground voltage. 2N type transistor and
A third NAND gate in which the first input end is coupled to the output end of the thirteenth inverter and the second input end is coupled to the output end of the fifteenth inverter.
A third NOR gate whose first input end is coupled to the output end of the thirteenth inverter and whose second input end is coupled to the output end of the fourteenth inverter.
A tenth P-type transistor whose first end is coupled to the power supply voltage and whose control end is coupled to the output end of the third NAND gate.
The first end is coupled to the second end of the 10P transistor to provide the corresponding reversed-phase data signal, the control end is coupled to the output end of the third NOR gate, the second end is coupled to the ground voltage, and so on. The data includes a third N-type transistor including the data signal and the differential signal of the reverse phase data signal, and
9. The memory device according to claim 9. The data write circuit further includes a control signal generation circuit, and the control signal generation circuit generates the first light latch signal and the second light latch signal based on the initial light latch signal and the light mask signal, and the second light latch signal is generated. Includes 16 inverters, 17th inverters, 18th inverters and signal generation circuits
The 16th inverter is coupled in series with the 17th inverter, the input end of the 16th inverter receives the initial write latch signal, and the 17th inverter transmits the parity write latch signal to the parity data read / write circuit. The 18th inverter receives the initial write latch signal and outputs the reverse phase parity write latch signal to the parity data read / write circuit.
The signal production circuit
The 19th inverter whose output end receives the corresponding light mask signal,
A fourth NAND in which the first input end receives the initial write latch signal, the second input end is coupled to the output end of the 19th inverter, and the output end outputs the opposite phase signal of the corresponding first write latch signal. With the gate
A 20th inverter whose input end is coupled to the output end of the 4th NAND gate and whose output end outputs the corresponding 1st write latch signal.
A fifth NAND gate in which the first input end receives the initial write latch signal, the second input end receives the corresponding light mask signal, and the output end outputs the opposite phase signal of the corresponding second light latch signal. When,
A 21st inverter whose input end is coupled to the output end of the 5th NAND gate and whose output end outputs the corresponding 2nd write latch signal.
10. The memory device according to claim 10. The syndrome arithmetic circuit is
It is coupled to the data read / write circuit and the parity data read / write circuit, selectively receives the output signal of the data read circuit or the data correction circuit based on the read operation or the write operation, and generates the parity data write signal. A syndrome generating circuit that generates a syndrome signal by comparing the parity data write signal and the corresponding parity data, and
A syndrome decoding circuit that is coupled to the syndrome generation circuit and decodes the syndrome signal to generate an error-decoded signal.
The memory device according to claim 1. When the data read / write circuit executes the read operation, the syndrome generating circuit generates the parity data write signal based on the read bit signal, and when the data read / write circuit executes the write operation, the syndrome occurs. The memory device according to claim 12, wherein the generating circuit manufactures the parity data write signal based on the correction bit signal or the data output signal. The parity data read / write circuit reads the parity data and outputs a parity read signal to the syndrome generation circuit.
Includes a plurality of heat transmission gates and a plurality of second 1XOR gate, said data output signal by controlling the plurality of transmission gates, selectively providing the correction bit signal or the read bit signals to said plurality of first 1XOR gate , The internal arithmetic circuit that outputs the parity data write signal, and
A plurality of second XOR gates that receive the parity data write signal from the internal arithmetic circuit, receive the corresponding parity read signal from the parity data read / write circuit, and output the syndrome signal.
12. The memory device according to claim 12. The parity data read / write circuit
A parity data read circuit that is coupled to the parity data memory cell array and the syndrome arithmetic circuit, reads the parity data from the parity data memory cell array, and outputs a parity read signal to the syndrome arithmetic circuit.
A parity data write circuit that is coupled to the parity data memory cell array and the syndrome calculation circuit and is used to write the corrected parity data to the parity data memory cell array.
The memory device according to claim 1.

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