TW202038391A - Package stack structure, manufacturing method and carrier module thereof - Google Patents

Abstract

This invention provides a package stack structure and manufacturing method thereof, which disposes an electronic component on the uppermost side of a plurality of organic material substrates, and the other organic material substrates are not disposed any wafers, so that the circuit layers of the predetermined number of layers are respectively disposed in the organic substrates to disperse heat by the organic material substrates, such that the problem of separation between the lowermost organic substrate and the circuit board due to CTE mismatch can be avoided.

Description

Package stack structure and its manufacturing method and carrier board assembly

The present invention relates to a packaging process, in particular to a packaging stack structure and its manufacturing method and carrier assembly.

With the vigorous development of portable electronic products in recent years, various related products have gradually developed toward the trend of high density, high performance, and light, thin, short, and small.

As shown in FIG. 1, it is a schematic cross-sectional view of the conventional electronic device 1. The electronic device 1 includes a motherboard 1b like a circuit board and an electronic package 1a mounted on the motherboard 1b. The electronic package 1a includes a packaging substrate 11, a semiconductor chip 10 using a plurality of conductive bumps 100 to flip-chip the packaging substrate 11, and a primer 12 for fixing the semiconductor chip 10 and covering the conductive bumps 100. The packaging substrate 11 of the electronic package 1a is connected to the motherboard 1b with a plurality of solder balls 13.

In the development of semiconductor technology, the size of the semiconductor chip 10 (or the electronic package 1a) in the flip-chip packaging process tends to be larger and larger, which results in the semiconductor chip 10 being subjected to stress concentration after packaging. The die corner stress (Die Corner Stress) formed at each corner is also getting higher and higher, causing a strong stress to be generated between it and the primer 12. As shown in the dotted circle in Figure 1, the semiconductor chip 10 Cracks will occur along the corners. To solve this problem, the industry generally uses Ultra low Coefficient of Thermal Expansion (CTE) absolute The edge substrate is used as the board body of the package substrate 11, such as copper clad laminate (CCL), ABF (Ajinomoto Build-up Film), Prepreg (PP), solder mask (Solder Mask, referred to as SM) and other materials to reduce the die corner stress (Die Corner Stress).

However, in the conventional electronic device 1, the CTE of the board of the motherboard 1b does not match the package substrate 11 and becomes smaller, resulting in separation between the package substrate 11 and the motherboard 1b due to CTE mismatch. Furthermore, there is a problem of the reliability of the solder ball 13, causing the package substrate 11 to be unable to effectively electrically connect to the motherboard 1b (e.g. open circuit) or fail the reliability test (e.g. not fully bonded). The yield rate is poor.

Furthermore, because the size of the package substrate 11 will be larger and larger according to the increase in the number of chips, and the number of layers will also be higher, so the process yield of the package substrate 11 will also decrease (that is, the more the number of layers The greater the error, the greater the error), which causes the manufacturing cost of the package substrate 11 to increase dramatically. For example, taking the packaging substrate 11 with ten circuit layers as an example, the production yield of each circuit layer is about 95%, and the yield of the packaging substrate 11 with ten circuit layers is 59.8% (ie 0.95 ¹⁰ ) Therefore, it is difficult to complete the production of the package substrate 11 with the existing manufacturing process, and the manufacturing process may need to be re-planned, thus greatly increasing the difficulty of the manufacturing process.

Therefore, how to overcome the various problems of the above-mentioned conventional technology has become an urgent problem to be solved at present.

In view of the above-mentioned deficiencies in the prior art, the present invention provides a package stack structure, which includes: at least one electronic component; and a carrier assembly with a plurality of circuit layers, including a first organic substrate with a first circuit portion And at least one second organic material substrate with a second circuit portion, and the first organic material substrate is stacked on the second organic material substrate by a plurality of supports, wherein The number of layers of the plurality of circuit layers that are electrically connected to the electronic component is distributed among the first circuit portion and the second circuit portion, and the electronic component is connected to the first organic substrate and electrically connected to the plurality Line layer.

The present invention further provides a method for manufacturing a package stack structure, which includes: providing a first organic substrate with a first circuit portion and at least one second organic substrate with a second circuit portion; connecting at least one electronic component to the And stacking the first organic material substrate on the second organic material substrate through a plurality of supports to form a carrier assembly with a plurality of circuit layers, and the electronic component is electrically connected to the A plurality of circuit layers, wherein the number of layers of the plurality of circuit layers used to electrically connect the electronic component is allocated to the first circuit part and the second circuit part.

In the aforementioned package stack structure and its manufacturing method, the number of circuit layers of the first circuit portion is different from the number of circuit layers of the second circuit portion.

In the aforementioned package stack structure and its manufacturing method, the number of circuit layers of the first circuit portion is the same as the number of circuit layers of the second circuit portion.

In the aforementioned package stack structure and its manufacturing method, it further includes disposing a heat sink on the first organic substrate.

In the aforementioned package stack structure and its manufacturing method, the first organic material substrate is stacked with a plurality of the second organic material substrates, and each of the second organic material substrates is stacked by a plurality of supports.

In the aforementioned package stack structure and its manufacturing method, the support system is electrically connected to the first organic material substrate and the second organic material substrate.

The aforementioned package stack structure and its manufacturing method further include stacking the second organic material substrate on a circuit board through a plurality of conductive elements. For example, the conductive element is electrically connected to the circuit board and the second organic substrate, and the thermal expansion coefficient of the second organic substrate is between the thermal expansion coefficient of the circuit board and the thermal expansion coefficient of the first organic substrate . In addition, the thermal expansion coefficient of the second organic substrate is different from the thermal expansion coefficient of the circuit board.

In the aforementioned package stack structure and its manufacturing method, the thermal expansion coefficient of the first organic substrate is different from the thermal expansion coefficient of the second organic substrate.

The present invention also provides a carrier board assembly configured with a plurality of circuit layers. The carrier board assembly includes: a first organic material substrate having a first circuit portion; and a second organic material substrate having a second circuit portion, And the first organic material substrate is stacked on the second organic material substrate by a plurality of supports, wherein the number of layers of the plurality of circuit layers is distributed among the first circuit part and the second circuit part.

In the aforementioned carrier board assembly, the number of circuit layers of the first circuit portion is different from the number of circuit layers of the second circuit portion.

In the aforementioned carrier board assembly, the number of circuit layers of the first circuit portion is the same as the number of circuit layers of the second circuit portion.

In the aforementioned carrier assembly, the first organic material substrate is stacked with a plurality of the second organic material substrates, and each of the second organic material substrates is stacked by a plurality of supports. Further, the compound includes a coating layer formed between each of the second organic material substrates, which covers the plurality of support members.

In the aforementioned carrier assembly, the support system is electrically connected to the first organic material substrate and the second organic material substrate.

In the aforementioned carrier assembly, the thermal expansion coefficient of the first organic material substrate is different from the thermal expansion coefficient of the second organic material substrate.

The aforementioned carrier assembly includes a coating layer covering the plurality of supports.

It can be seen from the above that, in the package stack structure and its manufacturing method and carrier assembly of the present invention, the expected number of circuit layers are respectively arranged in the first and second organic substrates, which is compared with the conventional technology. In the present invention, the second organic material substrate can disperse thermal stress to avoid the problem of phase separation between the first organic material substrate and the circuit board due to CTE mismatch, so that the second organic material substrate can effectively The circuit board may be able to pass the reliability test if it is connected to the circuit board, thereby increasing the yield of the product.

Furthermore, even if the number of circuit layers is getting higher and higher, the expected number of circuit layers can still be laid on the first and second organic substrates respectively to increase the process yield and effectively reduce the production cost.

In addition, the CTE of the first and second organic substrates is different, so that the CTE of the package stack structure is gradually changed, and the problem of warping of the package stack structure due to excessive thermal stress changes is avoided.

1‧‧‧Electronic device

1a‧‧‧Electronic package

1b‧‧‧Motherboard

10‧‧‧Semiconductor chip

100‧‧‧Conductive bump

11‧‧‧Packaging substrate

12,202‧‧‧ Primer

13‧‧‧Solder ball

2,3‧‧‧Package stack structure

2a, 3a, 4a, 4b‧‧‧Carrier board assembly

20‧‧‧Electronic components

20a‧‧‧working surface

20b‧‧‧Inactive surface

200‧‧‧electrode pad

201‧‧‧Conductive bump

21‧‧‧The first organic substrate

21a‧‧‧First surface

21b‧‧‧Second surface

21’‧‧‧First Circuit Department

210‧‧‧First insulation layer

211‧‧‧First circuit layer

22‧‧‧Second organic substrate

22a‧‧‧First side

22b‧‧‧Second side

22’‧‧‧Second Circuit Department

220‧‧‧Second insulating layer

221‧‧‧Second circuit layer

23‧‧‧Radiator

23a‧‧‧Combination layer

23b‧‧‧Adhesive layer

230‧‧‧sheet

231‧‧‧Foot

24‧‧‧Support

25‧‧‧Conductive element

26‧‧‧Circuit board

30‧‧‧Support

40‧‧‧Coating

S‧‧‧Empty Space

Figure 1 is a schematic cross-sectional view of a conventional electronic device.

2A to 2E are schematic cross-sectional views of the manufacturing method of the package stack structure of the present invention.

FIG. 3 is a schematic cross-sectional view of another embodiment of the package stack structure of the present invention.

4A and 4B are schematic cross-sectional views of different embodiments of the carrier assembly of the present invention.

The following specific examples illustrate the implementation of the present invention. Those familiar with the art can easily understand the other advantages and effects of the present invention from the contents disclosed in this specification.

It should be noted that the structures, proportions, sizes, etc. shown in the drawings in this manual are only used to match the contents disclosed in the manual for the understanding and reading of those familiar with the art, and are not intended to limit the implementation of the present invention Therefore, it does not have any technical significance. Any structural modification, proportional relationship change, or size adjustment should still fall within the scope of the present invention without affecting the effects and objectives that can be achieved. The technical content disclosed by the invention can be covered. At the same time, terms such as "first", "second", and "one" cited in this specification are only for ease of description It is clear that it is not used to limit the scope of implementation of the present invention, and the change or adjustment of the relative relationship shall be regarded as the scope of the implementation of the present invention without substantially changing the technical content.

2A to 2E are schematic cross-sectional views of the manufacturing method of the package stack structure 2 of the present invention.

As shown in Fig. 2A, a first organic substrate 21 having a first circuit portion 21' is provided.

In this embodiment, the first organic substrate 21 is a circuit structure with a core layer or a coreless layer, such as a package substrate, which defines a first surface 21a and a second surface 21b opposite to each other. And the first circuit portion 21 ′ includes at least one first insulating layer 210 and a first circuit layer 211 disposed on the first insulating layer 210. For example, a fan-out first circuit layer 211 is formed by a redistribution layer (RDL) method, the material of which is copper, and the material for forming the first insulating layer 210 is such as Diazobenzene (Polybenzoxazole, PBO for short), Polyimide (PI for short), Prepreg (PP for short) and other dielectric materials or solder resist materials such as green paint and graphite.

As shown in FIG. 2B, at least one electronic component 20 is connected to the first organic substrate 21, and the electronic component 20 is electrically connected to the first circuit layer 211 of the first circuit portion 21'.

In this embodiment, the electronic component 20 is, for example, a package, an active component, a passive component, or a combination of the three, etc., wherein the package is, for example, a Chip Scale Package (CSP), and the active component is For example, semiconductor chips, the passive components are resistors, capacitors, and inductors. In this embodiment, the electronic component 20 is an active component, which has an active surface 20a and a non-active surface 20b opposite to each other. The active surface 20a has a plurality of electrode pads 200, so that the electrode pads 200 are made of a plurality of materials such as solder. The conductive bumps 201 are arranged on the first surface 21a of the first organic substrate 21 in a flip-chip manner and are electrically connected to the first circuit layer 211, and the conductive bumps 201 are covered with a primer 202; or The electronic component 20 may have its non-acting surface 20b disposed on the first surface 21a of the first organic material substrate 21, and the electrode pads 200 may be electrically connected to the first surface 21a by a plurality of bonding wires (not shown). Circuit layer 211; or, the electronic element The component 20 can directly contact the first circuit layer 211 to electrically connect to the first circuit layer 211. However, the manner in which the electronic component 20 is electrically connected to the first organic substrate 21 is not limited to the above.

Furthermore, there are many ways of disposing the electronic component 20, such as being arranged on the second surface 21b of the first organic substrate 21, there is no particular limitation.

As shown in FIG. 2C, a heat dissipation element 23 can be selectively disposed on the first surface 21a of the first organic substrate 21.

In this embodiment, the heat sink 23 is a metal structure and includes a sheet 230 and a leg portion 231, and the sheet 230 is bonded to the non-active surface 20b of the electronic component 20 through a bonding layer 23a, and The legs 231 of the heat sink 23 are erected on the first surface 21a (or the first circuit layer 211) of the first organic substrate 21 via the adhesive layer 23b. For example, the bonding layer 23a is made of thermal interface material (Thermal Interface Material, TIM), thermally conductive glue or other suitable materials, and the adhesive layer 23b is made of insulating glue, conductive glue or other suitable materials.

As shown in FIG. 2D, the first organic material substrate 21 is stacked on at least one second organic material substrate 22 having a second circuit portion 22' through a plurality of supports 24, and the second organic material substrate 22 is not The wafer is connected, and an empty space S is presented between the first and second organic substrates 21 and 22.

In this embodiment, the second organic material substrate 22 is a circuit structure with a core layer or a coreless layer, such as a package substrate, which defines a first side 22a and a second side 22b opposite to each other. , So that the first organic material substrate 21 is stacked on the first side 22a of the second organic material substrate 22 with its second surface 21b, and the second circuit portion 22' includes at least a second insulating layer 220 and The second circuit layer 221 is provided on the second insulating layer 220. For example, a fan-out type second circuit layer 221 is formed by a redistribution layer (RDL) method, the material of which is copper, and the material for forming the second insulating layer 220 is such as Diazobenzene (Polybenzoxazole, PBO for short), Polyimide (PI for short), Prepreg (PP for short) and other dielectric materials or solder resist materials such as green paint and graphite.

Furthermore, the coefficient of thermal expansion (CTE) of the first organic material substrate 21 is different (eg, smaller than) the coefficient of thermal expansion of the second organic material substrate 22. For example, when the number of layers of the first circuit layer 211 of the first circuit portion 21' is the same as the number of layers of the second circuit layer 221 of the second circuit portion 22', by forming the material of the first insulating layer 210 Different from the material used to form the second insulating layer 220, the thermal expansion coefficient of the first organic substrate 21 is different from the thermal expansion coefficient of the second organic substrate 22.

Alternatively, when the material for forming the first insulating layer 210 is the same as the material for forming the second insulating layer 220, the first circuit layer 211 (or the first insulating layer 210) of the first circuit portion 21' The number of layers is different from that of the second circuit layer 221 (or the second insulating layer 220) of the second circuit portion 22', so that the thermal expansion coefficient of the first organic substrate 21 is different from that of the second organic substrate The coefficient of thermal expansion of 22.

In addition, the support 24 is a solder ball, a copper core ball, or a metal piece such as copper or gold (such as column, block, or needle), etc., which are electrically connected to the first and The second organic substrate 21, 22.

As shown in FIG. 2E, the second organic substrate 22 with its second side 22b is connected to a circuit board 26 via a plurality of conductive elements 25.

In this embodiment, the material of the insulating body of the circuit board 26 is different from the materials of the first and second insulating layers 210, 220, and the thermal expansion coefficient of the second organic material substrate 22 is different from (for example, smaller than) the circuit Coefficient of thermal expansion of plate 26.

Furthermore, the conductive element 25 is a solder ball, a copper core ball, or a metal piece such as copper or gold (such as column, block, or needle), etc., which are electrically connected to the circuit board 26 and the second organic substrate 22.

The manufacturing method of the present invention is mainly by arranging the expected number of circuit layers on the first organic material substrate 21 and the second organic material substrate 22, and then the first organic material substrate 21 and the second organic material substrate The boards 22 are combined (eg stacked) to form the carrier assembly 2a with the required number of circuit layers, and the CTEs of the first organic material substrate 21 and the second organic material substrate 22 are different, so compared to the prior art, the The manufacturing method of the invention can buffer the overall thermal expansion and deformation of the carrier assembly 2a by the second organic material substrate 22 when the CTE of the circuit board 26 remains unchanged, so as to avoid the carrier assembly 2a and the circuit board. The problem of the separation between the 26 due to the CTE mismatch, that is, the problem of the connection reliability of the conductive element 25 is avoided, so the second organic substrate 22 can effectively electrically connect the circuit board 26 or the carrier board assembly 2a. Pass the reliability test to improve the yield of the product.

Furthermore, even if the size of the carrier assembly 2a becomes larger and larger in accordance with the increase in the number of chips required, resulting in higher and higher circuit layers, the expected number of circuit layers (first and second The two circuit layers 211, 221) are respectively arranged in the first and second organic material substrates 21, 22 to improve the process yield of the carrier assembly 2a, and thus can effectively reduce the manufacturing cost of the carrier assembly 2a.

For example, taking the carrier assembly 2a with ten circuit layers as an example, the first circuit layer 211 of seven layers can be arranged on the first organic substrate 21, and the second circuit layer 221 of three layers can be arranged on the second organic substrate 22, if the production yield of each layer of the wiring layer is about 95%, the yield of the first organic material of the substrate 21 was 68.8% (i.e. 0.95 ^7), and the second substrate 22 of the organic material good The rate is 85.7% (ie, 0.95 ³ ), so the carrier assembly 2a can be manufactured by the existing manufacturing process, thus greatly reducing the manufacturing cost.

It should be understood that the six-layer first circuit layer 211 can also be arranged on the first organic material substrate 21, and the four-layer second circuit layer 221 can be arranged on the second organic material substrate 22; alternatively, the The five-layer first circuit layer 211 is disposed on the first organic material substrate 21, and the five-layer second circuit layer 221 is disposed on the second organic material substrate 22. Therefore, the number of related circuit layers can be arranged in the first and second organic substrates 21, 22 according to requirements.

Moreover, in the package stack structure 2, the arrangement of the board structures can be in order according to the size of the CTE, such as the first organic material substrate 21 (the smallest CTE) and the second organic material substrate 22 (from top to bottom) CTE Between the first organic substrate and the circuit board) and the circuit board 26 (maximum CTE), so that the CTE gradually changes from top to bottom, so as to avoid the problem of warping due to excessive thermal stress changes.

In another embodiment, the package stack structure 3 as shown in FIG. 3 can also be configured such that the carrier assembly 3a includes a plurality of second organic material substrates 22 according to yield requirements, and each of the second organic material substrates Between 22 is stacked by a plurality of supporting members 30. For example, the thermal expansion coefficients of the second organic material substrates 22 may be the same or different, and the supporting member 30 is a solder ball, a copper core ball, or a metal member such as copper or gold (such as pillars). Shape, block or needle), etc., which electrically connect the circuit board 26 and each of the second organic substrate 22. Specifically, if the thermal expansion coefficients of the second organic material substrates 22 are not the same, the values of the thermal expansion coefficients of the second organic material substrates 22 can be in order from the side of the first organic material substrate 21 to the side of the circuit board 26 Increase.

Therefore, if the carrier assembly 3a with ten circuit layers is taken as an example, two first circuit layers 211 can be arranged on the first organic substrate 21, and two second circuit layers 221 can be arranged on four For the second organic material substrate 22, if the production yield of the circuit layer of each layer is about 95%, the yield of the first organic material substrate 21 is 90.3% (ie 0.95 ² ), and each of the second organic material substrates The yield rate of 22 is 90.3% (ie 0.95 ² ), so the production of the carrier assembly 3a can be completed with the existing manufacturing process, thus greatly reducing the manufacturing cost.

The present invention further provides a packaging stack structure 2 and 3, which includes: a first organic material substrate 21, at least one electronic component 20, and at least one second organic material substrate 22.

The first organic material substrate 21 has a first circuit portion 21'.

The electronic component 20 is connected to the first organic substrate 21 and electrically connected to the first circuit portion 21'.

The second organic material substrate 22 has a second circuit portion 22' and the first organic material substrate 21 is stacked on it by a plurality of supports 24, wherein the second organic material substrate 22 is not connected with Wafer.

In one embodiment, the number of circuit layers of the first circuit portion 21' is different from the number of circuit layers of the second circuit portion 22'.

In one embodiment, the number of circuit layers of the first circuit portion 21' is the same as the number of circuit layers of the second circuit portion 22'.

In one embodiment, a heat sink 23 is provided on the first organic substrate 21.

In one embodiment, the first organic material substrate 21 is stacked with a plurality of second organic material substrates 22, and each of the second organic material substrates 22 is stacked by a plurality of supports 30.

In one embodiment, the supporting body 24 is electrically connected to the first and second organic substrates 21 and 22.

In one embodiment, the package stacking structures 2 and 3 include a circuit board 26 for the second organic material substrate 22 to be stacked on it via a plurality of conductive elements 25. For example, the conductive element 25 is electrically connected to the circuit board 26 and the second organic substrate 22. In addition, the thermal expansion coefficient of the second organic substrate 22 is different from the thermal expansion coefficient of the circuit board 26.

In one embodiment, the thermal expansion coefficient of the first organic material substrate 21 is different from the thermal expansion coefficient of the second organic material substrate 22.

Please refer to Figures 4A and 4B together. The present invention also provides a carrier board assembly 2a, 3a, 4a, 4b, which is configured with a plurality of circuit layers, and the carrier board assembly 2a, 3a, 4a, 4b includes: at least one An organic material substrate 21 and at least one second organic material substrate 22.

The first organic material substrate 21 has a first circuit portion 21'.

The second organic material substrate 22 has a second circuit portion 22', and the first organic material substrate 21 is stacked on the second organic material substrate 22 by a plurality of supports 24, wherein the carrier assembly 2a The number of layers of the plural circuit layers of 3a, 4a, 4b is allocated to the first circuit portion 21' and the second circuit portion 22'.

In one embodiment, the number of circuit layers of the first circuit portion 21' is different from the number of circuit layers of the second circuit portion 22'.

In one embodiment, the number of circuit layers of the first circuit portion 21' is the same as the number of circuit layers of the second circuit portion 22'.

In one embodiment, the first organic material substrate 21 is stacked with a plurality of second organic material substrates 22, and each of the second organic material substrates 22 is stacked by a plurality of supports 30. Furthermore, the carrier assembly 4b further includes a coating layer 40 formed between the second organic material substrates 22, which covers the plurality of support members 30. Specifically, the coating layer 40 is an insulating material, such as polyimide (PI), dry film, epoxy (epoxy) encapsulant or molding compound.

In one embodiment, the supporting body 24 is electrically connected to the first organic material substrate 21 and the second organic material substrate 22.

In one embodiment, the thermal expansion coefficient of the first organic material substrate 21 is different from the thermal expansion coefficient of the second organic material substrate 22.

In one embodiment, the carrier board assembly 4b includes a covering layer 40 covering the plurality of supports 24. Specifically, the coating layer 40 is an insulating material, such as polyimide (PI), dry film, epoxy encapsulant or encapsulant.

In summary, the package stack structure and its manufacturing method and carrier assembly of the present invention are achieved by arranging a predetermined number of circuit layers on the first and second organic substrates, and the first and second The CTE of the organic material substrate is different, so the present invention can use the second organic material substrate to disperse the thermal stress to avoid the problem of phase separation between the first organic material substrate and the circuit board due to CTE mismatch. The second organic material substrate can be effectively and electrically connected to the circuit board or the first and second organic material substrates can pass the reliability test, thereby improving the yield of the product.

Furthermore, even if there is a large demand for the number of circuit layers, the expected number of circuit layers can still be arranged on multiple second organic substrates to increase the process yield of each organic substrate, which can effectively reduce The production cost of each organic substrate.

In addition, in the package stack structure, the organic substrate and the circuit board can be arranged in sequence according to the size of the CTE to avoid the problem of warping due to excessive thermal stress changes.

The above-mentioned embodiments are used to exemplify the principles and effects of the present invention, but not to limit the present invention. Anyone who is familiar with the art can modify the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the rights of the present invention should be listed in the scope of patent application described later.

2‧‧‧Package stack structure

2a‧‧‧Carrier board assembly

20‧‧‧Electronic components

21‧‧‧The first organic substrate

21’‧‧‧First Circuit Department

210‧‧‧First insulation layer

211‧‧‧First circuit layer

22‧‧‧Second organic substrate

22b‧‧‧Second side

22’‧‧‧Second Circuit Department

220‧‧‧Second insulating layer

221‧‧‧Second circuit layer

23‧‧‧Radiator

25‧‧‧Conductive element

26‧‧‧Circuit board

Claims (28)

A packaging stack structure includes: at least one electronic component; and a carrier assembly with a plurality of circuit layers, including a first organic substrate with a first circuit portion and at least one second circuit with a second circuit portion An organic material substrate, and the first organic material substrate is stacked on the second organic material substrate by a plurality of supports, wherein the electronic component is connected to the first organic material substrate and electrically connected to the plurality of circuit layers, and The number of layers of the plurality of circuit layers used to electrically connect the electronic component is allocated to the first circuit portion and the second circuit portion. According to the package stack structure described in claim 1, wherein the number of circuit layers of the first circuit portion is different from the number of circuit layers of the second circuit portion. In the package stack structure described in claim 1, wherein the number of circuit layers of the first circuit portion is the same as the number of circuit layers of the second circuit portion. According to the package stack structure described in item 1 of the scope of patent application, a heat sink is provided on the first organic substrate. According to the package stack structure described in claim 1, wherein the first organic material substrate is stacked with a plurality of the second organic material substrates, and a plurality of support members are provided between each of the second organic material substrates Phase stacking. According to the package stack structure described in claim 1, wherein the supporting system is electrically connected to the first organic material substrate and the second organic material substrate. The package stack structure described in the first item of the scope of the patent application further includes a circuit board on which the second organic substrate is stacked via a plurality of conductive elements. The package stack structure described in item 7 of the scope of patent application, wherein the conductive element The circuit board and the second organic substrate are electrically connected. The package stack structure described in claim 7, wherein the thermal expansion coefficient of the second organic material substrate is different from that of the circuit board, and the thermal expansion coefficient of the second organic material substrate is between that of the circuit board Between the thermal expansion coefficient and the thermal expansion coefficient of the first organic material substrate. According to the package stack structure described in claim 1, wherein the thermal expansion coefficient of the first organic material substrate is different from the thermal expansion coefficient of the second organic material substrate. A manufacturing method of a package stack structure includes: providing a first organic material substrate with a first circuit portion and at least one second organic material substrate with a second circuit portion; connecting at least one electronic component to the first organic material And the first organic material substrate is stacked on the second organic material substrate by a plurality of supports to form a carrier assembly having a plurality of circuit layers, and the electronic component is electrically connected to the plurality of circuit layers, Wherein, the number of layers of the plurality of circuit layers used to electrically connect the electronic component is allocated to the first circuit portion and the second circuit portion. The manufacturing method of the package stack structure as described in claim 11, wherein the number of circuit layers of the first circuit part is different from the number of circuit layers of the second circuit part. The manufacturing method of the package stack structure as described in claim 11, wherein the number of circuit layers of the first circuit portion is the same as the number of circuit layers of the second circuit portion. The manufacturing method of the package stack structure as described in item 11 of the scope of the patent application includes arranging a heat sink on the first organic substrate. The manufacturing method of the package stack structure described in claim 11, wherein the first organic material substrate is stacked with a plurality of the second organic material substrates, and each of the second organic material substrates The space is stacked by a plurality of support members. According to the manufacturing method of the package stack structure described in claim 11, wherein the supporting system is electrically connected to the first organic material substrate and the second organic material substrate. The manufacturing method of the package stack structure as described in item 11 of the scope of patent application includes stacking the second organic material substrate on a circuit board through a plurality of conductive elements. According to the method of manufacturing the package stack structure described in the scope of the patent application, the conductive element is electrically connected to the circuit board and the second organic substrate. The manufacturing method of the package stack structure as described in claim 17, wherein the thermal expansion coefficient of the second organic material substrate is different from the thermal expansion coefficient of the circuit board, and the thermal expansion coefficient of the second organic material substrate is between the circuit board Between the thermal expansion coefficient of the board and the thermal expansion coefficient of the first organic substrate. According to the manufacturing method of the package stack structure described in claim 11, the thermal expansion coefficient of the first organic material substrate is different from the thermal expansion coefficient of the second organic material substrate. A carrier board assembly is configured with a plurality of circuit layers. The carrier board assembly includes: a first organic material substrate having a first circuit part; and a second organic material substrate having a second circuit part, and the first The organic material substrate is stacked on the second organic material substrate by a plurality of supports, wherein the number of layers of the plurality of circuit layers is allocated to the first circuit portion and the second circuit portion. The carrier board assembly described in claim 21, wherein the number of circuit layers of the first circuit part is different from the number of circuit layers of the second circuit part. The carrier board assembly described in item 21 of the scope of patent application, wherein the number of circuit layers of the first circuit portion is the same as the number of circuit layers of the second circuit portion. The carrier assembly described in claim 21, wherein the first organic material substrate is stacked with a plurality of the second organic material substrates, and each of the second organic material substrates is connected by a plurality of supports Phase stacking. The carrier board assembly described in item 24 of the scope of patent application includes a coating layer formed between the second organic substrates and covering the plurality of support members. According to the carrier assembly described in claim 21, wherein the support system is electrically connected to the first organic material substrate and the second organic material substrate. The carrier assembly described in claim 21, wherein the thermal expansion coefficient of the first organic material substrate is different from the thermal expansion coefficient of the second organic material substrate. The carrier board assembly described in item 21 of the scope of patent application includes a coating layer covering the plurality of supports.

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