TW202034504A - Low-voltage fast erasing method for electronic writing erasable rewritable read-only memory implanting ions of the same type to increase the ion concentration so as to reduce the voltage difference for erasing - Google Patents

Abstract

A low-voltage fast erasing method for electronic writing erasable rewritable read-only memory is disclosed. The electronic writing erasable rewritable read-only memory is provided with a transistor structure on a semiconductor substrate, and the transistor structure has a first conductive gate. Also, ions of the same type are implanted in the semiconductor substrate at the junction between the first conductive gate and the source and the junction between the first conductive gate and the drain or in the ion doped regions of the source and the drain to increase the ion concentration in this region so as to reduce the voltage difference for erasing. In addition, the erasing method proposed by the corresponding device of the present invention includes the condition of setting the drain or source to floating, thereby achieving rapid erasing of a large number of memory cells. In addition to being applicable to a single gate transistor structure, the present invention is more suitable for electronic writing erasable rewritable read-only memory with a floating gate structure.

Description

Low-voltage fast erasing method of electronic writing erasable rewritable read-only memory

The present invention relates to an electronic write-erasable rewritable read-only memory technology, in particular to a low-voltage fast erasing method for electronic write-erasable rewritable read-only memory.

Nowadays, when computer information products are developed, electronically erasable programmable read-only memory (EEPROM) and non-volatile memory such as flash memory (Flash) are all non-volatile memories that can be used electronically. The semiconductor storage device with multiple rewriting only needs a specific voltage to erase the data in the memory in order to write new data, and the data will not disappear after the power is turned off, so it is widely used in various electronic products.

Since the non-volatile memory system is programmable, it uses stored charge to change the gate voltage of the transistor of the memory, or does not store charge to leave the gate voltage of the transistor of the original memory. The erase operation removes the charge stored in the non-volatile memory, so that the non-volatile memory returns to the gate voltage of the transistor of the original memory. For the current non-volatile memory, a high voltage difference is required during erasing, which will increase the area and increase the complexity of the manufacturing process.

In view of this, the applicant specifically proposes a low current and low voltage difference electronic write-erasable rewritable read-only memory in response to the above-mentioned deficiencies of the prior art. After further painstaking research, the applicant also proposes this memory architecture A low-pressure and fast erasure method.

The main purpose of the present invention is to provide a low-voltage fast erasing method for electronic write-erasable rewritable read-only memory, which uses electronic write-erasable rewritable read-only memory, and uses ion implantation for this memory. The increase of the input concentration increases the electric field between the transistor or the substrate and the gate, thereby reducing the voltage difference of the erasing; at the same time, by setting the source or the drain to float with the erasing conditions of the present invention, To achieve the effect of quickly erasing a large number of memory cells.

In order to achieve the above objective, the present invention proposes a low-voltage fast erasing method for electronic write-erasable rewritable read-only memory, which is applied to electronic write-erasable rewritable read-only memory. This electronic write erase The rewritable read-only memory mainly includes a semiconductor substrate on which at least one transistor structure is disposed. The transistor structure includes a first dielectric layer on the surface of the semiconductor substrate, and a first conductive gate disposed on the first dielectric. On the electrical layer, and at least two first ion-doped regions are respectively located in the semiconductor substrate and located on two sides of the first conductive gate to serve as source and drain respectively; wherein, ion implantation is used in the first conductive gate The semiconductor substrate or the first ion doping area at the junction of the electrode, the source electrode and the drain electrode is further implanted with homotype ions to increase the ion concentration and reduce the erase voltage difference.

Of course, in addition to the above-mentioned single-gate transistor structure, the present invention is also applicable to floating gate structures. Therefore, in addition to the aforementioned transistor structure, it also includes a capacitor structure located on the surface of the semiconductor substrate and connected to this transistor. Isolated, the capacitor structure includes a second ion doped region in the semiconductor substrate, a second dielectric layer on the surface of the second ion doped region, and a second conductive gate stacked on the second dielectric layer , And the second conductive gate is electrically connected to the first conductive gate to serve as a floating gate.

In addition, whether it is a single gate transistor structure or a floating gate structure, the implanted ions of the same type can increase the ion concentration in the semiconductor substrate or the first ion doping region by 1 to 10 times.

Wherein, when the above-mentioned transistor structure of the present invention is an N-type transistor, the first ion-doped region or the second ion-doped region is an N-type doped region, and the semiconductor substrate is a P-type semiconductor substrate or has a P-type well Semiconductor substrate. When the above-mentioned transistor structure is a P-type transistor, the first ion-doped region or the second ion-doped region is a P-type doped region, and the semiconductor substrate is an N-type semiconductor substrate or a semiconductor substrate with an N-type well .

Regardless of whether it is a single gate structure or a floating gate structure, there are different operating methods due to the different regions to increase the ion concentration and the different types of transistors.

When the above-mentioned transistor is an N-type transistor and the same type ions are implanted in the first ion doping region to increase its ion concentration, the erasing method of the present invention includes connecting the first conductive gate or floating gate, source A gate voltage V _g , a source voltage V _s , a drain voltage V _d and a substrate voltage V _sub are respectively applied to the electrode, the drain electrode and the semiconductor substrate, and meet the following conditions: V _sub = ground, V _d = high voltage, V _s = floating, and V _g =0 or less than 2V; or satisfying V _sub = ground, V _s = high voltage, V _d = floating, and V _g =0 or less than 2V.

When the above-mentioned transistor is a P-type transistor and the same type ions are implanted in the first ion doping region to increase its ion concentration, the erasing method of the present invention includes connecting the first conductive gate or floating gate, source A gate voltage V _g , a source voltage V _s , a drain voltage V _d and a substrate voltage V _sub are respectively applied to the electrode, the drain electrode and the semiconductor substrate, and meet the following conditions: V _sub = high voltage, V _s =0, V _d = floating, and V _g = high voltage or less than high voltage within 2V; or satisfy V _sub = high voltage, V _d =0, V _s = floating, and V _g = high voltage or less than high voltage within 2V.

When the above-mentioned transistors are either P-type transistors or N-type transistors, and increasing the concentration is to implant homo-type ions in the semiconductor substrate to increase its ion concentration, the erasing method of the present invention includes the first conductive gate or floating Connect the gate, source, drain and semiconductor substrate to apply a gate voltage V _g , source voltage V _s , drain voltage V _d and substrate voltage V _{sub respectively} , and meet the following conditions: When the transistor is an N-type electric Crystal, meet V _sub = ground, V _d = high voltage, V _s = floating, and V _g =0 or less than 2V; or meet V _sub = ground, V _s = high voltage, V _d = floating, and V _g = 0 or less than 2V. When the transistor is a P-type transistor, V _sub = high voltage, V _s =0, V _d = floating, and V _g = high voltage or less than high voltage within 2V; or V _sub = high voltage, V _d =0, V _s = floating, and V _g = high voltage or less than 2V.

The following detailed descriptions are provided with specific embodiments and accompanying drawings, so that it is easier to understand the purpose, technical content and effects of the present invention.

The present invention mainly provides a low-voltage fast erasing method for electronic write erasable rewritable read-only memory, which is applied to electronic write erasable rewritable read-only memory. This electronic write erasable rewritable read-only memory The read memory uses the increase of ion implantation concentration to increase the electric field between the transistor or the substrate and the gate, thereby reducing the voltage difference of erasing. With the erasing method of the present invention, the operating voltage is applied to all memories at the same time The gate, source, and drain of the cell are connected, and the condition that the source or drain is floating during erasing is used to achieve the effect of quickly erasing a large number of memory cells.

As shown in the first (a) and the first (b), the electronic write-erasable rewritable read-only memory proposed by the present invention mainly includes: a semiconductor substrate 10 with at least one transistor structure system Formed on the semiconductor substrate 10, the transistor structure 12 includes a first dielectric layer 14 located on the surface of the semiconductor substrate 10. A first conductive gate 16 is provided on the first dielectric layer 14, and at least two second An ion-doped region (18, 20) is respectively located in the semiconductor substrate 10 and on two sides of the first conductive gate 16 to serve as the source 18 and the drain 20 respectively. Among them, the present invention can use the voltage difference between the source/drain and the gate or the voltage difference between the substrate/well and the gate to allow electrons to pass through the dielectric layer (oxide layer) to achieve low current The erasure. Therefore, there are two ways to increase the ion implantation concentration. As shown in Figure 1(a), the first ion implantation is used at the junction of the first conductive gate 16 and the source 18 and the drain 20. The same type ions 22 are implanted in the doped regions 18, 20, that is, the first ion doped regions 18, 20 are P-type, then the P-type ions 22 are implanted, and the N-type ions 22 are implanted to increase The ion concentration increases the ion concentration in the first ion doped regions 18, 20 by 1 to 10 times the original concentration, so that the applied voltage is different from the transistor structure and the first conductive gate for erasing, and This reduces the voltage difference of erasing. The other is as shown in Figure 1 (b), using ion implantation in the semiconductor substrate 10 at the junction of the first conductive gate 16 and the source 18 and drain 20, and then implant the same type ions 22, that is, semiconductor If the substrate is P-type, P-type ions 22 are implanted, and N-type ions 22 are implanted to increase the ion concentration. Similarly, the ion concentration in the semiconductor substrate 10 is increased by 1 to 10 times the original concentration. In order to apply a voltage difference between the semiconductor substrate and the first conductive gate for erasing.

Continuing, a spacer (not shown in the figure) is further provided on the two sidewalls of the first dielectric layer and the second conductive gate of the transistor structure, and the first conductive gate 16 and the source 18 are in contact with each other. The same-type ions implanted in the first ion-doped region at the junction of the drain electrode 20 are implanted before the spacer is formed to increase the concentration of the doped region, and the first ion-doped region 18 , 20 has a lightly doped drain (LDD), at this time, the preferred doping position is this lightly doped drain (LDD) region.

Among them, in addition to the single gate structure described above, the method of using the aforementioned two structures to increase the ion concentration in the present invention is also applicable to a single floating gate structure. The only difference is that if it is a single floating gate structure, the present invention It further includes a capacitor structure, which electrically connects the second conductive gate electrode of the capacitor structure to the first conductive gate electrode as a single floating gate electrode. The detailed structure application and operation method will be explained in order as follows.

First, please refer to the second figure. The single memory cell structure of the electronic write-erasable rewritable read-only memory includes a P-type semiconductor substrate 30, which can also be a semiconductor substrate with P-type wells. Take the P-type semiconductor substrate 30 as an example. On the P-type semiconductor substrate 30, an N-type transistor 32, such as an N-type metal oxide semi-field effect transistor (MOSFET), is provided. The N-type transistor system includes a first dielectric layer 320 Located on the surface of the P-type semiconductor substrate 30, a first conductive gate electrode 322 is stacked above the first dielectric layer 320, and two N-type ion-doped regions are located in the P-type semiconductor substrate 30 to serve as their source electrodes 324, respectively And the drain electrode 326, a channel is formed between the source electrode 324 and the drain electrode 326; the first conductive gate electrode 322 includes a floating gate electrode 3221, a control dielectric layer 3222, and a control The gates 3223 are respectively stacked on the first dielectric layer 320, which is a single gate structure.

Secondly, please refer to the third figure again. The single memory cell structure of the electronic write-erasable rewritable read-only memory includes a P-type semiconductor substrate 30 on which an N-type transistor 32 and an N-type well are arranged. The (N-well) capacitor 34 is separated by an isolation element 36 between the two. The N-type transistor 32, such as an N-type metal oxide half field effect transistor (MOSFET), includes a first dielectric layer 320 on the surface of the P-type semiconductor substrate 30, and a first conductive gate 322 stacked on the first Above the dielectric layer 320 and two N-type ion doped regions are located in the P-type semiconductor substrate 30 to serve as its source 324 and drain 326 respectively, and a channel is formed between the source 324 and the drain 326. The N-type well capacitor 34 includes a second ion-doped region in the P-type semiconductor substrate 30 as an N-type well 340. A second dielectric layer 342 is located on the surface of the N-type well 340 and is located on the second dielectric layer 342 A second conductive gate 344 is provided on the top to form a top plate-dielectric layer-bottom plate capacitor structure. The first conductive gate 322 of the N-type transistor 32 and the second conductive gate 344 of the N-type well capacitor 34 are electrically connected and isolated by the isolation element 36 to form a single floating gate (floating gate). ) The structure of 38.

Please refer to the second and third diagrams at the same time. Regardless of the memory cell structure shown in the second or third diagram, the electronic write-erasable rewritable read-only memory has an N-type transistor 32 , And the source 324 and drain 326 ion doped regions near the junction of the first conductive gate 322 are implanted with N-type ions of the same type to increase the ion concentration, for example, by 1-10 times The erasing method of the present invention includes: applying a gate voltage V _g and a source voltage to the first conductive gate 322 or the single floating gate 38, the source 324, the drain 326, and the P-type semiconductor substrate 30, respectively V _s , drain voltage V _d and substrate voltage V _sub , and meet the following conditions at the same time: When the N-type transistor 32 is erased, V _sub = ground, V _d = high voltage, V _s = floating, and V _g =0 or less than 2V; or satisfy V _sub = ground, V _s = high voltage, V _d = floating, and V _g =0 or less than 2V.

Continuing, referring to the second and third diagrams at the same time, when the electronic write-erasable rewritable read-only memory has an N-type transistor 32 and is close to the first conductive gate 322 and the source The P-type semiconductor substrate 30 at the junction of 324 and the drain electrode 326 is further implanted with P-type ions of the same type to increase its ion concentration, for example, by 1-10 times. The erasing method of the present invention includes: applying a gate voltage V _g and a source voltage V to the first conductive gate 322 or the single floating gate 38, the source 324, the drain 326, and the P-type semiconductor substrate 30, respectively _s , drain voltage V _d and substrate voltage V _sub , and meet the following conditions at the same time: When the N-type transistor 32 is erased, V _sub = ground, V _d = high voltage, V _s = floating, and V _g = 0 or less than 2V; or satisfy V _sub = ground, V _s = high voltage, V _d = floating, and V _g =0 or less than 2V.

Please refer to FIG. 4 again. The single memory cell structure of the electronic write-erasable rewritable read-only memory includes an N-type semiconductor substrate 40, which may also be a semiconductor substrate with N-type wells, where N For example, the N-type semiconductor substrate 40 is provided with a P-type transistor 42, such as a P-type MOSFET. This P-type transistor system includes a first dielectric layer 420 located on On the surface of the N-type semiconductor substrate 40, a first conductive gate electrode 422 is stacked above the first dielectric layer 420, and two P-type ion-doped regions are located in the N-type semiconductor substrate 40 to serve as its source 424 and The drain electrode 426 is formed with a channel between the source electrode 424 and the drain electrode 426; the first conductive gate electrode 422 further includes a floating gate 4221, a control dielectric layer 4222, and a control gate from bottom to top. The poles 4223 are respectively stacked on the first dielectric layer 420, which is a single gate structure.

Then, as shown in Figure 5, the single memory cell structure of the electronic write-erasable rewritable read-only memory includes an N-type semiconductor substrate 40 on which a P-type transistor 42 and a P-type well (N- well) The capacitor 44 is separated by an isolation element 46 between the two. A P-type transistor 42, such as a P-type MOSFET (MOSFET), includes a first dielectric layer 420 on the surface of the N-type semiconductor substrate 40, and a first conductive gate 422 stacked on the first dielectric layer. Above the electrical layer 420, and two N-type ion-doped regions are located in the N-type semiconductor substrate 40 to serve as its source 424 and drain 426, respectively. A channel is formed between the source 424 and the drain 426. The P-type well capacitor 44 includes a second ion-doped region in the N-type semiconductor substrate 40 as a P-type well 440. A second dielectric layer 442 is located on the surface of the P-type well 440 and is located on the second dielectric layer 442 A second conductive gate 444 is provided on the top to form a top plate-dielectric layer-bottom plate capacitor structure. The first conductive gate 422 of the P-type transistor 42 and the second conductive gate 444 of the P-type well capacitor 44 are electrically connected and separated by an isolation element 46 to form a single floating gate (floating gate). ) The structure of 48.

Please refer to the fourth and fifth diagrams at the same time. No matter it is the memory cell structure shown in the fourth or fifth diagram, when this electronic write-erasable rewritable read-only memory has a P-type transistor 42 And in the ion doped region of the source 424 and the drain 426 near the junction of the first conductive gate 422, P-type ions of the same type are implanted to increase the ion concentration, for example, by 1-10 times . The erasing method of the present invention includes: applying a gate voltage V _g and a source voltage V to the first conductive gate 422 or the single floating gate 48, the source 424, the drain 426, and the N-type semiconductor substrate 40, respectively _s , drain voltage V _d and substrate voltage V _sub , and meet the following conditions at the same time: When the P-type transistor 42 is erased, V _sub = high voltage, V _s =0, V _d = floating, and V _g = High voltage or less than high voltage within 2V; or satisfy V _sub = high voltage, V _d =0, V _s = floating, and V _g = high voltage or less than high voltage within 2V.

Continuing, as shown in Figures 4 and 5, when the electronic write-erasable rewritable read-only memory has a P-type transistor 42 and is close to the first conductive gate 422 and the source 424 The N-type semiconductor substrate 40 at the junction with the drain electrode 426 is further implanted with N-type ions of the same type to increase its ion concentration, for example, by 1-10 times. The erasing method of the present invention includes: applying a gate voltage V _g and a source voltage to the first conductive gate 422 or the single floating gate 48, the source 424, the drain 426, and the N-type semiconductor substrate 40, respectively V _s , drain voltage V _d and substrate voltage V _sub , and meet the following conditions at the same time: When the P-type transistor 42 is erased, V _sub = high voltage, V _s =0, V _d = floating, and V _g = High voltage or less than high voltage within 2V; or satisfy V _sub = high voltage, V _d =0, V _s = floating, and V _g = high voltage or less than high voltage within 2V.

According to the electronic write-erasable rewritable read-only memory disclosed in the present invention, since the erasing is related to the concentration of the drive, it may even affect the applied voltage of the source, drain, and gate. Therefore, the source As long as there is a sufficient voltage difference between the drain and gate, the erasing effect can be achieved. Therefore, negative voltage can also be used instead of grounding, which can reduce the conventional high-voltage voltage; for this kind of memory that can achieve low-voltage operation According to the structure, the present invention specifically proposes that the source or drain can be set to a floating condition during erasing, so that the erasing operation of the memory cell is simpler and faster.

The above-mentioned embodiments are only to illustrate the technical ideas and features of the present invention. Their purpose is to enable those familiar with the art to understand the content of the present invention and implement them accordingly. When they cannot limit the scope of the present invention, that is, Any equivalent changes or modifications made in accordance with the spirit of the present invention should still be covered by the patent scope of the present invention.

10: Semiconductor substrate 12: Transistor structure 14: The first dielectric layer 16: first conductive gate 18: Source 20: Dip pole 22: ion 30: P-type semiconductor substrate 32: N-type transistor 320: first dielectric layer 322: first conductive gate 3221: Floating gate 3222: control dielectric layer 3223: control gate 324: Source 326: Drain 34: N type well capacitor 340: N-type well 342: second dielectric layer 344: second conductive gate 36: isolation element 38: Single floating gate 40: N-type semiconductor substrate 42: P-type transistor 420: first dielectric layer 422: first conductive gate 4221: Floating gate 4222: control dielectric layer 4223: control gate 424: Source 426: Explosion 44: P type well capacitor 440: P well 442: second dielectric layer 444: second conductive gate 46: isolation element 48: Single floating gate

The first (a) figure is a structural diagram of the electronic write-erasable rewritable read-only memory of the present invention in the first ion doped region (source/drain) and then ion implantation. The first (b) figure is a structural diagram of the electronic write-erasable rewritable read-only memory of the present invention in a semiconductor substrate and then ion implantation. The second figure is a schematic diagram of a single memory cell structure with an N-type transistor and a single gate structure according to the present invention. The third figure is a schematic diagram of a single memory cell structure with an N-type transistor and a single floating gate structure according to the present invention. The fourth figure is a schematic diagram of a single memory cell structure with a P-type transistor and a single gate structure according to the present invention. The fifth figure is a schematic diagram of a single memory cell structure with a P-type transistor and a single floating gate structure according to the present invention.

30: P-type semiconductor substrate

32: N-type transistor

320: first dielectric layer

322: first conductive gate

3221: Floating gate

3222: control dielectric layer

3223: control gate

324: Source

326: Drain

Claims (17)

A low-voltage rapid erasing method for electronic write-erasable rewritable read-only memory. The electronic write-erasable rewritable read-only memory includes a semiconductor substrate on which at least one N-type transistor structure is provided, The N-type transistor structure has a first conductive gate and at least two first ion-doped regions located in the semiconductor substrate and on two sides of the first conductive gate to serve as a source and a drain respectively, and the The first ion-doped region at the junction of the first conductive gate and the source and drain is further implanted with ions of the same type to increase its ion concentration. The erasing method includes: in the first conductive gate, A gate voltage V _g , a source voltage V _s , a drain voltage V _d and a substrate voltage V _sub are respectively applied to the source, drain and the semiconductor substrate, and meet the following conditions: V _sub = ground, V _d = high voltage , V _s = floating, and V _g =0 or less than 2V; or meet V _sub = ground, V _s = high voltage, V _d = floating, and V _g =0 or less than 2V. The low-voltage fast erasing method of electronic write-erasable rewritable read-only memory as described in claim 1, wherein the electronic write-erasable rewritable read-only memory further includes a capacitor structure on the semiconductor substrate The surface is separated from the at least one N-type transistor structure. The capacitor structure includes a second ion-doped region located in the semiconductor substrate, and a second conductive gate electrically connected to the first conductive gate to serve as Single floating gate, at this time, the single floating gate applies the gate voltage V _g . The low-voltage fast erasing method for electronic write-erasable rewritable read-only memory according to claim 1, wherein implanting the same type of ion increases the ion concentration in the semiconductor substrate or the first ion doping region 1 to 10 times. The low-voltage fast erasing method for electronic write-erasable rewritable read-only memory as described in claim 1, wherein the N-type transistor structure is an N-type metal oxide half field effect transistor (MOSFET). According to the low-voltage fast erasing method of electronic write erasable rewritable read-only memory according to claim 1, wherein the first doped region further includes a lightly doped drain (LDD). A low-voltage fast erasing method for electronic write-erasable rewritable read-only memory. The electronic write-erasable rewritable read-only memory includes a semiconductor substrate on which at least one P-type transistor structure is provided, The P-type transistor structure has a first conductive gate and at least two first ion-doped regions located in the semiconductor substrate and on two sides of the first conductive gate to serve as a source and a drain respectively, and the The first ion-doped region at the junction of the first conductive gate and the source and drain is further implanted with ions of the same type to increase its ion concentration. The erasing method includes: in the first conductive gate, A gate voltage V _g , a source voltage V _s , a drain voltage V _d and a substrate voltage V _sub are respectively applied to the source, drain and the semiconductor substrate, and meet the following conditions: V _sub = high voltage, V _s =0 , V _d = floating, and V _g = high voltage or less than high voltage within 2V; or satisfy V _sub = high voltage, V _d =0, V _s = floating, and V _g = high voltage or less than high voltage within 2V. The low-voltage fast erasing method of electronic write-erasable rewritable read-only memory as described in claim 6, wherein the electronic write-erasable rewritable read-only memory further includes a capacitor structure on the semiconductor substrate The surface is separated from the at least one P-type transistor structure. The capacitor structure includes a second ion-doped region located in the semiconductor substrate, and a second conductive gate electrically connected to the first conductive gate to serve as Single floating gate, at this time, the single floating gate applies the gate voltage V _g . The low-voltage fast erasing method for electronic write-erasable rewritable read-only memory according to claim 6, wherein implanting the same type ions increases the ion concentration in the semiconductor substrate or in the first ion doped region 1 to 10 times. According to claim 6, the low-voltage fast erasing method of electronic write erasable rewritable read-only memory, wherein the P-type transistor structure is a P-type metal oxide semi-field effect transistor (MOSFET). According to claim 6, the low-voltage fast erasing method of electronic write erasable rewritable read-only memory, wherein the first doped region further includes a lightly doped drain (LDD). A low-voltage fast erasing method for electronic write-erasable rewritable read-only memory. The electronic write-erasable rewritable read-only memory includes a semiconductor substrate on which at least one transistor structure is provided. The crystal structure has a first conductive gate and at least two first ion-doped regions located in the semiconductor substrate and on two sides of the first conductive gate to serve as a source and a drain respectively, and the first conductive gate The semiconductor substrate at the junction of the electrode and the source and drain is further implanted with homo-type ions to increase the ion concentration. The erasing method includes: applying the first conductive gate, the source, the drain, and the semiconductor A gate voltage V _g , a source voltage V _s , a drain voltage V _d and a substrate voltage V _sub are respectively applied to the substrate, and meet the following conditions: When the transistor structure is an N-type transistor: meet V _sub = ground, V _d = high voltage, V _s = floating, and V _g =0 or less than 2V; or V _sub = ground, V _s = high voltage, V _d = floating, and V _g =0 or less than 2V; and when The transistor structure is a P-type transistor: V _sub = high voltage, V _s =0, V _d = floating, and V _g = high voltage or less than 2V; or V _sub = high voltage, V _d =0, V _s = floating, and V _g = high voltage or less than 2V. The low-voltage fast erasing method of electronic write-erasable rewritable read-only memory according to claim 11, wherein the electronic write-erasable rewritable read-only memory further includes a capacitor structure located on the semiconductor substrate The surface is isolated from the at least one transistor structure. The capacitor structure includes a second ion-doped region located in the semiconductor substrate, and a second conductive gate electrically connected to the first conductive gate to serve as a single floating When the gate is connected, the single floating gate applies the gate voltage Vg. The low-voltage fast erasing method for electronic write-erasable rewritable read-only memory according to claim 12, wherein when the transistor structure is the N-type transistor, the first ion-doped region and the second The two-ion doped region is an N-type doped region, and the semiconductor substrate is a P-type semiconductor substrate or a semiconductor substrate with a P-type well; and when the transistor structure is the P-type transistor, the first ion The doped region and the second ion doped region are P-type doped regions, and the semiconductor substrate is an N-type semiconductor substrate or a semiconductor substrate with an N-type well. The low-voltage fast erasing method for electronic write-erasable rewritable read-only memory according to claim 11, wherein when the transistor structure is the N-type transistor, the first ion doping region is N Type doped region, and the semiconductor substrate is a P-type semiconductor substrate or a semiconductor substrate with a P-type well; and when the transistor structure is the P-type transistor, the first ion doped region is P-type doped Miscellaneous regions, and the semiconductor substrate is an N-type semiconductor substrate or a semiconductor substrate with an N-type well. The low-pressure fast erasing method for electronic write-erasable rewritable read-only memory according to claim 11, wherein implanting the same type of ion increases the ion concentration in the semiconductor substrate or the first ion doped region 1 to 10 times. According to claim 11, the low-voltage fast erasing method of electronic write erasable rewritable read-only memory, wherein the transistor structure is a metal oxide semi-field effect transistor (MOSFET). According to claim 11, the low-voltage fast erasing method of electronic write erasable rewritable read-only memory, wherein the first doped region further includes a lightly doped drain (LDD).

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