TW202034317A - Current-voltage converting circuit, reference voltage generating circuit and non-volatile semiconductor storage device - Google Patents

Abstract

A reference voltage generating circuit supplying stable reference voltage in a layout area smaller than prior art is provided. The reference voltage generating circuit includes a current-voltage converting circuit and outputs a reference voltage based on an output voltage of the current-voltage converting circuit. The current-voltage converting circuit includes a first current mirror circuit including a first MOS transistor and a second MOS transistor, an output resistor, and a depletion type N-channel MOS transistor. The depletion type N-channel MOS transistor is inserted between an inputted first voltage and the first MOS transistor and the second MOS transistor, and has a gate with a feedback output voltage from the output resistor. The current-voltage converting circuit generates the output voltage by a current corresponding to a reference current flowing into the second MOS transistor and the output resistor as the reference current flowed into the first MOS transistor.

Description

Current-voltage conversion circuit, reference voltage generating circuit and non-volatile semiconductor storage device

The present invention relates to a current-voltage conversion circuit, a reference voltage generating circuit using the current-voltage conversion circuit, and a non-volatile semiconductor storage device using the reference voltage generating circuit.

FIG. 1 is a block diagram showing a configuration example of a voltage generating circuit used in a NAND flash memory in the prior art. Non-volatile semiconductor storage devices such as reverse flash memory require many types of voltages for reading, programming, and erasing operations. Generally, as shown in FIG. 1, these voltages are generated by voltage generating circuits such as a charge pump circuit 21 and a regulator circuit 22, and pass through a word line decoder circuit 11 It is supplied to the memory array 10. [Prior Art Literature] [Patent Literature]

[Patent Document 1] Japanese Patent Laid-Open No. 2013-196622

[The problem to be solved by the invention]

However, there is a voltage ripple in the output voltage from the charge pump circuit 21, which affects the pressure of the memory cell and is dependent on the position of the word line (FIG. 1). In order to reduce the ripple, several voltages are supplied to the self-regulator circuit 22, but there is a problem of consuming extra layout area.

The purpose of the present invention is to solve the above problems and provide a current-voltage conversion circuit that can supply a stable reference voltage in a smaller layout area than the prior art, a reference voltage generating circuit using the current-voltage conversion circuit, and the use of all The non-volatile semiconductor storage device of the reference voltage generating circuit. [Means to solve the problem]

The current-to-voltage conversion circuit of the present invention is characterized by including: The first current mirror circuit includes a pair of first Metal Oxide Semiconductor (MOS) transistors, a second MOS transistor, and an output resistor; and a depletion N-channel MOS transistor, which is inserted into the first input Voltage between the first MOS transistor and the second MOS transistor, and has a gate that is fed back the output voltage from the output resistor; and when a reference current has been input to the first MOS transistor In the middle, the output voltage is generated by the current corresponding to the reference current flowing in the second MOS transistor and the output resistor. [Effects of the invention]

Therefore, according to the present invention, it is possible to provide a current-voltage conversion circuit capable of supplying a stable reference voltage in a smaller layout area than the prior art, a reference voltage generating circuit using the current-voltage conversion circuit, and a reference voltage generating circuit using the reference voltage Circuit of non-volatile semiconductor storage device.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, the same reference numerals are given to the same or the same constituent elements.

(Comparative example) 2A is a circuit diagram showing a configuration example of a current-voltage conversion circuit of a comparative example. Furthermore, for example, Patent Document 1 discloses a current-voltage conversion circuit using a current mirror circuit.

In FIG. 2A, a simple current mirror circuit including a pair of P-channel MOS transistors M1 and P-channel MOS transistors M2 to convert current into voltage is shown. Here, the gate and source of MOS transistor M1 are respectively connected to the gate and source of MOS transistor M2, and the gates of MOS transistor M1 and MOS transistor M2 are connected to the drain of MOS transistor M1. Between the drain of the MOS transistor M2 and the ground, a variable resistor R1 for adjusting the output voltage VOUT is connected. Furthermore, during installation, the variable resistor R1 uses, for example, a semi-fixed resistor that can be set digitally.

In the current-voltage conversion circuit configured as described above, the power supply voltage V1 is applied to each source of the MOS transistor M1 and the MOS transistor M2. Since the MOS transistor M1 and MOS transistor M2 constitute the current mirror circuit, if the reference current Iref1 flows into the MOS transistor M1, the current Iref2 corresponding to the reference current Iref1 flows into the MOS transistor M2 and the variable resistor R1. At this time, the output voltage VOUT is generated and output in the variable resistance R1 as the output resistance.

Here, the output voltage VOUT must consider the breakdown voltage BVds2 between the drain and the source of the MOS transistor M2. The output voltage VOUT may be set to, for example, 0 V, so the power supply voltage V1 must be made smaller than the breakdown voltage BVds2.

(Embodiment 1) 2B is a circuit diagram showing a configuration example of the current-voltage conversion circuit of the first embodiment. Compared with the current-voltage conversion circuit of FIG. 2A, the current-voltage conversion circuit of FIG. 2B is different in the following aspects. (1) A depletion type N-channel MOS transistor DM1 is inserted between the power supply voltage V1 and each source of a pair of MOS transistors M1 and MOS transistors M2.

In FIG. 2B, the drain of the MOS transistor DM1 is connected to the power supply voltage V1, and the source of the MOS transistor DM1 is connected to the sources of the MOS transistor M1 and the MOS transistor M2. The gate (control terminal) of the MOS transistor DM1 is connected to one end of the variable resistor R1 and the terminal of the output voltage VOUT. Furthermore, the voltage of each source of MOS transistor M1 and MOS transistor M2 is set to V2.

In the current-to-voltage conversion circuit constructed as described above, a pair of MOS transistors M1 and MOS transistors M2 constitute a current mirror circuit. Here, between the node N2 of the voltage V2 and the node N1 of the voltage V1, a depletion N-channel MOS transistor DM1 is inserted. The gate of the MOS transistor DM1 is connected to the terminal of the output voltage VOUT, and the output voltage VOUT is fed back to The gate. Thereby, the current flowing into the MOS transistor DM1 corresponding to the output voltage VOUT is controlled, thereby controlling the voltage V2 of the node N2.

Fig. 2C is a graph showing a comparison of the operations of the current-voltage conversion circuits of Figs. 2A and 2B.

The depleted N-channel MOS transistor DM1 has a negative threshold voltage Vth. Therefore, as shown in FIG. 2C, the voltage V2 of the node N2 is controlled by maintaining the output voltage VOUT+Vth of the MOS transistor DM1. This means that the breakdown voltage BVds2 is always maintained near the threshold voltage Vth of the MOS transistor DM1. Therefore, as long as the threshold voltage Vth of the MOS transistor DM1 is less than the breakdown voltage BVds2, the output voltage VOUT is supplied with a higher voltage than the current-voltage conversion circuit of FIG. 2A.

The next breakdown voltage higher than the breakdown voltage Vds2 of the MOS transistor DM1 is the junction breakdown voltage BVj. If the voltage V1 is set close to the junction breakdown voltage BVj, the maximum value of the output voltage VOUT approximately becomes V1-Vth.

As explained above, as is clear from FIG. 2C, it can be seen that the presence of the threshold voltage Vth of the MOS transistor DM1 causes the voltage range VR2 of the current-voltage conversion circuit of FIG. 2B to be greater than that of the current-voltage conversion circuit of FIG. 2A. The voltage range VR1 is greatly expanded. In addition, the current-voltage conversion circuit of FIG. 2B may constitute a reference voltage generating circuit that generates an output voltage VOUT as a reference voltage corresponding to the reference current Iref1.

(Embodiment 2) FIG. 3 is a block diagram showing a configuration example of a voltage generating circuit for a NAND flash memory according to the second embodiment.

In FIG. 3, the reference voltage generating circuit 24 is constituted by a reference voltage generating circuit using, for example, a current-to-voltage conversion circuit including a current mirror circuit of Embodiment 1, and generates a predetermined reference voltage VREF based on the voltage from the charge pump circuit 23 and It is applied to the gate of MOS transistor Q1. On the other hand, the clamping operation performed by the MOS transistor Q1 clamps the voltage from the charge pump circuit 21 to a predetermined voltage or less corresponding to the reference voltage VREF. This clamping method can be called a clamping MOS method. The MOS transistor Q1 of the clamp MOS method of FIG. 3 can be used to supply the word line voltage to be supplied to the word line of the word line decoder circuit 11 and the memory array 10 with reduced ripples compared with the prior art Specified value voltage.

4 is a circuit diagram showing a configuration example of a voltage generating circuit including a reference voltage generating circuit using the current-to-voltage conversion circuit of FIG. 2B. In FIG. 4, it includes a charge pump circuit 21, a charge pump circuit 23, a plurality of reference voltage generating circuits 24-1 to a reference voltage generating circuit 24-4, and MOS transistors M41 to M44 of a clamp MOS method. constitute.

In FIG. 4, each of the reference voltage generating circuit 24-1 to the reference voltage generating circuit 24-4 is characterized in that in the reference voltage generating circuit using the current-voltage conversion circuit of FIG. 2B, the MOS transistor M2 and the variable resistor Between R1, a MOS transistor M3 is inserted to form a current mirror circuit with MOS transistor M41 to MOS transistor M44 of the clamp MOS method. Here, the gate of MOS transistor M3 is connected to its drain.

The circuit operation of the circuit of the reference voltage generating circuit 24-1 and the MOS transistor M41 will be described below. Based on the voltage V1 from the charge pump circuit 23, the reference voltage generating circuit 24-1 applies the reference voltage VREF, which is the output voltage VOUT corresponding to the reference current Iref1, to the gate of the MOS transistor M41. The MOS transistor M3 and the MOS transistor M41 constitute a current mirror circuit, and the charge pump voltage VCPOUT is applied from the charge pump circuit 21 to the drain of the MOS transistor M41. In these circuits, the current corresponding to the current Iref2 flowing into the MOS transistor M3 flows into the MOS transistor M41, and the target voltage V _TARGET as the source voltage of the MOS transistor M3 can clamp the MOS transistor of the MOS method The clamped reference voltage appears in the source of M41.

In addition, the circuit of the reference voltage generating circuit 24-2 and the MOS transistor M42, the circuit of the reference voltage generating circuit 24-3 and the MOS transistor M43, and the circuit of the reference voltage generating circuit 24-4 and the MOS transistor M44 are also similar to those mentioned above. The circuit operates similarly.

According to the voltage generating circuit of FIG. 4 configured as described above, due to the mirror effect of the current mirror circuit, the target voltage V _TARGET is correctly transmitted to the memory array 10 from the charge pump circuit 21, the charge The ripple of the pump circuit 23 sharply decreases.

(Embodiment 2) FIG. 5 is a block diagram showing a specific configuration example of a voltage generating circuit for a reverse flash memory according to the second embodiment.

In FIG. 5, the voltage generating circuit includes a plurality of charge pump circuits 21 in order to generate the following various voltages used in the reverse flash memory and supply them to the memory array 10 through the word line decoder circuit 11 -1 to a charge pump circuit 21-4, and a plurality of regulator circuits 22-1 and 22-2. (1) the programming voltage V _PGM; (2) a voltage for unselected word lines V _PASS1 / voltage V _PASS2 / voltage V _PASS3; (3) read or verify voltage V _RD; (4) select gate voltage V _SG ; (5) Other voltages.

Here, the regulator circuit 22-1 and the regulator circuit 22-2 can be constructed using the reference voltage generating circuit, for example, and in particular, the more accurate voltage V _PASS1 and the voltage V _{RD that} must reduce the ripple are provided by the regulator circuit 22-1. The regulator circuit 22-2 is generated.

6A is a circuit diagram for explaining conditions for applying operating voltages to the low voltage side of a word line in the second embodiment. In addition, FIG. 6B is a circuit diagram for explaining the conditions for applying each operating voltage to the high voltage side of the word line in the second embodiment.

FIG. 6A is a diagram illustrating the conditions for applying various operating voltages to the low voltage side of the word line, and the circuit with the voltage V _{PASS3 bears} the most load. In contrast, if the selected word line moves toward the high voltage side, as shown in FIG. 6B, the load on the circuit of voltage V _PASS3 is significantly reduced, and the heaviest load is _received on the circuit of voltage V _PASS2 . In particular, in circuits of unselected voltages, the circuit scale of each charge pump circuit becomes larger, and it is necessary to cover a wide range of loads.

(Embodiment 3) FIG. 7 is a block diagram showing a specific configuration example of a voltage generating circuit for a NAND flash memory of the third embodiment.

In FIG. 7, the reference voltage generating circuit 24 is configured using the circuit of FIG. 4, and generates a predetermined reference voltage VREF based on the voltage V1 from the charge pump circuit 23, and applies it to the clamped MOS method MOS transistor M51. ~ In each gate of MOS transistor M55. On the other hand, MOS transistors M51 to M55 of the clamp MOS method are used to generate predetermined and necessary voltages for the charge pump voltage VCPOUT from the charge pump circuit 21 and supply them to the memory via the word line decoder circuit 11.体array10中。 Volume array 10.

The voltage generating circuit of FIG. 7 includes a charge pump circuit 21. If the charge pump circuit is used, the total load is the same, and various voltages can be generated regardless of the position of the selected word line, and the layout area can be saved.

Fig. 8 is a graph showing an example of voltage generation by the voltage generation circuit of Fig. 7. As is clear from FIG. 8, there are still some ripples in the charge pump voltage VCPOUT from the charge pump circuit, but after passing through the clamp MOS method MOS transistor M51 to MOS transistor M55, the ripple is sufficiently reduced.

(Embodiment 4) FIG. 9 is a block diagram showing a configuration example of a voltage generating circuit for a NAND flash memory according to the fourth embodiment. Although the voltage generating circuit of Fig. 7 can reduce noise, the accuracy of correcting the output voltage is still not high. In order to solve this problem, the voltage generating circuit of FIG. 9 is proposed.

In FIG. 9, a current mirror circuit 50 is formed by MOS transistor M3 and MOS transistor M4, and a source follower circuit for applying appropriate voltages to each node of the memory array 10 is formed. ) 60. In order to forcibly change the respective voltages to appropriate voltages, the MOS transistor M5 of the source follower circuit 60 through which the tail current I _TC flows by applying a predetermined bias gate voltage VBIAS to the MOS transistor M5 of the source follower circuit 60 and The MOS transistor M4 is connected in series. Furthermore, C _LOAD represents the parasitic capacitance of the voltage supply line.

According to the voltage generating circuit of FIG. 9 configured as described above, the current densities of the MOS transistor M3 and the MOS transistor M4 become the same. Since the same current density, the same threshold voltage Vth of the threshold voltage of the MOS transistor of the MOS transistors M3 and M4 Vth, target voltage V _TARGET so as each voltage V _RD, the voltage V _PASS1 ~ voltage V _PASS3, and the voltage The V _PGM is transferred to the memory array 10 correctly.

(Modification) In the above embodiments, the voltage generating circuit used in the NAND flash memory has been described, but the present invention is not limited to this, and can also be applied to other various non-volatile semiconductor storage devices.

10: Memory array 11: Word line decoder circuit 21, 23, 21-1~21-4: Charge pump circuit 22, 22-1, 22-2: Regulator circuit 24, 24-1~24-4: Reference voltage generating circuit 50: current mirror circuit 60: source follower circuit BVds2, Vds2: breakdown voltage BVj: junction breakdown voltage C _LOAD : parasitic capacitance D: drain DM1, M1 ~ M55, Q1: MOS transistor G: gate pole Iref1: a reference current Iref2: current I _TC: tail current N1, N2: node R1: variable resistor S: source V1: mains voltage _{V2, V PASS1, V PASS2,} V PASS3: voltage VBIAS: gate bias voltage VCPOUT: charge pump voltage VOUT: output voltage V _PGM : programming voltage V _RD : read or verify voltage; VR1, VR2: voltage range VREF: reference voltage Vth: threshold voltage V _TARGET : target voltage

FIG. 1 is a block diagram showing an example of the structure of a voltage generating circuit for a NAND flash memory in the prior art. 2A is a circuit diagram showing a configuration example of a current-voltage conversion circuit of a comparative example. 2B is a circuit diagram showing a configuration example of the current-voltage conversion circuit of the first embodiment. Fig. 2C is a graph showing a comparison of the operations of the current-voltage conversion circuits of Figs. 2A and 2B. FIG. 3 is a block diagram showing a configuration example of a voltage generating circuit for a NAND flash memory according to the second embodiment. 4 is a circuit diagram showing a configuration example of a voltage generating circuit including a reference voltage generating circuit using the current-to-voltage conversion circuit of FIG. 2B. FIG. 5 is a block diagram showing a specific configuration example of a voltage generating circuit for a reverse flash memory according to the second embodiment. 6A is a circuit diagram for explaining conditions for applying operating voltages to the low voltage side of a word line in the second embodiment. 6B is a circuit diagram for explaining the conditions for applying each operating voltage to the high voltage side of the word line in the second embodiment. FIG. 7 is a block diagram showing a configuration example of a voltage generating circuit for a NAND flash memory according to the third embodiment. Fig. 8 is a graph showing an example of voltage generation by the voltage generation circuit of Fig. 7. FIG. 9 is a block diagram showing a configuration example of a voltage generating circuit for a NAND flash memory according to the fourth embodiment.

D: Dip pole

DM1: MOS transistor

G: Gate

Iref1: Reference current

Iref2: current

M1, M2: MOS transistor

N1, N2: Node

R1: Variable resistor

S: source

V1: Power supply voltage

V2: Voltage

Vds2: breakdown voltage

VOUT: output voltage

Claims (6)

A current-to-voltage conversion circuit is characterized by comprising: The first current mirror circuit includes a pair of a first metal oxide semiconductor transistor and a second metal oxide semiconductor transistor and an output resistor; and The depleted N-channel metal oxide semiconductor transistor is inserted between the input first voltage and the first metal oxide semiconductor transistor and the second metal oxide semiconductor transistor, and has the feedback from all The gate of the output voltage of the output resistance; and When a reference current has been input to the first metal oxide semiconductor transistor, an output is generated by a current corresponding to the reference current flowing in the second metal oxide semiconductor transistor and the output resistor Voltage. A reference voltage generating circuit, which is a reference voltage generating circuit including the current-to-voltage conversion circuit as described in item 1 of the scope of patent application, characterized in that: The output voltage of the current-voltage conversion circuit is output as a reference voltage. The reference voltage generating circuit as described in item 2 of the scope of the patent application includes: A third metal oxide semiconductor transistor is inserted between the second metal oxide semiconductor transistor and the output resistor, and has a gate and a drain connected to each other; and The fourth metal oxide semiconductor transistor clamps the input second voltage according to the reference voltage; The third metal oxide semiconductor transistor and the fourth metal oxide semiconductor transistor are constructed as a second current mirror circuit, and The output voltage from the fourth metal oxide semiconductor transistor is output as a reference voltage. The reference voltage generating circuit according to the third item of the scope of patent application, which includes a source follower circuit that outputs the output voltage, and the source of the fourth metal oxide semiconductor transistor Connect and flow the specified current. According to the reference voltage generating circuit described in claim 4, the source follower circuit includes a fifth metal oxide semiconductor transistor having a gate to which a prescribed bias voltage has been applied. A non-volatile semiconductor storage device, which is a non-volatile semiconductor storage device including a memory array, is characterized in that: Including the reference voltage generating circuit described in any one of items 2 to 5 of the scope of the patent application, and The output voltage from the reference voltage generating circuit is supplied to the memory array of the non-volatile semiconductor storage device.

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