CN104779948A - Square law expander circuit - Google Patents
Square law expander circuit Download PDFInfo
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- CN104779948A CN104779948A CN201510106955.XA CN201510106955A CN104779948A CN 104779948 A CN104779948 A CN 104779948A CN 201510106955 A CN201510106955 A CN 201510106955A CN 104779948 A CN104779948 A CN 104779948A
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- Prior art keywords
- pmos
- amplifier
- square
- nmos tube
- voltage
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Abstract
The invention discloses a square law expander circuit, which comprises two amplifiers, two PMOS (P-channel Metal Oxide Semiconductor) tubes, an NMOS (N-channel Metal Oxide Semiconductor) tube and a resistor, wherein two parallel branches are arranged between the working voltage and the ground; the first branch is formed by the PMOS tube I and the NMOS tube I which are connected in series; the second branch is formed by the PMOS tube II and the resistor which are connected in series; an input end of the circuit is connected to a grid electrode of the NMOS tube I through the amplifier I; and a drain electrode of the PMOS tube II is connected to an output end of the circuit through the amplifier II. According to the square law expander circuit, the voltage of the output end of the circuit has a square relation with the voltage of the input end of the circuit, and the square law expander circuit can be used for design of an IP (Intellectual Property) core.
Description
Technical field
The application relates to the expanded circuit in a kind of compandor (compander, compander).
Background technology
Some signal has very large dynamic range (dynamic range), such as audio signal, light signal etc.These signals handled by electronic equipment, such as, can carry out transmitting or storing, expand (expand) again for primary signal during use after compression (compress).
The Chinese invention patent application that application publication number is CN101800051A, Shen Qing Publication day is on August 11st, 2010 discloses a kind of system of audio signal, which includes the expander of the dynamic range for extended audio signal, Fig. 5 of this file gives a kind of example of expander.
The Chinese utility model patent that mandate publication No. is CN202586939U, mandate date of publication is on December 5th, 2012 briefly introduces audio frequency companding technology, and discloses a kind of voice receiver.Which includes the digital expander of the dynamic range for expanding digital audio signal, Fig. 5 of this file gives a kind of example of digital expander.
Traditional expansion means normally utilize the exponential relationship between the current strength of PN junction and bias voltage, and such as conventional in telephone communication μ restrains (μ-law) companding and A restrains (A-law) companding.Adopt the expanded circuit of logarithmic companding usually to manufacture PN junction with bipolar process, and be not suitable for and manufacture with CMOS technology.
Summary of the invention
Technical problems to be solved in this application are to provide a kind of square-law expanded circuit, and input voltage can be made to expand to output voltage according to quadratic relationship, and this expanded circuit is compatibility standard CMOS technology also.
For solving the problems of the technologies described above, the application's square-law expanded circuit comprises two amplifiers, two PMOS, a NMOS tube and resistance; There are between operating voltage and ground two parallel branches; First branch road is PMOS one and the NMOS tube one of series connection; Second branch road is PMOS two and the resistance of series connection; Described PMOS one and PMOS two constitute current mirror, make the electric current of two parallel branches identical or become integral multiple; Circuit input end connects the grid of NMOS tube one by amplifier one; The drain electrode of PMOS two is by amplifier two connecting circuit output.
The application can make circuit output end voltage become quadratic relationship with circuit input end voltage, can be used for the design of IP kernel.
Accompanying drawing explanation
Fig. 1 is the output voltage dynamic range of expanded circuit and the schematic diagram of input voltage dynamic range;
Fig. 2 is a specific embodiment of the application's square-law expanded circuit;
Fig. 3 is the simulation result schematic diagram of the application's square-law expanded circuit.
Embodiment
Refer to Fig. 1, the application is used to provide a kind of expanded circuit, can be the larger dynamic range of output voltage by the less dynamic range expansion of input voltage.
Refer to Fig. 2, the square-law expanded circuit of the application comprises two amplifiers, two PMOS, a NMOS tube and resistance.Between operating voltage VDD and ground GND, there are two parallel branches.
First branch road is PMOS one MP1 and NMOS tube one MN1 of series connection, and electric current is i1.Such as, operating voltage VDD connects the source electrode of PMOS one MP1, and the drain electrode of PMOS one MP1 connects the drain electrode of NMOS tube one MN1, and the source electrode of NMOS tube one MN1 connects ground GND.
Second branch road is PMOS two MP2 and the resistance R of series connection, and electric current is i2.Such as, operating voltage VDD connects the source electrode of PMOS two MP2, the first end of the drain electrode contact resistance R of PMOS two MP2, and second end of resistance R connects ground GND.
In described two parallel branches, PMOS one MP1 and PMOS two MP2 constitutes current mirror (currentmirror), this make the electric current of two parallel branches identical or become integral multiple.In addition, the grid of PMOS one MP1 is connected with the grid of PMOS two MP2, and is connected with the drain electrode of NMOS tube one MN1 with the drain electrode of PMOS one MP1.
Circuit input end IN connects the grid of NMOS tube one MN1 by amplifier one AMP1.Such as, circuit input end IN connects the positive input terminal of amplifier one AMP1, and the negative input end of amplifier one AMP1 is connected with output and is connected the grid of NMOS tube one MN1.
The drain electrode of PMOS two MP2 is by amplifier two AMP2 connecting circuit output OUT.Such as, the drain electrode of PMOS two MP2 connects the positive input terminal of amplifier two AMP2, and the negative input end of amplifier two AMP2 is connected with output and connecting circuit output OUT.
The operation principle of the square-law expanded circuit of the application is as follows.For ease of describing, the grid of NMOS tube one MN1 being called A point, the drain electrode of PMOS two MP2 is called B point.Amplifier one AMP1, PMOS one MP1 and resistance R constitute a voltage follower (voltage follower), and can obtain formula one for V
a=V
iN, wherein V
arefer to A point voltage, V
iNrefer to circuit input end voltage.NMOS tube one MN1 can obtain formula two according to the current equation of MOSFET (field-effect transistor)
wherein V
tHrefer to the threshold voltage (threshold voltage) of NMOS tube one MN1.PMOS one MP1 and PMOS two MP2 constitutes current mirror, and can obtain formula three for i2=N × i1, and wherein N is positive integer.Resistance R can obtain formula four for V according to Ohm's law
b=i2 × R, wherein V
brefer to B point voltage.Amplifier two AMP2, as buffer amplifier, therefore can obtain formula five for V
oUT=V
b, wherein V
oUTrefer to circuit output end voltage.Can obtain formula six according to above-mentioned formula one to formula five is
by formula six known circuit output end voltage V
oUTwith (V
iN-V
tH)
2be directly proportional, this shows circuit output end voltage V
oUTwith circuit input end voltage V
iNbecome quadratic relationship, this has carried out verifying (as shown in Figure 3) by experiment.
Existing expanded circuit is all based on the exponential relationship between the electric current of PN junction and voltage, bipolar process therefore can only be utilized to form PN junction, can not adopt CMOS technology.And the main flow manufacturing process of large scale integrated circuit is CMOS technology at present, this application provides the quadratic relationship between a kind of electric current based on MOSFET (metal-oxide type field-effect transistor) and voltage and the square-law expanded circuit that formed, the CMOS technology of main flow can be adopted realize.
These are only the preferred embodiment of the application, and be not used in restriction the application.For a person skilled in the art, the application can have various modifications and variations.Within all spirit in the application and principle, any amendment done, equivalent replacement, improvement etc., within the protection range that all should be included in the application.
Claims (10)
1. a square-law expanded circuit, is characterized in that, comprises two amplifiers, two PMOS, a NMOS tube and resistance; There are between operating voltage and ground two parallel branches; First branch road is PMOS one and the NMOS tube one of series connection; Second branch road is PMOS two and the resistance of series connection; Described PMOS one and PMOS two constitute current mirror, make the electric current of two parallel branches identical or become integral multiple; Circuit input end connects the grid of NMOS tube one by amplifier one; The drain electrode of PMOS two is by amplifier two connecting circuit output.
2. square-law expanded circuit according to claim 1, is characterized in that, described amplifier one, PMOS one and resistance constitute a voltage follower, makes the grid voltage of NMOS tube one equal circuit input end voltage.
3. square-law expanded circuit according to claim 1, is characterized in that, described amplifier two is as buffer amplifier.
4. square-law expanded circuit according to claim 1, is characterized in that, V
oUTwith V
iNbecome quadratic relationship, wherein V
iNcircuit input end voltage, V
oUTcircuit output end voltage.
5. square-law expanded circuit according to claim 4, is characterized in that, V
oUTwith (V
iN-V
tH)
2be directly proportional, wherein V
tHit is the threshold voltage of NMOS tube one.
6. square-law expanded circuit according to claim 1, is characterized in that, in described first branch road, operating voltage connects the source electrode of PMOS one, and the drain electrode of PMOS one connects the drain electrode of NMOS tube one, and the source electrode of NMOS tube one connects ground.
7. square-law expanded circuit according to claim 1, is characterized in that, in described second branch road, operating voltage connects the source electrode of PMOS two, the first end of the drain electrode contact resistance of PMOS two, and the second end of resistance connects ground.
8. square-law expanded circuit according to claim 1, is characterized in that, in described two parallel branches, the grid of PMOS one is connected with the grid of PMOS two, and is connected with the drain electrode of NMOS tube one with the drain electrode of PMOS one.
9. square-law expanded circuit according to claim 1, is characterized in that, the annexation of described amplifier one is: circuit input end connects the positive input terminal of amplifier one, and the negative input end of amplifier one is connected with output and is connected the grid of NMOS tube one.
10. square-law expanded circuit according to claim 1, is characterized in that, the annexation of described amplifier two is: the drain electrode of PMOS two connects the positive input terminal of amplifier two, and the negative input end of amplifier two is connected with output and connecting circuit output.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510106955.XA CN104779948A (en) | 2015-03-11 | 2015-03-11 | Square law expander circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510106955.XA CN104779948A (en) | 2015-03-11 | 2015-03-11 | Square law expander circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104779948A true CN104779948A (en) | 2015-07-15 |
Family
ID=53621226
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510106955.XA Pending CN104779948A (en) | 2015-03-11 | 2015-03-11 | Square law expander circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2020141366A (en) * | 2019-03-01 | 2020-09-03 | 力晶積成電子製造股▲ふん▼有限公司Ｐｏｗｅｒｃｈｉｐ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｍａｎｕｆａｃｔｕｒｉｎｇ Ｃｏｒｐｏｒａｔｉｏｎ | Reference voltage generation circuit and nonvolatile semiconductor memory device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6586995B1 (en) * | 2002-04-03 | 2003-07-01 | Mitsubishi Denki Kabushiki Kaisha | Amplifier |
| CN101796730A (en) * | 2007-07-03 | 2010-08-04 | 爱萨有限公司 | Programmable analog-to-digital converter for low-power DC-DC SMPS |
| CN102983853A (en) * | 2012-11-26 | 2013-03-20 | 电子科技大学 | Analog squaring circuit |
| CN103873066A (en) * | 2014-03-17 | 2014-06-18 | 上海华虹宏力半导体制造有限公司 | Square root compressor circuit |
-
2015
- 2015-03-11 CN CN201510106955.XA patent/CN104779948A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6586995B1 (en) * | 2002-04-03 | 2003-07-01 | Mitsubishi Denki Kabushiki Kaisha | Amplifier |
| CN101796730A (en) * | 2007-07-03 | 2010-08-04 | 爱萨有限公司 | Programmable analog-to-digital converter for low-power DC-DC SMPS |
| CN102983853A (en) * | 2012-11-26 | 2013-03-20 | 电子科技大学 | Analog squaring circuit |
| CN103873066A (en) * | 2014-03-17 | 2014-06-18 | 上海华虹宏力半导体制造有限公司 | Square root compressor circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2020141366A (en) * | 2019-03-01 | 2020-09-03 | 力晶積成電子製造股▲ふん▼有限公司Ｐｏｗｅｒｃｈｉｐ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｍａｎｕｆａｃｔｕｒｉｎｇ Ｃｏｒｐｏｒａｔｉｏｎ | Reference voltage generation circuit and nonvolatile semiconductor memory device |
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| C06 | Publication | ||
| PB01 | Publication | ||
| EXSB | Decision made by sipo to initiate substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20150715 |
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| RJ01 | Rejection of invention patent application after publication |