TW202025502A - Semiconductor structure for improving thermal stability and schottky behavior - Google Patents

Semiconductor structure for improving thermal stability and schottky behavior Download PDF

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TW202025502A
TW202025502A TW107145979A TW107145979A TW202025502A TW 202025502 A TW202025502 A TW 202025502A TW 107145979 A TW107145979 A TW 107145979A TW 107145979 A TW107145979 A TW 107145979A TW 202025502 A TW202025502 A TW 202025502A
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semiconductor
gate
nitrogen
semiconductor structure
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TWI692111B (en
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杜志翰
連羿韋
林哲楷
王偉州
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穩懋半導體股份有限公司
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Abstract

A semiconductor structure for improving the thermal stability and Schottky behavior by engineering the stress in a III-nitride semiconductor, comprising a III-nitride semiconductor and a gate metal layer. The III-nitride semiconductor has a top surface on which a conductive area and a non-conductive area are defined. The gate metal layer is formed directly on the top surface of the III-nitride semiconductor and comprises a gate connection line and at least one gate contact extending from the gate connection line in a second direction perpendicular to the length of the gate connection line. The at least one gate contact forms a Schottky contact with the III-nitride semiconductor on the conductive area, and the gate connection line is in direct contact with the III-nitride semiconductor on the non-conductive area. The non-conductive area of the III-nitride semiconductor is at least partially covered by the gate connection line.

Description

改良熱穩定性及蕭基行為的半導體結構 Semiconductor structure with improved thermal stability and Schauer behavior

本發明係有關一種半導體結構,尤指一種基本以III-氮族半導體製成的半導體結構以及包括該半導體結構的單晶微波積體電路(Monolithic Microwave Integrated Circuit,MMIC)。 The present invention relates to a semiconductor structure, in particular to a semiconductor structure basically made of III-nitrogen semiconductor and a monocrystalline microwave integrated circuit (Monolithic Microwave Integrated Circuit, MMIC) including the semiconductor structure.

III-氮族半導體材料以其寬能隙(band gap)的特性而為人所知,例如氮化鎵(GaN)的能隙高達3.4eV,而氮化鋁(AlN)的能隙甚至可達到6.0eV。此一特性在諸如高功率開關和微波功率放大器等高功率和高頻MMIC的應用上是有益的。一III-氮族半導體MMIC可包括多個III-氮族半導體場效電晶體(FET)。在一常見的電路布局中,此多個III-氮族半導體場效電晶體的閘極接觸層形成一梳狀,其具有成於III-氮族半導體導電區域上的多個閘極接觸指以及形成於III-氮族半導體非導電區域上且連接所有閘極接觸指的一閘極連接線,再由此閘極連接線通過金屬連接線連接到一閘極接觸墊,以輸入控制電壓至電晶體的閘極電極。 III-Nitrogen semiconductor materials are known for their wide band gap characteristics. For example, the band gap of gallium nitride (GaN) is as high as 3.4 eV, while the band gap of aluminum nitride (AlN) can even reach 6.0eV. This feature is beneficial in high power and high frequency MMIC applications such as high power switches and microwave power amplifiers. A III-nitrogen semiconductor MMIC may include a plurality of III-nitrogen semiconductor field effect transistors (FETs). In a common circuit layout, the gate contact layers of the plurality of III-nitrogen semiconductor field effect transistors form a comb shape, which has a plurality of gate contact fingers formed on the III-nitrogen semiconductor conductive region and A gate connection line formed on the non-conductive area of the III-nitrogen semiconductor and connected to all gate contact fingers, and then the gate connection line is connected to a gate contact pad through a metal connection line to input the control voltage to the electric The gate electrode of the crystal.

III-氮族半導體MMIC在高溫及高電壓領域具有廣泛的應用。因此,元件性能在高溫及高電壓中的穩定性極為重要。在一昔知的III-氮族半導體MMIC中,閘極接觸指在導電區域與III-氮族半導體形成蕭基接觸(Schottky contact),而閘極連接線則是形成於非導電區域上的一介電層 上。然而在昔知III-氮族半導體MMIC中,在高電壓運作時,諸如崩潰電壓及臨界電壓等蕭基性能有很大的變化。此外,昔知III-氮族半導體MMIC在高溫測試中會產生高漏電流。因此,為達到在高電壓及高溫下更佳的應用性,必須改良III-氮族半導體MMIC的蕭基行為及熱穩定性。 III-nitrogen semiconductor MMIC has a wide range of applications in high temperature and high voltage fields. Therefore, the stability of component performance at high temperature and high voltage is extremely important. In the formerly known III-nitrogen semiconductor MMIC, the gate contact refers to the formation of Schottky contact with the III-nitrogen semiconductor in the conductive area, and the gate connection line is a dielectric formed on the non-conductive area. Electric layer on. However, in the formerly known III-nitrogen semiconductor MMICs, during high-voltage operation, the Schottky performance such as breakdown voltage and threshold voltage has great changes. In addition, it is known that the III-nitrogen semiconductor MMIC generates high leakage current during high temperature testing. Therefore, in order to achieve better applicability under high voltage and high temperature, the Schottky behavior and thermal stability of the III-nitrogen semiconductor MMIC must be improved.

有鑑於此,為解決上述的問題,本發明提供一種III-氮族半導體結構,其能藉由處理在一III-氮族半導體中的應力來有效改良高電壓運作下的蕭基性能及高溫運作下的元件可靠性,從而改良該III-氮族半導體MMIC的熱穩定性及蕭基行為。 In view of this, in order to solve the above-mentioned problems, the present invention provides a III-nitrogen semiconductor structure, which can effectively improve the Schottky performance under high-voltage operation and high-temperature operation by treating the stress in a III-nitrogen semiconductor Lower component reliability, thereby improving the thermal stability and Schoo base behavior of the III-nitrogen semiconductor MMIC.

為達上述目的,本發明提供一種藉由處理在一III-氮族半導體中的應力來改良熱穩定性及蕭基行為的半導體結構,其包括一III-氮族半導體和一閘極金屬層;該III-氮族半導體具有一上表面,在該上表面上定義有一導電區域和一非導電區域;該閘極金屬層係直接形成於該III-氮族半導體的上表面上,其包括一閘極連接線和至少一閘極接觸,其中該閘極連接線在一第一方向上具有一第一長度,且在垂直於該第一方向的一第二方向上具有一第一寬度,該至少一閘極接觸係自該閘極連接線以一第二寬度在該第二方向上延伸;其中該至少一閘極接觸在該導電區域與III-氮族半導體形成蕭基接觸,而該閘極連接線係在該非導電區域與III-氮族半導體形成直接接觸,且其中該III-氮族半導體的該非導電區域至少部分被該閘極連接線覆蓋。 To achieve the above objective, the present invention provides a semiconductor structure that improves thermal stability and Schiff behavior by treating stress in a III-nitrogen semiconductor, which includes a III-nitrogen semiconductor and a gate metal layer; The III-nitrogen semiconductor has an upper surface on which a conductive area and a non-conductive area are defined; the gate metal layer is directly formed on the upper surface of the III-nitrogen semiconductor, which includes a gate The electrode connection line is in contact with at least one gate electrode, wherein the gate electrode connection line has a first length in a first direction and a first width in a second direction perpendicular to the first direction, and the at least A gate contact extends in the second direction with a second width from the gate connection line; wherein the at least one gate contact forms a Schottky contact with the III-nitrogen semiconductor in the conductive region, and the gate The connecting wire is in direct contact with the III-nitrogen semiconductor in the non-conductive region, and the non-conductive region of the III-nitrogen semiconductor is at least partially covered by the gate connecting wire.

於實施時,前述閘極連接線的第一寬度是前述至少一閘極接觸的第二寬度的5%至30%。 In implementation, the first width of the gate connection line is 5% to 30% of the second width of the at least one gate contact.

於實施時,前述閘極連接線的第一寬度範圍為2至50μm。 In implementation, the first width of the aforementioned gate connection line ranges from 2 to 50 μm.

於實施時,前述半導體結構更包括設置在前述閘極金屬層上 用於絕緣的一介電層。 During implementation, the aforementioned semiconductor structure further includes a structure disposed on the aforementioned gate metal layer A dielectric layer used for insulation.

於實施時,前述半導體結構包括設置在前述閘極金屬層上用於絕緣的一介電層,且更包括設置在該介電層上用於抑制電場的一傳導金屬層。 In implementation, the aforementioned semiconductor structure includes a dielectric layer disposed on the gate metal layer for insulation, and further includes a conductive metal layer disposed on the dielectric layer for suppressing electric field.

於實施時,前述III-氮族半導體更包括一第一III-氮族半導體層和一第二III-氮族半導體層,一傳導通道形成於該第一和第二III-氮族半導體層之間,一源極接觸和一汲極接觸在所述導電區域與III-氮族半導體形成歐姆接觸,並耦合於該傳導通道以傳導電流,前述至少一閘極接觸係在所述導電區域插入該源極接觸和汲極接觸之間,並耦合於該傳導通道以控制電流。 In implementation, the aforementioned III-nitrogen semiconductor further includes a first III-nitrogen semiconductor layer and a second III-nitrogen semiconductor layer, and a conductive channel is formed between the first and second III-nitrogen semiconductor layers At the same time, a source contact and a drain contact form an ohmic contact with the III-nitrogen semiconductor in the conductive area, and are coupled to the conductive channel to conduct current. The aforementioned at least one gate contact is inserted into the conductive area The source contact and the drain contact are coupled to the conduction channel to control the current.

於實施時,前述半導體結構為一場效電晶體(FET)的一部份。 In implementation, the aforementioned semiconductor structure is part of a field-effect transistor (FET).

於實施時,前述半導體結構為一微波積體電路(MMIC)的一部份。 In implementation, the aforementioned semiconductor structure is a part of a microwave integrated circuit (MMIC).

為對於本發明之特點與作用能有更深入之瞭解,茲藉實施例配合圖式詳述於後。 In order to have a more in-depth understanding of the features and functions of the present invention, detailed descriptions are given below with reference to embodiments and drawings.

10‧‧‧基板 10‧‧‧Substrate

20‧‧‧III-氮族半導體 20‧‧‧III-Nitrogen semiconductor

22‧‧‧導電區域 22‧‧‧Conductive area

24‧‧‧非導電區域 24‧‧‧Non-conductive area

30‧‧‧第一III-氮族半導體層 30‧‧‧The first III-nitrogen semiconductor layer

40‧‧‧傳導通道 40‧‧‧Conduction channel

50‧‧‧第二III-氮族半導體層 50‧‧‧The second III-nitrogen semiconductor layer

110‧‧‧閘極金屬層 110‧‧‧Gate metal layer

112‧‧‧閘極接觸 112‧‧‧Gate contact

114‧‧‧閘極連接線 114‧‧‧Gate connection line

120‧‧‧汲極接觸 120‧‧‧Dip pole contact

130‧‧‧源極接觸 130‧‧‧Source contact

140‧‧‧介電層 140‧‧‧Dielectric layer

150‧‧‧傳導金屬層 150‧‧‧Conductive metal layer

h‧‧‧第一長度 h‧‧‧First length

w1‧‧‧第一寬度 w1‧‧‧First width

w2‧‧‧第二寬度 w2‧‧‧Second width

第1圖為本發明一種半導體結構之一實施例的上視示意圖。 FIG. 1 is a schematic top view of an embodiment of a semiconductor structure of the present invention.

第2圖為本發明一種半導體結構之一實施例的側視示意圖。 FIG. 2 is a schematic side view of an embodiment of a semiconductor structure of the present invention.

第3圖為在先前技術(線A)及本發明(線B)所提供的一種電池中在閘極電極上所測得的電流-電壓(I-V)圖。 Figure 3 is a graph of current-voltage (I-V) measured on the gate electrode in a battery provided by the prior art (line A) and the present invention (line B).

第4A及4B圖分別顯示在先前技術(4A)及本發明(4B)所提供的一種MMIC中在開啟狀態所測得的電流-電壓(I-V)圖。 Figures 4A and 4B respectively show the current-voltage (I-V) graphs measured in the on state in an MMIC provided by the prior art (4A) and the present invention (4B).

第1圖為本發明一種半導體結構之一實施例的上視示意圖,其包括一III-氮族半導體20和一閘極金屬層110;III-氮族半導體20具有一上表面,在該上表面上定義有一導電區域22和一非導電區域24;閘極金屬層110係直接形成於III-氮族半導體20的上表面上,其包括一閘極連接線114和至少一閘極接觸112;閘極連接線114在沿著一第一方向(y軸)上具有一第一長度h且在沿著垂直於第一方向的一第二方向(x軸)上具有一第一寬度w1,閘極接觸112係自閘極連接線114以一第二寬度w2在第二方向上延伸;閘極接觸112在導電區域22與III-氮族半導體20形成蕭基接觸,而閘極連接線114係在非導電區域24與III-氮族半導體20形成直接接觸,且其中III-氮族半導體20的非導電區域24至少部分被閘極連接線114覆蓋。 FIG. 1 is a schematic top view of an embodiment of a semiconductor structure of the present invention, which includes a III-nitrogen semiconductor 20 and a gate metal layer 110; the III-nitrogen semiconductor 20 has an upper surface on the upper surface A conductive region 22 and a non-conductive region 24 are defined above; the gate metal layer 110 is directly formed on the upper surface of the III-nitrogen semiconductor 20, and includes a gate connection line 114 and at least one gate contact 112; gate The pole connecting line 114 has a first length h along a first direction (y-axis) and a first width w1 along a second direction (x-axis) perpendicular to the first direction. The gate The contact 112 extends from the gate connection line 114 with a second width w2 in the second direction; the gate contact 112 forms a Schottky contact with the III-nitrogen semiconductor 20 in the conductive region 22, and the gate connection line 114 is The non-conductive region 24 is in direct contact with the III-nitrogen semiconductor 20, and the non-conductive region 24 of the III-nitrogen semiconductor 20 is at least partially covered by the gate connection line 114.

在一個實施例中,一場效電晶體(FET)包括本發明所提供的半導體結構。所述FET包括形成於一基板10上的一III-氮族半導體20。III-氮族半導體20包括一第一III-氮族半導體層30和一第二III-氮族半導體層50,一傳導通道40形成於第一III-氮族半導體層30和第二III-氮族半導體層50之間,一源極接觸130和一汲極接觸120在導電區域22與III-氮族半導體20形成歐姆接觸,並耦合於傳導通道40以傳導電流,如第2圖所示,一閘極接觸112係在導電區域22上插入源極接觸130和汲極接觸120之間,並耦合於傳導通道40以控制電流。 In one embodiment, a field effect transistor (FET) includes the semiconductor structure provided by the present invention. The FET includes a III-nitrogen semiconductor 20 formed on a substrate 10. The III-nitrogen semiconductor 20 includes a first III-nitrogen semiconductor layer 30 and a second III-nitrogen semiconductor layer 50, and a conductive channel 40 is formed in the first III-nitrogen semiconductor layer 30 and the second III-nitrogen semiconductor layer 30 and the second III-nitrogen semiconductor layer. Between the group semiconductor layers 50, a source contact 130 and a drain contact 120 form an ohmic contact with the III-nitrogen semiconductor 20 in the conductive region 22, and are coupled to the conduction channel 40 to conduct current, as shown in Figure 2. A gate contact 112 is inserted between the source contact 130 and the drain contact 120 on the conductive area 22 and is coupled to the conductive channel 40 to control current.

在本發明半導體結構的製造過程的一個實施例中,在源極接觸130和汲極接觸120與III-氮族半導體20形成歐姆接觸之後,以遮罩覆蓋III-氮族半導體20的導電區域22,並對III-氮族半導體20進行離子佈植製程,III-氮族半導體20未覆蓋區域的晶體結構受到射入離子破壞而變成絕 緣性,藉以形成非導電區域24。一閘極接處區域形成於介於源極接觸130和汲極接觸120之間的導電區域22上。包括多個閘極接觸112和一閘極連接線114的閘極金屬層110係設置在III-氮族半導體20的上表面上,其中該多個閘極接觸112設置在導電區域22上並與III-氮族半導體20形成蕭基接觸,而連接多個閘極接觸112的閘極連接線114則設置在非導電區域24上。 In an embodiment of the manufacturing process of the semiconductor structure of the present invention, after the source contact 130 and the drain contact 120 form an ohmic contact with the III-nitrogen semiconductor 20, the conductive region 22 of the III-nitrogen semiconductor 20 is covered with a mask. , And perform an ion implantation process on the III-nitrogen semiconductor 20. The crystal structure of the uncovered area of the III-nitrogen semiconductor 20 is destroyed by the injected ions and becomes insulator In this way, the non-conductive area 24 is formed. A gate contact area is formed on the conductive area 22 between the source contact 130 and the drain contact 120. The gate metal layer 110 including a plurality of gate contacts 112 and a gate connection line 114 is disposed on the upper surface of the III-nitrogen semiconductor 20, wherein the plurality of gate contacts 112 are disposed on the conductive region 22 and are connected with The III-nitrogen semiconductor 20 forms a Schottky contact, and a gate connection line 114 connecting a plurality of gate contacts 112 is provided on the non-conductive area 24.

在一個實施例中,III-氮族半導體20的非導電區域24至少部分被閘極連接線114覆蓋。在一個實施例中,閘極連接線114的第一寬度w1是該至少一閘極接觸112的第二寬度w2的5%至30%。在一個實施例中,閘極連接線114的第一寬度w1的範圍較佳為2至50μm,更佳為10至35μm。閘極連接線114至導電區域22之間的距離較佳為3至30μm,更佳為5至20μm。 In one embodiment, the non-conductive area 24 of the III-nitrogen semiconductor 20 is at least partially covered by the gate connection line 114. In one embodiment, the first width w1 of the gate connection line 114 is 5% to 30% of the second width w2 of the at least one gate contact 112. In one embodiment, the range of the first width w1 of the gate connection line 114 is preferably 2-50 μm, more preferably 10 to 35 μm. The distance between the gate connection line 114 and the conductive region 22 is preferably 3 to 30 μm, more preferably 5 to 20 μm.

在一個實施例中,一介電層140設置於閘極金屬層110上且大致覆蓋整個閘極金屬層110,以用於絕緣。介電層140可由任何介電材料製成,其中較佳由SiN製成。在一個實施例中,介電層140上更設置一傳導金屬層150,以用於抑制電場。 In one embodiment, a dielectric layer 140 is disposed on the gate metal layer 110 and substantially covers the entire gate metal layer 110 for insulation. The dielectric layer 140 can be made of any dielectric material, and is preferably made of SiN. In one embodiment, a conductive metal layer 150 is further provided on the dielectric layer 140 to suppress the electric field.

在一個實施例中,第一III-氮族半導體層30包括氮化鎵(GaN)。在一個實施例中,第二III-氮族半導體層50包括氮化鋁鎵(AlGaN)、氮化銦鋁(InAlN)、氮化鋁(AlN)或氮化鎵(GaN)層。 In one embodiment, the first III-nitrogen semiconductor layer 30 includes gallium nitride (GaN). In one embodiment, the second III-nitrogen semiconductor layer 50 includes an aluminum gallium nitride (AlGaN), indium aluminum nitride (InAlN), aluminum nitride (AlN), or gallium nitride (GaN) layer.

本發明提供的半導體結構能改良在非導電區域中的應力,從而改良熱穩定性及蕭基行為。相較於先前技術中的MMIC,本發明提供的MMIC顯示改良的電子特性。在一個實施例中,此MMIC為一電池,其包括多個形成於本發明所提供的半導體結構上的FET。第3圖顯示在先前技術(線A)及本發明(線B)所提供的一個電池中在閘極電極上所測得的電 流-電壓(I-V)圖。如圖所示,在本發明(線B)所提供的MMIC中的閘極電極的開啟電壓Von高於先前技術MMIC的開啟電壓。顯示本發明閘極電極改良的蕭基行為。 The semiconductor structure provided by the present invention can improve the stress in the non-conductive area, thereby improving the thermal stability and the Schiff behavior. Compared with the MMIC in the prior art, the MMIC provided by the present invention shows improved electronic characteristics. In one embodiment, the MMIC is a battery, which includes a plurality of FETs formed on the semiconductor structure provided by the present invention. Figure 3 shows the electricity measured on the gate electrode in a battery provided by the prior art (line A) and the present invention (line B) Current-voltage (I-V) diagram. As shown in the figure, the turn-on voltage Von of the gate electrode in the MMIC provided by the present invention (line B) is higher than that of the prior art MMIC. Shows the improved Schottky behavior of the gate electrode of the present invention.

第4A及4B圖分別顯示在先前技術(4A)及本發明(4B)所提供的一種MMIC中在開啟狀態下在汲極電極上所測得的I-V圖。在先前技術MMIC的I-V曲線中,當外加汲極電壓增大時臨界電壓值明顯向上移,而在本發明的MMIC中,即使在高外加汲極電壓下,臨界電壓也大致維持在同樣的閾值。 Figures 4A and 4B respectively show the I-V diagrams measured on the drain electrode in an on-state MMIC provided by the prior art (4A) and the present invention (4B). In the IV curve of the prior art MMIC, when the applied drain voltage increases, the critical voltage value obviously shifts upwards, while in the MMIC of the present invention, even at a high applied drain voltage, the critical voltage is approximately maintained at the same threshold value .

本發明提供的半導體結構亦能改良元件的熱穩定性。在一熱穩定性測試中,本發明所提供的元件和一先前技術元件在高溫及高逆向偏壓條件下進行測試。本發明所提供元件的臨界電壓的變化在25個小時的高溫測試期間小於5%,而先前技術元件在高溫下則大部分退化,故障率大於90%。 The semiconductor structure provided by the present invention can also improve the thermal stability of the device. In a thermal stability test, the device provided by the present invention and a prior art device are tested under high temperature and high reverse bias conditions. The change in the critical voltage of the component provided by the present invention is less than 5% during the 25-hour high temperature test, while the prior art component is mostly degraded at high temperature, and the failure rate is greater than 90%.

因此,本發明具有以下優點: Therefore, the present invention has the following advantages:

1.在本發明所提供的MMIC中,閘極電極的開啟電壓較高,漏電流較彽,其整體蕭基行為獲得改良。 1. In the MMIC provided by the present invention, the turn-on voltage of the gate electrode is relatively high, the leakage current is relatively low, and its overall Schottky behavior is improved.

2.在本發明所提供的MMIC中,臨界電壓在高電壓下能大致維持在同樣的閾值,其蕭基性能在高電壓下的穩定性獲得改良。 2. In the MMIC provided by the present invention, the threshold voltage can be approximately maintained at the same threshold under high voltage, and the stability of its Schottky performance under high voltage is improved.

3.本發明所提供的MMIC的臨界電壓在長時間的高問測試中只有很小的變化,其熱穩定性獲得改良。 3. The threshold voltage of the MMIC provided by the present invention has only a small change in the long-term high-level test, and its thermal stability is improved.

4.本發明所提供半導體結構的閘極接觸和閘極連接線是由同一製程步驟形成,因此本發明III-氮族半導體結構的製程較為簡化。 4. The gate contact and the gate connection line of the semiconductor structure provided by the present invention are formed by the same process step, so the manufacturing process of the III-nitrogen semiconductor structure of the present invention is relatively simplified.

綜上所述,本發明提供的半導體結構確實可達到預期之目的,能有效改良高電壓運作下的蕭基性能及高溫運作下的元件可靠性,從 而改良該III-氮族半導體MMIC的熱穩定性及蕭基行為。其確具產業利用之價值,爰依法提出發明專利申請。 In summary, the semiconductor structure provided by the present invention can indeed achieve the intended purpose, and can effectively improve the Schottky performance under high-voltage operation and the reliability of components under high-temperature operation. And to improve the thermal stability and Schiff base behavior of the III-nitrogen semiconductor MMIC. It is indeed of value for industrial use, and Yan filed an application for a patent for invention in accordance with the law.

又上述說明與圖示僅是用以說明本發明之實施例,凡熟於此業技藝之人士,仍可做等效的局部變化與修飾,其並未脫離本發明之技術與精神。 Moreover, the above descriptions and diagrams are only used to illustrate the embodiments of the present invention, and those who are familiar with the art can still make equivalent partial changes and modifications, which do not depart from the technology and spirit of the present invention.

20‧‧‧III-氮族半導體 20‧‧‧III-Nitrogen semiconductor

22‧‧‧導電區域 22‧‧‧Conductive area

24‧‧‧非導電區域 24‧‧‧Non-conductive area

110‧‧‧閘極金屬層 110‧‧‧Gate metal layer

112‧‧‧閘極連接線 112‧‧‧Gate connection line

114a‧‧‧第一閘極指 114a‧‧‧First Gate Finger

114b‧‧‧第二閘極指 114b‧‧‧Second Gate Finger

116a‧‧‧第一終端錨 116a‧‧‧First terminal anchor

116b‧‧‧第二終端錨 116b‧‧‧Second terminal anchor

120‧‧‧源極接觸金屬 120‧‧‧Source contact metal

130a‧‧‧第一汲極接觸金屬 130a‧‧‧The first drain contacts the metal

130b‧‧‧第二汲極接觸金屬 130b‧‧‧The second drain contacts the metal

w1a、w1b、w2‧‧‧寬度 w1a, w1b, w2‧‧‧width

Claims (11)

一種藉由處理在一III-氮族半導體中的應力來改良熱穩定性及蕭基行為的半導體結構,其包括:一III-氮族半導體,其具有一上表面,在該上表面上定義有一導電區域和一非導電區域;一閘極金屬層,係直接形成於該III-氮族半導體的該上表面上,其包括一閘極連接線和至少一閘極接觸,其中該閘極連接線在一第一方向上具有一第一長度,且在垂直於該第一方向的一第二方向上具有一第一寬度,該至少一閘極接觸係自該閘極連接線以一第二寬度在該第二方向上延伸,其中該至少一閘極接觸在該導電區域與該III-氮族半導體形成蕭基接觸,而該閘極連接線係在該非導電區域與該III-氮族半導體形成直接接觸,以及其中該III-氮族半導體的該非導電區域至少部分被該閘極連接線覆蓋。 A semiconductor structure that improves thermal stability and Schorch behavior by treating the stress in a III-nitrogen semiconductor, which includes: a III-nitrogen semiconductor, which has an upper surface, on which an upper surface is defined A conductive region and a non-conductive region; a gate metal layer is directly formed on the upper surface of the III-nitrogen semiconductor, which includes a gate connection line and at least one gate contact, wherein the gate connection line Has a first length in a first direction, and has a first width in a second direction perpendicular to the first direction, and the at least one gate contact has a second width from the gate connection line Extending in the second direction, wherein the at least one gate contact forms a Schottky contact with the III-nitrogen semiconductor in the conductive region, and the gate connection line is formed with the III-nitrogen semiconductor in the non-conductive region Direct contact, and wherein the non-conductive area of the III-nitrogen semiconductor is at least partially covered by the gate connection line. 如申請專利範圍第1項所述之半導體結構,其中該閘極連接線的該第一寬度是該至少一閘極接觸的該第二寬度的5%至30%。 In the semiconductor structure described in claim 1, wherein the first width of the gate connection line is 5% to 30% of the second width of the at least one gate contact. 如申請專利範圍第1項所述之半導體結構,其中該閘極連接線的該第一寬度範圍為2至50μm。 In the semiconductor structure described in item 1 of the scope of patent application, the first width of the gate connection line is in the range of 2 to 50 μm. 如申請專利範圍第1項所述之半導體結構,其中該閘極連接線至該導電區域之間的距離為3至30μm。 According to the semiconductor structure described in item 1 of the scope of patent application, the distance between the gate connection line and the conductive region is 3 to 30 μm. 如申請專利範圍第1項所述之半導體結構,其中該III-氮族半導體更包括一第一III-氮族半導體層和一第二III-氮族半導體層,一傳導通道形成於該第一和第二III-氮族半導體層之間,一源極接觸和一汲極接觸在該導電區域與該III-氮族半導體形成歐姆接觸,並耦合於該傳導通道以傳 導電流,該至少一閘極接觸係在該導電區域插入該源極接觸和汲極接觸之間,並耦合於該傳導通道以控制電流。 According to the semiconductor structure described in claim 1, wherein the III-nitrogen semiconductor further includes a first III-nitrogen semiconductor layer and a second III-nitrogen semiconductor layer, and a conductive channel is formed in the first And the second III-nitrogen semiconductor layer, a source contact and a drain contact form an ohmic contact with the III-nitrogen semiconductor in the conductive region, and are coupled to the conductive channel for transmission Conducting current, the at least one gate contact is inserted between the source contact and the drain contact in the conductive region, and is coupled to the conductive channel to control the current. 如申請專利範圍第5項所述之半導體結構,其中該III-氮族半導體包含氮化鎵。 The semiconductor structure described in item 5 of the scope of patent application, wherein the III-nitrogen semiconductor includes gallium nitride. 如申請專利範圍第5項所述之半導體結構,其中該III-氮族半導體包含氮化鋁鎵、氮化銦鋁、氮化鋁或氮化鎵。 The semiconductor structure described in item 5 of the patent application, wherein the III-nitrogen semiconductor includes aluminum gallium nitride, indium aluminum nitride, aluminum nitride, or gallium nitride. 如申請專利範圍第1項所述之半導體結構,更包括設置在該閘極金屬層上用於絕緣的一介電層。 The semiconductor structure described in item 1 of the scope of patent application further includes a dielectric layer for insulation provided on the gate metal layer. 如申請專利範圍第8項所述之半導體結構,更包括設置在該介電層上用於抑制電場的一傳導金屬層。 The semiconductor structure described in item 8 of the scope of patent application further includes a conductive metal layer disposed on the dielectric layer to suppress the electric field. 如申請專利範圍第1項所述之半導體結構,其中該半導體結構為一場效電晶體的一部份。 The semiconductor structure described in item 1 of the scope of the patent application, wherein the semiconductor structure is a part of a field effect transistor. 如申請專利範圍第1項所述之半導體結構,其中該半導體結構為一微波積體電路的一部份。 The semiconductor structure described in claim 1, wherein the semiconductor structure is a part of a microwave integrated circuit.
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