TW202025403A - Semiconductor package - Google Patents

Abstract

A semiconductor package includes a semiconductor chip including a chip pad on a first surface thereof, an external pad electrically connected to the chip pad of the semiconductor chip, an external connection terminal covering the external pad, and an intermediate layer between the external pad and the external connection terminal, the intermediate layer including a third metal material that is different from a first metal material included in the external pad and a second metal material included in the external connection terminal.

Description

Semiconductor package

The technical concept of the present invention relates to a semiconductor package, and more specifically, to a wafer level package.

Generally, a semiconductor package is manufactured by performing a semiconductor packaging process on a semiconductor wafer prepared by performing various semiconductor processes on the wafer. Recently, in order to save the production cost of semiconductor packages, a wafer-level packaging technology has been proposed in which semiconductor packaging processes are performed at the wafer level and the wafer-level semiconductor packages that have undergone the semiconductor packaging process are cut one by one.

The technical idea of the present invention aims to provide a semiconductor package and its manufacturing method.

In order to solve the above technical problems, the technical idea of the present invention provides a semiconductor package, the semiconductor package includes: a semiconductor chip, which includes a chip pad provided on the first surface; The chip pad is electrically connected; an external connection terminal, which covers the external pad; and an intermediate layer, which is disposed between the external pad and the external connection terminal and includes a third metal material, the third metal material being different The first metal material included in the external pad and the second metal material included in the external connection terminal.

According to an exemplary embodiment, the third metal material of the intermediate layer includes gold (Au).

According to an exemplary embodiment, the semiconductor package further includes an insulating layer on the first surface of the semiconductor wafer, and the external connection terminal covers the sidewall of the external pad and is in contact with the upper surface of the insulating layer. Surface contact.

According to an exemplary embodiment, the semiconductor package is characterized in that, for the first direction parallel to the first surface of the semiconductor wafer, the uppermost end of the side wall of the external pad is connected to the outside of the external connection terminal. Between the surfaces, the thickness of the external connection terminal along the first direction is between 10um and about 30um.

According to an exemplary embodiment, the semiconductor package is characterized by further comprising an insulating layer on the first surface of the semiconductor wafer, and for the second direction perpendicular to the first surface of the semiconductor wafer, the insulating layer The upper surface of the layer shall prevail, and the height of the outer pad along the second direction is between 10um and 50um.

According to an exemplary embodiment, a semiconductor package is characterized by further including a wiring pattern that extends between a die pad of the semiconductor wafer and the external pad and electrically connects the die pad and the external pad.

According to an exemplary embodiment, the semiconductor package includes a fan-out shape semiconductor package.

In order to solve the above-mentioned technical problems, the technical idea of the present invention provides a semiconductor package including: a semiconductor wafer including a wafer pad provided on a first surface; an external pad that is electrically connected to the wafer pad of the semiconductor wafer Connection; and an external connection terminal, which covers the external pad and includes solder, wherein the external connection terminal further includes a second metal material, and the second metal material is different from that included in the solder and the The first metal material in the outer pad.

According to an exemplary embodiment, the semiconductor package is characterized in that the second metal material accounts for between 0.00001 wt% and 1 wt% of the entire weight of the external connection terminal.

According to an exemplary embodiment, the semiconductor package is characterized in that the second metal material includes gold (Au).

According to an exemplary embodiment, the semiconductor package is characterized in that the external connection terminal covers the sidewall of the external pad, and for the first direction parallel to the first surface of the semiconductor wafer, the external pad Between the uppermost end of the side wall and the outer surface of the external connection terminal, the thickness of the external connection terminal along the first direction is between 10um and about 30um.

In addition, in order to solve the above technical problems, the technical idea of the present invention provides a semiconductor package, including: a substrate including a conductive pad provided on a first surface; and an insulating pattern exposing at least a part of the conductive pad And placed on the first surface; a lower metal layer, which is connected to the conductive pad; an upper metal layer, which is placed on the lower metal layer; and external connection terminals, which cover the upper metal layer The entire upper surface and the entire sidewall surface, wherein the lateral profile of the lower metal layer is located inside compared to the sidewall surface of the upper metal layer.

According to an exemplary embodiment, the semiconductor package is characterized in that a side surface of the lower metal layer includes a concave curved surface, and the upper metal layer includes a protrusion that protrudes in a lateral direction relative to the lower metal layer, The external connection terminal includes an extension that extends to a lower portion of the protruding portion of the upper metal layer.

According to an exemplary embodiment, the semiconductor package is characterized in that the external connection terminal contacts the lower surface of the upper metal layer.

According to an exemplary embodiment, the semiconductor package is characterized in that the extension part contacts the side surface of the lower metal layer.

According to an exemplary embodiment, the semiconductor package is characterized by further including an intermetallic compound between the external connection terminal and the upper metal layer.

According to an exemplary embodiment, the semiconductor package is characterized in that the external connection terminal contacts the sidewall surface of the upper metal layer and the upper surface of the insulating pattern near the sidewall surface.

According to an exemplary embodiment, the semiconductor package is characterized in that the conductive pad is a wafer pad electrically connected to the semiconductor substrate.

According to an exemplary embodiment, the semiconductor package is characterized in that the lower metal layer is electrically connected to the conductive pad through a wiring pattern, the thickness of the wiring pattern is 3 μm to 8 μm, and the thickness of the wiring pattern is T1 The ratio T2/T1 to the sum of the thicknesses of the upper metal layer and the lower metal layer T2 is 1.25-40.

According to an exemplary embodiment, the semiconductor package is characterized in that the thickness of the upper metal layer in a direction perpendicular to the first surface is about 10um to about 100um.

Hereinafter, preferred embodiments of the inventive concept will be described in detail with reference to the drawings. However, the embodiments of the inventive concept can be deformed into various different forms, and should not be construed as limiting the scope of the inventive concept to the embodiments described in detail below. It should be understood that embodiments of the concept of the present invention are provided to more fully explain the concept of the present invention to those of ordinary skill in the art. The same symbol always represents the same element. Furthermore, various elements and regions in the drawing are schematically illustrated. Therefore, the concept of the present invention is not limited to the relative sizes or intervals shown in the drawings.

Although terms such as first and second may be used to describe various constituent elements, the constituent elements are not limited to the terms. The terms are only used to distinguish one constituent element from other constituent elements. For example, without departing from the scope of rights of the concept of the present invention, the first constituent element may be named as the second constituent element, on the contrary, the second constituent element may be named as the first constituent element.

The terms used in this application are only used to describe specific embodiments and not to limit the concept of the present invention. Unless clearly indicated otherwise, expressions in the singular form also include expressions in the plural form. In this application, expressions such as "including" or "having" should be understood as used to formulate the existence of the features, quantities, steps, actions, constituent elements, components, or combinations thereof recorded in the specification, rather than excluding one in advance. The existence or additional possibility of more other features, quantities, actions, constituent elements, components, or combinations thereof.

Unless there are other definitions, all terms used herein, including technical terms and scientific terms, have the same meaning as commonly understood by those of ordinary skill in the technical field to which the concept of the present invention belongs. In addition, it should be understood that the commonly used terms defined in the dictionary should be interpreted as having the meaning consistent with the meaning expressed in the context of the relevant technology. Unless clearly defined here, they should not be excessive Interpreted as superficial meaning.

In the case where some embodiments can be implemented differently, a specific process can be performed differently from the described order. For example, the two processes described in succession may actually be performed simultaneously or in the reverse order of the described order.

In the diagram, for example, based on manufacturing technology and/or tolerances, the deformation of the shown shape can be predicted. Therefore, the embodiments of the present invention should not be construed as being limited to the specific shape of the area shown in this specification, for example, to include changes in the shape caused during the manufacturing process. All "and/or" used herein include all or all combinations of one or more of the constituent elements involved. Also, the term "substrate" used in this specification may include the substrate itself, or a stacked structure including the substrate and a predetermined layer or film formed on the surface thereof. In addition, in this specification, the "surface of the substrate" may include the surface of the substrate itself exposed, or the outer surface of a predetermined layer or film formed on the substrate.

FIG. 1 is a cross-sectional view of a semiconductor package 100 according to an exemplary embodiment of the present invention.

1, the semiconductor package 100 may include a semiconductor chip 110, a rewiring structure 120 on the semiconductor chip 110, external pads 150, and external connection terminals 160.

A plurality of individual devices of various types may be formed on the semiconductor wafer 110. For example, the plurality of individual devices may include various microelectronic devices (microelectronic devices), for example, metal oxide semiconductor field effect devices such as complementary metal-oxide-semiconductor (CMOS) transistors, etc. Crystal (metal-oxide-semiconductor field effect transistor (MOSFET)), large scale integrated circuit (LSI: large scale integration) system, image sensor such as CMOS image sensor (CIS), micro-electro-mechanical system (micro-electro-mechanical system) mechanical system (MEMS)), active components, and passive components.

The semiconductor wafer 110 may include a wafer pad 111 disposed on the first surface 118. The wafer pad 111 may be electrically connected to the various elements formed on the semiconductor wafer 110. Also, the semiconductor wafer 110 may include a passivation film 113 covering the first surface 118.

According to an exemplary embodiment, the semiconductor wafer 110 may be, for example, a memory semiconductor wafer. The memory semiconductor chip can be, for example, a volatile memory semiconductor chip such as a dynamic random access memory (Dynamic Random Access Memory (DRAM)) or a static random access memory (Static Random Access Memory (SRAM)), or Phase-change Random Access Memory (PRAM), Magnetoresistive Random Access Memory (MRAM), Ferroelectric Random Access Memory (FeRAM) , Or resistive random access memory (RRAM) non-volatile memory semiconductor chip.

Alternatively, according to an exemplary embodiment, the semiconductor wafer 110 may be a logic wafer. For example, the semiconductor chip 110 may be a central processor unit (CPU), a microprocessor (MPU), a graphic processor unit (GPU), or an application processor (application processor). processor (AP)).

Also, although FIG. 1 shows that the semiconductor package 100 includes one semiconductor wafer 110, the semiconductor package 100 may include more than two semiconductor wafers 110. The two or more semiconductor wafers 110 included in the semiconductor package 100 may be semiconductor wafers of the same type or different types of semiconductor wafers. According to some embodiments, the semiconductor package 100 may be a system in package (SIP: system in package) that operates as a system by electrically connecting different types of semiconductor chips to each other.

The rewiring structure 120 may be disposed on the first surface 118 of the semiconductor wafer 110. The rewiring structure 120 may include an insulating pattern 230 and a wiring pattern 140.

The insulating pattern 230 may be disposed on the first surface 118 of the semiconductor wafer 110. The insulating pattern 230 may have a structure in which a plurality of insulating films are stacked. For example, the insulating pattern 230 may include a first insulating pattern 131 and a second insulating pattern 133 sequentially stacked on the first surface 118 of the semiconductor wafer 110.

For example, the first insulating pattern 131 and the second insulating pattern 133 may be respectively made of insulating polymer, epoxy, silicon oxide film, silicon nitride film, insulating polymer, or a combination thereof.

The wiring pattern 140 may be disposed in the insulating pattern 230 and electrically connect the wafer pad 111 of the semiconductor wafer 110 and the external pad 150. More specifically, a part of the wiring pattern 140 may be connected to the wafer pad 111 of the semiconductor wafer 110 through the opening of the first insulating pattern 131, and another part of the wiring pattern 140 may be extended along the surface of the first insulating pattern 131. For example, the wiring pattern 140 may be made of tungsten (W: tungsten), copper (Cu: copper), zirconium (Zr: zirconium), titanium (Ti: titanium), tantalum (Ta: tantalum), aluminum (Al: aluminum), ruthenium (Ru:ruthenium), palladium (Pd:palladium), platinum (Pt:platinum), cobalt (Co:cobalt), nickel (Ni: nickel), or a combination thereof.

Although FIG. 1 illustrates that the wiring pattern 140 has a single-layer structure, the wiring pattern 140 may also have a multilayer structure in which a plurality of wiring layers are stacked in a vertical direction.

The external pad 150 is disposed on the second insulating pattern 133 and may be used as a pad where the external connection terminal 160 is disposed. The external pad 150 may be connected to the wiring pattern 140 through the opening of the second insulating pattern 133, and may be electrically connected to the die pad 111 of the semiconductor chip 110 through the wiring pattern 140. For example, the external pad 150 may be an under bump metal layer (UBM).

The external pad 150 may be formed to be thicker than the wiring pattern 140. For example, compared to the wiring pattern 140 being formed to have a thickness of about 3 μm to 8 μm, the outer pad 150 may be formed to have a thickness of 10 μm or more.

For the second direction (for example, the Z-direction) perpendicular to the first surface 118 of the semiconductor wafer 110, the height 150h of the outer pad 150 may indicate the distance of the outer pad 150 along the first surface with the upper surface of the second insulating pattern 133 Height in two directions. According to an exemplary embodiment, the height 150h of the outer pad 150 may be between 10um and 50um. For example, the height 150h of the outer pad 150 may be about 30um.

The outer pad 150 may include a lower metal layer 151 and an upper metal layer 153 on the lower metal layer 151.

The lower metal layer 151 may be formed on the wiring pattern 140 exposed through the opening of the second insulating pattern 133 and extended along the surface of the second insulating pattern 133. The lower metal layer 151 may be, for example, a seed layer or an adhesion layer for forming the upper metal layer 153. For example, the lower metal layer 151 may include titanium (Ti), copper (Cu), chromium (Cr), tungsten (W), nickel (Ni), aluminum (Al), palladium (Pd), gold (Au), or combination.

According to an exemplary embodiment, although the lower metal layer 151 may be one metal layer, it may have a multilayer structure including a plurality of metal layers. For example, the lower metal layer 151 may include a first sub-metal layer and a second sub-metal layer sequentially stacked on the second insulating pattern 133 and the wiring pattern 140. The first sub-metal layer may include a metal material having excellent bonding characteristics with the second insulating pattern. For example, the first sub-metal layer may include titanium (Ti). The second submetal layer may be used as a seed layer for forming the upper metal layer 153. For example, the second submetal layer may include copper (Cu).

The upper metal layer 153 may be disposed on the lower metal layer 151. For example, the upper metal layer 153 can be formed by a gold plating method using the lower metal layer 151 as a seed. The upper metal layer 153 may have a pillar shape erected on the insulating pattern 230 and have a structure in which the center portion thereof is recessed. According to an exemplary embodiment, the upper metal layer 153 may include copper (Cu) or an alloy thereof, but is not limited thereto.

The external connection terminal 160 may be provided on the external pad 150. The external connection terminal 160 may be a wafer-substrate connection terminal for mounting the semiconductor chip 110 on an external substrate. According to an exemplary embodiment, the external connection terminal 160 may have a rectangular shape. For example, the external connection terminal 160 may include tin (Sn), silver (Ag), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), zinc (Zn), lead (Pb), and/ Or its alloys.

According to an exemplary embodiment, the external connection terminal 160 may cover the external pad 150. For example, the external connection terminal 160 may cover the upper surface of the external pad 150 and the side wall 158. Also, the external connection terminal 160 may cover the surface of the second insulation pattern 133 near the external pad 150 and form a surface contact with the upper surface of the second insulation pattern 133.

According to an exemplary embodiment, regarding the first direction (for example, the X direction or the Y direction) parallel to the first surface 118 of the semiconductor wafer 110, on the sidewall 158 of the external pad 150, the external connection terminal 160 is The thickness in the first direction may be at least 5 μm. For example, on the sidewall 158 of the external pad 150, the thickness of the external connection terminal 160 along the first direction may be at least 5 μm. According to some exemplary embodiments, between the uppermost end of the sidewall 158 of the external connection terminal 160 and the external surface of the external connection terminal 160, the thickness of the external connection terminal 160 along the first direction may be between 10 μm and 30 μm. Also, according to some exemplary embodiments, between the lowermost end of the sidewall 158 of the external connection terminal 160 and the external surface of the external connection terminal 160, the thickness of the external connection terminal 160 along the first direction may be between 5 μm and 20 μm. .

According to an exemplary embodiment of the present invention, the external connection terminal 160 can completely cover the external pad 150 to prevent the external pad 150 from being exposed, and can prevent damage to the external pad 150 caused by the external pad 150 from being exposed, thereby improving the reliability of the semiconductor chip 110 Sex.

The semiconductor package 100 may be a semiconductor package with a fan-in structure. Alternatively, the semiconductor package 100 may be a semiconductor package with a fan-out structure. In the case that the semiconductor package 100 is a fan-out semiconductor package, the wiring pattern 140 may be further extended to the outside of the semiconductor chip 110, and at least one external pad 150 and at least one external connection terminal 160 may be provided on the semiconductor chip 110 outside.

FIG. 2 is a cross-sectional view showing a semiconductor package 100a according to an exemplary embodiment of the present invention. The semiconductor package 100a shown in FIG. 2 may have substantially the same configuration as the semiconductor package 100 shown in FIG. 1 except that the cover layer 170 is further included and the external connection terminals 160 (refer to FIG. 1) are omitted. Regarding FIG. 2, the description overlapping with the description of FIG. 1 is omitted or briefly described.

Referring to FIG. 2, the semiconductor package 100 a may include a cover layer 170 covering the external pad 150. For example, the cover layer 170 may be formed by an electroless plating method or a sputtering method, and may be formed to cover at least a part of the surface of the external pad 150.

According to an exemplary embodiment, the cover layer 170 may be formed to cover the entire surface of the external pad 150. In other words, the cover layer 170 may cover the upper surface of the outer pad 150 and the sidewall 158. Alternatively, according to other exemplary embodiments, the cover layer 170 may be formed to cover only a part of the surface of the outer pad 150. For example, the cover layer 170 may be formed only on the sidewall 158 of the outer pad 150.

When the external connection terminal 160 (refer to FIG. 1) is further formed on the external pad 150, the cover layer 170 can improve the fluidity of the material constituting the external connection terminal 160. For example, in a reflow soldering process for forming the external connection terminal 160, solder in a molten state may spread along the surface of the covering layer 170 made of a metal material excellent in wettability. Therefore, the external connection terminal 160 may be formed to thickly cover the side wall 158 of the external pad 150.

According to an exemplary embodiment, the cover layer 170 may include a metal material excellent in wettability. For example, the capping layer 170 may include a noble metal of gold (Au), silver (Ag), or palladium (Pd). For example, the capping layer 170 may include gold (Au), palladium (Pd), nickel (Ni), copper (Cu), solder, or a combination thereof.

Alternatively, according to other exemplary embodiments, the wire may be attached to the cover layer 170. The wire may extend between the external substrate and the covering layer 170 and electrically connect the external substrate and the covering layer 170.

The cover layer 170 may be a thin metal film formed on the surface of the outer pad 150. According to an exemplary embodiment, the thickness of the cover layer 170 may be 0.001 μm or more, 0.005 μm or more, 0.01 μm or more, 0.05 μm or more, or 0.1 μm or more. When the thickness of the cover layer 170 is less than 0.001 μm, the wettability of the cover layer 170 is reduced. Therefore, when the cover layer 170 is used to perform reflow soldering on the external connection terminal 160 (see FIG. 1), the external connection terminal 160 is formed The fluidity of the material is not sufficiently enhanced. As a result, the sidewall of the external pad 150 may not be covered by the external connection terminal 160, or the external connection terminal 160 on the sidewall of the external pad 150 may be formed to be too thin.

Also, according to an exemplary embodiment, the thickness of the cover layer 170 may be 1 μm or less, 0.95 μm or less, 0.9 μm or less, 0.85 μm or less, or 0.8 μm or less. In the case where the thickness of the cover layer 170 is greater than 1 μm, when the cover layer 170 is used to perform reflow soldering on the external connection terminal 160, the fluidity of the material constituting the external connection terminal 160 may be excessively strengthened, resulting in a low height of the external connection terminal , And an excessively thick intermetallic compound may be formed between the external connection terminal 160 and the external pad 150.

3 is a cross-sectional view showing a part of the semiconductor package 100b according to an exemplary embodiment of the present invention, and is a cross-sectional view showing an area corresponding to the area indicated by "III" of FIG. Except for including the intermediate layer 171, the semiconductor package 100b shown in FIG. 3 may have substantially the same configuration as the semiconductor package 100 shown in FIG. Regarding FIG. 3, descriptions overlapping with those described above are omitted or briefly described.

1 and 3, the semiconductor package 100b may include an intermediate layer 171 disposed between the external pad 150 and the external connection terminal 160. The intermediate layer 171 may include an intermetallic compound. The intermetallic compound is formed by the metal material included in the external pad 150 and the metal material included in the external connection terminal 160 reacting at a relatively high temperature. The intermetallic compound may be formed along the surface of the outer pad 150.

According to an exemplary embodiment, in addition to the first metal material included in the external pad 150 and the second metal material included in the external connection terminal 160, the intermediate layer 171 may further include a third metal material. The metal material is different from the first metal material and the second metal material. According to an exemplary embodiment, the third metal material of the intermediate layer 171 may include a metal material excellent in wettability. For example, the third metal material of the intermediate layer 171 may include a material with a contact angle of 0˚ to 90˚, a material with a contact angle of 10˚ to 80˚, or a material with a contact angle of 20˚ to 70˚. It is a measure of wettability between the intermediate layer 171 and the external connection terminal 160. For example, the third metal material of the intermediate layer 171 may include a noble metal of gold (Au), silver (Ag), or palladium (Pd). For example, the third metal material of the intermediate layer 171 may include gold (Au), palladium (Pd), nickel (Ni), copper (Cu), solder, or a combination thereof.

For example, the intermediate layer 171 may be formed by performing a reflow soldering process in a state where a solder ball is located on the cover layer 170 (refer to FIG. 2). More specifically, in the reflow soldering process, the third metal material included in the covering layer 170 formed to have a thin thickness diffuses, and the third metal material of the covering layer 170 is in contact with the outer pad at a high temperature. The first metal material of 150 and the second metal material of the external connection terminal 160 react, and thus, an intermediate layer 171 may be generated between the external pad 150 and the external connection terminal 160. For example, when the external pad 150 includes copper and/or nickel, the external connection terminal 160 includes tin and/or copper, and the capping layer 170 includes gold, the intermediate layer 171 may include Cu-Ni-Sn-Au. However, the material or composition of the intermediate layer 171 is not limited thereto, but may vary according to the material of the external pad 150, the material of the external connection terminal 160, the material of the cover layer 170, and the temperature and time of the reflow soldering process.

According to an exemplary embodiment, in the reflow soldering for forming the external connection terminal 160, the third metal material included in the cover layer 170 diffuses, and thus, the external connection terminal 160 may include the third metal material. According to an exemplary embodiment, the content of the third metal material included in the external connection terminal 160 may be 0.00001wt% or more, 0.00005wt% or more, 0.0001wt% or more, 0.0003wt% of the entire weight of the external connection terminal 160 % Above, and above 0.0005wt%. In the case where the content of the third metal material including the external connection terminal 160 is less than 0.00001wt% of the entire weight of the external connection terminal 160, since the wettability of the covering layer 170 is reduced, When the connection terminal 160 is subjected to reflow welding, the fluidity of the material constituting the external connection terminal 160 is not sufficiently enhanced. As a result, the side wall of the external pad 150 is not covered by the external connection terminal 160, or the external connection on the side wall of the external pad 150 The terminal 160 may be formed to have an excessively thin thickness.

And, according to an exemplary embodiment, the content of the third metal material included in the external connection terminal 160 may be 1 wt% or less, 0.95 wt% or less, 0.85 wt% or less of the entire weight of the external connection terminal 160, and 0.8wt% or less. In the case where the content of the third metal material included in the external connection terminal 160 is greater than 1 wt% of the entire weight of the external connection terminal 160, in the reflow welding of the external connection terminal 160 using the covering layer 170, due to the composition The fluidity of the material of the external connection terminal 160 is excessively strengthened, so the height of the external connection terminal 160 may be too low, and the intermetallic compound between the external connection terminal 160 and the external pad 150 may be formed too thick.

In a general semiconductor package, the intermetallic compound formed at the interface between the external pad and the external connection terminal is exposed, or the external connection terminal covering the intermetallic compound on the sidewall of the external pad is formed to have an extremely thin thickness. The intermetallic compound is susceptible to external shocks, and the external shocks cause frequent cracks near the edges of the external pads, thereby reducing the reliability of the bonding between the semiconductor package and the external device.

However, according to an exemplary embodiment of the present invention, the reflow soldering process is performed in a state where the cover layer 170 excellent in wettability is formed. Thus, the external connection terminal 160 covering the intermetallic compound on the side wall 158 of the external pad 150 may be formed to have a thicker thickness. For example, regarding the first direction (for example, the X direction or the Y direction) parallel to the first surface 118 of the semiconductor wafer 110, between the uppermost end 157 of the side wall 158 of the external pad 150 and the external surface of the external connection terminal 160, The first thickness 159 of the external connection terminal 160 along the first direction may be at least 10 μm. For example, the first thickness 159 of the external connection terminal 160 may be between 10 μm and 30 μm. Here, the first thickness 159 of the external connection terminal 160 may represent the distance in the first direction between the uppermost end 157 of the side wall 158 of the external pad 150 and the external surface of the external connection terminal 160 minus the external pad 150 A value derived from the thickness of the intermediate layer 171 on the sidewall 158 of the φ in the first direction. Therefore, according to the exemplary embodiment of the present invention, the external connection terminal 160 covering the side wall 158 of the external pad 150 can reduce external impact, thereby suppressing the occurrence of cracks near the external pad 150, and ultimately improving the semiconductor package 100b and Reliability of bonding between external devices.

4A to 4H are cross-sectional views sequentially showing a method of manufacturing a semiconductor package according to an exemplary embodiment of the present invention. Hereinafter, a method of manufacturing the semiconductor package 100 of FIG. 1 will be described with reference to FIGS. 4A to 4H.

Referring to FIG. 4, a first insulating pattern 131 is formed on the first surface 118 of the semiconductor wafer 110. For example, in order to form the first insulating pattern 131, a first insulating film covering the first surface 118 of the semiconductor wafer 110 may be formed, and a part of the first insulating film may be removed to expose the wafer pad 111 of the semiconductor wafer 110.

After the first insulating pattern 131 is formed, the wiring pattern 140 is formed on the first insulating pattern 131. The wiring pattern 140 may be formed on the first insulating pattern 131 and the die pad 111 of the semiconductor chip 110 exposed by the first insulating pattern 131. For example, the wiring pattern 140 may be formed by a seed film formation process, a mask process mask, and a gold plating process.

After the wiring pattern 140 is formed, the second insulating pattern 133 is formed on the first insulating pattern 131. The second insulation pattern 133 may include an opening 133H for exposing a part of the wiring pattern 140. For example, in order to form the first insulating pattern 131, a second insulating film covering the first insulating pattern 131 and the wiring pattern 140 may be formed, and a part of the second insulating film may be removed to form an opening 133H exposing a part of the wiring pattern 140 .

4B, a lower metal layer 151m is formed, and the lower metal layer 151m covers the second insulating pattern 133 and the wiring pattern 140 exposed through the opening 133H of the second insulating pattern 133. For example, the lower metal layer 151m can be formed by a sputtering process. The lower metal layer 151m may include, for example, titanium (Ti), copper (Cu), chromium (Cr), tungsten (W), nickel (Ni), aluminum (Al), palladium (Pd), gold (Au), or a combination thereof .

4C, after the lower metal layer 151m is formed, a first mask pattern 181 is formed on the lower metal layer 151m. The first mask pattern 181 may include an opening 181H exposing a part of the lower metal layer 151m. For example, the first mask pattern 181 may form a photosensitive material film on the lower metal layer 151m, and may form a pattern in the photosensitive material film by exposing and developing the photosensitive material film.

4D, after the first mask pattern 181 is formed, the upper metal layer 153 is formed in the opening 181H of the first mask pattern 181. The upper metal layer 153 may be formed by a gold plating process using the lower metal layer 151m as a seed.

4E, after the upper metal layer 153 is formed, the first mask pattern 181 is removed (refer to FIG. 4D), and a part of the lower metal layer 151m (refer to FIG. 4D) located below the first mask pattern 181 is removed. For example, the first mask pattern 181 may be removed by a strip process, and the first portion of the lower metal layer 151m may be removed by an etching process. The upper metal layer 153 and the lower metal layer 151 under the upper metal layer 153 may constitute the external pad 150.

Referring to FIG. 4F, a cover layer 170 is formed on the outer pad 150. The cover layer 170 may be formed to cover at least a part of the external pad 150. For example, in order to form the covering layer 170, a metal film including a metal material with excellent wettability is formed on the outer pad 150 by performing an electroless gold plating or sputtering process. The metal film may be formed to have a thin thickness, for example, a thickness between about 0.001 μm and about 1 μm or between about 0.01 μm and about 0.9 μm. For example, the cover layer 170 may include a metal material with excellent wettability, for example, gold (Au), palladium (Pd), nickel (Ni), copper (Cu), solder, or a combination thereof.

4G, a flux 180 is coated on the cover layer 170, and solder balls 163 are provided on the cover layer 170 on which the flux 180 is coated. The solder ball 163 may have a rectangular shape.

4H, solder balls 163 (refer to FIG. 7G) may be placed on the cover layer 170 (refer to FIG. 4G) and then a reflow soldering process sequence may be performed to form the external connection terminal 160. At a high temperature, for example, a temperature of about 200°C to about 280°C The reflow welding process can be performed for several tens of seconds to several minutes. During the reflow soldering process, the cover layer 170 is diffused, and the third metal material included in the cover layer 170 and the first metal material included in the external pad 150 and the second metal material included in the external connection terminal 160 are in contact with each other. As a result of the high temperature reaction, intermetallic compounds can be formed.

Later, the semiconductor package manufactured at the wafer level is cut along the scribe channel to cut the semiconductor package into individual semiconductor packages.

In the case where the outer pad 150 is formed to have a thickness of 150h (refer to FIG. 1) having a height of 10 μm or more, it frequently occurs in a general semiconductor package that the sidewall of the outer pad is still exposed or covered by the reflow soldering process. The external connection terminal of the side wall is not formed thick enough. However, according to an exemplary embodiment of the present invention, the reflow welding process is performed in a state where the cover layer 170 (refer to FIG. 4G) is formed on the outer pad 150. Therefore, the solder in the molten state diffuses along the surface of the covering layer 170 made of a metal material with excellent wettability, and the external connection terminal 160 formed according to the result of the reflow soldering process may be formed to cover the external pad 150 with a thickness的wall158。 The external connection terminal 160 covering the side wall 158 of the external pad 150 can reduce external impact, and therefore, the occurrence of cracks near the external pad 150 can be suppressed, and finally the bonding reliability between the semiconductor package and the external device can be improved.

FIG. 5 is a cross-sectional view of a semiconductor package 100c according to an exemplary embodiment of the present invention. Fig. 6 is an enlarged cross-sectional view showing the area indicated by "VI" in Fig. 5;

Referring to FIGS. 5 and 6, the semiconductor package 100 d may include a semiconductor chip 110, a rewiring structure 120 on the semiconductor chip 110, and external connection terminals 160. The rewiring structure 120 may be disposed on the first surface 118 of the semiconductor wafer 110. The rewiring structure 120 may include an insulating pattern 130, a wiring pattern 140, and an external pad 150.

The outer pad 150 may include a lower metal layer 151 and an upper metal layer 153 on the lower metal layer 151.

The lower metal layer 151 may be formed on the wiring pattern 140 exposed through the opening of the second insulating pattern 133 and extended along the surface of the second insulating pattern 133. The lower metal layer 151 may be, for example, a seed layer or an adhesion layer for forming the upper metal layer 153. For example, the lower metal layer 151 may include titanium (Ti), copper (Cu), chromium (Cr), tungsten ( W), nickel (Ni), aluminum (Al), palladium (Pd), gold (Au), or a combination thereof.

According to an exemplary embodiment, the lower metal layer 151 may be one metal layer, or may have a multilayer structure including a plurality of metal layers. For example, the lower metal layer 151 may include a first sub-metal layer and a second sub-metal layer sequentially stacked on the second insulating pattern 133 and the wiring pattern 140. The first sub-metal layer may include a metal material having excellent bonding characteristics with the second insulating pattern 133. For example, the first sub-metal layer may include titanium (Ti). The second sub-metal layer may form a seed layer of the upper metal layer 153 with a scope. For example, the second submetal layer may include copper (Cu).

According to an exemplary embodiment, the lower metal layer 151 may include a protrusion 1511 protruding from the sidewall 1531 of the upper metal layer 153. The protrusion 1511 of the lower metal layer 151 may be extended along the surface of the second insulation pattern 133. Regarding the first direction (for example, the X direction or the Y direction) parallel to the first surface 118 of the semiconductor wafer 110, the protrusion 1511 of the lower metal layer 151 protrudes from the side wall 1531 of the upper metal layer 153 along the first direction. The length can be between 5 μm and 50 μm. Alternatively, according to an exemplary embodiment, the length of the protrusion 1511 of the lower metal layer 151 from the sidewall 1531 of the upper metal layer 153 along the first direction may be between 5 μm and 50 μm or between 10 μm and 30 μm .

The upper metal layer 153 may be disposed on the lower metal layer 151. For example, the upper metal layer 153 can be formed by a gold plating method using the lower metal layer 151 as a seed. The upper metal layer 153 may have the shape of a pillar erected on the insulating pattern 130 and have a structure in which the center portion is recessed. The upper metal layer 153 may have sidewalls 1531 perpendicular to the first surface 118 of the semiconductor wafer 110. According to an exemplary embodiment, the upper metal layer 153 may include copper (Cu) or an alloy thereof, but the technical idea of the present invention is not limited thereto.

The external connection terminal 160 may be provided on the external pad 150. The external connection terminal 160 may be a wafer-substrate connection terminal for mounting the semiconductor package 100d on an external substrate. According to an exemplary embodiment, the external connection terminal 160 may have a rectangular shape. For example, the external connection terminal 160 may include tin (Sn), silver (Ag), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), zinc (Zn), lead (Pb), and/ Or its alloys.

According to an exemplary embodiment, the external connection terminal 160 may cover the external pad 150. For example, the external connection terminal 160 may cover the upper surface of the upper metal layer 153 and the sidewall 1531 of the upper metal layer 153. Also, the external connection terminal 160 may cover the surface of the second insulation pattern 133 near the external pad 150. The external connection terminal 160 may form a surface contact with the surface of the second insulation pattern 133.

According to an exemplary embodiment, regarding the first direction (for example, the X direction or the Y direction) that is parallel to the first surface 118 of the semiconductor wafer 110, when the sidewall 1531 of the metal layer 153 is aligned with the When a part of the external connection terminal 160 overlapping in the first direction is defined as the first part 169 of the external connection terminal 160, the first part 169 of the external connection terminal 160 based on the sidewall 1531 of the upper metal layer 153 is along the first direction. The minimum thickness of 169t may be between 5 μm and 50 μm, or may be between 10 μm and 30 μm.

In other words, the minimum distance along the first direction between the sidewall 1531 of the upper metal layer 153 and the outer peripheral surface of the first portion 169 of the external connection terminal 160 may be 5 μm to 50 μm, or may be 10 μm to 30 μm.

According to an exemplary embodiment of the present invention, the external connection terminal 160 may completely cover the external pad 150 to prevent the external pad 150 from being exposed, and may improve the semiconductor package by preventing damage to the external pad 150 due to the external pad 150 being exposed. 100c reliability.

7A to 7F are cross-sectional views sequentially showing a method of manufacturing a semiconductor package according to an exemplary embodiment of the present invention.

Referring to FIG. 7A, a product corresponding to the product of FIG. 4D is prepared, and the first mask pattern 181 is removed (refer to FIG. 4D). The first mask pattern 181 may be removed by, for example, a lift-off process.

Referring to FIG. 7B, after removing the first mask pattern 181 (refer to FIG. 4D), a second mask pattern 183 is formed on the lower metal layer 151m. The second mask pattern 183 may include an opening 183H exposing the upper metal layer 153. For example, the second mask pattern 183 may form a photosensitive material film on the lower metal layer 151m, and form a pattern in the photosensitive material film by exposing and developing the photosensitive material film.

According to an exemplary embodiment, the opening part 183H of the second mask pattern 183 may be formed to have a larger width than the upper metal layer 153. The upper surface of the upper metal layer 153 and the sidewall 1531 can be exposed through the opening 183H of the second mask pattern 183, and the lower part can be exposed between the sidewall 1531 of the upper metal layer 153 and the inner wall of the second mask pattern 183 Part of the metal layer 151m.

The inner wall of the second mask pattern 183 formed by the opening 183H of the second mask pattern 183 may be spaced apart from the sidewall of the upper metal layer 153 by a certain distance. According to an exemplary embodiment, regarding the first direction (for example, the X direction or the Y direction) parallel to the first surface 118 of the semiconductor wafer 110, the sidewall 1531 of the upper metal layer 153 and the inner wall of the second mask pattern 183 The separation distance may be between 5 μm and 50 μm, or may be between 10 μm and 30 μm.

Referring to FIG. 7C, after the second mask pattern 183 is formed, a preliminary metal layer 161 covering the external pad 150 is formed in the opening 183H of the second mask pattern 183. For example, the preliminary metal layer 161 may cover the upper surface of the upper metal layer 153, the sidewall 1531 of the upper metal layer 153, and the lower metal layer exposed between the sidewall 1531 of the upper metal layer 153 and the inner wall of the second mask pattern 183 151m. For example, the preliminary metal layer 161 may be formed by a gold plating process.

For example, the preliminary metal layer 161 may include tin (Sn), silver (Ag), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), zinc (Zn), lead (Pb), and/ Or its alloys. According to an exemplary embodiment, the preliminary metal layer 161 may be made of the same material as the solder balls 163 (refer to FIG. 7E) provided on the preliminary metal layer 161 through a subsequent process.

According to an exemplary embodiment, the preliminary metal layer 161 may be formed to fill the space between the sidewall 1531 of the upper metal layer 153 and the inner wall of the second mask pattern 183. Thus, the thickness of the preliminary metal layer 161 covering the sidewall 1531 of the upper metal layer 153 along the first direction (for example, the X direction or the Y direction) may correspond to the thickness of the sidewall 1531 of the upper metal layer 153 and the second mask pattern 183 The separation distance between the inner walls. For example, the thickness of the preliminary metal layer 161 covering the sidewall 1531 of the upper metal layer 153 along the first direction may be between 5 μm and 50 μm, or may be between 10 μm and 30 μm.

Referring to FIG. 7D, after forming the preliminary metal layer 161, the second mask pattern 183 is removed (refer to FIG. 5C). The second mask pattern 183 may be removed by, for example, a lift-off process.

After the second mask pattern 183 is removed, a part of the lower metal layer 151m (see FIG. 7C) exposed by removing the second mask pattern 183 is removed. In other words, the first part of the lower metal layer 151m (refer to FIG. 7C) covered by the preliminary metal layer 161 and the upper metal layer 153 may remain, and the lower metal layer 151m (refer to FIG. 7C) exposed due to the removal of the second mask pattern 183 Can be removed. For example, the second portion of the lower metal layer 151m (refer to FIG. 7C) may be removed by an etching process.

Referring to FIG. 7E, a flux 180 is coated on the preliminary metal layer 161, and solder balls 163 are provided on the preliminary metal layer 161 coated with the flux 180. The solder ball 163 may have a rectangular shape.

Referring to FIG. 7F, the external connection terminals 160 may be formed by placing solder balls 163 (refer to FIG. 7E) on the preliminary metal layer 161 (refer to FIG. 7E) and then performing a reflow soldering process. In the reflow soldering process, since the solder balls 163 and the preliminary metal layer 161 are melted and hardened at a high temperature, the external connection terminals 160 formed by the solder balls 163 and the preliminary metal layer 161 as a whole can be formed.

Since the reflow soldering process is performed in a state where the preliminary metal layer 161 is formed in advance, the external connection terminal 160 formed by the preliminary metal layer 161 may cover the sidewall 1531 of the upper metal layer 153. In this case, on the sidewall of the upper metal layer 153, the thickness of the external connection terminal 160 along the first direction (for example, the X direction or the Y direction) may be equal to or greater than the thickness of the preliminary metal layer 161 along the first direction. The thickness in one direction. For example, on the sidewall 1531 of the upper metal layer 153, the minimum thickness of the external connection terminal 160 along the first direction may be 5 μm to 50 μm, or may be 10 μm to 30 μm.

Afterwards, the semiconductor packages manufactured at the wafer level are cut along the scribe channel to individualize the semiconductor packages to form individual semiconductor packages.

According to an exemplary embodiment of the present invention, since the preliminary metal layer 161 (refer to FIG. 7D) covering the external pad 150 is formed in advance and then the reflow soldering process is performed, the external connection terminal 160 may be formed to completely cover the external pad 150. The external pad 150 can be protected by the external connection terminal 160, so that damage to the external pad 150 can be prevented.

FIG. 8 is a cross-sectional view of a semiconductor package 100e according to an exemplary embodiment of the present invention. Except for further including the diffusion barrier layer 175, the semiconductor package 100e shown in FIG. 8 may have substantially the same configuration as the semiconductor package 100d shown in FIGS. 5 and 6. Regarding FIG. 8, descriptions that overlap with those of FIGS. 5 and 6 are omitted or briefly described.

Referring to FIG. 8, the semiconductor package 100 e may include a semiconductor wafer 110, a rewiring structure 120 on the semiconductor wafer 110, external connection terminals 160, and a diffusion barrier layer 175.

The diffusion barrier layer 175 may be located between the external connection terminal 160 and the external pad 150. The diffusion barrier layer 170 may, for example, cover the upper surface of the upper metal layer 153 and the sidewall 1531 of the upper metal layer 153. In addition, the diffusion barrier layer 175 may cover the protrusion 1511 of the lower metal layer 151 protruding from the sidewall 1531 of the upper metal layer 153 (refer to FIG. 6).

For example, the diffusion barrier layer 175 may include nickel (Ni), cobalt (Co), copper (Cu), or a combination thereof.

According to an exemplary embodiment, the diffusion barrier layer 175 may include a different material from the external connection terminal 160 and may also include a different material from the external pad 150. For example, in the case where the upper metal layer 153 of the external pad 150 includes copper (Cu) and the external connection terminal 160 includes tin (Sn) and silver (Ag), the diffusion barrier layer 175 may include nickel (Ni) or an alloy thereof.

The diffusion barrier layer 175 may be located between the external connection terminal 160 and the external pad 150 to prevent excessive metal compounds from being generated due to the reaction between the external connection terminal 160 and the external pad 150.

Furthermore, the diffusion barrier layer 175 can prevent the external pad 150 from being exposed by covering the external pad 150, and can prevent the external pad 150 from being damaged due to the external pad 150 being exposed, thereby improving the reliability of the semiconductor package 100e.

9A to 9C are cross-sectional views sequentially showing the method of manufacturing the semiconductor package 100e shown in FIG. 8.

9A, a structure corresponding to the product of FIG. 4F is prepared, and a diffusion barrier layer 175 covering the outer pad 150 is formed in the opening 183H of the second mask pattern 183. The diffusion barrier layer 175 may cover the upper surface of the upper metal layer 153, the sidewall 1531 of the upper metal layer 153, and the lower metal layer 151m exposed between the sidewall 1531 of the upper metal layer 153 and the inner wall of the second mask pattern 183 . For example, the diffusion barrier layer 175 may be formed by a gold plating process.

According to an exemplary embodiment, the diffusion barrier layer 175 may be formed to fill the space between the sidewall 1531 of the upper metal layer 153 and the inner wall of the second mask pattern 183. Thus, the thickness of the diffusion barrier layer 175 covering the sidewall 1531 of the upper metal layer 153 along the first direction (for example, the X direction or the Y direction) may correspond to the thickness of the sidewall 1531 of the upper metal layer 153 and the second mask pattern 183 The separation distance between the inner walls. For example, the thickness along the first direction of the diffusion barrier layer 175 covering the sidewall 1531 of the upper metal layer 153 may be between 5 μm and 50 μm, or may be between 10 μm and 330 μm.

Referring to FIG. 9B, the second mask pattern 183 is removed after the diffusion barrier layer 175 is formed (refer to FIG. 9A). For example, the second mask pattern 183 can be removed by a lift-off process (FIG. 9A).

9C, the external connection terminal 160 is formed on the diffusion barrier layer 175. In order to form the external connection terminal 160, similar to the content described with reference to FIGS. 4G and 4H, a cosolvent 180 (refer to FIG. 4G) may be coated on the diffusion barrier layer 175, and on the diffusion barrier layer 175 coated with the cosolvent A solder ball 163 is provided (refer to FIG. 4H), and a reflow soldering process may be performed to melt and harden the solder ball 163.

Later, the semiconductor package manufactured at the wafer level may be cut along the scribe channel to cut the semiconductor package into a single semiconductor package 100e as shown in FIG. 8.

According to an exemplary embodiment of the present invention, even in the case where the external connection terminal 160 formed by the reflow soldering process is formed not to cover the sidewall 1531 of the upper metal layer 153 of the external pad 150, the external pad is also formed to cover The reflow soldering process is performed in the state of the diffusion barrier layer 175 of 150, and therefore, the outer pad 150 may be completely covered by the diffusion barrier layer 175.

FIG. 10 is a cross-sectional view showing a part of a semiconductor package according to an exemplary embodiment of the present invention.

10, the horizontal width 194 of the external connection terminal 160 may be greater than the height 195 of the external connection terminal 160. Here, the horizontal width 194 of the external connection terminal 160 may represent the maximum value of the width of the external connection terminal 160 along the first direction (for example, the X direction or the Y direction) parallel to the first surface 118 of the semiconductor wafer 110, or It may represent the distance between two points at which the arbitrary straight line passes through the center 160M of the external connection terminal 160 along the first direction and the external surface of the external connection terminal 160. Also, the height 195 of the external connection terminal 160 may be the height of the external connection terminal 160 along the second direction (for example, the Z direction) based on the upper surface of the insulating pattern 230. According to an exemplary embodiment, the horizontal width 194 of the external connection terminal 160 may be between 1.2 times and 1.4 times the height 195 of the external connection terminal 160. For example, the horizontal width 194 of the external connection terminal 160 may be between 210 μm and 250 μm. For example, the height 195 of the external connection terminal 160 may be 165 μm to 200 μm.

In an exemplary embodiment, the thickness 191 of the external pad 150 may be 0.09 to 0.5 times the height 195 of the external connection terminal 160. In the case where the thickness 191 of the external pad 150 is greater than 0.5 times the height 195 of the external connection terminal 160, the side wall of the external pad 150 will not be covered by the external connection terminal 160, or the external connection terminal 160 on the side wall of the external pad 150 The thickness may be formed to have an excessively thin thickness. Also, in the case where the thickness 191 of the external pad 150 is less than 0.09 times the height 195 of the external connection terminal 160, the size of the external connection terminal 160 is formed to have a size larger than the required size compared to the size of the external pad 150 . Therefore, since the height of the external connection terminal 160 is too high, the reliability of the bonding between the semiconductor package 100 and the external device may be reduced, and a short circuit may also occur between adjacent external connection terminals 160.

According to an exemplary embodiment, the width 196 of the external pad 150 may be between 0.6 and 0.9 times the horizontal width 194 of the external connection terminal 160. In the case where the width 196 of the external pad 150 is greater than 0.9 times the horizontal width 194 of the external connection terminal 160, the sidewall of the external pad 150 will not be covered by the external connection terminal 160, or it is possible that the external connection on the sidewall of the external pad 150 The terminal 160 is formed to have an excessively thin thickness. Also, in the case where the width 196 of the external pad 150 is less than 0.6 times the horizontal width 194 of the external connection terminal 160, the external connection terminal 160 is formed to have a medium or small size larger than the required size compared to the size of the external pad 150. Therefore, because the height 195 of the external connection terminal 160 is too high, the reliability of the bonding between the semiconductor package 100 and the external device is reduced, and a short circuit may also occur between adjacent external connection terminals 160.

According to an exemplary embodiment, on the sidewall 158 of the external pad 150, the thickness of the external connection terminal 160 along the first direction (for example, the X direction or the Y direction) may be at least 5 μm. For example, on the sidewall 158 of the external pad 150, the thickness of the external connection terminal 160 along the first direction may be at least 5um. For example, between the uppermost end 157 of the sidewall 158 of the external pad 150 and the external surface of the external connection terminal 160, the thickness 193 of the external connection terminal 160 along the first direction may be between 10 μm and 30 μm. For example, between the lowermost end of the sidewall 158 of the external pad 150 and the external surface of the external connection terminal 160, the thickness 197 of the external connection terminal 160 along the first direction may be between 5 μm and 20 μm.

Regarding a cross section of the external connection terminal 160 parallel to the first surface 118 of the semiconductor wafer 110 and having the largest width along the first direction, when the center of a cross section of the external connection terminal 160 is defined as the center of the external connection terminal 160 At 160M, the center 160M of the external connection terminal 160 may be lower than the center of the external connection terminal of a general package. The lower the center 160M of the external connection terminal 160 is, the thicker the external connection terminal 160 on the side wall 158 of the external pad 150 may be formed. For example, when the distance along the second direction between the center 160M of the external connection terminal 160 and the upper surface of the insulating pattern 230 is defined as the height 190 of the center 160M of the external connection terminal 160, the center of the external connection terminal 160 The height 190 of 160M may be 0.4 times or less, 0.35 times or less, and 0.3 times or less the height 195 of the external connection terminal 160. In the case where the height 190 of the center 160M of the external connection terminal 160 is greater than 0.4 times the height 195 of the external connection terminal 160, the sidewall of the external pad 150 may not be covered by the external connection terminal 160, or it is possible that the sidewall of the external pad 150 The thickness of the external connection terminal 160 is formed too thin. Also, according to an exemplary embodiment, the height 190 of the center 160M of the external connection terminal 160 may be 0.1 times or more, 0.15 times or more, or 0.2 times the height 195 of the external connection terminal 160. In the case where the height 190 of the center 160M of the external connection terminal 160 is less than 0.1 times the height 195 of the external connection terminal 160, the height of the external connection terminal 160 may be too low.

The height 190 of the center 160M of the external connection terminal 160 can be adjusted according to the thickness 191 of the external pad 150, the width 196 of the external pad 150, and/or the horizontal width 194 of the external connection terminal 160.

The center 160M of the external connection terminal 160 is spaced apart from the external pad 150 along the second direction (for example, the Z direction) and abuts the external pad 150. The closer the center 160M of the external connection terminal 160 is to the external pad 150, the greater the thickness of the external connection terminal 160 covering the side wall 158 of the external pad 150 may be. For example, the shortest distance 192 along the second direction between the center 160M of the external connection terminal 160 and the external pad 150 may be between 0.5 and 6 times the thickness of the external pad 150. For example, the shortest distance along the second direction between the center 160M of the external connection terminal 160 and the external pad 150 may be between 10um and 60um.

According to an exemplary embodiment, with respect to the second direction, the shortest distance 192 between the center 160M of the external connection terminal 160 and the external pad 150 along the second direction may be equal to or less than that of the external pad 150 along the first direction. 191 thickness in two directions.

In a general semiconductor package, the intermetallic compound formed at the interface between the external pad and the external connection terminal is exposed, or the external connection terminal covering the intermetallic compound on the side wall of the external pad is formed to have an extremely thin thickness . The intermetallic compound is susceptible to external shocks, and the external shocks cause frequent cracks near the edges of the external pads, thereby reducing the reliability of the bonding between the semiconductor package and the external device.

FIG. 11 is a cross-sectional view of a semiconductor package 200 according to an exemplary embodiment of the present invention. Fig. 12 is an enlarged cross-sectional view showing the area indicated by "XII" in Fig. 11;

11 and 12, the semiconductor package 200 may include a semiconductor chip 210, a rewiring structure 220 on the semiconductor chip 210, and external connection terminals 260.

Multiple individual devices of various categories may be formed in the semiconductor wafer 210. For example, the plurality of individual components may include various microelectronic devices, such as metal oxide semiconductor field effect transistors (MOSFETs) such as complementary metal oxide semiconductors (CMOS), large-scale integrated circuits ( large scale integration), image sensors such as CMOS image sensor (CIS), micro electromechanical system (MEMS), active components, and passive components.

The semiconductor wafer 210 may include a wafer pad 211 disposed on the first surface 218. The wafer pad 211 may be electrically connected to the various elements formed in the semiconductor wafer 210. Also, the semiconductor wafer 210 may include a passivation film 213 covering the first surface 218.

According to an exemplary embodiment, the semiconductor wafer 210 may be a memory semiconductor device, for example. The memory semiconductor device may be a volatile memory semiconductor device such as dynamic random access memory (DRAM) or static random access memory (SRAM), or phase change random access memory (PRAM), magnetic Non-volatile memory semiconductor devices such as resistive random access memory (MRAM), ferroelectric random access memory (FeRAM), or resistive random access memory (RRAM).

Alternatively, according to an exemplary embodiment, the semiconductor wafer 210 may be a logic wafer. For example, the semiconductor chip 210 may be a central processing unit (CPU), a microprocessor (MPU), a graphics processing unit (GPU), or an application processor (AP).

Also, although FIG. 11 shows that the semiconductor package 200 includes one semiconductor wafer 210, the semiconductor package 200 may include two or more semiconductor wafers 210. The two or more semiconductor wafers 210 included in the semiconductor package 200 may be the same type of semiconductor wafer, or may be different types of semiconductor wafers. According to some embodiments, the semiconductor package 200 may be a system in package (SIP: system in package) in which different types of semiconductor chips are electrically connected to each other and operated as a system.

The rewiring structure 220 may be disposed on the first surface 218 of the semiconductor wafer 210. The rewiring structure 220 may include an insulating pattern 230, a wiring pattern 240, and an external pad 250.

The insulating pattern 230 may be disposed on the first surface 218 of the semiconductor wafer 210. The insulating pattern may have a structure in which a plurality of insulating films are stacked. For example, the insulating pattern 230 may include a first insulating pattern 231 and a second insulating pattern 233 sequentially stacked on the first surface 218 of the semiconductor wafer 210.

For example, the first insulating pattern 231 and the second insulating pattern 233 may be made of insulating polymer, epoxy, silicon oxide film, silicon nitride film, insulating polymer, or a combination thereof, respectively.

The wiring pattern 240 may be disposed in the insulating pattern 230 and electrically connect the wafer pad 211 of the semiconductor wafer 210 and the external pad 250. More specifically, a part of the wiring pattern 240 may be connected to the wafer pad 211 of the semiconductor wafer 210 through the opening of the first insulating pattern 231, and another part of the wiring pattern 240 may be extended along the surface of the first insulating pattern 231. For example, the wiring pattern 240 may be made of tungsten (W), copper (Cu), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), ruthenium (Ru), palladium (Pd), platinum (Pt) ), cobalt (Co), nickel (Ni), or a combination thereof.

Although the drawing shows that the wiring pattern 240 has a single-layer structure, the wiring pattern 240 may have a multilayer structure in which a plurality of wiring layers are stacked in a vertical direction.

An external pad 150 may be disposed on the second insulating pattern 233 and used as a pad for disposing the external connection terminal 260. The external pad 250 may be connected to the wiring pattern 240 through the opening of the second insulating pattern 233, and may be electrically connected to the die pad 211 of the semiconductor chip 210 through the wiring pattern 140.

The external pad 250 may be formed to be thicker than the wiring pattern 240. For example, compared to the wiring pattern 240 being formed to have a thickness between about 3 μm and 8 μm, the outer pad 250 may be formed to have a thickness of 10 μm or more. The thickness of the outer pad 250 may be the sum of the thickness of the upper metal layer 253 and the thickness of the lower metal layer 251 described later. According to some embodiments, the ratio of the thickness T2 of the outer pad 250 to the thickness T1 of the wiring pattern 240 (ie, T2/T1) may be about 1.25 to about 40, about 2 to about 35, or about 5 to about 20. If the ratio of the thickness of the external pad 250 to the thickness of the wiring pattern 240 is too small, there will be a problem in adhesion due to insufficient growth of the intermetallic compound. If the ratio is too large, the manufactured semiconductor device The thickness may be too large.

For the second direction (for example, the Z direction) perpendicular to the first surface 218 of the semiconductor wafer 210, the height 250h of the outer pad 250 may represent the length of the outer pad 250 along the upper surface of the second insulating pattern 233. The thickness in the second direction. According to an exemplary embodiment, the height 250h of the outer pad 250 may be between about 10 μm and about 120 μm. According to some embodiments, the height 250h of the outer pad 250 may be between about 20 μm and about 50 μm, or about 30 μm.

The outer pad 250 may include a lower metal layer 251 and an upper metal layer 253 on the lower metal layer 251.

The lower metal layer 251 may be formed on the wiring pattern 240 exposed through the opening of the second insulating pattern 233 and extended along the surface of the second insulating pattern 233. The lower metal layer 251 may be, for example, a seed layer or a bonding layer for forming the upper metal layer 253. For example, the lower metal layer 251 may include titanium (Ti), copper (Cu), chromium (Cr), tungsten (W), nickel (Ni), aluminum (Al), palladium (Pd), gold (Au), or combination.

According to an exemplary embodiment, although the lower metal layer 251 may be one metal layer, it may also have a multilayer structure including a plurality of metal layers. For example, the lower metal layer 251 may include a first sub-metal layer and a second sub-metal layer sequentially stacked on the second insulation pattern 233 and the wiring pattern 240. The first sub-metal layer may include a metal material having excellent bonding characteristics with the second insulating pattern 233. For example, the first sub-metal layer may include titanium (Ti). The second submetal layer may be used as a seed layer for forming the upper metal layer 253. For example, the second submetal layer may include copper (Cu).

The upper metal layer 253 may be disposed on the lower metal layer 251. For example, the upper metal layer 253 can be formed by a gold plating method using the lower metal layer 251 as a seed. The upper metal layer 253 may have a pillar shape erected on the insulating pattern 230 and have a structure in which the center portion is recessed. The upper metal layer 253 may have sidewalls 2531 perpendicular to the first surface 218 of the semiconductor wafer 210. According to an exemplary embodiment, the upper metal layer 253 may include copper (Cu) or an alloy of copper, but the technical idea of the present invention is not limited thereto.

According to some embodiments, the upper metal layer 253 may have a thickness of about 10 μm to about 100 μm, about 15 μm to about 80 μm, or about 20 μm to about 60 μm.

According to some embodiments, the lower metal layer 251 may have a thickness of about 1 μm to about 20 μm, about 3 μm to about 15 μm, or about 4 μm to about 10 μm.

According to an exemplary embodiment, the lower metal layer 251 may have a lateral profile located on the inner side than the sidewall 2531 of the upper metal layer 253. In other words, compared to the sidewall 2531 of the upper metal layer 253, the sidewall 2511 of the lower metal layer 251 may retract toward the center of the lower metal layer 251. In other words, the upper metal layer 253 may include a protrusion 2533 protruding to the lower metal layer 251 in a lateral direction.

According to some embodiments, the sidewall 2511 of the lower metal layer 251 may have a profile recessed toward the center of the lower metal layer 251. According to some embodiments, the sidewall 2511 of the lower metal layer 251 may have a profile recessed toward the center of the lower metal layer 251. For example, the contour of the depression can be substantially a circular arc, a parabola, an elliptical arc, and the like. According to some embodiments, the sidewall 2511 of the lower metal layer 251 may have a substantially straight profile along the vertical direction (Z direction).

The sidewall 2511 of the lower metal layer 251 may be located on the surface of the second insulation pattern 233. In other words, the central portion of the lower metal layer 251 contacts the wiring pattern 240, and the edge of the lower metal layer 251 may extend to the upper portion of the second insulating pattern 233.

Regarding the first direction parallel to the first surface 218 of the semiconductor wafer 210 (for example, the X direction or the Y direction), the sidewall 2511 of the lower metal layer 251 may face the sidewall 2531 of the upper metal layer 253 compared to the sidewall 2531 of the upper metal layer 253. The center of the upper and lower metal layer 251 retracts toward the inside by a first width. The first width may be, for example, about 0.1 μm to about 50 μm, about 8 μm to about 30 μm, or about 10 μm to about 25 μm. However, the present invention is not limited to this.

The external connection terminal 260 may be provided on the external pad 250. The external connection terminal 260 may be a wafer-substrate connection terminal for mounting the semiconductor package 200 on an external substrate. According to an exemplary embodiment, the external connection terminal 260 may have a rectangular shape. For example, the external connection terminal 260 may include tin (Sn), silver (Ag), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), zinc (Zn), lead (Pb), and/ Or its alloys.

According to an exemplary embodiment, the external connection terminal 260 may cover the external pad 250. For example, the external connection terminal 260 may cover the upper surface of the upper metal layer 253 and the sidewall 2531 of the upper metal layer 253. Also, the external connection terminal 260 may cover a part of the surface of the second insulation pattern 233 near the external pad 250. The external connection terminal 260 may form a surface contact with the surface of the second insulation pattern 233.

According to an exemplary embodiment, with regard to the first direction (for example, the X direction or the Y direction) parallel to the first surface 218 of the semiconductor wafer 210, the sidewall 2511 of the lower metal layer 251 and the upper metal layer 253 When the part of the external connection terminal 260 overlapping the side wall 2531 along the first direction is defined as the first part 269 of the external connection terminal 260, the first part 269 of the external connection terminal 260 is based on the side wall 2531 of the upper metal layer 253 The minimum thickness 269t along the first direction may be between 5 μm and 50 μm, or may be between 10 μm and 30 μm.

In other words, the minimum distance along the first direction between the sidewall of the upper metal layer 253 and the outer peripheral surface of the first portion 269 of the external connection terminal 260 may be between 5 μm and 50 μm, or may be between 10 μm and 30 μm.

The external connection terminal 260 may include an extension portion 260 e extended to a lower portion of the protruding portion 2533. The extension 260e may be a part of the first part 269. The upper portion of the extension portion 260e may contact the lower surface of the upper metal layer 253, and the lower portion of the extension portion 260e may contact the upper surface of the second insulating pattern 233. Furthermore, the extension portion 260e may contact at least a part of the sidewall 2511 of the lower metal layer 251. According to some embodiments, the extension portion 260e may be extended to the inside of the recessed portion of the side wall 251.

The extension 260e may extend about 5 μm to about 50 μm, about 8 μm to about 30 μm, or about 10 μm to about 25 μm toward the center of the lower metal layer 251 in the horizontal direction based on the sidewall 2531 of the upper metal layer 253.

According to an exemplary embodiment of the present invention, the external connection terminal 260 may completely cover the external pad 250 to prevent the external pad 250 from being exposed, and may prevent damage to the external pad 250 due to the external pad 250 being exposed. Furthermore, the external connection terminal 260 is extended to the lower part of the upper metal layer 253 of the external pad 250 to expand the contact area between the external connection terminal 260 and the external pad 250, so that the reliability of the semiconductor package 200 can be improved.

According to an exemplary embodiment, the horizontal width 294 of the external connection terminal 260 may be greater than the height 295 of the external connection terminal 260. Here, the horizontal width 294 of the external connection terminal 260 may indicate the maximum value of the width of the external connection terminal 260 in the second direction (for example, the X direction or the Y direction) parallel to the first surface 218 of the semiconductor wafer 210, or may indicate Regarding an arbitrary straight line passing through the center 260M of the external connection terminal 260 along the second direction, the distance between two points at which the arbitrary straight line and the external surface of the external connection terminal 260 intersect. Also, the height 295 of the external connection terminal 260 may be the height of the external connection terminal 260 along the first direction (for example, the Z direction) based on the upper surface of the insulating pattern 230. According to an exemplary embodiment, the horizontal width 294 of the external connection terminal 260 may be between 1.2 times and 1.4 times the height 295 of the external connection terminal 260. For example, the horizontal width 294 of the external connection terminal 260 may be between 210 μm and 250 μm. For example, the height 295 of the external connection terminal 260 may be between 165 μm and 200 μm.

According to an exemplary embodiment, the height 250h of the external pad 250 may be between 0.09 times and 0.5 times the height 295 of the external connection terminal 260. In the case where the height 250h of the external pad 250 is greater than 0.5 times the height 295 of the external connection terminal 260, the side wall of the external pad 250 will not be covered by the external connection terminal 260, or the external connection terminal 260 on the side wall of the external pad 250 The thickness may be formed to have an excessively thin thickness. Also, in a case where the height 250h of the external pad 250 is less than 0.09 times the height 295 of the external connection terminal 260, the external connection terminal 260 is formed to have a size larger than the required size compared to the size of the external pad. Therefore, since the height 295 of the external connection terminal 260 is too high, the bonding reliability between the semiconductor package 200 and the external device may be reduced, and a short circuit may occur between adjacent external connection terminals 260.

According to an exemplary embodiment, the width 296 of the external pad 250 may be between 0.6 and 0.9 times the horizontal width 294 of the external connection terminal 260. In the case where the width 296 of the external pad 250 is greater than 0.9 times the horizontal width 294 of the external connection terminal 260, the side wall of the external pad 250 will not be covered by the external connection terminal 260, or it is possible that the external connection on the side wall of the external pad 250 The terminal 260 is formed to have an excessively thin thickness. Also, in a case where the width 296 of the external pad 250 is less than 0.6 times the horizontal width 294 of the external connection terminal 260, the external connection terminal 260 is formed to have a size larger than a required size compared to the size of the external pad 250. Therefore, since the height 295 of the external connection terminal 260 is too high, the bonding reliability between the semiconductor package 200 and the external device may be reduced, and a short circuit may occur between adjacent external connection terminals 260.

For example, between the uppermost end of the sidewall of the external pad 250 and the external surface of the external connection terminal 260, the thickness 293 of the external connection terminal 260 along the first direction may be between 5 μm and 50 μm.

Regarding a cross section of the external connection terminal 260 parallel to the first surface 218 of the semiconductor wafer 210 and having the largest width along the second direction (for example, the X direction or the Y direction), when one of the external connection terminals 260 is The center of the cross-section is defined as the center 260M of the external connection terminal 260, and the center 260M of the external connection terminal 260 may be lower than the center of the external connection terminal of a general package. The lower the center 260M of the external connection terminal 260 is, the thicker the external connection terminal 260 of 2531 on the side wall of the external pad 250 may be formed. For example, when the distance between the center 260M of the external connection terminal 260 and the upper surface of the insulating pattern 230 along the first direction (for example, the Z direction) is defined as the height 290 of the center 260M of the external connection terminal 260, The height 290 of the center 260M of the external connection terminal 260 may be equal to or less than 0.4 times, 0.35 times, or 0.3 times the height 295 of the external connection terminal 260. In the case where the height 290 of the center 260M of the external connection terminal 260 is greater than 0.4 times the height 295 of the external connection terminal 260, the side wall of the external pad 250 will not be covered by the external connection terminal 260, or it may be on the side wall of the external pad 250 The external connection terminal 260 is formed to have an excessively thin thickness. Also, according to an exemplary embodiment, the height 290 of the center 260M of the external connection terminal 260 may be equal to or greater than 0.1 times, 0.15 times, or 0.2 times the height 295 of the external connection terminal 260. In the case where the height 290 of the center 260M of the external connection terminal 260 is less than 0.1 times the height 295 of the external connection terminal 260, the height of the external connection terminal 260 may be too low.

The height 290 of the center 260M of the external connection terminal 260 can be adjusted according to the height 250h of the external pad 250, the width 296 of the external pad 250, and/or the horizontal width 294 of the external connection terminal 260.

The center 260M of the external connection terminal 260 may be spaced apart from the external pad 250 in the first direction (for example, the Z direction) and adjacent to the external pad 250. The more the center 260M of the external connection terminal 260 is adjacent to the external pad 250, the thicker the thickness of the external connection terminal 260 covering the side wall 2531 of the external pad 250 may be. For example, the shortest distance 292 along the first direction between the center 260M of the external connection terminal 260 and the external pad 250 may be 0.5 to 6 times the height 250h of the external pad 250. For example, the shortest distance 292 along the first direction between the center 260M of the external connection terminal 260 and the external pad 250 may be between 10 μm and 60 μm.

According to an exemplary embodiment, with respect to the first direction, the shortest distance 292 between the center 260M of the external connection terminal 260 and the external pad 250 along the first direction may be equal to or less than that of the external pad 250 along the first direction. The height in one direction is 250h.

13A to 13K are cross-sectional views sequentially illustrating a method of manufacturing the semiconductor package 200 in FIG. 11 according to an embodiment of the present invention.

13A, a first insulating pattern 231 is formed on the first surface 218 of the semiconductor wafer 210. For example, in order to form the first insulating pattern 231, a first insulating film covering the first surface 218 of the semiconductor wafer 210 may be formed, and a part of the first insulating film may be removed to expose the wafer pad 211 of the semiconductor wafer 210.

According to some embodiments, before forming the first insulating pattern 231, a passivation film exposing the wafer pad 211 may be formed. The passivation film may be formed by covering the entire surface of the first surface 218 with a passivation material film and then performing patterning to expose the wafer pad 211. The passivation material film can be, for example, silicon nitride, silicon oxynitride, silicon oxide, etc., and can be formed by physical vapor deposition (PVD: physical vapor deposition), chemical vapor deposition (CVD: chemical vapor deposition), etc. .

After the first insulating pattern 231 is formed, the wiring pattern 240 is formed on the first insulating pattern 231. The wiring pattern 240 may be formed on the first insulating pattern 231 and the die pad 211 of the semiconductor chip 210 exposed by the first insulating pattern 231. For example, the wiring pattern 240 can be formed by a seed film formation process, a mask process, and a gold plating process.

After the wiring pattern 240 is formed, the second insulating pattern 233 is formed on the first insulating pattern 231. The second insulating pattern 233 may include an opening part 233H for exposing a part of the wiring pattern 240. For example, in order to form the first insulating pattern 231, a second insulating film covering the first insulating pattern 231 and the wiring pattern 240 may be formed, and a part of the second insulating film may be removed to form an opening 233H exposing a part of the wiring pattern 240 .

13B, a lower metal layer 251m is formed, and the lower metal layer 251m covers the second insulating pattern 233 and the wiring pattern 240 exposed through the opening 233H of the second insulating pattern 233. For example, the lower metal layer 251m may be formed by a sputtering process. The lower metal layer 251m may include, for example, titanium (Ti), copper (Cu), chromium (Cr), tungsten (W), nickel (Ni), aluminum (Al), palladium (Pd), gold (Au), or a combination thereof .

13C, after the lower metal layer 251m is formed, a first mask pattern 281 is formed on the lower metal layer 251m. The first mask pattern 281 may include an opening 281H exposing a part of the lower metal layer 251m. For example, the first mask pattern 281 may form a photosensitive material film on the lower metal layer 251m, and form a pattern in the photosensitive material film by exposing and developing the photosensitive material film.

13D, after forming the first mask pattern 281, an upper metal layer 253 is formed in the opening 281H of the first mask pattern 281. The upper metal layer 253 may be formed by a gold plating process using the lower metal layer 251m as a seed. According to some embodiments, the plating process sequence may be an electrolytic gold plating process.

Referring to FIG. 13E, after the upper metal layer 253 is formed, the first mask pattern 281 on the lower metal layer 251m is removed (refer to FIG. 13D). For example, the first mask pattern 281 may be removed by a strip process (refer to FIG. 13D).

Referring to FIG. 13F, after removing the first mask pattern 281 (refer to FIG. 13D), a second mask pattern 283 is formed on the lower metal layer 251m. The second mask pattern 283 may include an opening 283H exposing the upper metal layer 253. For example, the second mask pattern 283 may form a photosensitive material film on the lower metal layer 251m, and form a pattern in the photosensitive material film by exposing and developing the photosensitive material film.

According to an exemplary embodiment, the opening portion 283H of the second mask pattern 283 may be formed to have a width larger than that of the upper metal layer 253. The upper surface of the upper metal layer 253 and the sidewall 2531 can be exposed through the opening 283H of the second mask pattern 283, and a part of the lower metal layer 251m near the sidewall 2531 of the upper metal layer 253 can be exposed.

The inner wall of the second mask pattern 283 formed by the opening 283H of the second mask pattern 283 may be separated from the sidewall 2531 of the upper metal layer 253 by a certain distance. According to an exemplary embodiment, for the first direction (for example, the X direction or the Y direction) parallel to the first surface 218 of the semiconductor wafer 210, the sidewall 2531 of the upper metal layer 253 and the inner portion of the second mask pattern 283 The separation distance 283t between the walls may be between 5um and 50um, or may be between 10um and 30um.

13G, after the second mask pattern 283 is formed, a preliminary external connection terminal layer 261 covering the external pad 250 is formed in the opening 283H of the second mask pattern 283. For example, the preliminary external connection terminal layer 261 may cover the upper surface of the upper metal layer 253, the sidewall 2531 of the upper metal layer 253, and the lower portion exposed between the sidewall 2531 of the upper metal layer 253 and the inner wall of the second mask pattern 283 Metal layer 251m. For example, the preliminary external connection terminal layer 261 may be formed by a gold plating process.

For example, the preliminary external connection terminal layer 261 may include tin (Sn), silver (Ag), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), gold (Au), zinc (Zn), Lead (Pb), and/or its alloys. According to an exemplary embodiment, the preliminary external connection terminal layer 261 may be composed of the same material as the solder balls 263 (refer to FIG. 13J) provided on the preliminary external connection terminal layer 261 by a subsequent process. According to some embodiments, the preliminary external connection terminal layer 261 may be a single metal layer such as a gold (Au) layer. According to some embodiments, the preliminary external connection terminal layer 261 may be a laminate in which a single metal layer is stacked.

According to an exemplary embodiment, the preliminary external connection terminal layer 261 may be formed to fill the space between the sidewall 2531 of the upper metal layer 253 and the inner wall of the second mask pattern 283. Thus, the thickness of the preliminary external connection terminal layer 261 covering the sidewall 2531 of the upper metal layer 253 along the first direction (for example, the X direction or the Y direction) may correspond to the sidewall 2531 of the upper metal layer 253 and the second mask pattern The separation distance between the inner walls of 283 is 283t (refer to FIG. 13F). For example, the thickness of the preliminary external connection terminal layer 261 covering the sidewall 2531 of the upper metal layer 253 along the first direction may be between 5 μm and 50 μm, or may be between 10 μm and 30 μm.

Referring to FIG. 13H, after forming the preliminary external connection terminal layer 261, the second mask pattern 283 is removed (refer to FIG. 13G). For example, the second mask pattern 283 can be removed by a lift-off process (FIG. 13G).

Referring to FIG. 13I, after removing the second mask pattern 283 (FIG. 13G), a part of the lower metal layer 251m (FIG. 13G) exposed by the second mask pattern 283 (FIG. 13G) is removed. That is, the first part of the lower metal layer 251m (FIG. 13G) covered by the preliminary external connection terminal layer 261 and the upper metal layer 253 remains, and the lower metal layer 251m is exposed due to the removal of the second mask pattern 283 (FIG. 13G) (Figure 13G) The second part can be removed. For example, the second part of the lower metal layer 251m (FIG. 13G) may be removed by an etching process.

The second part of the lower metal layer 251m (FIG. 13G) can be removed by isotropic etching. In the lower metal layer 251m (FIG. 13G), not only the lower part (ie, the second part) of the second mask pattern 283 (FIG. 13G) can be removed, but also the prepared external connection terminal layer 261 and the upper part can be removed. A part of the edge of the portion of the lower metal layer (ie, the first portion) covered by the metal layer 253. By removing a part of the edge of the first portion as described above, the sidewall of the lower metal layer 251 may have a lateral profile located on the inner side than the sidewall 2531 of the upper metal layer 253. In other words, the sidewall 2511 (refer to FIG. 12) of the lower metal layer 251 may be retracted toward the inner side of the center of the outer metal layer 251 than the sidewall 2531 of the upper metal layer 253.

Fig. 14 is a partially enlarged view enlarging the part denoted by "XIV" in Fig. 13I.

Referring to FIG. 14, the sidewall 2511 of the lower metal layer 251 may have a concave curved surface. Specifically, the sidewall 2511 may have a concave profile facing the center of the lower metal layer 251. According to some embodiments, in the sidewall 2511, the tip portion 2511a of the portion contacting the upper metal layer 253 may be closer to the lower metal layer 251 than the tip portion 2511b of the portion contacting the second insulating pattern 233. The center retracts even more.

Compared with the side wall 2531 of the upper metal layer 253, the side wall 2511 of the lower metal layer 251 is retracted toward the center of the lower metal layer 251 inwardly by a first width 251W. Here, the first width 251W may be based on the most retracted point from the sidewall 2531 of the upper metal layer 253 in the profile of the sidewall 2511 of the lower metal layer 251.

According to some embodiments, the first width 251W may be about 5 μm to about 50 μm, about 8 μm to about 30 μm, or about 10 μm to about 25 μm. However, the present invention is not limited to this.

13J, a solvent 280 is coated on the preliminary external connection terminal layer 261, and solder balls 263 are provided on the preliminary external connection terminal layer 261 coated with the solvent 280. The solder ball 263 may have a rectangular shape.

Referring to FIG. 13K, after the solder balls 263 (FIG. 13J) are provided on the preliminary external connection terminal layer 261 (FIG. 13J), a reflow soldering process is performed to form the external connection terminals 260. The reflow soldering process can be performed for several tens of seconds to several minutes at a high temperature, for example, at a temperature of about 200°C to about 280°C. In the reflow soldering process, the solder ball 263 (FIG. 13J) and the preliminary external connection terminal 261 (FIG. 13J) are melted at high temperature and then hardened, thereby forming the solder ball 263 (FIG. 13J) and the preliminary external connection terminal 261 (FIG. 13J) 13J) Integrated external connection terminal 260.

Since the reflow soldering process is performed in a state where the preliminary external connection terminal 261 (FIG. 13J) is formed in advance, the side wall 2531 of the upper metal layer 253 can be covered by the external connection terminal 260 of the preliminary external connection terminal 261 (FIG. 13J ). In this case, on the sidewall 2531 of the upper metal layer 253, the thickness of the external connection terminal 260 along the first direction (for example, the X direction or the Y direction) may be equal to or greater than the preliminary external connection terminal 261 (FIG. 13J) The thickness along the first direction. For example, on the sidewall 2531 of the upper metal layer 253, the minimum thickness of the external connection terminal 260 along the first direction may be between 5 μm and 50 μm, or may be between 10 μm and 30 μm.

In addition, in the case where the composition of the preliminary external connection terminal 261 (FIG. 13J) is the same as that of the solder ball 263 (FIG. 13J), it is possible to generate an unrecognizable gap between the preliminary external connection terminal 261 (FIG. 13J) and the solder ball. The external connection terminals 260 are bordered and substantially uniform. According to some embodiments, in the case where the thickness of the preliminary external connection terminal 261 (FIG. 13J) is sufficiently thin, the components constituting the preliminary external connection terminal rapidly diffuse into the solder ball during reflow soldering, so that unidentifiable The boundary line between the preliminary external connection terminal 261 (FIG. 13J) and the solder ball is substantially uniform external connection terminal 260.

According to some embodiments, in the case where the preliminary external connection terminal 261 (FIG. 13J) includes a single metal layer such as a gold (Au) layer, by the reflow soldering, the preliminary external connection terminal 261 (FIG. 13J) ) Can form an intermetallic compound (IMC: intermetallic compound) with the specific composition of the upper metal layer 253 and/or the solder ball 263 (FIG. 13J). In this case, the IMC may be located between the external connection terminal 260 and the external pad 250.

According to some embodiments, the IMC generated by reflow welding can fill a part of the unevenness or all the unevenness on the outer pad 250.

Later, the semiconductor package prepared at the wafer level may be cut along the scribe channel to cut the semiconductor package into individual semiconductor packages 200 as shown in FIG. 11.

According to some embodiments, in the step shown in FIG. 13G, the formation of the preliminary external connection terminal layer 261 may be omitted. In this case, the steps in FIGS. 13F to 13H can be omitted. In other words, without forming the second mask pattern 283 (FIG. 13G), the exposed portion of the lower metal layer 251m (FIG. 13G) can be directly removed after the step shown in FIG. 13E.

According to an exemplary embodiment of the present invention, the external connection terminal 260 may completely cover the external pad 250. In particular, when the outer pad 250 is formed to have a thickness of 250h (see FIG. 12) with a height of 10 μm or more, it frequently occurs after the reflow soldering process that the edge of the outer pad 250 is still exposed and the lower metal layer 251 and the upper part The problem of poor adhesion of the metal layer 253. However, according to an exemplary embodiment of the present invention, a reflow soldering process is performed after the preliminary external connection terminal 261 (FIG. 13J) covering the external pad 250 is formed in advance, so that the external connection terminal 260 can be formed to completely cover the external pad 250 and It extends to the lower part of the upper metal layer 253 and contacts the lower metal layer 251. The external pad 250 is isolated from the outside due to the external connection terminals 260, so that damage to the external pad 250 can be prevented.

15A to 15D are cross-sectional views sequentially showing a method of manufacturing the semiconductor package 200 shown in FIG. 11 according to another embodiment of the present invention.

The steps of the manufacturing method of this embodiment in FIGS. 13A to 13D are the same as the manufacturing method of the embodiment described with reference to FIGS. 13A to 13K. Therefore, the different manufacturing steps are mainly described.

The steps shown in FIG. 15A are subsequent steps of the steps in FIGS. 13A to 13D. 15A, after the upper metal layer 253 is formed, the first mask pattern 281 on the lower metal layer 251m is removed (refer to FIG. 13D). For example, the second mask pattern 281 may be removed by a strip process (refer to FIG. 13D).

Next, a part of the lower metal layer 251m (see FIG. 13D) exposed by removing the first mask pattern 281 (see FIG. 13D) is removed. In other words, the first part of the lower metal layer 251m (refer to FIG. 13D) covered by the upper metal layer 253 may remain, and the lower metal layer 251m (refer to FIG. 13D) exposed by removing the first mask pattern 281 (refer to FIG. 13D) The second part can be removed. For example, the second portion of the lower metal layer 251m (refer to FIG. 13D) may be removed by an etching process.

The second part of the lower metal layer 251m (refer to FIG. 13D) can be removed by isotropic etching. In the lower metal layer 251m (refer to FIG. 13D), not only the lower part (ie, the second part) of the first mask pattern 281 (refer to FIG. 13D) can be removed, but also the part covered by the upper metal layer 253 can be removed. A part of the edge of the lower metal layer part (ie the first part). By removing a part of the edge of the first portion as described above, the side of the lower metal layer 251 may have a lateral profile that is located on the inner side than the sidewall 2531 of the upper metal layer 253. In other words, the sidewall 2511 (refer to FIG. 12) of the lower metal layer 251 may be retracted toward the center of the outer metal layer 251 toward the inner side compared with the sidewall 2531 of the upper metal layer 253.

15B, after removing the first mask pattern 281 (FIG. 13D), a second mask pattern 283 is formed on the second insulating pattern 233. The second mask pattern 283 may include an opening 283H exposing the upper metal layer 253. For example, the second mask pattern 283 may form a photosensitive material film on the second insulating pattern 233 and the upper metal layer 253, and the photosensitive material film may be exposed and developed through the photosensitive material film. The material film is patterned.

According to an exemplary embodiment, the opening portion 283H of the second mask pattern 283 may be formed to have a width greater than that of the upper metal layer 253. The upper surface of the upper metal layer 253 and the sidewall 2531 may be exposed through the opening 283H of the second mask pattern 283, and a part of the second insulating pattern 233 near the sidewall 2531 of the upper metal layer 253 may be exposed.

The inner wall of the second mask pattern 283 formed by the opening 283H of the second mask pattern 283 may be spaced apart from the sidewall 2531 of the upper metal layer 253 by a certain distance. According to an exemplary embodiment, regarding the first direction (for example, the X direction or the Y direction) parallel to the first surface 218 of the semiconductor wafer 210, the sidewall 2531 of the upper metal layer 253 and the inner portion of the second mask pattern 283 The separation distance 283t between the walls may be between 5 μm and 50 μm, or may be between 10 μm and 30 μm.

15C, after the second mask pattern 283 is formed, a preliminary external connection terminal layer 261 covering the external pad 250 is formed in the opening 283H of the second mask pattern 283. For example, the preliminary external connection terminal layer 261 may cover the upper surface of the upper metal layer 253, the sidewalls of the upper metal layer 253, and the second exposed between the sidewall 2531 of the upper metal layer 253 and the inner wall of the second mask pattern 283. Insulation pattern 233. For example, the preliminary external connection terminal layer 261 can be formed by a gold plating process.

For example, the preliminary external connection terminal layer 261 may include tin (Sn), silver (Ag), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), zinc (Zn), lead (Pb), And/or its alloys. According to an exemplary embodiment, the preliminary external connection terminal layer 261 may be composed of the same material as the solder balls 263 (refer to FIG. 13J) provided on the preliminary external connection terminal layer 261 by a subsequent process.

According to an exemplary embodiment, the preliminary external connection terminal layer 261 may be formed to fill the space between the sidewall 2531 of the upper metal layer 253 and the inner wall of the second mask 283. Thus, the thickness of the preliminary external connection terminal layer 261 covering the sidewall 2531 of the upper metal layer 253 along the first direction (for example, the X direction or the Y direction) may correspond to the sidewall 2531 of the upper metal layer 253 and the second mask pattern The separation distance between the inner walls of 283 is 283t (refer to FIG. 13F). For example, the thickness of the preliminary external connection terminal layer 261 covering the sidewall 2531 of the upper metal layer 253 along the first direction may be between 5 μm and 50 μm, or may be between 10 μm and 30 μm.

Referring to FIG. 15D, the second mask pattern 283 is removed after the preliminary external connection terminal layer 261 is formed (refer to FIG. 15C). For example, the second mask pattern 283 can be removed by a lift-off process (refer to FIG. 15C).

Fig. 16 is a partially enlarged view enlarging the part denoted by "XVI" in Fig. 15D.

Referring to FIG. 16, the sidewall 2511 of the lower metal layer 251 may have a concave curved surface. Specifically, the sidewall 2511 may have a profile recessed toward the center of the lower metal layer 251. The shape and structure of the side wall 2511 are described in detail with reference to FIG. 14, so detailed description is omitted here.

The preliminary external connection terminal layer 261 may include an extension portion 261 e extended to a lower portion of the protruding portion 2533. The upper portion of the extension portion 261e may contact the lower surface of the upper metal layer 253, and the lower portion of the extension portion 261e may contact the upper surface of the second insulating pattern 233. Furthermore, the extension portion 261e may contact at least a part of the sidewall 2511 of the lower metal layer 251.

Then, the semiconductor package 200 may be manufactured according to the steps described with reference to FIGS. 13J and 13K.

FIG. 17 is a cross-sectional view of a semiconductor package 200a according to an exemplary embodiment of the present invention. Except for further including the diffusion barrier layer 270, the semiconductor package 200a shown in FIG. 17 may have substantially the same configuration as the semiconductor package 200 shown in FIGS. 11 and 12. Regarding FIG. 17, the description overlapping with the description of FIG. 11 and FIG. 12 is omitted or briefly described.

Referring to FIG. 17, the semiconductor package 200 a may include a semiconductor wafer 210, a rewiring structure 220 on the semiconductor wafer 210, external connection terminals 260, and a diffusion barrier layer 270.

The diffusion barrier layer 270 may be located between the external connection terminal 260 and the external pad 250. The diffusion barrier layer 270 may, for example, cover the upper surface of the upper metal layer 253 and the sidewall 2531 of the upper metal layer 253. In addition, the lower surface of the diffusion barrier layer 270 may be located on the same plane as the lower surface of the upper metal layer 253. In other words, the lower surface of the diffusion barrier layer 270 may be located on the same plane as the upper surface of the lower metal layer 251.

For example, the diffusion barrier layer 270 may include nickel (Ni), cobalt (Co), copper (Cu), or a combination thereof.

According to an exemplary embodiment, the diffusion barrier layer 270 may include a different material from the external connection terminal 260 and may also include a different material from the external pad 250. For example, in the case where the upper metal layer 253 of the external pad 250 includes copper (Cu) and the external connection terminal 260 includes tin (Sn) and silver (Ag), the diffusion barrier layer 270 may include nickel (Ni) or a nickel alloy.

The diffusion barrier layer 20 may be located between the external connection terminal 260 and the external pad 250 to prevent excessive metal compounds from being generated due to the reaction between the external connection terminal 260 and the external pad 250.

Furthermore, the diffusion barrier layer 270 can cover the external pad 250 to prevent the external pad 250 from being exposed, and can improve the reliability of the semiconductor package 200a by preventing the external pad 250 from being damaged due to the external pad 250 being exposed.

18A to 18C are cross-sectional views sequentially showing a method of manufacturing the semiconductor package 200a shown in FIG. 17.

Referring to FIG. 18A, a structure corresponding to the product of FIG. 13F is prepared, and a diffusion barrier layer 270 covering the outer pad 250 is formed in the opening 283H of the second mask pattern 283. The diffusion barrier layer 270 may cover the upper surface of the upper metal layer 253, the sidewall 2531 of the upper metal layer 253, and the lower metal layer 251m exposed between the sidewall 2531 of the upper metal layer 253 and the inner wall of the second mask pattern 283. For example, the diffusion barrier layer 270 may be formed by a gold plating process.

According to an exemplary embodiment, the diffusion barrier layer 270 may be formed to fill the space between the sidewall 2531 of the upper metal layer 253 and the inner wall of the second mask pattern 283. Thus, the thickness of the diffusion barrier layer 270 covering the sidewall 2531 of the upper metal layer 253 in the first direction (for example, the X direction or the Y direction) may correspond to the thickness of the sidewall 2531 of the upper metal layer 253 and the second mask pattern 283. The separation distance between the inner walls. For example, the thickness of the diffusion barrier layer 270 covering the sidewall 2531 of the upper metal layer 253 along the first direction may be between 5 μm and 50 μm, or may be between 10 μm and 30 μm.

Referring to FIG. 18B, after the diffusion barrier layer 270 is formed, the second mask pattern 283 is removed (refer to FIG. 18A). For example, the second mask pattern 283 can be removed by a lift-off process (refer to FIG. 18A).

After the second mask pattern 283 (FIG. 18A) is removed, a part of the lower metal layer 251m (FIG. 18A) exposed by removing the second mask pattern 283 (refer to FIG. 18A) is removed. In other words, the first portion of the lower metal layer 251m (see FIG. 18A) covered by the diffusion barrier layer 270 and the upper metal layer 253 may remain, and the lower metal layer 251m (see FIG. 18A) exposed by removing the second mask pattern 283 (see FIG. 18A) Refer to Figure 18A) The second part can be removed. For example, the second portion of the lower metal layer 251m (FIG. 18A) can be removed by an etching process.

The formation of the lower metal layer 251 is described with reference to FIG. 13I and the like, so detailed description is omitted here.

Referring to FIG. 18C, external connection terminals 260 are formed on the diffusion barrier layer 270. In order to form external connection terminals, similar to the content described with reference to FIGS. 13J and 13K, a reflow soldering process may be performed, which coats the flux 280 (refer to FIG. 13J) on the diffusion barrier layer 270, and applies the flux to the The diffusion barrier layer 270 is provided with solder balls 263 (refer to FIG. 13J), and the solder balls 263 are melted and hardened.

Later, the semiconductor package prepared at the wafer level may be cut along the scribing channel to cut the semiconductor package into individual semiconductor packages 200a as shown in FIG. 17.

According to an exemplary embodiment of the present invention, even in the case where the external connection terminal 260 formed by the reflow soldering process is formed so as not to cover the sidewall 2531 of the upper metal layer 253 of the external pad 250, since it is formed to cover the external pad 250 The reflow soldering process is performed in the state of the diffusion barrier layer 270, therefore, the outer pad 250 may also be completely covered by the diffusion barrier layer 270.

FIG. 19 is a cross-sectional view of a semiconductor package 200b according to an exemplary embodiment of the present invention. FIG. 20 is a cross-sectional view showing the area indicated by "XX" in FIG. 19 in an enlarged manner.

19 and 20, the semiconductor package 200b is the same as the semiconductor package described with reference to FIGS. 11 and 12, except that an intermetallic compound region 255 is further formed between the external connection terminal 260 and the external pad 250. Therefore, the following description focuses on the above-mentioned differences of the semiconductor package 200b.

As shown in FIG. 19, after the external connection terminal 260 is formed by reflow welding, an intermetallic compound region 255 may be formed between the external connection terminal 260 and the external pad 250. The intermetallic compound region 255 includes an alloy in which one or more metal elements constituting the outer pad 250 and one or more metal elements constituting the external connection terminal 260 form a compound in a predetermined stoichiometric ratio.

According to some embodiments, the composition of the intermetallic compound included in the intermetallic compound region 255 may vary according to position. 20, the intermetallic compound region 255 is adjacent to the lower metal layer 251 and has a first intermetallic compound region 255L, and is spaced apart from the lower metal layer 251 and has a second intermetallic compound region 255H.

According to some embodiments, the concentration of the intermetallic compound including the metal element constituting the lower metal layer 251 in the first intermetallic compound region 255L may be relatively higher than that of the second intermetallic compound region 255H. According to some embodiments, in the intermetallic compound of the first intermetallic compound region 255L, the concentration of the metal element constituting the external connection terminal 260 may be higher than the concentration of the metal element constituting the lower metal layer 251 . According to some embodiments, in the intermetallic compound of the second intermetallic compound region 255H, the metal element constituting the upper metal layer 253 and the external connection terminal 260 is compared with the concentration of the metal element constituting the lower metal layer 251 The concentration will be higher.

The intermetallic compound region 255 as described above can be formed by, for example, a reflow welding process as shown in FIG. 13K. In other words, as shown in FIG. 13J, after the solder balls 263 are provided on the preparatory external connection terminal layer 261 coated with the flux 280, the reflow soldering process is performed as shown in FIG. 13K, so that the external connection terminal 260 and the external pad can be connected An intermetallic compound region 255 is formed between 250.

According to an exemplary embodiment of the present invention, the reflow welding process is performed in a state where a covering layer excellent in wetting is formed. Therefore, the external connection terminal covering the intermetallic compound on the sidewall of the external pad can be formed to have a thicker thickness. The external impact can be reduced by the external connection terminals covering the sidewall of the external pad. Therefore, cracks can be prevented from occurring near the external pad, and as a result, the bonding reliability between the semiconductor package and the external device can be improved.

As described above, exemplary embodiments are disclosed in the drawings and specification. Although specific terms are used in this specification to describe the embodiments, this is only for the purpose of explaining the technical idea of the present disclosure and not for limiting the meaning or limiting the scope of the present disclosure described in the patent application. Therefore, those of ordinary skill in the art should understand that various modifications and equivalent other embodiments can be implemented according to this specification. Therefore, the true technical protection scope of the present disclosure should depend on the technical ideas of the attached patent application scope.

100, 100a, 100b, 100d, 100e: semiconductor package 110: Semiconductor wafer 111: Wafer Pad 113: Passivation film 118: first surface 120: Rewiring the structure 130: Insulation pattern 131: first insulation pattern 133: second insulation pattern 133H: opening 140: Line pattern 150: External pad 150h: height 151, 151m: height lower metal layer 153: upper metal layer 157: top 158: Sidewall 159: first thickness 160: External connection terminal 160M: Center 161: Preparing Metal Layer 163: Solder Ball 169: Part One 169t: minimum thickness 170: cover layer 171: middle layer 175: diffusion barrier 180: Cosolvent 181: The first mask pattern 181H: opening 183: The second mask pattern 183H: opening 190: height 191: Thickness 192: shortest distance 193: Thickness 194: Horizontal width 195: height 196: width 197: Thickness 200, 200a, 200b: semiconductor package 210: semiconductor wafer 211: Wafer Pad 213: Passivation film 218: First Surface 220: rewiring structure 230: Insulation pattern 231: first insulation pattern 233: second insulation pattern 233H: opening 240: Wiring pattern 250: External pad 250h: height 251, 251m: Lower metal layer 251W: first width 253: upper metal layer 255: Intermetallic compound area 255L: the first intermetallic compound region 255H: second intermetallic compound region 260: External connection terminal 260e: Extension 260M: Center 261: Prepare external connection terminal layer 261e: Extension 263: Solder Ball 269: Part One 269t: minimum thickness 270: diffusion barrier 280: (Co) solvent 281: The first mask pattern 281H: opening 283: second mask pattern 283t: separation distance 283H: opening 290: height 292: shortest distance 293: Thickness 294: Horizontal width 295: height 296: width 1511, 2533: protrusion 1531, 2511, 2531: side wall 2511a, 2511b: tip part

FIG. 1 is a cross-sectional view of a semiconductor package according to an exemplary embodiment of the present invention. FIG. 2 is a cross-sectional view showing a semiconductor package according to an exemplary embodiment of the present invention. 3 is a cross-sectional view showing a part of a semiconductor package according to an exemplary embodiment of the present invention, and is a cross-sectional view showing a region corresponding to the region indicated by “III” of FIG. 1. 4A to 4H are cross-sectional views sequentially showing a method of manufacturing a semiconductor package according to an exemplary embodiment of the present invention. FIG. 5 is a cross-sectional view of a semiconductor package according to an exemplary embodiment of the present invention. Fig. 6 is an enlarged cross-sectional view showing the area indicated by "VI" in Fig. 5; 7A to 7F are cross-sectional views sequentially showing a method of manufacturing a semiconductor package according to an exemplary embodiment of the present invention. FIG. 8 is a cross-sectional view of a semiconductor package according to an exemplary embodiment of the present invention. 9A to 9C are cross-sectional views showing the manufacturing method of the semiconductor package shown in FIG. 8 in order. FIG. 10 is a cross-sectional view showing a part of a semiconductor package according to an exemplary embodiment of the present invention. FIG. 11 is a cross-sectional view of a semiconductor package according to an exemplary embodiment of the present invention. Fig. 12 is an enlarged cross-sectional view showing the area indicated by "XII" in Fig. 11; FIGS. 13A to 13K are cross-sectional views sequentially showing a method of manufacturing the semiconductor package shown in FIG. 11 according to an embodiment of the present invention. Fig. 14 is a partial enlarged view of the part indicated by "XIV" in Fig. 13I. 15A to 15D are cross-sectional views sequentially showing a method of manufacturing the semiconductor package shown in FIG. 11 according to another embodiment of the present invention. Fig. 16 is a partially enlarged view of the part indicated by "XVI" in Fig. 15D. FIG. 17 is a cross-sectional view of a semiconductor package according to an exemplary embodiment of the present invention. 18A to 18C are cross-sectional views showing the manufacturing method of the semiconductor package shown in FIG. 17 in order. FIG. 19 is a cross-sectional view of a semiconductor package according to an exemplary embodiment of the present invention. Fig. 20 is an enlarged cross-sectional view showing the area indicated by "XX" in Fig. 19;

100: Semiconductor package

110: Semiconductor wafer

120: Rewiring the structure

130: insulating layer

131: first insulation pattern

133: second insulation pattern

140: Wiring pattern

150: External pad

150h: height

151: lower metal layer

153: upper metal layer

160: External connection terminal

Claims (20)

A semiconductor package includes: A semiconductor wafer including a wafer pad provided on the first surface; An external pad that is electrically connected to the chip pad of the semiconductor chip; External connection terminal, which covers the external pad; and An intermediate layer, which is provided on the external pad and the external connection terminal and includes a third metal material that is different from the first metal material included in the external pad and included in the external connection The second metal material in the terminal. The semiconductor package according to claim 1, wherein the third metal material of the intermediate layer includes a noble metal including gold, and the intermediate layer is formed by a non-electrolyte method. The semiconductor package according to claim 1, further comprising an insulating layer on the first surface of the semiconductor chip, and the external connection terminal covers the side wall of the external pad and is connected to the upper surface of the insulating layer contact. The semiconductor package according to claim 3, wherein, for the first direction balanced with the first surface of the semiconductor wafer, the uppermost end of the side wall of the external pad is connected to the external connection terminal Between the external surfaces, the thickness of the external connection terminal along the first direction is between 10 μm and 30 μm. The semiconductor package according to claim 1, further comprising an insulating layer on the first surface of the semiconductor wafer, and for the second direction perpendicular to the first surface of the semiconductor wafer, the insulating layer The upper surface of the layer shall prevail, and the height of the outer pad along the second direction is between 10 μm and 50 μm. The semiconductor package according to claim 1, further comprising a wiring pattern that extends between the semiconductor package and the external pad and electrically connects the die pad and the external pad. The semiconductor package according to claim 1, wherein the semiconductor package is a fan-out shape semiconductor package. A semiconductor package includes: A semiconductor wafer including a wafer pad provided on the first surface; An external pad that is electrically connected to the chip pad of the semiconductor chip; An external connection terminal, which covers the external pad and includes solder; Wherein, the external connection terminal includes a second metal material, and the second metal material is different from the first metal material included in the solder and the external pad. The semiconductor package according to claim 8, wherein the second metal material accounts for between 0.00001 wt% and 1 wt% of the entire weight of the external connection terminal. The semiconductor package according to claim 8, wherein the second metal material includes a precious metal. The semiconductor package according to claim 8, wherein the external connection terminal covers the side wall of the external pad, and between the uppermost end of the side wall of the external pad and the external surface of the external connection terminal, the The thickness of the external connection terminal along the first direction is between 10 μm and 30 μm. A semiconductor package includes: A substrate, which includes a conductive pad provided on the first surface; An insulating pattern that exposes at least a part of the conductive pad and is disposed on the first surface; A lower metal layer connected to the conductive pad; An upper metal layer, which is disposed on the lower metal layer; and External connection terminals, which cover the entire upper surface and the entire sidewall surface of the upper metal layer; Wherein, the lateral profile of the lower metal layer is located on the inner side than the sidewall surface of the upper metal layer. The semiconductor package according to claim 12, wherein: The side surface of the lower metal layer includes a concave curved surface, The upper metal layer includes protrusions protruding in a lateral direction relative to the lower metal layer, The external connection terminal includes an extension that extends to a lower portion of the protruding portion of the upper metal layer. The semiconductor package according to claim 13, wherein the external connection terminal contacts the lower surface of the upper metal layer. The semiconductor package according to claim 14, wherein the extension part contacts the side surface of the lower metal layer. The semiconductor package according to claim 12, wherein an intermetallic compound is further included between the external connection terminal and the upper metal layer. The semiconductor package according to claim 12, wherein the external connection terminal contacts the side wall surface of the upper metal layer and the upper surface of the insulating pattern near the side wall surface. The semiconductor package according to claim 12, wherein the substrate includes a semiconductor substrate, and the conductive pad is a wafer pad electrically connected to the semiconductor substrate. The semiconductor package according to claim 12, wherein: The lower metal layer is electrically connected to the conductive pad through a wiring pattern, The thickness of the wiring pattern is 3 μm to 8 μm, The ratio of the thickness of the wiring pattern to the sum of the thicknesses of the upper metal layer and the lower metal layer is 1.25-40. The semiconductor package according to claim 12, wherein a thickness of the upper metal layer in a direction perpendicular to the first surface is 10 μm to 100 μm.

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