CN112466838A - Semiconductor package structure and manufacturing method thereof - Google Patents

Semiconductor package structure and manufacturing method thereof Download PDF

Info

Publication number
CN112466838A
CN112466838A CN202011092825.2A CN202011092825A CN112466838A CN 112466838 A CN112466838 A CN 112466838A CN 202011092825 A CN202011092825 A CN 202011092825A CN 112466838 A CN112466838 A CN 112466838A
Authority
CN
China
Prior art keywords
dielectric layer
layer
conductive
semiconductor package
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202011092825.2A
Other languages
Chinese (zh)
Inventor
吕文隆
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Semiconductor Engineering Inc
Original Assignee
Advanced Semiconductor Engineering Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Engineering Inc filed Critical Advanced Semiconductor Engineering Inc
Priority to CN202011092825.2A priority Critical patent/CN112466838A/en
Publication of CN112466838A publication Critical patent/CN112466838A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)

Abstract

The present disclosure provides a semiconductor package structure and a method of manufacturing the same. One embodiment of the semiconductor package structure comprises: the stacked dielectric layer is formed by stacking at least one first dielectric layer, the first dielectric layer is provided with a first surface, a second surface opposite to the first surface and a first concave part extending from the first surface to the second surface, the first surface is provided with a conductive structure penetrating through the first concave part, and an adhesive layer is arranged between the conductive structure and the first dielectric layer; the conductive connection structure is arranged on the second surface of the first dielectric layer at the lowest layer of the stacked dielectric layers, and an adhesive layer is arranged between the conductive connection structure and the conductive structure of the first dielectric layer at the lowest layer of the stacked dielectric layers; an electronic component connected to the conductive connection structure through the conductive structure in the stacked dielectric layers; and the underfill is filled between the stacked dielectric layers and the electronic component.

Description

Semiconductor package structure and manufacturing method thereof
Technical Field
The disclosure relates to the technical field of semiconductor packaging, in particular to a semiconductor packaging structure and a manufacturing method thereof.
Background
The semiconductor package structure may include electrical connection structures, such as solder balls, that interface the electronic component to the substrate. Generally, the conductive pillars are first arranged to maintain a predetermined distance to form a predetermined space, and then underfill is filled into the predetermined space when the electronic component is coupled to the substrate. During the process of manufacturing the electrical connection structure (e.g., during a reflow process), the solder forming the solder ball may contact the conductive pillar to form an Intermetallic Compound (IMC), and the presence of the IMC may cause cracks to the solder joint, thereby reducing the reliability of the solder joint and affecting the electrical performance.
Disclosure of Invention
In a first aspect, the present disclosure provides a semiconductor package structure, including: the stacked dielectric layer is formed by stacking at least one first dielectric layer, the first dielectric layer is provided with a first surface, a second surface opposite to the first surface and a first concave part extending from the first surface to the second surface, the first surface is provided with a conductive structure penetrating through the first concave part, and an adhesive layer is arranged between the conductive structure and the first dielectric layer; the conductive connection structure is arranged on the second surface of the first dielectric layer at the lowest layer of the stacked dielectric layers, and an adhesive layer is arranged between the conductive connection structure and the conductive structure of the first dielectric layer at the lowest layer of the stacked dielectric layers; an electronic component connected to the conductive connection structure through the conductive structure in the stacked dielectric layers; and the underfill is filled between the stacked dielectric layers and the electronic component.
In some alternative embodiments, the thickness of the first dielectric layer is between 5 μm and 20 μm.
In some alternative embodiments, the bottom of the first recess is circular in shape and the diameter of the bottom of the first recess is between 10 μm and 50 μm.
In some alternative embodiments, the conductive structure includes at least one conductive trace having a line width and line spacing L/S between 2 μm/2 μm and 3 μm/3 μm.
In some alternative embodiments, the thickness of the conductive traces is between 2 μm and 3 μm.
In some alternative embodiments, the conductive connection structure includes: barrier layer, solder layer and solder element.
In some alternative embodiments, the barrier layer is a titanium copper alloy or a titanium nickel copper alloy.
In some alternative embodiments, the solder layer is gold, silver, copper, nickel, an aluminum alloy, or an alloy thereof.
In some alternative embodiments, the solder layer has a thickness between 0.1 μm and 3 μm.
In some alternative embodiments, the solder elements are solder balls having a diameter between 5 μm and 80 μm.
In some alternative embodiments, the solder element is tin or a tin-silver alloy.
In some alternative embodiments, the conductive connection structure includes at least one solder bump having a diameter and pitch of 5 μm/5 μm or less.
In some alternative embodiments, the conductive structure has a third surface adjacent to the second surface, wherein the third surface is completely covered by the first dielectric layer and the adhesion layer.
In some alternative embodiments, the adhesion layer comprises titanium.
In some optional embodiments, the semiconductor package structure further comprises: and the packaging material wraps the electronic component.
In a second aspect, the present disclosure provides a method of manufacturing a semiconductor package structure, the method comprising: providing a vector; forming a conductive connection structure on the carrier; forming a stacked dielectric layer on the conductive connection structure, wherein the stacked dielectric layer is formed by stacking at least one first dielectric layer, the first dielectric layer is provided with a first surface, a second surface opposite to the first surface and a first concave part extending from the first surface to the second surface, the first surface is provided with a conductive structure penetrating through the first concave part, and an adhesive layer is arranged between the conductive structure and the first dielectric layer; placing an electronic component on the stacked dielectric layer, electrically connecting the electronic component with the stacked dielectric layer, and filling underfill between the electronic component and the stacked dielectric layer.
In some alternative embodiments, forming a conductive connection structure on a carrier includes: forming a seed layer on the carrier; forming a second dielectric layer on the seed layer; forming a second concave part on the second dielectric layer, and forming a conductive connection structure on the second concave part; and the method further comprises: and removing the carrier, the seed layer and the second dielectric layer.
In some alternative embodiments, forming stacked dielectric layers at the electrically conductive connection structure comprises: forming a first dielectric layer on the conductive connection structure, and forming a first recess on the first dielectric layer to expose the conductive connection structure;
in some alternative embodiments, the adhesion layer and the conductive structure are sequentially formed on the first dielectric layer.
In some alternative embodiments, the first dielectric layer and the second dielectric layer are different materials.
In some optional embodiments, the method further comprises: portions of the first dielectric layer are removed.
In some alternative embodiments, the conductive connection structure includes a barrier layer, a solder layer, and a solder element.
In some alternative embodiments, the solder elements are solder balls, and the method further comprises: and performing reflow treatment on the solder to form a solder ball.
In some optional embodiments, the method further comprises: and injecting the packaging material to coat the electronic component.
The problem that reliability of a welding spot is reduced due to generation of intermetallic compounds in a semiconductor packaging structure in the prior art is solved. The semiconductor packaging structure and the manufacturing method thereof provided by the disclosure define the concave part with the preset height on the dielectric layer to maintain the preset distance to facilitate the filling of the underfill, and set the conductive structure penetrating through the concave part to realize the electrical connection function of the conductive post, and then set the bonding layer to wrap the conductive structure, thereby avoiding the conductive structure from being exposed to contact with the solder ball to form intermetallic compounds.
Drawings
Other features, objects and advantages of the disclosure will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:
fig. 1 is a schematic structural diagram of one embodiment of a semiconductor package structure according to the present disclosure;
fig. 2 is a schematic structural diagram of yet another embodiment of a semiconductor package structure according to the present disclosure;
fig. 3A to 3Q are schematic structural diagrams in the manufacturing process of the semiconductor package structure of the embodiment of fig. 2.
Description of the symbols:
11-stacked dielectric layer, 111-first recess, 112-first dielectric layer, 12-conductive structure, 13-adhesive layer, 14-conductive connection structure, 15-electronic component, 16-underfill, 17-encapsulant, 31-carrier, 32-seed layer, 33-second dielectric layer, 34-second recess.
Detailed Description
The following description of the embodiments of the present disclosure will be provided in conjunction with the accompanying drawings and examples, and those skilled in the art can easily understand the technical problems and effects of the present disclosure. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and not restrictive of the invention. In addition, for convenience of description, only portions related to the related invention are shown in the drawings.
It should be noted that the structures, proportions, and dimensions shown in the drawings and described in the specification are for the understanding and reading of the present disclosure, and are not intended to limit the conditions under which the present disclosure can be implemented, so they are not technically significant, and any modifications of the structures, changes in the proportions and adjustments of the dimensions should be made without affecting the efficacy and attainment of the same. In addition, the terms "above", "first", "second" and "a" as used herein are for the sake of clarity only, and are not intended to limit the scope of the present disclosure, and changes or modifications of the relative relationship may be made without substantial changes in the technical content.
Referring to fig. 1, fig. 1 shows a schematic structural diagram of one embodiment of a semiconductor package structure according to the present disclosure. The semiconductor package structure 100 may include a stacked dielectric layer 11, a conductive structure 12, an adhesive layer 13, a conductive connection structure 14, an electronic component 15, and an underfill 16. The stacked dielectric layer 11 is formed by stacking at least one first dielectric layer 112, the first dielectric layer 112 has a first surface, a second surface opposite to the first surface, and a first concave portion 111 extending from the first surface to the second surface, the first surface is provided with a conductive structure 12 penetrating through the first concave portion 111, and an adhesive layer 13 is arranged between the conductive structure 12 and the first dielectric layer 112; a conductive connection structure 14 disposed on the second surface of the lowest first dielectric layer 112 of the stacked dielectric layers 11, wherein an adhesive layer 13 is disposed between the conductive connection structure 14 and the conductive structure 12 of the lowest first dielectric layer 112 of the stacked dielectric layers 11; an electronic component 15 connected to the conductive connection structure 14 through the conductive structure 12 in the stacked dielectric layer 11; and an underfill 16 filled between the stacked dielectric layer 11 and the electronic component 15.
The at least one first dielectric layer 112 included in the stacked dielectric layer 11 may employ various organic materials, such as Epoxy resin (Epoxy), PI resin, and the like.
The electronic components 15 may be active components, such as chips, etc., or passive components, such as capacitors, inductors, resistors, etc.
The underfill Paste 16 may be, for example, Capillary Underfill (CUF), Molded Underfill (MUF), Non-conductive Paste (NCP), or the like. The underfill 16 may fill the voids for reinforcement purposes.
The adhesion layer 13 can improve the bonding force between the conductive structure 12 and the first dielectric layer 112, and can also prevent inter-metal diffusion.
In some alternative embodiments, the thickness of the first dielectric layer 112 is between 5 μm and 20 μm.
In some alternative embodiments, the bottom shape of the first recess 111 is circular, and the bottom diameter of the first recess 111 is between 10 μm and 50 μm.
In some alternative embodiments, the conductive structure 12 includes at least one conductive trace having a Line width and a Line spacing Line/Space between 2 μm/2 μm and 3 μm/3 μm.
In some alternative embodiments, the thickness of the conductive traces is between 2 μm and 3 μm.
In some alternative embodiments, the conductive connection structure 14 includes: barrier layer, solder layer and solder element.
In some alternative embodiments, the barrier layer is a titanium copper alloy or a titanium nickel copper alloy.
In some alternative embodiments, the solder layer is gold, silver, copper, nickel, an aluminum alloy, or an alloy thereof.
In some alternative embodiments, the solder layer has a thickness between 0.1 μm and 3 μm.
In some alternative embodiments, the solder elements are solder balls having a diameter between 5 μm and 80 μm.
In some alternative embodiments, the solder element is tin or a tin-silver alloy.
In some alternative embodiments, the conductive connection structure 14 includes at least one solder bump having a diameter and pitch of less than or equal to 5 μm/5 μm.
In some alternative embodiments, the adhesion layer 13 comprises titanium.
In some alternative embodiments, the conductive structure 12 has a third surface adjacent to the second surface, wherein the third surface is completely covered by the first dielectric layer 112 and the adhesion layer 13. This avoids exposure of the conductive structure 12.
In some optional embodiments, the semiconductor package structure further comprises: and an encapsulating material 17, wherein the electronic component 15 is encapsulated by the encapsulating material 17.
Here, the sealing material 17 may be, for example, Epoxy resin (Epoxy), PI resin, bt (bismeimide triazine), or the like.
The semiconductor package structure 100 defines the first concave portion 111 on the first dielectric layer 112, sets the conductive structure 12 penetrating through the first concave portion 111, and sets the adhesive layer 13 to wrap the conductive structure 12, so as to prevent the conductive structure 12 from being exposed and further contacting with the solder ball to form an intermetallic compound.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a semiconductor package structure according to another embodiment of the disclosure. The semiconductor package structure 200 is a schematic structural view of the stacked dielectric layers 11 in the semiconductor package structure 100 including a first dielectric layer 112.
Fig. 3A to 3Q are schematic structural diagrams in the manufacturing process of the semiconductor package structure of the embodiment of fig. 2. The figures have been simplified for a better understanding of various aspects of the disclosure.
Referring to fig. 3A, a carrier 31 is provided. Various processes may be employed to form seed layer 32 on carrier 31. Seed layer 32 may be copper or other suitable material.
Referring to fig. 3B, a second dielectric layer 33 is formed on the seed layer 32. The second dielectric layer 33 may employ an organic material, such as Epoxy (Epoxy), PI resin, or the like.
Referring to fig. 3C, a second recess 34 is formed in the second dielectric layer 33. The second recess 34 may be formed by other suitable processes such as laser drilling or photolithographic etching.
Referring to fig. 3D, the conductive connection structure 14 is formed in the second recess 34. Solder, solder layer, and barrier layer may be sequentially plated in the second recess 34 to form the conductive connection structure 14.
Referring to fig. 3E, a first dielectric layer 112 is formed on the second dielectric layer 33. The first dielectric layer 112 and the second dielectric layer 33 may be made of different materials.
Referring to fig. 3F, a first recess 111 is formed in the first dielectric layer 112. The first recess 111 may be formed by other suitable processes such as laser drilling or photolithographic etching.
Referring to fig. 3G, an adhesion layer 13 is formed on the first dielectric layer 112. An adhesive layer 13 may be plated on the first dielectric layer 112, the adhesive layer 13 penetrating the first recess 111.
Referring to fig. 3H, a metal layer is formed on the adhesion layer 13. The adhesion layer 13 may be plated with a metal layer, which may be copper or another suitable material.
Referring to fig. 3I, a conductive structure 12 is patterned on the metal layer. The conductive structure 12 is defined by a process such as photolithography and etching.
Referring to fig. 3J, the electronic device 15 is electrically connected to the first dielectric layer 112, and an underfill 16 is filled between the electronic device 15 and the first dielectric layer 112. The bump of the electronic component 15 may be abutted against the conductive structure 12, the electronic component 15 is electrically connected to the first dielectric layer 112, and the underfill 16 is filled between the electronic component 15 and the first dielectric layer 112 to fill the gap between the electronic component 15 and the first dielectric layer 112.
Referring to fig. 3K, an encapsulant 17 is injected to encapsulate the electronic component 15.
Referring to fig. 3L, the carrier 31 is removed.
Referring to fig. 3M, the seed layer 32 is removed. Etching may be used to remove seed layer 32.
Referring to fig. 3N, the second dielectric layer 33 is removed. The second dielectric layer 33 may be removed using lift-off.
Referring to fig. 3O, a portion of the first dielectric layer 112 is removed. A lift-off may be used to remove portions of the first dielectric layer 112.
Referring to fig. 3P, solder balls are formed by the solder reflow process. After the reflow process, the solder (solder paste) plated in fig. 3D may be heated and melted to be in a liquid state, and then cooled to form spherical solder balls (bumps).
In some alternative embodiments, referring to fig. 3Q, fig. 3Q is a bottom view of the schematic structure shown in fig. 3P, which shows a solder ball array formed after the reflow process. Here, the regular or irregular arrangement may be set according to actual design needs.
While the present disclosure has been described and illustrated with reference to particular embodiments thereof, such description and illustration are not intended to limit the present disclosure. It will be clearly understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not be drawn to scale. There may be a difference between the art reproduction in the present disclosure and the actual device due to variables in the manufacturing process, and the like. There may be other embodiments of the disclosure that are not specifically illustrated. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. Although the methods disclosed herein have been described with reference to particular operations performed in a particular order, it should be understood that these operations may be combined, sub-divided, or reordered to form equivalent methods without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations is not a limitation of the present disclosure.

Claims (10)

1. A semiconductor package structure, comprising:
the stacked dielectric layers are formed by stacking at least one first dielectric layer, the first dielectric layer is provided with a first surface, a second surface opposite to the first surface and a first concave part extending from the first surface to the second surface, the first surface is provided with a conductive structure penetrating through the first concave part, and an adhesive layer is arranged between the conductive structure and the first dielectric layer;
the conductive connection structure is arranged on the second surface of the first dielectric layer at the lowest layer of the stacked dielectric layers, and an adhesive layer is arranged between the conductive connection structure and the conductive structure of the first dielectric layer at the lowest layer of the stacked dielectric layers;
an electronic component connected with the conductive connection structure through the conductive structure in the stacked dielectric layers;
and the underfill is filled between the stacked dielectric layers and the electronic component.
2. The semiconductor package structure of claim 1, wherein the thickness of the first dielectric layer is between 5 μ ι η and 20 μ ι η, the bottom shape of the first recess is circular, and the bottom diameter of the first recess is between 10 μ ι η and 50 μ ι η.
3. The semiconductor package structure of claim 1, wherein the conductive structure comprises at least one conductive trace having a line width and a line spacing L/S between 2 μ ι η/2 μ ι η to 3 μ ι η/3 μ ι η.
4. The semiconductor package structure of claim 1, wherein the electrically conductive connection structure comprises: barrier layer, solder layer and solder element.
5. The semiconductor package structure of claim 1, wherein the conductive structure has a third surface adjacent to the second surface, wherein the third surface is completely covered by the first dielectric layer and the adhesion layer.
6. The semiconductor package structure of claim 1, wherein the adhesion layer comprises titanium.
7. The semiconductor package structure of any one of claims 1-6, wherein the semiconductor package structure further comprises:
and the packaging material wraps the electronic component.
8. A method of fabricating a semiconductor package structure, comprising:
providing a vector;
forming a conductive connection structure on the carrier;
forming a stacked dielectric layer on the conductive connection structure, wherein the stacked dielectric layer is formed by stacking at least one first dielectric layer, the first dielectric layer has a first surface, a second surface opposite to the first surface, and a first recess extending from the first surface to the second surface, the first surface is provided with a conductive structure penetrating through the first recess, and an adhesive layer is arranged between the conductive structure and the first dielectric layer;
placing an electronic component on the stacked dielectric layer, electrically connecting the electronic component with the stacked dielectric layer, and filling underfill between the electronic component and the stacked dielectric layer.
9. The method of claim 8, wherein said forming conductive connection structures on said carrier comprises:
forming a seed layer on the carrier;
forming a second dielectric layer on the seed layer;
forming a second concave part on the second dielectric layer, and forming a conductive connection structure on the second concave part; and the method further comprises:
and removing the carrier, the seed layer and the second dielectric layer.
10. The method of claim 8 or 9, wherein said forming a stacked dielectric layer at said electrically conductive connection structure comprises:
forming a first dielectric layer on the conductive connection structure, forming a first recess on the first dielectric layer to expose the conductive connection structure;
and sequentially forming the bonding layer and the conductive structure on the first dielectric layer.
CN202011092825.2A 2020-10-13 2020-10-13 Semiconductor package structure and manufacturing method thereof Pending CN112466838A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202011092825.2A CN112466838A (en) 2020-10-13 2020-10-13 Semiconductor package structure and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202011092825.2A CN112466838A (en) 2020-10-13 2020-10-13 Semiconductor package structure and manufacturing method thereof

Publications (1)

Publication Number Publication Date
CN112466838A true CN112466838A (en) 2021-03-09

Family

ID=74833807

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202011092825.2A Pending CN112466838A (en) 2020-10-13 2020-10-13 Semiconductor package structure and manufacturing method thereof

Country Status (1)

Country Link
CN (1) CN112466838A (en)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000008756U (en) * 1998-10-27 2000-05-25 김영환 Hybrid package
KR20020058215A (en) * 2000-12-29 2002-07-12 마이클 디. 오브라이언 Semiconductor package and its Encapsulation method
US20100155116A1 (en) * 2008-12-24 2010-06-24 Ibiden Co., Ltd. Printed wiring board and method for manufacturing the same
CN102088004A (en) * 2009-11-05 2011-06-08 台湾积体电路制造股份有限公司 Integrated circuit element and flip chip package
US9406531B1 (en) * 2014-03-28 2016-08-02 STATS ChipPAC Pte. Ltd. Integrated circuit packaging system with photoimagable dielectric-defined trace and method of manufacture thereof
CN109390312A (en) * 2017-08-09 2019-02-26 日月光半导体制造股份有限公司 Semiconductor encapsulation device and its manufacturing method
KR20200079159A (en) * 2018-12-24 2020-07-02 주식회사 네패스 Semiconductor package

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000008756U (en) * 1998-10-27 2000-05-25 김영환 Hybrid package
KR20020058215A (en) * 2000-12-29 2002-07-12 마이클 디. 오브라이언 Semiconductor package and its Encapsulation method
US20100155116A1 (en) * 2008-12-24 2010-06-24 Ibiden Co., Ltd. Printed wiring board and method for manufacturing the same
CN102088004A (en) * 2009-11-05 2011-06-08 台湾积体电路制造股份有限公司 Integrated circuit element and flip chip package
US9406531B1 (en) * 2014-03-28 2016-08-02 STATS ChipPAC Pte. Ltd. Integrated circuit packaging system with photoimagable dielectric-defined trace and method of manufacture thereof
CN109390312A (en) * 2017-08-09 2019-02-26 日月光半导体制造股份有限公司 Semiconductor encapsulation device and its manufacturing method
KR20200079159A (en) * 2018-12-24 2020-07-02 주식회사 네패스 Semiconductor package

Similar Documents

Publication Publication Date Title
US11682651B2 (en) Bump-on-trace interconnect
KR102425720B1 (en) Semiconductor package and fabricating method thereof
KR101905334B1 (en) Method for semiconductor packaging and electronic device
TWI483357B (en) Package structure
TWI453840B (en) Protected solder ball joints in wafer level chip-scale packaging
KR101579673B1 (en) Method for fabricating semiconductor package and semiconductor package using the same
US9263412B2 (en) Packaging methods and packaged semiconductor devices
US8431478B2 (en) Solder cap bump in semiconductor package and method of manufacturing the same
US10224301B2 (en) Semiconductor package device and method of manufacturing the same
TWI419300B (en) Electronic component built-in substrate and method of manufacturing electronic component built-in substrate
CN103515362A (en) Package on package device and method of packaging semiconductor die
CN103311138A (en) Packaging methods and packaged semiconductor devices
US11145624B2 (en) Semiconductor device package and method for manufacturing the same
KR100842921B1 (en) Method for fabricating of semiconductor package
KR101982905B1 (en) Semiconductor package and fabricating method thereof
US20190279924A1 (en) Semiconductor package structure and method of manufacturing the same
US11676915B2 (en) Semiconductor package
US9024439B2 (en) Substrates having bumps with holes, semiconductor chips having bumps with holes, semiconductor packages formed using the same, and methods of fabricating the same
US7642639B2 (en) COB type IC package to enhanced bondibility of bumps embedded in substrate and method for fabricating the same
JP3857574B2 (en) Semiconductor device and manufacturing method thereof
CN112466838A (en) Semiconductor package structure and manufacturing method thereof
US8430969B2 (en) Method for exposing and cleaning insulating coats from metal contact surfaces
CN112435996A (en) Semiconductor package device and method of manufacturing the same
US20240145361A1 (en) Semiconductor package and method for fabricating the same
US11404386B2 (en) Semiconductor device package and method of manufacturing the same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination