TW202018497A - Addressing method for integrated circuit chip and system thereof - Google Patents

Abstract

The present invention provides an addressing system for integrated circuit chip and the system includes a control unit and a plurality of circuit boards. The control unit is configured to transmit a first control signal and a second control signal. The circuit boards are electrically connected to the control unit via a plurality of signal transmission serial interfaces and each of the circuit boards includes a plurality of integrated circuit chips. The integrated circuit chips will receive the first control signal to synchronize the integrated circuit chips and receive the second control signal to address the integrated circuit chips.

Description

Addressing method and system of integrated circuit chip

The present invention relates to an addressing method and system for an integrated circuit chip, and in particular to an addressing method and system for an integrated circuit chip without using resistors to achieve the purpose of chip addressing.

The application of virtual currency mining machine, blockchain server, cloud computing server, artificial intelligence computer or industrial computer requires strong computing power, so usually multiple computing boards are installed in the above host, and each computing There are multiple identical arithmetic units on the board to increase the data calculation and processing capability of the host.

In the operation process of several applications, it is necessary to know which operation unit completes the calculation, so it is necessary to address each operation unit. In the addressing methods of the existing arithmetic units, most of them use a resistor to give each arithmetic unit a digital address, so that the host computer can know which calculation unit is currently performing the calculation.

However, the addressing method using resistors needs to occupy the position of the operation board, which will increase the area of the operation board, thereby increasing the manufacturing cost of the operation board. Therefore, how to design a new addressing method to overcome the above-mentioned shortcomings has become one of the important issues that the cause wants to solve.

The technical problem to be solved by the present invention is to provide an addressing system for an integrated circuit chip that does not require the use of a resistor addressing integrated circuit chip for the deficiencies of the prior art And methods.

In order to solve the above technical problems, the technical solution adopted by the present invention is to provide an addressing system for an integrated circuit chip, which includes a control unit and a plurality of circuit boards. The control unit is used to transmit a first control signal and a second control signal; a plurality of circuit boards are connected to the control unit through a plurality of signal transmission serial interfaces, and each circuit board includes a plurality of integrated circuit chips. The integrated circuit chip receives the first control signal to synchronize the signal transmitted by the integrated circuit chip with the first control signal, and the integrated circuit chip receives the second control signal to address each integrated circuit chip.

In order to solve the above technical problems, another technical solution adopted by the present invention is to provide an addressing method for an integrated circuit chip. A plurality of integrated circuit chips are in an initial state, and the output of each of the integrated circuit chips is connected. The signal transmitted by the pin will change with the signal received by the input pin. The addressing method includes: outputting a first control signal to the integrated circuit chips through a control unit to synchronize the integrated circuit chips; The control unit sequentially outputs a second control signal to address each integrated circuit chip; the step of addressing each integrated circuit chip is repeated until the addressing of all integrated circuit chips is completed.

The beneficial effect of the present invention is that the addressing system and method of the integrated circuit chip provided by the present invention omits the use of resistors, thereby reducing the circuit area of the circuit board.

In order to further understand the features and technical contents of the present invention, please refer to the following detailed description and drawings of the present invention. However, the drawings provided are for reference and explanation only, and are not intended to limit the present invention.

10‧‧‧Integrated circuit chip addressing system

102‧‧‧Control unit

104‧‧‧ circuit board

106‧‧‧Integrated circuit chip

106A‧‧‧First integrated circuit chip

106B‧‧‧Second integrated circuit chip

106N‧‧‧Nth integrated circuit chip

1061‧‧‧Input pin

1062‧‧‧Output pin

108‧‧‧Signal transmission serial interface

S301~S303‧‧‧Step

FIG. 1 is a block diagram of an addressing system for an integrated circuit chip according to an embodiment of the invention.

2 is a block diagram of some components of the addressing system of the integrated circuit chip of the present invention.

3 is a flowchart of an addressing method of an integrated circuit chip according to an embodiment of the invention.

The following is a specific embodiment to illustrate the implementation of the addressing method and system of the integrated circuit chip disclosed by the present invention. Those skilled in the art can understand the advantages and effects of the present invention from the content disclosed in this specification. The present invention can be implemented or applied through other different specific embodiments. Various details in this specification can also be based on different viewpoints and applications, and various modifications and changes can be made without departing from the concept of the present invention. In addition, the drawings of the present invention are merely schematic illustrations, and are not drawn according to actual sizes, and are declared in advance. The following embodiments will further describe the related technical content of the present invention, but the disclosed content is not intended to limit the protection scope of the present invention.

It should be understood that although terms such as “first”, “second”, and “third” may be used herein to describe various elements or signals, these elements or signals should not be limited by these terms. These terms are mainly used to distinguish one component from another component, or one signal from another signal. In addition, the term "or" as used herein may include any combination of any one or more of the associated listed items, depending on the actual situation.

In the addressing method and system of the integrated circuit chip of the present invention, the integrated circuit chip is preferably disposed on a circuit board, and this circuit board may also be called an arithmetic board or a hash board. In a computer host that requires a lot of computing power (such as a virtual currency mining machine, etc.), multiple computing boards need to be installed on the signal transmission serial interface of the computer host (such as an asynchronous serial interface (Universal Asynchronous Receiver Transmitter, UART ) Or Serial Peripheral Interface (SPI), etc.). Moreover, in the process of calculation, you need to know which integrated circuit chip completes the calculation. The computer host will verify the calculation result and then return the verification result to the mining pool. If the calculation result of the integrated circuit chip is correct, tell which product The integrated circuit chip operates correctly, and the integrated circuit chip performs the next operation. If the operation result of the integrated circuit chip is incorrect, it is notified which integrated circuit chip has the incorrect operation. Similarly, the integrated circuit chip performs the next operation. Therefore, all integrated circuit crystals The chip is addressed so that it can be known which integrated circuit chip has completed the calculation.

[Example of addressing system of integrated circuit]

Referring to FIG. 1, FIG. 1 is a block diagram of an addressing system for an integrated circuit chip according to an embodiment of the invention. The integrated circuit chip addressing system 10 of the present invention includes a control unit 102, a plurality of circuit boards 104, and a plurality of integrated circuit chips 106. The control unit 102 may also be referred to as a control board (Control board), and the circuit board 104 may be an arithmetic board or a power board, but it is not limited herein. The control unit 102 is connected to a plurality of signal transmission serial interfaces 108, and the circuit board 104 is installed on the signal transmission serial interfaces 108. Further, the circuit board 104 is connected to the control unit 102 through a signal transmission serial interface 108, each circuit board 104 includes a plurality of integrated circuit chips 106, and a plurality of integrated circuits on each circuit board 104 The wafer 106 is connected in series. The signal transmission serial interface 108 is preferably an asynchronous serial interface or serial peripheral interface. However, in different embodiments, the signal transmission serial interface 108 may also be an RS-232 transmission interface, which is not limited herein.

Referring to FIG. 2, FIG. 2 is a block diagram of some components of the addressing system of the integrated circuit chip of the present invention. When the addressing system 10 of the integrated circuit chip of the present invention is turned on, each integrated circuit chip 106 is in an initial state. In the initial state, the output pin (Txo) 1062 of each integrated circuit chip 106 transmits The signal will change with the input pin (Txi) 1061 signal. For example, the signal transmitted to the input pin 1061 of the integrated circuit chip 106 and the signal output from the output pin 1062 of the integrated circuit chip 106 may have the same or relative relationship, but the signal period tends to be consistent. The so-called approaching consistency is not exactly the same time period, because the time delay caused by the circuit characteristics causes an error within 1% of the time period.

At this time, the control unit 102 sends a first control signal to the integrated circuit chip 106 on the circuit board 104. The first control signal is a Not Operation Command (NOP CMD) signal. At this time, the integrated circuit chip 106 on the same circuit board 104 will perform a Baud rate connection with the signal transmission serial interface 108 Synchronized action. The so-called signal synchronization action of the integrated circuit chip 106 is to synchronize the internal signals of all integrated circuit chips 106 with the first control signal and maintain the signals of the output pins 1062 of all integrated circuit chips 106 in a locked state. The so-called locked state means that the output signal does not change with the input signal. For example, when the input signal is at a high level (1), the output signal can be arbitrary (1 or 0), and when the input signal is at a low level (0), the output signal can also be arbitrary (1 or 0).

Among the plurality of integrated circuit chips 106 on the same circuit board 104, the first integrated circuit chip 106A, the second integrated circuit chip 106B to the Nth product Body circuit wafer 106N. After the synchronization of all integrated circuit chips 106 is completed, the control unit 102 sequentially transmits a second control signal to the first integrated circuit chip 106A, the second integrated circuit chip 106B to the N-th integrated circuit chip 106N. The second control signal is a set address signal (Set ID CMD). Because the first integrated circuit chip 106A is first connected in series with the control unit 102, if the first integrated circuit chip 106A has not set an address, the first integrated circuit chip 106A will preferentially set the address of its integrated circuit chip 106 . When the first integrated circuit chip 106A receives the second control signal, the address is set, and the remaining integrated circuit chip 106 does not receive the second control signal.

Then, after the first integrated circuit chip 106A completes the address setting operation, the control unit 102 transmits another second control signal to the integrated circuit chip 106. At this time, because the first integrated circuit chip 106A has finished setting the address, the first integrated circuit chip 106A will not receive the second control signal transmitted this time, and the second control signal will pass through the first integrated circuit chip 106A, It is transferred to the second integrated circuit wafer 106B. At this time, if the second integrated circuit chip 106B has not set the address, the second integrated circuit chip 106B will receive the second control signal and perform the address setting operation, while the remaining integrated circuit chip 106 will not receive Here comes the second control signal. And so on, until the Nth integrated circuit chip 106N completes the address setting operation. In addition, it should be noted here that although the first integrated circuit chip 106A is the first integrated circuit chip 106 to complete address setting, the first integrated circuit chip 106A The address of is not necessarily the first numbered integrated circuit chip 106, the control unit 102 can assign any address number to each integrated circuit chip 106, and the address number of each integrated circuit chip 106 is different .

With the integrated circuit chip addressing system 10 of the present invention, each integrated circuit chip 106 is set with an address number. When each integrated circuit chip 106 completes the calculation, the addressing system 10 only knows which integrated circuit The circuit chip 106 completes the calculation without installing additional resistors in the addressing system 10, which can also achieve the purpose of addressing.

[Example of addressing method of integrated circuit]

Referring to FIG. 3, FIG. 3 is a flowchart of an addressing method of an integrated circuit chip according to an embodiment of the present invention. In the addressing method of this embodiment, the addressing system of the integrated circuit chip described above is used to complete the addressing work. In the present invention, when the integrated circuit chip is in the initial state, the signal transmitted by the output pin (Txo) of the integrated circuit chip will change with the signal received by the input pin (Txi), according to the serial connection with the control unit In order, the multiple integrated circuit chips are named the first integrated circuit chip, the second integrated circuit chip up to the Nth integrated circuit chip, the first integrated circuit chip is the first product connected in series with the control unit Integrated circuit chip, the Nth integrated circuit chip is the last integrated circuit chip connected in series with the control unit. At this time, for example, the signal transmitted to the input pin of the integrated circuit chip and the signal output from the integrated circuit chip are both high-voltage signals, and their signal periods tend to be consistent.

The addressing method of the integrated circuit chip of the present invention includes the following steps. In step S301, a first control signal is output to a plurality of integrated circuit chips via the control unit, so that the multiple integrated circuit chips perform a synchronous operation. The first control signal is a Not Operation Command (NOP CMD) signal. The so-called synchronous operation of integrated circuit chips means that all integrated circuit chips synchronize the Baud rate with the signal transmission serial interface, and is The signals of the output pins of all integrated circuit chips are maintained in a locked state. After the synchronization action of the integrated circuit chip is completed, the signal level of all integrated circuit chips will remain locked. At this time, only the first product The body circuit chip can receive signals.

Then, in step S302, the control unit sequentially outputs a second control signal to address each integrated circuit chip. The second control signal is a Set ID CMD signal. When the control unit outputs the second control signal, the second control signal of the set address is sequentially transmitted to each integrated circuit through the signal transmission serial interface Wafer. The first integrated circuit chip will receive the set address signal first. If the first integrated circuit chip has not set the address, the first integrated circuit chip turns on the first integrated circuit chip after receiving the second control signal Output pin (Txo). When the control unit transmits the second control signal again, because the first integrated circuit chip has completed addressing, the second control signal will pass through the first integrated circuit chip, that is to say the first integrated circuit chip will not receive the second Control signal. The second control signal reaches the second integrated circuit chip. If the second integrated circuit chip has not been addressed, the second integrated circuit chip will receive the second control signal. If the second integrated circuit chip has been addressed, the second control signal Similarly, the second integrated circuit chip will reach the integrated circuit chip at the next position, and all addressing steps of the integrated circuit chip will be completed in sequence.

In addition, it should be noted here that the first integrated circuit chip is not necessarily the first integrated circuit chip with the address number. The control unit can select any address number for the integrated circuit chip. The number of bulk circuit chips is set to be different.

Finally, in step S303, step S302 is repeated until the addressing of each integrated circuit chip is completed. After the addressing of each integrated circuit chip is completed, calculation work can be given to each integrated circuit chip, and each integrated circuit chip can start calculation.

Through the above addressing method and the method of command setting, each integrated circuit chip is given an address number. After the integrated circuit chip completes the calculation, the system will know which integrated circuit chip has completed the calculation. Whether the calculation of the circuit chip is correct. Improve the way to use resistor positioning and reduce the use of resistors.

[Beneficial effect of embodiment]

The beneficial effect of the present invention is that the addressing system and method of the integrated circuit chip provided by the present invention omits the use of resistors, thereby reducing the circuit area of the circuit board.

The content disclosed above is only a preferred and feasible embodiment of the present invention, and therefore does not limit the scope of the patent application of the present invention, so any equivalent technical changes made by using the description and drawings of the present invention are included in the application of the present invention. Within the scope of the patent.

10‧‧‧Integrated circuit chip addressing system

102‧‧‧Control unit

104‧‧‧ circuit board

106‧‧‧Integrated circuit chip

108‧‧‧Signal transmission serial interface

Claims (11)

An addressing system for an integrated circuit chip, including: a control unit for transmitting a first control signal and a plurality of second control signals; and a plurality of circuit boards connected to the control unit through a plurality of signal transmission serial interfaces And each of the circuit boards includes a plurality of integrated circuit chips; wherein the integrated circuit chips receive the first control signal to synchronize the signals transmitted by the integrated circuit chips with the first control signal, each The integrated circuit chips receive each of the second control signals to address each of the integrated circuit chips. The addressing system of an integrated circuit chip according to claim 1, wherein the control unit names the integrated circuit chips in the order of serial connection with the integrated circuit chips. The addressing system for an integrated circuit chip according to claim 1, wherein the second control signals are set address signals, and the control unit transmits the second control signals one at a time to sequentially address the integrated circuits Wafer. The addressing system of an integrated circuit chip according to claim 1, wherein the first control signal is a non-operation command signal, which is used to synchronize the internal signals of the integrated circuit chips with the first control signal and to The signals of the output pins of the integrated circuit chips are in a locked state. The addressing system of an integrated circuit chip according to claim 4, wherein the internal signals of the integrated circuit chips are synchronized with the first control signal, that is, the serial interface of the integrated circuit chips and the signal transmission The Baud rate is synchronized. The addressing system of an integrated circuit chip as described in claim 4, wherein the signals of the output pins of the integrated circuit chips are in a locked state, which means that the output signal does not change with the input signal. The addressing system for an integrated circuit chip according to claim 1, wherein the control unit can assign any address number to the integrated circuit chips. An addressing method for an integrated circuit chip, in which when a plurality of integrated circuit chips are in an initial state, the signal transmitted by the output pin of each of the integrated circuit chips changes with the signal received by the input pin, The addressing method includes: outputting a first control signal to the integrated circuit chips through a control unit, synchronizing the signal transmitted by each of the integrated circuit chips with the first control signal, and making each of the some control signals The output pin signal of the integrated circuit chip is in a locked state; the control unit sequentially outputs a second control signal to address each of the integrated circuit chips and release each of the integrated circuit chips The locked state; and repeating the step of addressing each of the integrated circuit chips until the addressing of the integrated circuit chips is completed. The addressing method of the integrated circuit chip according to claim 8, wherein after the step of synchronizing the integrated circuits, the control unit further includes naming the integrated circuit chips in the order of connecting the integrated circuit chips in series. The addressing method of the integrated circuit chip according to claim 8, wherein in the step of synchronizing the integrated circuit chips, the baud rate synchronization of the integrated circuit chips and a signal transmission serial interface is performed. The addressing method of the integrated circuit chip according to claim 8, wherein in the step of sequentially outputting the second control signal to address each of the integrated circuit chips, the control unit may be the integrated circuits The circuit chip designates any addressing number.

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