TW202017187A - High electron mobility transistor and methods for forming the same - Google Patents

Abstract

A high electron mobility transistor includes a substrate; a plurality of pairs of alternating layers, disposed over the substrate and each pair of the plurality of pairs of alternating layers including a carbon doped gallium nitride layer and an undoped gallium nitride layer; at least one stress-relief layer disposed between the plurality of pairs of alternating layers; and a gallium nitride layer disposed over the plurality of pairs of alternating layers.

Description

High electron mobility transistor device and manufacturing method thereof

The present disclosure relates to a semiconductor manufacturing technology, in particular to a high electron mobility transistor device and a manufacturing method thereof.

High electron mobility transistor (HEMT), also known as heterostructure field effect transistor (HFET) or modulation-doped field effect transistor (MODFET), is a kind of A field effect transistor (FET) is composed of semiconductor materials with different energy gaps. A two-dimensional electron gas (2 DEG) layer is generated at the formed interface adjacent to different semiconductor materials. Due to the high electron mobility of the two-dimensional electron gas, the high electron mobility transistor can have the advantages of high breakdown voltage, high electron mobility, low on-resistance and low input capacitance, and is therefore suitable for high power components.

Doping carbon in the gallium nitride layer of the high electron mobility transistor can increase the resistivity of the gallium nitride material, making it reach a high withstand voltage application. However, in the process of doping carbon, for example, the growth of gallium nitride at low temperatures and a low ratio of Group V to Group III, may introduce defects that affect the performance of high electron mobility transistors. Therefore, existing high electron mobility transistors cannot The noodles are satisfactory.

According to some embodiments of the present disclosure, a high electron mobility transistor device is provided. The device includes a substrate; a plurality of pairs of alternating layers are disposed above the substrate and each pair of alternating layers includes a carbon-doped gallium nitride layer and an undoped gallium nitride layer; at least one stress relaxation layer is disposed between these alternating layers; And a gallium nitride layer is provided above these alternating layers.

In some embodiments, the stress relaxation layer is an aluminum-containing layer.

In some embodiments, the aluminum-containing layer includes aluminum nitride, aluminum gallium nitride, or a combination of the foregoing.

In some embodiments, a stress relaxation layer is provided between every two pairs of these alternating layers.

In some embodiments, the thickness in the stress relaxation layer is in the range of 0.1 nm to 10 nm.

In some embodiments, the thickness of the carbon-doped gallium nitride layer is in the range of 1 nm to 600 nm, and the thickness of the undoped gallium nitride layer is in the range of 1 nm to 200 nm.

In some embodiments, the ratio of the thickness of the carbon-doped gallium nitride layer to the thickness of the undoped gallium nitride layer is in the range of 3.5 to 5.

In some embodiments, the high electron mobility transistor device further includes a nucleation layer disposed between the substrate and these alternating layers.

In some embodiments, the nucleation layer includes aluminum nitride, aluminum gallium nitride, or a combination of the foregoing.

In some embodiments, the high electron mobility transistor device A buffer layer is included between the substrate and these alternating layers.

In some embodiments, the buffer layer includes gallium nitride, aluminum nitride, aluminum gallium nitride, or a combination of the foregoing.

In some embodiments, the buffer layer includes a graded buffer layer, a superlattice buffer layer, or a combination of the foregoing.

In some embodiments, the high electron mobility transistor device further includes a barrier layer disposed above the gallium nitride layer; and the source, drain, and gate are disposed above the barrier layer.

According to some embodiments of the present disclosure, a method for manufacturing a high electron mobility transistor device is provided. The method includes: forming a substrate; forming a plurality of pairs of alternating layers above the substrate, wherein each pair of alternating layers includes a carbon-doped gallium nitride layer and an undoped gallium nitride layer; forming at least one stress between these alternating layers A relaxed layer; and forming a gallium nitride layer above these alternating layers.

In some embodiments, these alternating layers include aluminum nitride, aluminum gallium nitride, or a combination of the foregoing, and the stress relaxation layer includes aluminum nitride (AlN), aluminum gallium nitride (AlGaN), or a combination of the foregoing.

In some embodiments, a method of manufacturing a high electron mobility transistor device further includes forming a stress relaxation layer between every two pairs of these alternating layers.

In some embodiments, the thickness of the stress relaxation layer is in the range of 0.1 nm to 10 nm.

In some embodiments, the thickness of the carbon-doped gallium nitride layer is in the range of 1 nm to 600 nm, the thickness of the undoped gallium nitride layer is in the range of 1 nm to 200 nm, and the thickness of the carbon-doped gallium nitride layer Thickness and undoped GaN The ratio of the thickness of the layers is in the range of 3.5 to 5.

In some embodiments, a method of manufacturing a high electron mobility transistor device further includes forming a nucleation layer between the substrate and these alternating layers, where the nucleation layer includes aluminum nitride, aluminum gallium nitride, or a combination of the foregoing.

In some embodiments, a method of manufacturing a high electron mobility transistor device further includes forming a buffer layer between the substrate and these alternating layers, where the buffer layer includes a graded buffer layer, a superlattice buffer layer, or a combination of the foregoing.

110‧‧‧ base

120‧‧‧Nuclear layer

130‧‧‧buffer layer

140‧‧‧ alternating layer

142‧‧‧Carbon-doped gallium nitride layer

144‧‧‧ undoped gallium nitride layer

150‧‧‧stress relaxation layer

160‧‧‧GaN layer

170‧‧‧ barrier layer

180‧‧‧Source

190‧‧‧Gate

200‧‧‧ Jiji

220‧‧‧Super lattice buffer layer

222a, 224a, 226a‧‧‧‧AlGaN layer

222b, 224b, 226b ‧‧‧ aluminum nitride layer

230‧‧‧gradient buffer layer

232,234,236‧‧‧‧AlGaN layer

1000, 2000, 3000, 4000 ‧‧‧ high electron mobility transistor device

The embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. It should be noted that according to standard practices in the industry, various features are not drawn to scale and are used for illustration only. In fact, the size of the elements may be arbitrarily enlarged or reduced to clearly show the features of the present disclosure.

FIGS. 1A-1E are schematic cross-sectional views illustrating various stages of manufacturing a high electron mobility transistor device according to some embodiments.

Figures 2-4 are schematic cross-sectional views of a high electron mobility transistor device according to some embodiments.

Some embodiments are summarized below so that those with ordinary knowledge in the technical field to which the present invention belongs can more easily understand the present invention, but these embodiments are not intended to limit the present invention. It can be understood that those with ordinary knowledge in the technical field to which the present invention belongs can adjust the embodiments described below according to needs, for example, changing the process sequence and/or including more or fewer steps than described herein. In addition, other elements may be added on the basis of the embodiments described below. For example, the description of "forming a second element on a first element" might include Embodiments in which an element directly contacts the second element may also include embodiments in which there are other elements between the first element and the second element so that the first element does not directly contact the second element, and the first element and the second element The up and down relationship of elements may change as the device is operated or used in different orientations.

In the following, according to some embodiments of the present invention, it is described that an alternating layer including a carbon-doped gallium nitride layer and an undoped gallium nitride layer is provided in a high electron mobility transistor device to improve the withstand voltage while improving Crystal quality. In addition, at least one stress relaxation layer is provided above the alternating layer to relieve the stress, thereby increasing the alternating layer and the thickness, so that the high electron mobility transistor device reaches a higher withstand voltage level.

FIGS. 1A-1E are schematic cross-sectional views illustrating various stages of manufacturing a high electron mobility transistor device 1000 according to some embodiments. As shown in FIG. 1A, the high electron mobility transistor device 1000 includes a substrate 110, which may be a bulk semiconductor substrate or a composite substrate formed of different materials, and any suitable for semiconductor devices may be used. Substrate materials, such as silicon, germanium, silicon carbide, gallium nitride, and sapphire.

In some embodiments, a nucleation layer 120 is formed over the substrate 110 to alleviate the lattice difference between the substrate 110 and the film layer grown above. For example, the material of the nucleation layer 120 may include, for example, aluminum nitride (Aluminium Nitride, AlN), aluminum gallium nitride (Aluminium Gallium Nitride, AlGaN), similar materials, or a combination of the foregoing, and the thickness of the nucleation layer 120 It may be in the range of about 100 nanometers (nm) to about 1000 nm, for example about 200 nm. The formation of the nucleation layer 120 may include a deposition process, such as metal organic chemical vapor deposition (Metal Organic Chemical Vapor Deposition, MOCVD), Molecular Beam Epitaxy (MBE), Liquid Phase Epitaxy (LPE) or other deposition techniques.

In some embodiments, a buffer layer 130 is formed over the nucleation layer 120 to alleviate the lattice difference between different film layers. The nucleation layer 120 is selective. In other embodiments, the nucleation layer 120 is not provided, and the buffer layer 130 is formed directly on the substrate. The buffer layer 130 may include group III nitrides, such as gallium nitride (Gallium Nitride, GaN), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), similar materials, or a combination of the foregoing, and the thickness of the buffer layer 130 It may be in the range of about 0.1 micrometer (μm) to about 10 μm, for example about 0.3 μm. The formation of the buffer layer 130 may include a deposition process, such as organic metal chemical vapor deposition, molecular beam epitaxy, liquid phase epitaxy, or other deposition techniques.

Then, as shown in FIG. 1B, an alternating layer 140 is formed over the buffer layer 130. The alternating layer 140 includes a carbon-doped gallium nitride layer (Carbon-doped Gallium Nitride, CGaN) 142 and an undoped gallium nitride layer ( undoped Gallium Nitride (uGaN)144. Doping carbon in the gallium nitride layer to form a carbon-doped gallium nitride layer (CGaN) 142 can increase the resistivity and enable the high electron mobility transistor device 1000 to achieve high withstand voltage applications. In some embodiments, the carbon-doped gallium nitride layer (CGaN) 142 has a carbon concentration in the range of about 10 ¹⁸ to about 10 ²² /cubic centimeter. In the process of doping carbon, in order for carbon to easily enter the gallium nitride layer, gallium nitride can be grown at a low temperature and a low ratio of Group V to Group III. However, such growth conditions are likely to cause problems such as poor crystal quality and surface roughness, and as the thickness of the carbon-doped gallium nitride layer (CGaN) increases, the above-mentioned problems become more significant, which in turn affects high electron mobility transistor devices Adversely affects its performance, such as the characteristics of the two-dimensional electron gas.

In this regard, an undoped gallium nitride layer (uGaN) 144 is formed over the carbon-doped gallium nitride layer (CGaN) 142 to improve the rough surface of the carbon-doped gallium nitride layer (CGaN) 142, and It is possible to increase the thickness of the carbon-doped gallium nitride layer (CGaN) 142 while maintaining the crystal quality of the overall gallium nitride layer and having a less rough surface. In other words, forming an undoped gallium nitride layer (uGaN) 144 over the carbon-doped gallium nitride layer (CGaN) 142 can maintain the performance of the high electron mobility transistor device 1000, such as two-dimensional electron gas characteristics , Can also further improve the degree of withstand voltage.

Different numbers of alternating layers 140 may be provided according to requirements, for example, forming 14 pairs of alternating layers 140, wherein each pair of alternating layers 140 each includes a carbon-doped gallium nitride layer (CGaN) 142 and an undoped gallium nitride layer层(uGaN)144.

In some embodiments, the formation of a carbon-doped gallium nitride layer (CGaN) 142 and an undoped gallium nitride layer (uGaN) 144 may include a deposition process, such as organic metal chemical vapor deposition, molecular beam epitaxy , Liquid phase epitaxy or other deposition techniques. The thickness of the carbon-doped gallium nitride layer (CGaN) 142 may be in the range of about 1 nm to about 600 nm, for example, about 500 nm. The thickness of the undoped gallium nitride layer (uGaN) 144 may be in the range of about 1 nm to about 200 nm, for example about 125 nm. The ratio of the thickness of the carbon-doped gallium nitride layer (CGaN) 142 to the thickness of the undoped gallium nitride layer (uGaN) 144 is in the range of about 3.5 to about 5, such as about 4.

The thicker the undoped gallium nitride layer (uGaN) 144, that is, the smaller the ratio of the thickness of the carbon-doped gallium nitride layer (CGaN) 142 to the thickness of the undoped gallium nitride layer (uGaN) 144 , The more compensated the carbon doped gallium nitride layer (CGaN) 142 Crystal quality and surface roughness. On the other hand, the thicker the carbon-doped gallium nitride layer (CGaN) 142, the thicker the carbon-doped gallium nitride layer (CGaN) 142 and the undoped gallium nitride layer (uGaN) 144 The greater the ratio of the thickness, the better pressure resistance can be achieved. The ratio of the thickness of the carbon-doped gallium nitride layer (CGaN) 142 to the thickness of the undoped gallium nitride layer (uGaN) 144 may be set according to requirements.

As shown in FIG. 1C, at least one stress relaxation layer 150 is formed on the alternating layer 140. In some embodiments, the stress relaxation layer 150 may be an aluminum-containing layer, such as aluminum nitride (AlN), aluminum gallium nitride (AlGaN), or a combination of the foregoing, and the thickness of the stress relaxation layer 150 may be about 0.1 nm to A range of about 10 nm, for example about 1 nm. The formation of the stress relaxation layer 150 may include a deposition process, such as organic metal chemical vapor deposition, molecular beam epitaxy, liquid phase epitaxy, or other deposition techniques.

As mentioned above, multiple pairs of alternating layers 140 can be provided according to requirements. However, due to the different thermal expansion coefficients of the alternating layers 140 and the substrate 110, as the number and thickness of the alternating layers 140 increase, the greater the stress, resulting in curvature ( bow), cracks and uneven thickness, these problems limit the number of alternating layers 140 that can be provided. In this case, the stress relaxation layer 150 is provided on the alternating layer 140 to relieve the stress of the alternating layer 140. Therefore, the number and thickness of the alternating layer 140 can be increased, and the high electron mobility transistor device 1000 can reach a higher withstand voltage.

Then, as shown in FIG. 1D, according to some embodiments, a gallium nitride layer 160 is formed over the stress relaxation layer 150. The gallium nitride layer 160 has better crystal quality and can provide a flat surface for forming other devices. GaN layer 160 The formation may include a deposition process, such as organic metal chemical vapor deposition, molecular beam epitaxy, liquid phase epitaxy, or other deposition techniques. The thickness of the gallium nitride layer 160 can be selected according to requirements. In some embodiments, the thickness of the gallium nitride layer 160 is in the range of about 10 nm and about 1 μm, for example about 0.5 μm.

Then, as shown in FIG. 1E, a barrier layer 170 is formed over the gallium nitride layer 160. The formation of the barrier layer 170 may include a deposition process, such as organic metal chemical vapor deposition, molecular beam epitaxy, liquid phase epitaxy, or other deposition techniques. The thickness of the barrier layer 170 can be selected according to requirements. In some embodiments, the material of the barrier layer 170 may include a group III nitride, such as a group III-V compound semiconductor material. The barrier layer 170 may include a single-layer or multi-layer structure. For example, the barrier layer 170 includes AlN, AlGaN, AlInN, AlGaInN, similar materials, or a combination of the foregoing. The barrier layer 170 may be doped or undoped according to requirements. The material of the barrier layer 170 is selected to generate two-dimensional electron gas at the interface between the gallium nitride layer 160 and the barrier layer 170.

Then, according to some embodiments, the source electrode 180, the gate electrode 190, and the drain electrode 200 are disposed above the barrier layer 170 to form a high electron mobility transistor device 1000. The source 180, gate 190, and drain 200 can be formed using any suitable materials, processes, and sequences, and the pitch and position of the components can be adjusted according to requirements. In the embodiment shown in FIG. 1E, the source electrode 180, the gate electrode 190, and the drain electrode 200 are located on the barrier layer 170, but the present invention is not limited thereto.

In addition, the number and configuration of the stress relaxation layer 150 and the alternating layer 140 can be set according to requirements. Figures 2-4 are schematic cross-sectional views of a high electron mobility transistor device according to some other embodiments. According to some embodiments, as shown in FIG. 2, in the high electron mobility transistor device 2000, the two pairs alternate A stress relaxation layer 150 is disposed between the layers 140, and then a gallium nitride layer 160 contacting the alternating layer 140 is disposed above the alternating layer 140. Although not shown, according to some embodiments, multiple pairs of alternating layers 140 and multiple layers of stress relaxation layer 150 may be disposed between the alternating layer 140 and the gallium nitride layer 160 of the high electron mobility transistor device 2000. These stress relaxation layers 150 may be located above each pair of alternating layers 140, or only between specific alternating layers 140. The stress relaxation layers 150 may have the same or different thicknesses according to requirements.

In addition, according to other embodiments, as shown in FIG. 3, in the high electron mobility transistor device 3000, two stress relaxation layers 150 are respectively disposed above the two pairs of alternating layers 140, and then disposed above the stress relaxation layer 150 The gallium nitride layer 160 in contact with the stress relaxation layer 150. Although not shown, according to some embodiments, multiple pairs of alternating layers 140 and multiple layers of stress relaxation layer 150 may be disposed between the stress relaxation layer 150 and the gallium nitride layer 160 of the high electron mobility transistor device 3000. These stress relaxation layers 150 may be located above each pair of alternating layers 140, or only between specific alternating layers 140. The stress relaxation layers 150 may have the same or different thicknesses according to requirements.

In addition, according to some embodiments, as shown in FIG. 4, the buffer layer 130 of the high electron mobility transistor device 4000 may include a gradient buffer layer, a superlattice buffer layer, Similar buffer layers or combinations of the foregoing. Although FIG. 4 shows that the buffer layer 130 includes the superlattice buffer layer 220 and the graded buffer layer 230, only the superlattice buffer layer 220 or the graded buffer layer 230 may be used.

In some embodiments, the superlattice buffer layer 220 includes multiple sets of film layers with different concentration, and each set of film layers includes multiple pairs of aluminum nitride layers and aluminum gallium nitride Floor. For example, as shown in FIG. 4, the superlattice buffer layer 220 includes a first group of film layers including an aluminum gallium nitride layer 222a and an aluminum nitride layer 222b, and a second group includes an aluminum gallium nitride layer 224a and nitrogen The film layer of the aluminum oxide layer 224b and the third group of film layers include the aluminum gallium nitride layer 226a and the aluminum nitride layer 226b, but the present invention is not limited thereto, and the superlattice buffer layer 220 may include more sets of film layers and/or Or more pairs of aluminum nitride layer and aluminum gallium nitride layer. The formation of the superlattice buffer layer 220 may include a deposition process, such as organic metal chemical vapor deposition, molecular beam epitaxy, liquid phase epitaxy, or other deposition techniques. According to requirements, each pair of aluminum gallium nitride layer and aluminum nitride layer of superlattice buffer layer 220 and other pairs of aluminum gallium nitride layer and aluminum nitride layer may have the same or different thickness and that of aluminum gallium nitride layer Aluminum concentration.

In some embodiments, the graded buffer layer 230 includes multiple layers of aluminum gallium nitride with different concentration. For example, as shown in FIG. 4, the graded buffer layer 230 includes three aluminum gallium nitride layers 232, 234, and 236, but the present invention is not limited thereto, and more or fewer aluminum gallium nitride layers may be provided . The formation of the graded buffer layer 230 may include a deposition process, such as organic metal chemical vapor deposition, molecular beam epitaxy, liquid phase epitaxy, or other deposition techniques. According to requirements, each aluminum gallium nitride layer of the graded buffer layer 230 may have the same or different thickness and aluminum concentration.

As shown in FIG. 4, the provision of the buffer layer 130 including the superlattice buffer layer 220 and the graded buffer layer 230 can relieve the stress of the alternating layer 140 provided above the buffer layer 130 and avoid cracks, so the alternating layer can be added 140 thickness. In addition, at the same thickness, the formation of the buffer layer 130 including the superlattice buffer layer 220 and the graded buffer layer 230 can greatly shorten the growth time compared to the formation of the superlattice buffer layer 220 alone. In addition, compared to forming only a gradient buffer layer 230, forming an alternate layer 140 formed above the buffer layer 130 including the superlattice buffer layer 220 and the graded buffer layer 230 to have better crystal quality. Therefore, the efficiency and yield of the high electron mobility transistor device can be improved while increasing productivity.

Subsequently, referring to the aforementioned method, material and configuration, a plurality of pairs of alternating layers 140 and at least one stress relaxation layer 150 are provided above the graded buffer layer 230, and then a gallium nitride layer 160 is provided. Then, a barrier layer 170, a source electrode 180, a gate electrode 190, and a drain electrode 200 are provided to form a high electron mobility transistor device 4000.

In summary, according to some embodiments of the present invention, providing an undoped gallium nitride layer above the carbon-doped gallium nitride layer can improve the crystal quality and surface roughness of the carbon-doped gallium nitride layer . Therefore, it is possible to maintain the performance of the high electron mobility transistor device, such as the two-dimensional electron gas characteristics, and further improve the device withstand voltage.

In addition, according to some embodiments of the present invention, providing a stress relaxation layer above an alternating layer containing a carbon-doped gallium nitride layer and an undoped gallium nitride layer can relieve the stress of the alternating layer, and thus can increase the alternating The number and thickness of the layers enable the high electron mobility transistor device to reach a higher withstand voltage.

In addition, according to some embodiments of the present invention, providing a buffer layer including a graded buffer layer and a superlattice buffer layer above the substrate can alleviate the stress of the alternating layer provided above the buffer layer to avoid cracks or warpage, so The thickness of alternating layers can be increased. In addition, compared to forming only the superlattice buffer layer or the graded buffer layer, the buffer layer including the graded buffer layer and the superlattice buffer layer can improve the productivity while improving the high electron mobility transistor device Efficacy and yield.

Although the present invention has been described above with multiple embodiments, these embodiments are not intended to limit the present invention. Those of ordinary skill in the technical field to which the present invention belongs should understand that they can make various changes, substitutions, and replacements based on the embodiments of the present invention to achieve the same purpose as the multiple embodiments described herein And/or advantages. Those with ordinary knowledge in the technical field to which the present invention belongs can also understand that such modifications or designs do not depart from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be deemed as defined by the appended patent application scope.

110‧‧‧ base

120‧‧‧Nuclear layer

130‧‧‧buffer layer

140‧‧‧ alternating layer

142‧‧‧Carbon-doped gallium nitride layer

144‧‧‧ undoped gallium nitride layer

150‧‧‧stress relaxation layer

160‧‧‧GaN layer

170‧‧‧ barrier layer

180‧‧‧Source

190‧‧‧Gate

200‧‧‧ Jiji

1000‧‧‧High electron mobility transistor device

Claims (20)

A high electron mobility transistor (HEMT) device includes: a substrate; a plurality of pairs of alternating layers disposed on the substrate and each pair of alternating layers includes a carbon-doped gallium nitride layer and an undoped nitride A gallium layer; at least one stress relaxation layer disposed between the alternating layers; and a gallium nitride layer disposed above the alternating layers. The high electron mobility transistor device described in item 1 of the patent application scope, wherein the stress relaxation layer is an aluminum-containing layer. The high electron mobility transistor device described in item 2 of the patent application range, wherein the aluminum-containing layer includes aluminum nitride (AlN), aluminum gallium nitride (AlGaN), or a combination of the foregoing. A high electron mobility transistor device as described in item 1 of the patent application range, wherein the stress relaxation layer is disposed between every two pairs of the alternating layers. A high electron mobility transistor device as described in item 1 of the patent application range, wherein the thickness in the stress relaxation layer is in the range of 0.1 nm to 10 nm. The high electron mobility transistor device as described in item 1 of the patent application range, wherein the thickness of the carbon-doped gallium nitride layer is in the range of 1 nm to 600 nm, and the thickness of the undoped gallium nitride layer is 1nm to 200nm range. The high electron mobility transistor device as described in item 1 of the patent application range, wherein the ratio of the thickness of the carbon-doped gallium nitride layer to the thickness of the undoped gallium nitride layer is in the range of 3.5 to 5 . As described in item 1 of the patent application scope, a high electron mobility transistor device, It further includes a nucleation layer disposed between the substrate and the alternating layers. The high electron mobility transistor device as described in item 8 of the patent application range, wherein the nucleation layer includes aluminum nitride (AlN), aluminum gallium nitride (AlGaN), or a combination of the foregoing. The high electron mobility transistor device described in item 1 of the patent application scope further includes a buffer layer disposed between the substrate and the alternating layers. The high electron mobility transistor device described in item 10 of the patent application range, wherein the buffer layer includes gallium nitride (GaN), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), or a combination of the foregoing. The high electron mobility transistor device as described in item 10 of the patent application range, wherein the buffer layer includes a gradient buffer layer, a superlattice buffer layer, or a combination thereof. The high electron mobility transistor device described in item 1 of the patent application scope further includes: a barrier layer disposed above the gallium nitride layer; and a source electrode, a drain electrode, and a gate electrode Above the barrier layer. A method for manufacturing a high electron mobility transistor device includes: forming a substrate; forming a plurality of pairs of alternating layers above the substrate, wherein each pair of alternating layers includes a carbon-doped gallium nitride layer and an undoped nitrogen A gallium nitride layer; forming at least one stress relaxation layer between the alternating layers; and forming a gallium nitride layer above the alternating layers. Transistor device with high electron mobility as described in item 14 of the patent application Wherein the alternating layers include aluminum nitride, aluminum gallium nitride, or a combination of the foregoing, and the stress relaxation layer includes aluminum nitride, aluminum gallium nitride, or a combination of the foregoing. The method for manufacturing a high electron mobility transistor device as described in item 14 of the patent application scope further includes forming the stress relaxation layer between every two pairs of the alternating layers. The method for manufacturing a high electron mobility transistor device as described in item 14 of the patent application range, wherein the thickness of the stress relaxation layer is in the range of 1 nm to 500 nm. The method for manufacturing a high electron mobility transistor device as described in item 14 of the patent application range, wherein the thickness of the carbon-doped gallium nitride layer is in the range of 1 nm to 600 nm, and the thickness of the undoped gallium nitride layer The thickness is in the range of 1 nm to 200 nm, and the ratio of the thickness of the carbon-doped gallium nitride layer to the thickness of the undoped gallium nitride layer is in the range of 3.5 to 5. The method for manufacturing a high electron mobility transistor device as described in item 14 of the patent application scope further includes forming a nucleation layer between the substrate and the alternating layers, wherein the nucleation layer includes aluminum nitride and nitrogen Aluminum gallium or a combination of the foregoing. The method for manufacturing a high electron mobility transistor device as described in item 14 of the patent application scope further includes forming a buffer layer between the substrate and the alternating layers, wherein the buffer layer includes a graded buffer layer, a Superlattice buffer layer or a combination of the foregoing.

Images