TW202016937A - Data merge method, memory storage device and memory control circuit unit - Google Patents

Abstract

A data merge method for a rewritable non-volatile memory module including a plurality of physical units is provided according to an exemplary embodiment of the disclosure. The method includes: obtaining a first logical distance value between a first physical unit and a second physical unit among the physical units, wherein the first logical distance value reflects a logical dispersion degree between at least one first logical unit mapped by the first physical unit and at least one second logical unit mapped by the second physical unit; and performing a data merge operation according to the first logical distance value, so as to copy valid from a source node to a source node.

Description

Data consolidation method, memory storage device and memory control circuit unit

The invention relates to a flash memory technology, and in particular to a data consolidation method, a memory storage device and a memory control circuit unit.

Digital cameras, mobile phones and MP3 players have grown rapidly in recent years, and consumers' demand for storage media has also increased rapidly. The rewritable non-volatile memory module (for example, flash memory) has the characteristics of non-volatile data, power saving, small size, and no mechanical structure, so it is very suitable for internal Built in various portable multimedia devices exemplified above.

When the memory storage device is shipped from the factory, a part of the physical units in the memory storage device is configured as a plurality of idle physical units to use the idle physical units to store new data. After a period of use, the number of idle physical units in the memory storage device will gradually decrease. The memory storage device can copy the valid data from multiple source nodes to the recycling node (also known as the target node) and erase the physical units belonging to the source node through a data consolidation process (or garbage collection process) to release New idle physical unit. However, in the data consolidation process, the more scattered the logical units mapped to the multiple physical units selected as the source node, the more tables that record the management information (such as mapping information) of these logical units need to be accessed , Thereby increasing the number of accesses to the memory storage device and accelerating the wear and tear of the memory storage device (eg, memory cell).

The invention provides a data consolidation method, a memory storage device and a memory control circuit unit, which can effectively reduce the number of accesses to the memory storage device in the data consolidation process.

Example embodiments of the present invention provide a data consolidation method for a rewritable non-volatile memory module, where the rewritable non-volatile memory module includes a plurality of physical units. The data consolidation method includes: obtaining a first logical distance value between a first physical unit and a second physical unit of the physical units, wherein the first logical distance value reflects the mapping of the first physical unit The logical dispersion between the at least one first logical unit and the at least one second logical unit mapped by the second physical unit; and performing data consolidation based on the first logical distance value to remove valid data from The source node in the physical unit is copied to the recycling node in the physical unit.

In an exemplary embodiment of the present invention, the step of performing the data consolidation operation according to the first logical distance value includes: if the first logical distance value is not greater than the target distance value, the first physical unit Valid data in the copy to the recycling node and copy valid data in the second physical unit to the recycling node; and if the logical distance value is greater than the target distance value, copy the first physical unit The valid data in is copied to the recycling node and the valid data in the third physical unit of the physical units is copied to the recycling node.

In an exemplary embodiment of the present invention, the data consolidation method further includes: obtaining a second logical distance value between the first physical unit and the third physical unit, wherein the target distance value includes The second logical distance value.

In an exemplary embodiment of the present invention, the step of obtaining the first logical distance value between the first physical unit and the second physical unit of the physical units includes: mapping information according to a first table Obtaining the first logical distance value with the second table mapping information, wherein the first table mapping information reflects the logic-to-physical mapping information of the first logical unit recorded in at least one first logic-to-physical mapping table, and all The second table mapping information reflects the logic-to-entity mapping information of the second logic unit recorded in at least one second logic-to-entity mapping table.

In an exemplary embodiment of the present invention, the first table mapping information includes a first bit, the second table mapping information includes a second bit, and according to the first table mapping information and the first The step of obtaining the first logical distance value by the two-table mapping information includes: performing a first operation on the first bit and the second bit to obtain a third bit; and obtaining according to the third bit The first logical distance value.

In an exemplary embodiment of the present invention, the first table mapping information includes N first values, the second table mapping information includes N second values, and according to the first table mapping information and the The step of obtaining the first logical distance value from the second table mapping information includes: obtaining an N-dimensional distance between the N first values and the N second values; and obtaining the N-dimensional distance according to the N-dimensional distance The first logical distance value.

An exemplary embodiment of the present invention further provides a memory storage device, which includes a connection interface unit, a rewritable non-volatile memory module, and a memory control circuit unit. The connection interface unit is used for coupling to the host system. The rewritable non-volatile memory module includes multiple physical units. The memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is used to obtain a first logical distance value between the first physical unit and the second physical unit of the physical units. The first logical distance value reflects the degree of logical dispersion between at least one first logical unit mapped by the first physical unit and at least one second logical unit mapped by the second physical unit. The memory control circuit unit is further used to perform data consolidation according to the first logical distance value, so as to copy valid data from the source node in the physical unit to the recovery node in the physical unit.

In an exemplary embodiment of the present invention, the operation of the memory control circuit unit performing the data consolidation operation according to the first logical distance value includes: if the first logical distance value is not greater than the target distance value, Instruct to copy valid data in the first physical unit to the recycling node and copy valid data in the second physical unit to the recycling node; and if the logical distance value is greater than the target distance value Indicating that the valid data in the first physical unit is copied to the recycling node and the valid data in the third physical unit in the physical unit is copied to the recycling node.

In an exemplary embodiment of the present invention, the memory control circuit unit is further used to obtain a second logical distance value between the first physical unit and the third physical unit, and the target distance value includes The second logical distance value.

In an exemplary embodiment of the present invention, the operation of the memory control circuit unit to obtain the first logical distance value between the first physical unit and the second physical unit in the physical unit includes : Obtaining the first logical distance value according to the first table mapping information and the second table mapping information, wherein the first table mapping information reflects the logic-to-physical mapping information of the first logic unit recorded in at least one first logic To an entity mapping table, and the second table mapping information reflects the logic-to-entity mapping information of the second logical unit recorded in at least one second logic-to-entity mapping table.

In an exemplary embodiment of the present invention, the first table mapping information includes a first bit, the second table mapping information includes a second bit, and the memory control circuit unit is based on the first table The operation of obtaining the first logical distance value by the mapping information and the second table mapping information includes: performing a first operation on the first bit and the second bit to obtain a third bit; and according to all The third bit obtains the first logical distance value.

In an exemplary embodiment of the present invention, the first table mapping information includes N first values, the second table mapping information includes N second values, and the memory control circuit unit is based on the The operation of obtaining the first logical distance value by a table of mapping information and the second table of mapping information includes: obtaining an N-dimensional distance between the N first values and the N second values; and The N-dimensional distance obtains the first logical distance value.

The exemplary embodiment of the present invention further provides a memory control circuit unit for controlling a rewritable non-volatile memory module. The rewritable non-volatile memory module includes multiple physical units. The memory control circuit unit includes a host interface, a memory interface and a memory management circuit. The host interface is used to couple to the host system. The memory interface is used to couple to the rewritable non-volatile memory module. The memory management circuit is coupled to the host interface and the memory interface. The memory management circuit is used to obtain a first logical distance value between the first physical unit and the second physical unit of the physical units. The first logical distance value reflects the degree of logical dispersion between at least one first logical unit mapped by the first physical unit and at least one second logical unit mapped by the second physical unit. The memory management circuit is further used to perform data consolidation according to the first logical distance value, so as to copy valid data from the source node in the physical unit to the recovery node in the physical unit.

In an exemplary embodiment of the present invention, the logical-to-physical mapping information of the first logical unit is recorded in at least one first logical-to-physical mapping table, and the logical-to-physical mapping information of the second logical unit is recorded in at least one A second logical-to-physical mapping table, and the first logical distance value further reflects the degree of overlap between the first logical-to-physical mapping table and the second logical-to-physical mapping table.

In an exemplary embodiment of the present invention, the operation of the memory management circuit performing the data consolidation operation according to the first logical distance value includes: if the first logical distance value is not greater than the target distance value, indicating Copy valid data in the first physical unit to the recycling node and copy valid data in the second physical unit to the recycling node; and if the logical distance value is greater than the target distance value, Instruct to copy the valid data in the first physical unit to the recycling node and copy the valid data in the third physical unit in the physical unit to the recycling node.

In an exemplary embodiment of the present invention, the memory management circuit is further used to obtain a second logical distance value between the first physical unit and the third physical unit, and the target distance value includes Said second logical distance value.

In an exemplary embodiment of the present invention, the operation of the memory management circuit to obtain the first logical distance value between the first physical unit and the second physical unit in the physical unit includes: The first logical distance value is obtained according to the first table mapping information and the second table mapping information. The first table mapping information reflects a logical-to-physical mapping information of the first logical unit recorded in at least one first logical-to-physical mapping table. The second table mapping information reflects a logical-to-physical mapping information of the second logical unit recorded in at least one second logical-to-physical mapping table.

In an exemplary embodiment of the present invention, the first table mapping information includes a first bit, the second table mapping information includes a second bit, and the memory management circuit maps according to the first table The operation of obtaining the first logical distance value by the information and the second table mapping information includes: performing a first operation on the first bit and the second bit to obtain a third bit; and according to the The third bit obtains the first logical distance value.

In an exemplary embodiment of the present invention, the first table mapping information includes N first values, the second table mapping information includes N second values, and the memory management circuit is based on the first The operation of obtaining the first logical distance value by the table mapping information and the second table mapping information includes: obtaining an N-dimensional distance between the N first values and the N second values; and according to the The N-dimensional distance obtains the first logical distance value.

Based on the above, after obtaining the first logical distance value between the first physical unit and the second physical unit, the data consolidation operation may be performed according to the first logical distance value to copy valid data from the source node to the recycling node . By considering the logical dispersion between the first logical unit mapped by the first physical unit and the second logical unit mapped by the second physical unit, the number of accesses to the memory storage device in the data consolidation process can be effectively reduced To further increase the service life of the memory storage device.

In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, the embodiments are specifically described below in conjunction with the accompanying drawings for detailed description as follows.

Generally speaking, a memory storage device (also known as a memory storage system) includes a rewritable non-volatile memory module (rewritable non-volatile memory module) and a controller (also known as a control circuit). Usually, the memory storage device is used together with the host system, so that the host system can write data to the memory storage device or read data from the memory storage device.

FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an exemplary embodiment of the present invention. 2 is a schematic diagram of a host system, a memory storage device, and an I/O device according to another exemplary embodiment of the present invention.

Referring to FIGS. 1 and 2, the host system 11 generally includes a processor 111, a random access memory (RAM) 112, a read only memory (ROM) 113 and a data transmission interface 114. The processor 111, the random access memory 112, the read-only memory 113, and the data transmission interface 114 are all coupled to the system bus 110.

In the present exemplary embodiment, the host system 11 is coupled to the memory storage device 10 through the data transmission interface 114. For example, the host system 11 can store data to or read data from the memory storage device 10 via the data transmission interface 114. In addition, the host system 11 is coupled to the I/O device 12 through the system bus 110. For example, the host system 11 can transmit output signals to or receive input signals from the I/O device 12 via the system bus 110.

In the present exemplary embodiment, the processor 111, the random access memory 112, the read-only memory 113, and the data transmission interface 114 may be provided on the motherboard 20 of the host system 11. The number of data transmission interfaces 114 may be one or more. Through the data transmission interface 114, the motherboard 20 can be coupled to the memory storage device 10 via a wired or wireless method. The memory storage device 10 may be, for example, a flash drive 201, a memory card 202, a solid state drive (Solid State Drive, SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 may be, for example, a near field communication (NFC) memory storage device, a wireless facsimile (WiFi) memory storage device, a Bluetooth memory storage device, or a Bluetooth low energy memory Memory devices such as storage devices (for example, iBeacon) based on various wireless communication technologies. In addition, the motherboard 20 can also be coupled to the Global Positioning System (GPS) module 205, the network interface card 206, the wireless transmission device 207, the keyboard 208, the screen 209, the speaker 210, etc. through the system bus 110 I/O device. For example, in an exemplary embodiment, the motherboard 20 can access the wireless memory storage device 204 through the wireless transmission device 207.

In an exemplary embodiment, the mentioned host system is any system that can substantially cooperate with a memory storage device to store data. Although in the above exemplary embodiment, the host system is described as a computer system, however, FIG. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the present invention. Referring to FIG. 3, in another exemplary embodiment, the host system 31 may also be a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer, and the memory storage device 30 may be Various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34 are used. The embedded storage device 34 includes an embedded multi-media card (eMMC) 341 and/or an embedded multi-chip package (eMCP) storage device 342 and other types of memory modules directly coupled to Embedded storage device on the substrate of the host system.

FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the invention.

4, the memory storage device 10 includes a connection interface unit 402, a memory control circuit unit 404 and a rewritable non-volatile memory module 406.

The connection interface unit 402 is used to couple the memory storage device 10 to the host system 11. The memory storage device 10 can communicate with the host system 11 through the connection interface unit 402. In this exemplary embodiment, the connection interface unit 402 is compatible with the Serial Advanced Technology Attachment (SATA) standard. However, it must be understood that the present invention is not limited to this, and the connection interface unit 402 may also conform to the Parallel Advanced Technology Attachment (PATA) standard, Institute of Electrical and Electronic Engineers (IEEE) 1394 Standard, High-speed Peripheral Component Interconnect Express (PCI Express) standard, Universal Serial Bus (USB) standard, SD interface standard, Ultra High Speed-I (UHS-I) interface Standard, Ultra High Speed-II (UHS-II) interface standard, Memory Stick (MS) interface standard, MCP interface standard, MMC interface standard, eMMC interface standard, Universal Flash Memory (Universal Flash Storage (UFS) interface standard, eMCP interface standard, CF interface standard, Integrated Drive Electronics Interface (Integrated Device Electronics, IDE) standard or other suitable standards. The connection interface unit 402 can be packaged in one chip with the memory control circuit unit 404, or the connection interface unit 402 can be disposed outside a chip containing the memory control circuit unit 404.

The memory control circuit unit 404 is used to execute a plurality of logic gates or control commands implemented in a hardware type or a firmware type and execute data in a rewritable non-volatile memory module 406 according to commands of the host system 11 Write, read and erase operations.

The rewritable non-volatile memory module 406 is coupled to the memory control circuit unit 404 and is used to store data written by the host system 11. The rewritable non-volatile memory module 406 may be a single-level memory cell (SLC) NAND-type flash memory module (ie, a flash memory that can store 1 bit in a memory cell Module), Multi Level Cell (MLC) NAND flash memory module (that is, a flash memory module that can store 2 bits in a memory cell), tertiary memory cell ( Triple Level Cell (TLC) NAND flash memory module (ie, a flash memory module that can store 3 bits in a memory cell), Quad Level Cell (TLC) NAND flash Flash memory modules (that is, flash memory modules that can store 4 bits in one memory cell), other flash memory modules, or other memory modules with the same characteristics.

Each memory cell in the rewritable non-volatile memory module 406 stores one or more bits with a change in voltage (hereinafter also referred to as a threshold voltage). Specifically, each memory cell has a charge trapping layer between the control gate and the channel. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the critical voltage of the memory cell is also called "writing data to the memory cell" or "programming (programming) the memory cell". As the threshold voltage changes, each memory cell in the rewritable non-volatile memory module 406 has multiple storage states. By applying a read voltage, it can be determined which storage state a memory cell belongs to, thereby obtaining one or more bits stored in the memory cell.

In this exemplary embodiment, the memory cells of the rewritable non-volatile memory module 406 may constitute multiple physical programming units, and these physical programming units may constitute multiple physical erasing units. Specifically, the memory cells on the same character line may constitute one or more physical programming units. If each memory cell can store more than 2 bits, the physical programming unit on the same character line can be at least classified into a lower physical programming unit and an upper physical programming unit. For example, the least significant bit (LSB) of a memory cell belongs to the lower physical programming unit, and the most significant bit (MSB) of a memory cell belongs to the upper physical programming unit. Generally speaking, in MLC NAND flash memory, the writing speed of the lower physical programming unit is higher than that of the upper physical programming unit, and/or the reliability of the lower physical programming unit is higher than that of the upper Reliability of physical programming units.

In this exemplary embodiment, the physical programming unit is the smallest unit of programming. That is, the physical programming unit is the smallest unit to write data. For example, the physical programming unit may be a physical page or a sector. If the physical programming unit is a physical page, these physical programming units may include a data bit area and a redundancy bit area. The data bit area includes multiple physical fans to store user data, and the redundant bit area is used to store system data (eg, error correction codes and other management data). In this exemplary embodiment, the data bit area includes 32 physical fans, and the size of one physical fan is 512 bytes (byte, B). However, in other exemplary embodiments, the data bit area may also include 8, 16 or more or fewer physical fans, and the size of each physical fan may also be larger or smaller. On the other hand, the physical erasing unit is the smallest unit of erasing. That is, each physical erasing unit contains one of the minimum number of memory cells to be erased. For example, the physical erasing unit is a physical block.

5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the invention.

5, the memory control circuit unit 404 includes a memory management circuit 502, a host interface 504 and a memory interface 506.

The memory management circuit 502 is used to control the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 502 has a plurality of control commands, and when the memory storage device 10 is operating, the control commands are executed to perform operations such as writing, reading, and erasing of data. The following description of the operation of the memory management circuit 502 is equivalent to the operation of the memory control circuit unit 404.

In the present exemplary embodiment, the control commands of the memory management circuit 502 are implemented in the form of firmware. For example, the memory management circuit 502 has a microprocessor unit (not shown) and a read-only memory (not shown), and the control commands are burned into the read-only memory. When the memory storage device 10 is operating, these control commands are executed by the microprocessor unit to perform operations such as writing, reading, and erasing of data.

In another exemplary embodiment, the control commands of the memory management circuit 502 can also be stored in a specific area of the rewritable non-volatile memory module 406 in program code (for example, the memory module is dedicated to storing system data System area). In addition, the memory management circuit 502 has a microprocessor unit (not shown), a read-only memory (not shown), and a random access memory (not shown). In particular, the read-only memory has a boot code, and when the memory control circuit unit 404 is enabled, the microprocessor unit will first execute the boot code to store in the rewritable non-volatile memory The control commands in the body module 406 are loaded into the random access memory of the memory management circuit 502. Afterwards, the microprocessor unit will run these control commands to write, read, and erase data.

In addition, in another exemplary embodiment, the control commands of the memory management circuit 502 can also be implemented in a hardware type. For example, the memory management circuit 502 includes a microcontroller, a memory cell management circuit, a memory writing circuit, a memory reading circuit, a memory erasing circuit, and a data processing circuit. The memory cell management circuit, memory writing circuit, memory reading circuit, memory erasing circuit and data processing circuit are coupled to the microcontroller. The memory cell management circuit is used to manage memory cells or memory cell groups of the rewritable non-volatile memory module 406. The memory writing circuit is used to issue a write command sequence to the rewritable non-volatile memory module 406 to write data into the rewritable non-volatile memory module 406. The memory reading circuit is used to issue a read command sequence to the rewritable non-volatile memory module 406 to read data from the rewritable non-volatile memory module 406. The memory erasing circuit is used to issue an erase command sequence to the rewritable non-volatile memory module 406 to erase data from the rewritable non-volatile memory module 406. The data processing circuit processes data to be written to the rewritable non-volatile memory module 406 and data read from the rewritable non-volatile memory module 406. The write command sequence, read command sequence, and erase command sequence may each include one or more program codes or command codes and are used to instruct the rewritable non-volatile memory module 406 to perform the corresponding write, read Take and erase operations. In an exemplary embodiment, the memory management circuit 502 can also issue other types of command sequences to the rewritable non-volatile memory module 406 to instruct to perform the corresponding operation.

The host interface 504 is coupled to the memory management circuit 502. The memory management circuit 502 can communicate with the host system 11 through the host interface 504. The host interface 504 can be used to receive and identify commands and data sent by the host system 11. For example, the commands and data transmitted by the host system 11 can be transmitted to the memory management circuit 502 through the host interface 504. In addition, the memory management circuit 502 can transmit data to the host system 11 through the host interface 504. In this exemplary embodiment, the host interface 504 is compatible with the SATA standard. However, it must be understood that the present invention is not limited to this, the host interface 504 may also be compatible with the PATA standard, IEEE 1394 standard, PCI Express standard, USB standard, SD standard, UHS-I standard, UHS-II standard, MS standard , MMC standard, eMMC standard, UFS standard, CF standard, IDE standard or other suitable data transmission standards.

The memory interface 506 is coupled to the memory management circuit 502 and used to access the rewritable non-volatile memory module 406. In other words, the data to be written to the rewritable non-volatile memory module 406 is converted into a format acceptable to the rewritable non-volatile memory module 406 through the memory interface 506. Specifically, if the memory management circuit 502 wants to access the rewritable non-volatile memory module 406, the memory interface 506 will transmit the corresponding command sequence. For example, these command sequences may include a write command sequence instructing to write data, a read command sequence instructing to read data, an erase command sequence instructing to erase data, and various memory operations (for example, changing the read Take the voltage level or perform the garbage collection operation, etc.) the corresponding instruction sequence. These command sequences are generated by the memory management circuit 502 and transmitted to the rewritable non-volatile memory module 406 through the memory interface 506, for example. These command sequences may include one or more signals or data on the bus. These signals or data may include instruction codes or program codes. For example, in the read command sequence, the read identification code, memory address and other information will be included.

In an exemplary embodiment, the memory control circuit unit 404 further includes an error check and correction circuit 508, a buffer memory 510, and a power management circuit 512.

The error check and correction circuit 508 is coupled to the memory management circuit 502 and is used to perform error check and correction operations to ensure the accuracy of the data. Specifically, when the memory management circuit 502 receives the write command from the host system 11, the error checking and correction circuit 508 generates a corresponding error correcting code (ECC) for the data corresponding to the write command And/or error detection code (EDC), and the memory management circuit 502 writes the data corresponding to the write command and the corresponding error correction code and/or error check code to the rewritable non-volatile The memory module 406. After that, when the memory management circuit 502 reads data from the rewritable non-volatile memory module 406, it simultaneously reads the error correction code and/or error check code corresponding to the data, and the error check and correction circuit 508 Based on this error correction code and/or error check code, error checking and correction operations will be performed on the read data.

The buffer memory 510 is coupled to the memory management circuit 502 and is used to temporarily store data and commands from the host system 11 or data from the rewritable non-volatile memory module 406. The power management circuit 512 is coupled to the memory management circuit 502 and used to control the power of the memory storage device 10.

In an exemplary embodiment, the rewritable non-volatile memory module 406 of FIG. 4 is also referred to as a flash memory module, and the memory control circuit unit 404 is also referred to as a control flash memory The flash memory controller of the module, and/or the memory management circuit 502 of FIG. 5 are also referred to as flash memory management circuits.

6 is a schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the present invention.

6, the memory management circuit 502 can logically group the physical units 610(0) to 610(C) of the rewritable non-volatile memory module 406 into the storage area 601, the spare area 602 and System area 603. The physical units 610(0) to 610(A) in the storage area 601 store data. For example, the physical units 610(0)-610(A) in the storage area 601 can store valid data and invalid data. The physical units 610(A+1)~610(B) in the idle area 602 have not been used to store data (such as valid data). The physical units 610 (B+1) to 610 (C) in the system area 603 are used to store system data, such as logic to physical mapping tables, bad block management tables, device models, or other types of management data.

The memory management circuit 502 can select a physical unit from the physical units 610 (A+1) to 610 (B) in the idle area 602 and store data from the host system 11 or from at least one physical unit in the storage area 601 to all Selected solid element. At the same time, the selected physical unit will be associated with the storage area 601. In addition, after erasing a certain physical unit in the storage area 601, the erased physical unit will be re-associated to the idle area 602.

In this exemplary embodiment, each physical unit belonging to the storage area 601 is also referred to as a non-spare physical unit, and each physical unit belonging to the idle area 602 is also referred to as an idle physical unit. In this exemplary embodiment, a physical unit refers to a physical erasing unit. However, in another exemplary embodiment, one physical unit may also include multiple physical erasing units.

The memory management circuit 502 can configure the logical units 612(0)-612(D) to map the physical units 610(0)-610(A) in the storage area 601. In this exemplary embodiment, each logical unit refers to a logical address. However, in another exemplary embodiment, a logic unit may also refer to a logic programming unit, a logic erasing unit, or consist of multiple consecutive or non-contiguous logical addresses. In addition, each of the logical units 612(0) to 612(D) may be mapped to one or more physical units. It should be noted that the memory management circuit 502 may not be configured with a logical unit mapped to the system area 603 to prevent the system data stored in the system area 603 from being modified by the user.

The memory management circuit 502 records the mapping information between logical units and physical units (also referred to as logical-to-physical mapping information) in at least one logical-to-physical mapping table. The mapping information can reflect the mapping relationship between a certain physical unit and a certain logical unit in the storage area 601. The logical-to-physical mapping table is stored in the physical units 610(B+1)~610(C) of the system area 603. The memory management circuit 502 can perform data access operations to the memory storage device 10 according to this logic-to-physical mapping table. For example, the memory management circuit 502 may obtain a mapping relationship between a certain physical unit and a certain logical unit in the storage area 601 according to a certain logic-to-entity mapping table. The memory management circuit 502 can access the physical unit according to the mapping relationship.

In this exemplary embodiment, valid data is the latest data belonging to a certain logical unit, and invalid data is not the latest data belonging to any logical unit. For example, if the host system 11 stores a new piece of data in a logical unit and overwrites the old data originally stored in the logical unit (ie, updates the data belonging to the logical unit), the new piece of data stored in the storage area 601 The data is the latest data belonging to this logical unit and will be marked as valid, while the old data that is overwritten may still be stored in the storage area 601 but marked as invalid.

In this exemplary embodiment, if the data belonging to a logical unit is updated, the mapping relationship between the logical unit and the physical unit storing the old data belonging to the logical unit is removed, and the logical unit and The mapping relationship between the physical units storing the latest data belonging to this logical unit will be established. However, in another exemplary embodiment, if the data belonging to a logical unit is updated, the mapping relationship between the logical unit and the physical unit storing the old data belonging to the logical unit can still be maintained.

When the memory storage device 10 is shipped from the factory, the total number of physical units belonging to the idle area 602 will be a predetermined number (for example, 30). During the operation of the memory storage device 10, more and more physical units are selected from the idle area 602 and associated with the storage area 601 to store data (eg, user data from the host system 11). Therefore, the total number of physical units belonging to the idle area 602 may gradually decrease as the memory storage device 10 is used.

During the operation of the memory storage device 10, the memory management circuit 502 can continuously update the total number of physical units belonging to the idle area 602. The memory management circuit 502 may perform data consolidation according to the number of physical units in the idle area 602 (ie, the total number of idle physical units). For example, the memory management circuit 502 can determine whether the total number of physical units belonging to the idle area 602 is less than or equal to a threshold (also referred to as a first threshold). The first threshold value is, for example, 2 or greater (for example, 10), which is not limited by the present invention. If the total number of physical units belonging to the idle area 602 is less than or equal to the first threshold, the memory management circuit 502 may perform data consolidation. In an exemplary embodiment, the data consolidation operation is also referred to as a garbage collection operation.

In the data consolidation operation, the memory management circuit 502 may select at least one physical unit from the storage area 601 as the source node. The memory management circuit 502 may copy the valid data from the selected physical unit (ie, the source node) to at least one physical unit as the recycling node. The physical unit (that is, the recycling node) used to store the copied valid data is selected from the idle area 602 and will be associated with the storage area 601. If all the valid data stored in a certain physical unit has been copied to the recycling node, the physical unit can be erased and associated with the idle area 602. In an exemplary embodiment, the operation of reassociating a certain physical unit from the storage area 601 back to the idle area 602 (or the operation of erasing a certain physical unit) is also called releasing an idle physical unit. By performing the data consolidation operation, one or more idle physical units are released and the total number of physical units belonging to the idle area 602 is gradually increased.

After the data consolidation operation is started, if the physical unit belonging to the idle area 602 meets a specific condition, the data consolidation operation can be stopped. For example, the memory management circuit 502 can determine whether the total number of physical units belonging to the idle area 602 is greater than or equal to a threshold (hereinafter also referred to as a second threshold). For example, the second threshold value may be greater than or equal to the first threshold value. If the total number of physical units belonging to the idle area 602 is greater than or equal to the second threshold, the memory management circuit 502 may stop data consolidation and operation. It should be noted that stopping the data consolidation operation refers to ending the currently executing data consolidation operation. After stopping a data consolidation operation, if the total number of physical units belonging to the idle area 602 is again less than or equal to the first threshold, the next data consolidation operation can be executed again to release the new idle physical unit.

7 is a schematic diagram of data consolidation operation according to an exemplary embodiment of the present invention.

Referring to FIG. 7, in the data consolidation operation, the memory management circuit 502 may instruct to collect data 700 from the physical units 710(0) to 710(E) as the source node 701 and temporarily store the data 700 in the buffer memory 510. The physical units 710(0) to 710(E) belonging to the source node 701 are selected from the storage area 601 of FIG. 6. The data 700 is valid data. Then, the memory management circuit 502 may instruct to write the data 700 to the physical units 720(0) to 720(F) as the recovery node 702. The physical units 720(0) to 720(F) belonging to the recycling node 702 are selected from the idle area 602 of FIG. 6. In other words, in the data consolidation operation, the data 700 can be copied from the physical units 710(0) to 710(E) as the source node 701 to the physical units 720(0) to 720(F) as the recycling node 702.

In an exemplary embodiment, the memory management circuit 502 may select one or more physical units from the storage area 601 as the source node of valid data according to the logical distance value between the multiple physical units in the storage area 601 of FIG. 6 701. For example, assume that physical unit 610(0) (also known as the first physical unit) maps to one or more logical units (also known as the first logical unit) and physical unit 610(1) (also known as the second physical unit) ) Maps to one or more logical units (also called second logical units). The logical distance value between physical units 610(0) and 610(1) (also called the first logical distance value) can reflect the degree of dispersion between the first logical unit and the second logical unit (also called the first logical unit) Dispersion). For example, the first logical distance value may be positively related to this logical dispersion. For example, the larger the first logical distance value, the higher the logical dispersion between the first logical unit and the second logical unit.

In an exemplary embodiment, the degree of logical dispersion between the first logical unit and the second logical unit is related to the number concentration (or proximity) of the first logical unit and the second logical unit. Assuming that the numbers of the first logical unit and the second logical unit are more concentrated or closer (for example, the numbers of the first logical unit and the second logical unit fall within a certain number range), the first logical unit and the second logical unit can be determined The logical dispersion of the unit is low. Or, assume that the numbers of the first logical unit and the second logical unit are more scattered or less close (for example, the number of the first logical unit falls within a certain number range, and the number of the second logical unit falls within another number range) , It can be determined that the logical dispersion of the first logical unit and the second logical unit is high. In an exemplary embodiment, multiple consecutively numbered logical units have a smaller degree of logical dispersion, and multiple consecutively numbered logical units have a larger degree of logical dispersion.

In an exemplary embodiment, the memory management circuit 502 may preferentially select, as the source node 701, a plurality of physical units having the smallest logical distance value in the storage area 601 of FIG. 6. In an exemplary embodiment, the memory management circuit 502 may preferentially select, as the source node 701, a plurality of physical units having a smaller logical distance value in the storage area 601 of FIG. 6. For example, assume that the logical distance value (ie, the first logical distance value) between the physical unit 610(0) and the physical unit 610(1) is 5, and the physical unit 610(0) and the physical unit 610(A) (also known as If the logical distance value (also referred to as the second logical distance value) between the third physical units is 1, the memory management circuit 502 can compare the first logical distance value with the second logical distance value. According to the comparison result, the memory management circuit 502 may preferentially select the physical unit 610(0) and the physical unit 610(A) as the source node 701. Or, if the logical distance between the physical unit 610(0) and the physical unit 610(1) is 2, and the logical distance between the physical unit 610(0) and the physical unit 610(A) is 3, then remember The volume management circuit 502 may preferentially select the physical unit 610(0) and the physical unit 610(1) as the source node 701.

In an exemplary embodiment, the memory management circuit 502 may preferentially select, as the source node 701, a plurality of physical units in the storage area 601 of FIG. 6 whose logical distance value is less than a target distance value. For example, assuming that the target distance value is 3 and the logical distance value (ie, the first logical distance value) between the physical unit 610(0) and the physical unit 610(1) is 2, the memory management circuit 502 may use the first logic The comparison result of the distance value and the target distance value (that is, the first logical distance value is not greater than the target distance value) preferentially selects the physical unit 610(0) and the physical unit 610(1) as the source node 701. Alternatively, if the first logical distance value (eg, 5) is greater than the target distance value (eg, 3), the memory management circuit 502 may not select the physical unit 610(0) and/or the physical unit 610(1) as the source node 701.

In an exemplary embodiment, the memory management circuit 502 may set the target distance value according to the logical distance value (ie, the second logical distance value) between the physical unit 610(0) and the physical unit 610(A) in FIG. 6. For example, the memory management circuit 502 may directly set the second logical distance value as the target distance value. Alternatively, in an exemplary embodiment, the memory management circuit 502 may set the target distance value according to the logical distance value between all or at least part of the physical units in the storage area 601 in FIG. 6. For example, the target distance value may be an average value of the logical distance values between all or at least part of the physical units in the storage area 601. The memory management circuit 502 may determine whether to select the physical unit 610(0) according to whether the logical distance value (ie, the first logical distance value) between the physical unit 610(0) and the physical unit 610(1) is greater than the target distance value And/or physical unit 610(1) as source node 701.

In an exemplary embodiment, the memory management circuit 502 may also consider other rules to select one or more physical units from the storage area 601 of FIG. 6 as the source node 701. For example, the memory management circuit 502 may select one or more physical units as the source node 701 according to the amount of valid data stored in at least some of the physical units in the storage area 601 and the logical distance between the physical units. For example, in an exemplary embodiment, the memory management circuit 502 may select a plurality of physical units as candidate physical units according to the amount of valid data stored in at least part of the physical units in the storage area 601. Then, the memory management circuit 502 can select one or more physical units as the source node 701 according to the logical distance between the candidate physical units. Alternatively, in an exemplary embodiment, the memory management circuit 502 may select a plurality of physical units as candidate physical units according to the logical distance between at least some physical units in the storage area 601. Then, the memory management circuit 502 can select one or more physical units as the source node 701 according to the amount of valid data stored in the candidate physical units. In this way, the memory management circuit 502 can preferentially select the physical unit having a smaller logical distance value and/or storing less valid data as the source node 701.

In an exemplary embodiment, the logic-to-entity mapping information of the first logic unit is recorded in at least one logic-to-entity mapping table (also referred to as the first logic-to-entity mapping table). For example, the logic-to-entity mapping information of the first logical unit may reflect the mapping relationship between the first logical unit and the physical unit 610(0) of FIG. 6 (ie, the first physical unit). The logic-to-entity mapping information of the second logic unit is also recorded in at least one logic-to-entity mapping table (also called the second logic-to-entity mapping table). For example, the logic-to-entity mapping information of the second logical unit may reflect the mapping relationship between the second logical unit and the physical unit 610(1) of FIG. 6 (ie, the second physical unit). In an exemplary embodiment, the first logical distance value further reflects the degree of overlap between the first logical-to-physical mapping table and the second logical-to-physical mapping table. For example, if the more tables between the first logical-to-physical mapping table and the second logical-to-physical mapping table are duplicates, the greater the degree of overlap between the first logical-to-physical mapping table and the second logical-to-physical mapping table high.

In an exemplary embodiment, the degree of overlap between the first logical-to-physical mapping table and the second logical-to-physical mapping table is negatively related to the logical distance value between the first physical unit and the second physical unit. That is, the higher the degree of overlap between the first logical-to-physical mapping table and the second logical-to-physical mapping table, the smaller the logical distance value between the first physical unit and the second physical unit. The memory management circuit 502 may select one or more physical units as the source node 701 according to the degree of overlap between the first logical-to-physical mapping table and the second logical-to-physical mapping table and perform the data consolidation operation.

FIG. 8 is a schematic diagram of table mapping information according to an exemplary embodiment of the present invention.

Referring to FIG. 8, the table mapping information 801 corresponds to the physical unit 810(0), and the table mapping information 802 corresponds to the physical unit 810(1). The logical to physical mapping table 830 may be stored in the system area 603 of FIG. 6. The logical to physical mapping table 830 includes logical to physical mapping tables TB ₁ ˜TB _M. The logical-to-physical mapping tables TB ₁ ~TB _M are respectively used to record logical-to-physical mapping information of at least one logical unit within a certain number range.

The table mapping information 801 may reflect that the logical-to-physical mapping information of the logical unit mapped by the physical unit 810(0) is stored in at least one of the logical-to-physical mapping tables TB ₁ ˜TB _M. The table mapping information 802 may reflect that the logical-to-physical mapping information of the logical unit mapped by the physical unit 810(1) is stored in at least one of the logical-to-physical mapping tables TB ₁ ˜TB _M. For example, both table mapping information 801 and 802 may have bits b ₁ ~b _M. The value of bit b _i can be 0 or 1 to reflect whether the logical to physical mapping table TB _i is used. The value i is between 1 and M.

In an exemplary embodiment, assuming that the physical unit 810(0) is mapped to the logical units 612(1) and 612(3) of FIG. 6, the values of bits b ₁ and b ₃ in the table mapping information 801 may be 1 (the remaining bits can be 0) to reflect the logical-to-physical mapping information of the logical units 612(1) and 612(3) is recorded in the logical-to-physical mapping tables TB ₁ and TB ₃ . The logical to physical mapping tables TB ₁ and TB ₃ can be loaded into the buffer memory 510 of FIG. 5 to access the physical unit 810(0). In addition, assuming that the physical unit 810(1) is mapped to the logical units 612(1), 612(3), and 612(8) of FIG. 6, the bits b ₁ , b _3, and b ₈ in the table mapping information 802 The value can be 1 (the remaining bits can be 0) to reflect the logical-to-physical mapping information of the logical units 612(1), 612(3), and 612(8) is recorded in the logical-to-physical mapping tables TB ₁ , TB ₃ And TB ₈ . The logical to physical mapping tables TB ₁ , TB ₃ and TB ₈ can be loaded into the buffer memory 510 to access the physical unit 810 (1 ).

In the foregoing exemplary embodiment, the bits b ₁ and b ₃ in the table mapping information 801 and 802 are both 1, indicating multiple logical-to-physical mapping tables used to access the physical units 810(0) and 810(1) The logic to entity mapping tables TB ₁ and TB ₃ are repeated. When accessing the physical unit 810(0), the logical to physical mapping tables TB ₁ and TB ₃ can be loaded into the buffer memory 510 to query related mapping information. Then, if the physical unit 810(1) is accessed, only additional logic needs to be loaded into the physical mapping table TB ₈ .

In an exemplary embodiment of FIG. 7, the memory management circuit 502 may be based on table mapping information corresponding to the first physical unit (also called first table mapping information) and table mapping information corresponding to the second physical unit (also (Referred to as the second table mapping information) to obtain the first logical distance value. According to the first logical distance value, the memory management circuit 502 can select a specific physical unit as the source node 701 to reduce the number of logic-to-physical mapping tables that need to be loaded in the data consolidation operation. For example, by comparing the logical distance value between at least part of the physical units in the storage area 601 of FIG. 6 with the target distance value and selecting the physical unit that meets the condition as the source node 701, the rewriting of FIG. 4 can be effectively reduced Access times of the non-volatile memory module 406, and can extend the service life of the rewritable non-volatile memory module 406.

9A and 9B are schematic diagrams of obtaining logical distance values according to an exemplary embodiment of the invention.

Referring to FIG. 9A, it is assumed that the table mapping information 901 corresponds to the first physical unit and the table mapping information 902 corresponds to the second physical unit. Both table mapping information 901 and 902 have 16 bits. Bits b ₁ to b ₄ in the table mapping information 901 are 1, which reflects the logic to physical mapping tables TB ₁ to TB ₄ can be queried to access the first physical unit. Bits b ₁ to b ₄ and b ₉ in the table mapping information 902 are 1, which reflects the logical to physical mapping tables TB ₁ to TB ₄ and TB ₉ can be queried to access the second physical unit. After performing the first operation on the table mapping information 901 and 902 through the logic module 90, the table difference information 910 can be obtained. For example, the logic module 90 may perform an exclusive OR (XOR) operation on the bit b _j in the table mapping information 901 and 902 to obtain the bit b _j in the table difference information 910. j is between 1 and 16. The table difference information 910 may reflect the degree of dispersion between the first logical unit and the second logical unit (ie, the first logical dispersion). In addition, the table difference information 910 may also reflect the degree of overlap between the first logical-to-physical mapping table and the second logical-to-physical mapping table.

The first logical distance value between the first physical unit and the second physical unit can be obtained according to the table difference information 910. For example, the first logical distance value may be 1 according to the total number of values 1 in the table difference information 910. In this exemplary embodiment, the first logical distance value may reflect that there is only one logical-to-physical mapping table between the first logical-to-physical mapping table and the second logical-to-physical mapping table (that is, the logical-to-physical mapping table TB ₉ ). overlapping.

Please refer to FIG. 9B, assuming that the table mapping information 903 corresponds to the third physical unit. The table mapping information 903 also has 16 bits. Bits b ₄ , b ₆ , b ₉ , b ₁₂ and b ₁₅ in the table mapping information 903 are 1, which reflects the logical to physical mapping tables TB ₄ , TB ₆ , TB ₉ , TB ₁₂ and TB ₁₅ can be queried to Access the third physical unit. In other words, the table mapping information 903 may reflect the logical-to-physical mapping information of one or more logical units (also called third logical units) mapped by the third physical unit is recorded in the logical-to-physical mapping tables TB ₄ , TB ₆ , TB ₉ , TB ₁₂ and TB ₁₅ . After performing the first operation on the table mapping information 901 and 903 through the logic module 90, the table difference information 920 can be obtained. For example, the logic module 90 may perform an XOR operation on the bit b _j in the table mapping information 901 and 903 to obtain the bit b _j in the table difference information 920. j is between 1 and 16. The table difference information 920 may reflect the degree of dispersion between the first logical unit and the third logical unit (also referred to as the second logical dispersion). In addition, the table difference information 920 may also reflect the overlap between the first logical-to-physical mapping table and the logical-to-physical mapping table (also called the third logical-to-physical mapping table) that records the logical-to-physical mapping information of the third logical unit degree.

The second logical distance value between the first physical unit and the third physical unit can be obtained according to the table difference information 920. For example, the second logical distance value is 7 according to the total number of values in the table difference information 920. In this exemplary embodiment, the second logical distance value can reflect that there are 7 logical-to-physical mapping tables between the first logical-to-physical mapping table and the third logical-to-physical mapping table (that is, the logical-to-physical mapping tables TB ₁ ~TB _{3, TB 6, TB 9,} TB 12 and TB ₁₅₎ do not overlap. According to the first logical distance value and the second logical distance value, relative to the first physical unit and the third physical unit, the first physical unit and the second physical unit may be preferentially selected as the source node of the valid data (such as the source of FIG. 7 Node 701). In this way, the number of accesses to the rewritable non-volatile memory module 406 of FIG. 4 during the data consolidation operation can be reduced.

10A and 10B are schematic diagrams of obtaining logical distance values according to an exemplary embodiment of the invention.

Referring to FIG. 10A, in this exemplary embodiment, table mapping information 901 may be replaced by table mapping information 1001, and table mapping information 902 may be replaced by table mapping information 1002. The table mapping information 1001 includes values V ₁₁ ~V ₁₄ . The table mapping information 1002 includes values V ₂₁ ~V ₂₄ . The values V ₁₁ ~V ₁₄ respectively reflect the total number of values 1 in the four ranges 1010~1040 in the table mapping information 901. For example, the values V ₁₁ to V ₁₄ are 4, 0, 0, and 0, respectively. The values V ₂₁ ~V ₂₄ respectively reflect the total number of values 1 in the four ranges 1010~1040 in the table mapping information 902. For example, the values V ₂₁ ~V ₂₄ are 4, 0, 1, 0, respectively.

According to the N-dimensional distance (also referred to as N-dimensional spatial distance) between the table mapping information 1001 and 1002, the first logical distance value between the first physical unit and the second physical unit can be obtained. In this exemplary embodiment, N is 4. For example, the N-dimensional distance LD1 between the table mapping information 1001 and 1002 can be obtained according to the following equation (1). The N-dimensional distance LD1 can be determined as the first logical distance value.

(1.1)

(1.1)

Referring to FIG. 10B, in this exemplary embodiment, the table mapping information 903 may be replaced by the table mapping information 1003. The table mapping information 1003 includes values V ₃₁ ~V ₃₄ . The values V ₃₁ ~V ₃₄ respectively reflect the total number of values 1 in the four ranges 1010~1040 in the table mapping information 903. For example, the values V ₃₁ ~V ₃₄ are 1, 1, 2, and 1, respectively. According to the N-dimensional distance between the table mapping information 1001 and 1003, the second logical distance value between the first physical unit and the third physical unit can be obtained. For example, the N-dimensional distance LD2 between the table mapping information 1001 and 1002 can be obtained according to the following equation (1.2). The N-dimensional distance LD2 can be determined as the second logical distance value.

(1.2)

(1.2)

According to the first logical distance value and the second logical distance value, the first physical unit and the second physical unit can also be preferentially selected as the source node of the valid data (for example, the source node 701 of FIG. 7 ). In this way, the number of accesses to the rewritable non-volatile memory module 406 of FIG. 4 during the data consolidation operation can be reduced.

It should be noted that the exemplary embodiments of FIGS. 9A to 10B are only examples and are not intended to limit the present invention. In another exemplary embodiment, the total number of bits included in the table mapping information may also be more (for example, 32) or less (for example, 8). Other parameters can also be used to select the physical unit that is the source node of valid data in the data consolidation operation, as long as the access to the rewritable non-volatile memory module 406 of FIG. 4 during the data consolidation operation can be reduced Times. In addition, the operation of obtaining the first logical distance value and/or the second logical distance value may be performed before or after determining the first physical unit as the source node in the data consolidation operation, which is not limited by the present invention.

FIG. 11 is a flowchart of a data consolidation method according to an exemplary embodiment of the invention. Referring to FIG. 11, in step S1101, a first logical distance value between the first physical unit and the second physical unit is obtained. In step S1102, a data consolidation operation is performed according to the first logical distance value to copy valid data from the source node to the recycling node.

FIG. 12 is a flowchart of a data consolidation method according to an exemplary embodiment of the invention. Referring to FIG. 12, in step S1201, a first logical distance value between the first physical unit and the second physical unit is obtained. In step S1202, a second logical distance value between the first physical unit and the third physical unit is obtained. In step S1203, it is determined whether the first logical distance value is greater than the second logical distance value. If the first logical distance value is not greater than the second logical distance value, in step S1204, the first physical unit and the second physical unit are selected as the source nodes in the data consolidation operation. However, if the first logical distance value is greater than the second logical distance value, in step S1205, the first physical unit and the third physical unit are selected as the source nodes in the data consolidation operation. Then, valid data can be copied from the source node to the recovery node in the data consolidation operation. It should be noted that in an exemplary embodiment, step S1202 may be executed first and then step S1201 or steps S1201 and 1202 may be executed at the same time, which is not limited in the present invention.

13 is a flowchart of a data consolidation method according to an exemplary embodiment of the invention. Referring to FIG. 13, in step S1301, the first physical unit is selected as the source node in the data consolidation operation. After step S1301, valid data (also called first data) can be copied from the first physical unit to the recycling node. In step S1302, a first logical distance value between the first physical unit and the second physical unit is obtained. In step S1303, a second logical distance value between the first physical unit and the third physical unit is obtained. In step S1304, it is determined whether the first logical distance value is greater than the second logical distance value. If the first logical distance value is not greater than the second logical distance value, in step S1305, the second physical unit is selected as the source node in the data consolidation operation. After step S1305, valid data (also called second data) can be copied from the second physical unit to the recycling node. However, if the first logical distance value is greater than the second logical distance value, in step S1306, the third physical unit is selected as the source node in the data consolidation operation. After step S1306, valid data (also called third data) may be copied from the third physical unit to the recycling node. It should be noted that in an exemplary embodiment, step S1303 may be executed before step S1302 or steps S1302 and 1303 may be executed at the same time, which is not limited in the present invention.

However, the steps in FIGS. 11 to 13 have been described in detail as above, and will not be repeated here. It should be noted that the steps in FIGS. 11 to 13 can be implemented as multiple codes or circuits, and the invention is not limited thereto. In addition, the methods of FIG. 11 to FIG. 13 can be used with the above exemplary embodiments or can be used alone, and the present invention is not limited.

In summary, by considering the logical dispersion between the first logical unit mapped by the first physical unit and the second logical unit mapped by the second physical unit, the memory storage device is accessed during the data consolidation process The number of times can be effectively reduced, thereby extending the service life of the memory storage device.

Although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the appended patent application.

10.30: Memory storage device 11, 31: Host system 110: System bus 111: Processor 112: Random access memory 113: Read only memory 114: Data transmission interface 12: Input/output (I/O ) Device 20: motherboard 201: flash drive 202: memory card 203: solid state drive 204: wireless memory storage device 205: global positioning system module 206: network interface card 207: wireless transmission device 208: keyboard 209: screen 210: speaker 32: SD card 33: CF card 34: embedded storage device 341: embedded multimedia card 342: embedded multi-chip package storage device 402: connection interface unit 404: memory control circuit unit 406: rewritable non-volatile Volatile memory module 502: memory management circuit 504: host interface 506: memory interface 508: error checking and correction circuit 510: buffer memory 512: power management circuit 601: storage area 602: replacement area 603: storage area 610(0)~610(C), 710(0)~710(E), 720(0)~720(F), 810(0), 810(1): physical unit 612(0)~612(D ): logic unit 700: data 701: source node 702: recycling node 801, 802, 901~903, 1001~1003: table mapping information 830: logic to physical mapping tables 910, 920: table difference information 90: logic module 1010 ~1040: Range S1101: Step (obtaining the first logical distance value between the first physical unit and the second physical unit) S1102: Step (perform data consolidation according to the first logical distance value to remove valid data from the source node Copy to recycle node) S1201: Step (obtain the first logical distance value between the first physical unit and the second physical unit) S1202: Step (obtain the second logical distance value between the first physical unit and the third physical unit S1203: Step (whether the first logical distance value is greater than the second logical distance value) S1204: Step (select the first physical unit and the second physical unit as the source node) S1205: Step (select the first physical unit and the third physical unit As source node) S1301: Step (select the first physical unit as the source node) S1302: Step (, obtain the first logical distance value between the first physical unit and the second physical unit) S1303: Step (obtain the first physical unit S1304: Step (whether the first logical distance value is greater than the second logical distance value) S1305: Step (select the second physical unit as the source node) S1306: Step (select the (Three physical units as source nodes)

FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an exemplary embodiment of the present invention. 2 is a schematic diagram of a host system, a memory storage device, and an I/O device according to another exemplary embodiment of the present invention. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the present invention. FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the invention. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the invention. 6 is a schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the present invention. 7 is a schematic diagram of data consolidation operation according to an exemplary embodiment of the present invention. FIG. 8 is a schematic diagram of table mapping information according to an exemplary embodiment of the present invention. 9A and 9B are schematic diagrams of obtaining logical distance values according to an exemplary embodiment of the invention. 10A and 10B are schematic diagrams of obtaining logical distance values according to an exemplary embodiment of the invention. FIG. 11 is a flowchart of a data consolidation method according to an exemplary embodiment of the invention. FIG. 12 is a flowchart of a data consolidation method according to an exemplary embodiment of the invention. 13 is a flowchart of a data consolidation method according to an exemplary embodiment of the invention.

S1101: Step (obtain the first logical distance value between the first physical unit and the second physical unit)

S1102: Step (perform data consolidation according to the first logical distance value to copy valid data from the source node to the recycling node)

Claims (21)

A data consolidation method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes multiple physical units, and the data consolidation method includes: obtaining the physical units A first logical distance between a first physical unit and a second physical unit, wherein the first logical distance value reflects at least a first logical unit and the second entity mapped by the first physical unit A logical dispersion between at least one second logical unit mapped by the unit; and performing a data consolidation operation according to the first logical distance value to copy a valid data from a source node in the physical units to A recycling node in the physical units. The data consolidation method as described in item 1 of the patent application scope, wherein the logic-to-physical mapping information of the at least one first logical unit is recorded in at least one first-to-physical mapping table, and the at least one second logical unit A logical to physical mapping information is recorded in at least one second logical to physical mapping table, and the first logical distance value further reflects between the at least one first logical to physical mapping table and the at least one second logical to physical mapping table The degree of overlap. The data consolidation method as described in item 1 of the patent application scope, wherein the step of performing the data consolidation operation according to the first logical distance value includes: If the first logical distance value is not greater than a target distance value, the Valid data in a physical unit is copied to the recycling node and valid data in the second physical unit is copied to the recycling node; and if the logical distance value is greater than the target distance value, the The valid data is copied to the recycling node and the valid data in a third physical unit among the physical units is copied to the recycling node. The data consolidation method as described in item 3 of the patent application scope further includes: obtaining a second logical distance value between the first physical unit and the third physical unit, wherein the target distance value includes the second logic Distance value. The data consolidation method as described in item 1 of the patent application scope, wherein the step of obtaining the first logical distance value between the first physical unit and the second physical unit among the physical units includes: according to a first A table mapping information and a second table mapping information obtain the first logical distance value, wherein the first table mapping information reflects a logical-to-physical mapping information of the at least one first logical unit recorded in at least a first logical-to-entity A mapping table, and the second table mapping information reflects a logical-to-physical mapping information of the at least one second logical unit recorded in at least a second logical-to-physical mapping table. The data consolidation method as described in item 5 of the patent application scope, wherein the first table mapping information includes a first bit, the second table mapping information includes a second bit, and the information is mapped according to the first table The step of obtaining the first logical distance value by mapping information with the second table includes: performing a first operation on the first bit and the second bit to obtain a third bit; and according to the third bit The first logical distance value is obtained. The data consolidation method as described in item 5 of the patent application scope, wherein the first table mapping information includes N first values, the second table mapping information includes N second values, and the information is mapped according to the first table The step of obtaining the first logical distance value by mapping information with the second table includes: obtaining an N-dimensional distance between the N first values and the N second values; and obtaining the first logical distance according to the N-dimensional distance Logical distance value. A memory storage device includes: a connection interface unit for coupling to a host system; a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes multiple entities Unit; and a memory control circuit unit coupled to the connection interface unit and the rewritable non-volatile memory module, wherein the memory control circuit unit is used to obtain a first entity among the physical units A first logical distance value between the unit and a second physical unit, wherein the first logical distance value reflects at least one of the at least one first logical unit mapped by the first physical unit and the at least one mapped by the second physical unit A logical degree of dispersion between the second logical units, and the memory control circuit unit is further used to perform a data consolidation operation based on the first logical distance value to extract a valid data from a source in the physical units The node is copied to a recycling node in the physical units. The memory storage device as described in item 8 of the patent application range, wherein the logic-to-physical mapping information of the at least one first logical unit is recorded in at least one first-to-physical mapping table, and the at least one second logical unit A logical to physical mapping information is recorded in at least one second logical to physical mapping table, and the first logical distance value further reflects between the at least one first logical to physical mapping table and the at least one second logical to physical mapping table The degree of overlap. The memory storage device as recited in item 8 of the patent application range, wherein the memory control circuit unit performs the data consolidation operation according to the first logical distance value including: if the first logical distance value is not greater than a target The distance value indicates that the valid data in the first physical unit is copied to the recycling node and the valid data in the second physical unit is copied to the recycling node; and if the logical distance value is greater than the target distance value, indicating that The valid data in the first physical unit is copied to the recycling node and the valid data in a third physical unit among the physical units is copied to the recycling node. The memory storage device of claim 10, wherein the memory control circuit unit is further used to obtain a second logical distance value between the first physical unit and the third physical unit, and the target The distance value includes the second logical distance value. The memory storage device as recited in item 8 of the patent application range, wherein the memory control circuit unit obtains the value of the first logical distance between the first physical unit and the second physical unit of the physical units The operation includes: obtaining the first logical distance value according to a first table mapping information and a second table mapping information, wherein the first table mapping information reflects a logical-to-physical mapping information of the at least one first logical unit recorded in at least A first logical-to-physical mapping table, and the second table mapping information reflects a logical-to-physical mapping information of the at least one second logical unit recorded in at least one second logical-to-physical mapping table. The memory storage device according to item 12 of the patent application scope, wherein the first table mapping information includes a first bit, the second table mapping information includes a second bit, and the memory control circuit unit is based on The operations of obtaining the first logical distance value by the first table mapping information and the second table mapping information include: performing a first operation on the first bit and the second bit to obtain a third bit; and The first logical distance value is obtained according to the third bit. The memory storage device according to item 12 of the patent application, wherein the first table mapping information includes N first values, the second table mapping information includes N second values, and the memory control circuit unit is based on The operations of obtaining the first logical distance value by the first table mapping information and the second table mapping information include: obtaining an N-dimensional distance between the N first values and the N second values; and according to the N The dimension distance obtains the first logical distance value. A memory control circuit unit for controlling a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes a plurality of physical units, wherein the memory control circuit unit includes: a A host interface for coupling to a host system; a memory interface for coupling to the rewritable non-volatile memory module; and a memory management circuit for coupling to the host interface and the memory A body interface, wherein the memory management circuit is used to obtain a first logical distance value between a first physical unit and a second physical unit among the physical units, wherein the first logical distance value reflects the first A logical degree of dispersion between at least one first logical unit mapped by the physical unit and at least one second logical unit mapped by the second physical unit, and the memory management circuit is further used to determine the first logical distance value Perform a data consolidation operation to copy a valid data from a source node in the physical units to a recycling node in the physical units. The memory control circuit unit according to item 15 of the patent application scope, wherein the logic-to-physical mapping information of the at least one first logic unit is recorded in at least one first-to-physical mapping table, and the at least one second logic unit A logical-to-physical mapping information is recorded in at least one second logical-to-physical mapping table, and the first logical distance value further reflects the at least one first logical-to-physical mapping table and the at least one second logical-to-physical mapping table. Degree of overlap. The memory control circuit unit according to item 15 of the patent application scope, wherein the memory management circuit performs the data consolidation operation according to the first logical distance value includes: if the first logical distance value is not greater than a target The distance value indicates that the valid data in the first physical unit is copied to the recycling node and the valid data in the second physical unit is copied to the recycling node; and if the logical distance value is greater than the target distance value, indicating that The valid data in the first physical unit is copied to the recycling node and the valid data in a third physical unit among the physical units is copied to the recycling node. The memory control circuit unit as described in item 17 of the patent application range, wherein the memory management circuit is further used to obtain a second logical distance value between the first physical unit and the third physical unit, and the target The distance value includes the second logical distance value. The memory control circuit unit as described in item 15 of the patent application range, wherein the memory management circuit obtains the value of the first logical distance between the first physical unit and the second physical unit among the physical units The operation includes: obtaining the first logical distance value according to a first table mapping information and a second table mapping information, wherein the first table mapping information reflects a logical-to-physical mapping information of the at least one first logical unit recorded in at least A first logical-to-physical mapping table, and the second table mapping information reflects a logical-to-physical mapping information of the at least one second logical unit recorded in at least one second logical-to-physical mapping table. The memory control circuit unit of claim 19, wherein the first table mapping information includes a first bit, the second table mapping information includes a second bit, and the memory management circuit is based on The operations of obtaining the first logical distance value by the first table mapping information and the second table mapping information include: performing a first operation on the first bit and the second bit to obtain a third bit; and The first logical distance value is obtained according to the third bit. The memory control circuit unit of claim 19, wherein the first table mapping information includes N first values, the second table mapping information includes N second values, and the memory management circuit is based on The operations of obtaining the first logical distance value by the first table mapping information and the second table mapping information include: obtaining an N-dimensional distance between the N first values and the N second values; and according to the N The dimension distance obtains the first logical distance value.

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