TW202013509A - 鰭式結構 - Google Patents

鰭式結構 Download PDF

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TW202013509A
TW202013509A TW108123790A TW108123790A TW202013509A TW 202013509 A TW202013509 A TW 202013509A TW 108123790 A TW108123790 A TW 108123790A TW 108123790 A TW108123790 A TW 108123790A TW 202013509 A TW202013509 A TW 202013509A
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艾莫迪 福奧Ｈ 艾爾
徐移恒
瑞西克奇 克里斯南
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美商格芯（美國）集成電路科技有限公司
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Abstract

本發明關於半導體結構，特別是關於鰭式結構及製造方法。結構包含：由基板材料形成的複數個鰭式結構；位於複數個鰭式結構中的選定鰭式結構之間的半導體材料；以及在複數個鰭式結構之間的間隔內的隔離區域。

Description

鰭式結構
本發明關於半導體結構，且更特別地，關於鰭式結構和製造方法。
FinFET技術包含由基板材料所組成的鰭片。然而，在FinFET技術中，鰭片彎曲一直是個問題。鰭片彎曲的一部分是由於淺溝槽隔離區域的固化過程中產生的力所引起的，這導致材料的收縮並將鰭片向外拉。隨著每個縮小技術節點的出現，鰭片彎曲的影響變得更糟，並影響了裝置性能。舉例來說，由於鰭片的彎曲，裝置可能具有不同的Vt偏移或其他裝置變化。
在本發明一態樣中，一種結構，包含：複數個鰭式結構，其由基板材料所形成；一半導體材料，其位於該複數個鰭式結構中的多個選定鰭式結構之間；以及多個隔離區域，其在該複數個鰭式結構之間的多個間隔內。
在本發明一態樣中，一種方法，包含：形成複數個鰭式結構；在該複數個鰭式結構上形成一絕緣體襯層；在該複數個鰭式結構上方和之間沉積共形的厚的一半導體材料；蝕刻該半導體材料至一預定厚度； 在蝕刻的該半導體材料上沉積絕緣體材料；退火該絕緣體材料；以及使該絕緣體材料凹陷。
在本發明一態樣中，一種方法，包含：藉由在基板材料中蝕刻多個第一溝槽和多個第二溝槽蝕刻至一第一深度來從該基板材料形成複數個鰭式結構，其中該等第二溝槽的每一者的一寬度大於該等第一溝槽的任一者的一寬度；在該基板材料上和該複數個鰭式結構上形成一共形介電層；沉積共形半導體材料以填充該等第一溝槽並加襯該等第二溝槽；以及在該等第一溝槽和該等第二溝槽內形成多個鰭式隔離區域。
10‧‧‧結構
12‧‧‧基板
14‧‧‧鰭式結構
15‧‧‧溝槽
16‧‧‧介電襯層
18‧‧‧半導體材料
18’‧‧‧半導體材料
18”‧‧‧半導體材料
20‧‧‧隔離材料
22‧‧‧淺溝槽隔離區域
x‧‧‧間隔
x’‧‧‧間隔
利用本發明示範具體實施例的非限制範例，參考提及的許多圖式，從下列詳細描述當中描述本發明。
圖1顯示了根據本發明各態樣的複數個鰭式結構和相應的製造程序。
圖2顯示了根據本發明各態樣的沉積在複數個鰭式結構上的介電襯層和相應的製造程序。
圖3顯示了根據本發明各態樣的在介電襯層上的半導體材料層和相應的製造程序。
圖4顯示了根據本發明各態樣的半導體材料的蝕刻和相應的製造程序。
圖5除了其他特徵外還顯示了根據本發明各態樣的在複數個鰭式結構之間的隔離材料和相應的製造程序。
圖6除了其他特徵外還顯示了根據本發明各態樣的在複數個鰭式結構之間凹陷的淺溝槽隔離區域和相應的製造程序。
圖7顯示了使用透射電子顯微鏡(TEM)的鰭式結構的橫截面視圖。
本發明關於半導體結構，且更特別地，關於鰭式結構和製造方法。更具體地，本發明關於具有減低的彎曲或沒有彎曲的鰭片的FinFET技術。有利地，藉由實施本文所述的程序，現在將有可能降低鰭片彎曲，進而改善裝置性能。本文所述的程序將減少裝置的變化，並易於與當前的記錄製程整合。
在具體實施例中，減少鰭片彎曲的方法包含使用絕緣體材料(例如，氧化物)的襯層形成複數個鰭式結構。方法更包含在鰭式結構上沉積一共形半導體材料。在具體實施例中，半導體材料可為Si材料。使用非共形蝕刻製程將半導體材料蝕刻至期望的厚度，以在選定的相鄰鰭式結構之間保持一定的期望厚度。為了形成STI區域，將絕緣體材料沉積在半導體材料上方以及複數個鰭式結構之間，接著進行固化和退火製程。接著，使絕緣體材料凹陷，以形成STI區域。
在替代具體實施例中，減少鰭片彎曲的方法包含：藉由在基板中蝕刻第一和第二溝槽至第一深度來形成鰭片，其中每個第二溝槽的寬度大於任何一個第一溝槽的寬度；在基板上形成一共形介電層；在基板上沉積一共形半導體層以填充第一溝槽而不填充第二溝槽；以及藉由沉積、退火和凹陷介電材料形成鰭式隔離。
可使用多種不同的工具、以多種方式來製造本發明的鰭式結構和相關特徵。然而，一般而言，方法和工具係用以形成尺寸在微米及奈米尺度的結構。用以製造本發明的鰭式結構和相關特徵的方法(即技術)係採用自積體電路(IC)技術。舉例來說，結構建立於晶圓上並在晶圓頂部上實現於藉由微影製程而圖案化的材料薄膜中。特別地，鰭式結構和相關特徵的製造使用三個基本的構建塊：(i)在基板上沉積材料的薄膜，(ii)藉由光學微影成像在薄膜頂部施加圖案化光罩，以及(iii)對光罩選擇性地蝕刻薄 膜。
圖1顯示了根據本發明各態樣的複數個鰭式結構和相應的製造程序。更具體地，圖1的結構10包含基板12。在具體實施例中，基板12可由任何合適的材料構成，其包含但不限於Si、SiGe、SiGeC、SiC、GaAs、InAs、InP以及其他III/V或II/VI化合物半導體。在具體實施例中，基板12可為塊狀基板或絕緣層上半導體(SOI)技術。
使用傳統的微影和蝕刻製程(例如反應性離子蝕刻)從基板12形成複數個鰭片14。在具體實施例中，複數個鰭片14可為梯形；然而此處也可考慮其他形狀，例如矩形。舉例來說，在製造過程中，將形成在基板12上的抗蝕劑暴露於能量(光)以形成圖案(開口)。具有選擇性化學作用的蝕刻製程(例如反應性離子蝕刻(RIE))將用以通過抗蝕劑的開口在基板12中形成一或多個溝槽15。接著，可藉由傳統的氧灰化製程或其他已知的剝除技術來移除抗蝕劑。
在這些製程中，溝槽15形成於基板12中至一預定深度(例如150nm)，其中每一溝槽15包含間隔「x」、「x’」。在具體實施例中，間隔「x’」的寬度大於間隔「x」。在具體實施例中，相鄰鰭式結構14之間的間隔「x’」允許進行材料的共形蝕刻製程，其將對複數個溝槽15的側壁進行加襯，例如，對溝槽15和鰭式結構14加襯；然而，相鄰溝槽之間的間隔「x」將僅允許填充溝槽15的材料的非共形蝕刻製程。在更特定的具體實施例中，間隔「x」可為約15nm；而間隔「x’」大於15nm。
在替代具體實施例中，可使用側壁影像轉移(SIT)技術來製造複數個鰭式結構14。舉例來說，在SIT技術中，使用傳統的沉積、微影、和蝕刻製程在基板12上形成心軸。舉例來說，在SIT技術的示例中，使用傳統的CVD製程將例如SiO2的心軸材料沉積在基板12上。抗蝕劑形成在心軸材料上，並暴露於光以形成圖案(開口)。通過開口執行反應性離子蝕刻，以形成心軸。在具體實施例中，根據鰭式結構14之間的期望尺寸，心軸可具 有不同的寬度及/或間隔。間隙壁形成在心軸的側壁上，其較佳為與心軸不同的材料，且其使用所屬技術領域中具有通常知識者已知的傳統沉積方法形成。舉例來說，間隙壁可具有與鰭式結構14的尺寸匹配的寬度。使用對心軸材料有選擇性的傳統蝕刻製程來移除或剝除心軸。接著，在間隙壁的間隔內執行蝕刻以形成次微影特徵。接著，可剝除側壁間隙壁。在具體實施例中，如本發明所設想的，鰭式結構14也可在此或其他圖案化製程期間形成、或是通過其他傳統的圖案化製程形成。
圖2顯示了沉積在複數個鰭式結構14上的介電襯層16。在具體實施例中，介電襯層16是使用傳統成長製程在複數個鰭式結構14上成長的氧化物材料的共形層。舉例來說，可使用原位蒸汽產生製程來成長介電襯層16。在具體實施例中，介電襯層16可具有約10Å到約20Å的厚度；然而此處也考慮了其他尺寸。舉例來說，介電襯層16的厚度小於複數個相鄰鰭式結構14之間的間隔「x」。所屬技術領域中具有通常知識者還應該理解，氧化物材料通常不用於晶種層。
圖3顯示了根據本發明各態樣的在介電襯層16上的半導體材料層18和相應的製造程序。在具體實施例中，半導體材料18可為Si材料。在替代具體實施例中，半導體材料18為可在隨後的製造程序(例如氧化物材料的退火製程)期間消耗的任何材料。舉例來說，半導體材料18可為與基板12相同的任何材料。
仍然參考圖3，在介電襯層16上(例如在複數個鰭式結構14上方及其之間)共形地沉積半導體材料18至一期望厚度。舉例來說，在具體實施例中，可藉由化學氣相沉積(CVD)或其他傳統沉積製程，在複數個鰭式結構14上方和之間沉積半導體材料18至約25Å或更大的厚度；然而此處也考慮了其他尺寸。作為更特定的示例，半導體材料18實質地或完全地填充較小的間隔「x」，並對具有較大間隔「x’」的溝槽15進行加襯，例如不填充間隔「x’」。在更特定的具體實施例中，可將半導體材料18沉積至任何厚度， 該厚度將允許在相鄰鰭式結構14之間的較小間隔「x」內進行非共形的蝕刻製程(例如，將不允許在後續的退火製程期間完全消耗半導體材料18的一厚度)；同時允許在較大的間隔「x’」中進行半導體材料18的共形蝕刻(例如，減小半導體材料18的厚度，使其可在隨後的退火製程期間消耗)。
如圖4所示，蝕刻半導體材料18，以減小其在某些區域中的厚度，例如在相鄰鰭式結構14之間的較大間隔「x’」內。特別地，在具有較大間隔「x’」的溝槽15內共形地蝕刻半導體材料，並在具有較小間隔「x」的溝槽15內非共形地蝕刻半導體材料。以此方式，較大間隔「x’」內的半導體材料18’的厚度將比較小間隔「x」內的半導體材料18”的厚度減小得更多。舉例來說，較大間隔「x’」內的半導體材料18’的厚度可為約20Å到25Å或更小，這將允許在隨後的退火(例如，濕式及乾式)製程期間消耗半導體材料18’；而半導體材料18”的厚度將不允許在隨後的退火製程期間消耗。在一非限制性的說明性示例中，具有間隔「x」的溝槽15內的半導體材料18”的高度可為鰭式結構14的高度的大約30%-40%。
圖5除了其他特徵外還顯示了沉積在複數個鰭式結構14之間的隔離材料20。在具體實施例中，隔離材料20為絕緣體材料，例如氧化物。在更特定的具體實施例中，隔離材料20為可流動的氧化物材料。隔離材料20經歷本技術領域中具有通常知識者已知的固化製程，接著進行化學機械拋光(CMP)製程和退火製程(由圖5中的箭頭表示)。在固化製程期間，由於在複數個鰭式結構14的側面上的較小間隔「x」內的半導體材料18”的厚度，複數個鰭式結構14將不會彎曲(例如，保持垂直筆直)。此外，在退火製程期間，半導體材料18’將被隔離材料20(例如，氧化物)消耗。更具體地，當在氧氣存在下對Si薄膜(例如約20Å到25Å或更小)進行退火時，Si將被消耗，從而形成SiO2層。
在圖6中，使氧化物層20凹陷以在複數個鰭式結構14之間形成淺溝槽隔離區域22。在具體實施例中，可藉由選擇性蝕刻製程(例如RIE) 來使氧化物層20凹陷。氧化物層20應在具有間隔「x」的溝槽15中的Si材料18”之上。
圖7顯示了使用透射電子顯微鏡(TEM)的鰭式結構的橫截面視圖。如圖6所示，使氧化物層凹陷，以在複數個鰭式結構14之間形成淺溝槽隔離區域22。在具體實施例中，可藉由選擇性蝕刻製程(例如RIE)來使氧化物層凹陷。氧化物層20應在具有間隔「x」的溝槽15中的Si材料18”之上。
上述該(等)方法用於積體電路晶片的製造。結果積體電路晶片可由製造廠以原始晶圓形式(也就是具有多個未封裝晶片的單一晶圓)、當成裸晶粒或已封裝形式來散佈。在後者案例中，晶片固定在單晶片封裝內(像是塑膠載體，具有黏貼至主機板或其他更高層載體的導線)或固定在多晶片封裝內(像是一或兩表面都具有表面互連或內嵌互連的陶瓷載體)。然後在任何案例中，晶片與其他晶片、離散電路元件及/或其他信號處理裝置整合成為以下任一者的一部分：(a)中間產品，像是主機板，或(b)最終產品。該最終產品可為包含積體電路晶片的任何產品，範圍從玩具與其他低階應用到具有顯示器、鍵盤或其它輸入裝置以及中央處理器的進階電腦產品。
本發明許多具體實施例的描述已經為了例示而呈現，但不欲為窮盡性或將本發明限制在所揭示之具體實施例中。在不脫離所描述具體實施例之範疇與精神的前提下，所屬技術領域中具有通常知識者將瞭解許多修正例以及變化例。本文內使用的術語係經選擇，以最佳解釋具體實施例的原理、市場上所發現技術的實際應用或技術改進，或可讓其他所屬技術領域中具有通常知識者能理解本文所揭示的具體實施例。
12‧‧‧基板
14‧‧‧鰭式結構
16‧‧‧介電襯層
18”‧‧‧半導體材料
22‧‧‧淺溝槽隔離區域
x‧‧‧間隔
x’‧‧‧間隔

Claims (20)

  1. 一種結構，包含：
    複數個鰭式結構，其由基板材料所形成；
    一半導體材料，其位於該複數個鰭式結構中的多個選定鰭式結構之間；以及
    多個隔離區域，其在該複數個鰭式結構之間的多個間隔內。
  2. 如申請專利範圍第1項所述的結構，更包含覆蓋該複數個鰭式結構的一絕緣體襯層。
  3. 如申請專利範圍第2項所述的結構，其中該絕緣體襯層為氧化物。
  4. 如申請專利範圍第1項所述的結構，其中該半導體材料在該複數個鰭式結構之間的多個選定間隔內未消耗。
  5. 如申請專利範圍第4項所述的結構，其中該複數個鰭式結構的該等選定鰭式結構之間的該等選定間隔的每一者的一寬度「x」小於該複數個鰭式結構的多個其餘鰭式結構之間的多個間隔。
  6. 如申請專利範圍第5項所述的結構，其中該等隔離區域為多個淺溝槽隔離區域，其在該複數個鰭式結構中的該等選定鰭結構之間的該半導體材料之上。
  7. 如申請專利範圍第6項所述的結構，其中該半導體材料的一高度低於該複數個鰭式結構的一高度。
  8. 如申請專利範圍第5項所述的結構，其中該複數個鰭式結構中的該等其餘選定鰭式結構之間的該等間隔沒有該半導體材料。
  9. 如申請專利範圍第5項所述的結構，其中該半導體材料係定位以防止該複數個鰭式結構彎曲。
  10. 如申請專利範圍第1項所述的結構，其中該半導體材料為矽。
  11. 一種方法，包含：
    形成複數個鰭式結構；
    在該複數個鰭式結構上形成一絕緣體襯層；
    在該複數個鰭式結構上方和之間沉積共形的厚的一半導體材料；
    蝕刻該半導體材料至一預定厚度；
    在蝕刻的該半導體材料上沉積絕緣體材料；
    退火該絕緣體材料；以及
    使該絕緣體材料凹陷。
  12. 如申請專利範圍第11項所述的方法，其中蝕刻該半導體材料的步驟為在該複數個鰭式結構中的多個相鄰鰭式結構之間的多個較小間隔內的一非共形蝕刻製程，且為在該複數個鰭式結構中的多個其餘相鄰鰭式結構之間的多個較大間隔內的一共形蝕刻製程。
  13. 如申請專利範圍第12項所述的方法，其中經歷該非共形蝕刻製程的該半導體材料在退火該絕緣體材料的期間將不會被消耗。
  14. 如申請專利範圍第13項所述的方法，其中經歷該共形蝕刻製程的該半導體材料在退火該絕緣體材料的期間將被消耗。
  15. 如申請專利範圍第14項所述的方法，其中經歷該非共形蝕刻製程的該半導體材料比經歷該共形蝕刻製程的該半導體材料設置在多個相鄰鰭式結構之間的更小的間隔中。
  16. 如申請專利範圍第15項所述的方法，其中經歷該非共形蝕刻製程的該半導體材料防止了該複數個鰭式結構在該絕緣體材料的一固化期間的彎曲。
  17. 如申請專利範圍第15項所述的方法，更包含使該絕緣體材料凹陷至在該複數個鰭式結構之下以及在該半導體材料之上的一高度。
  18. 一種方法，包含：
    藉由在基板材料中蝕刻多個第一溝槽和多個第二溝槽蝕刻至一第一深度來從該基板材料形成複數個鰭式結構，其中該等第二溝槽的每一者的一寬度大於該等第一溝槽的任一者的一寬度；
    在該基板材料上和該複數個鰭式結構上形成一共形介電層；
    以共形半導體材料填充該等第一溝槽並加襯該等第二溝槽；以及
    在該等第一溝槽和該等第二溝槽內形成多個鰭式隔離區域。
  19. 如申請專利範圍第18項所述的方法，其中該半導體材料沒有填充該等第二溝槽。
  20. 如申請專利範圍第19項所述的方法，其中該等鰭式隔離區域的形成包含在該等第一溝槽和該等第二溝槽內沉積、退火和凹陷介電材料。
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US10790198B2 (en) 2020-09-29
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