TW202011097A - Display panel - Google Patents

Abstract

A display panel includes a first thin film transistor (TFT), a pixel electrode, a display dielectric layer, a light-blocking layer, a color filter, and at least one photodetector (PD). The pixel electrode is electrically connected to the first TFT. The display dielectric layer is disposed on the pixel electrode. The light-blocking layer is disposed on the display dielectric layer and has at least one first opening pattern and at least one second opening pattern. The color filter is disposed on the display dielectric layer, in which a vertical projection of the color filter onto the display dielectric layer overlaps with a vertical projection of the first opening pattern of the light-blocking layer onto the display dielectric layer. The PD is disposed on the display dielectric layer, in which a vertical projection of the PD onto the display dielectric layer overlaps with a vertical projection of the second opening pattern of the light-blocking layer onto the display dielectric layer.

Description

Display panel

The invention relates to a display panel.

With the development of technology, various portable electronic devices have gradually become mainstream products in the consumer market, such as smart phones, smart watches, tablets or notebook computers. The functionality of these portable electronic devices has gradually become more and more abundant with market trends, such as user privacy information, photos, and mobile payment authorization can be recorded in it. Therefore, such portable electronic devices are also equipped with identity authentication to ensure the privacy of users.

In this regard, due to the unique characteristics of fingerprints, fingerprints have been applied to identity authentication, so that portable electronic devices equipped with fingerprint authentication have also been developed. However, fingerprint authentication requires an additional sensor, which also leads to the issue of how to integrate the sensor with the original electronic device.

An embodiment of the present invention provides a display panel including a first thin film transistor, a pixel electrode, a display medium layer, a light-shielding layer, a color filter layer, and a light sensor. The pixel electrode is electrically connected to the first thin film transistor. The display medium layer is provided on the pixel electrode. The light shielding layer is provided on the display medium layer, and includes a first opening pattern and a second opening pattern. The color filter layer is disposed on the display medium layer, wherein the vertical projection of the color filter layer on the display medium layer overlaps with the vertical projection of the first opening pattern of the light shielding layer on the display medium layer. The photo sensor is disposed above the display medium layer, wherein the vertical projection of the photo sensor on the display medium layer partially overlaps with the vertical projection of the second opening pattern of the light shielding layer on the display medium layer.

In some embodiments, the display panel further includes a second thin film transistor. The second thin film transistor is electrically connected to the light sensor, wherein the light shielding layer is located between the display medium layer and the second thin film transistor.

In some embodiments, the photo sensor includes a metal electrode layer, and the vertical projection of the metal electrode layer on the display medium layer partially overlaps with the vertical projection of the first thin film transistor on the display medium layer.

In some embodiments, the light sensor further includes a light sensing layer, the light sensing layer has a lower surface and a side surface, the lower surface faces the array substrate and connects the side surface, and the lower surface and the side surface are covered by a metal electrode layer .

In some embodiments, the display panel further includes an insulating layer. The insulating layer is disposed on the light shielding layer and extends through the second opening pattern toward the display medium layer to form a recessed portion, wherein the photo sensor is located in the recessed portion and is separated from the light shielding layer through the insulating layer.

In some embodiments, the vertical projection of the light sensor on the display medium layer overlaps with the vertical projection of the light shielding layer on the display medium layer.

In some embodiments, the photo sensors are respectively located in the pixel area of the display panel, and the display panel further includes a circuit layer between the first thin film transistor and the pixel electrode, wherein the photo sensor and the light shielding layer Multiple overlapping areas are formed, and these overlapping areas are equal to each other.

An embodiment of the present invention provides a display panel including a thin film transistor, a circuit layer, a light emitting layer, and a light sensor. The thin film transistor is electrically connected to the circuit layer. The light-emitting layer is arranged on the circuit layer and electrically connected to the circuit layer. The light sensor is arranged on the circuit layer, wherein the display panel has a pixel area, the light sensors are respectively located in the pixel area, and form a plurality of overlapping areas with the circuit layer, and the plurality of overlapping areas are equal to each other.

In some embodiments, in each pixel area, the number of light-emitting elements is three and is used to provide colored light of different wavelengths, the number of light sensors is one, and the light sensors are located in three The same side of the light emitting element.

In some embodiments, the thin film transistor, the circuit layer, the pixel definition layer, and the light emitting element are formed on the first substrate, the light sensor is formed on the second substrate, the thin film transistor, the circuit layer, the pixel definition layer, The light emitting element and the light sensor are located between the first substrate and the second substrate, and the display panel further includes a dielectric layer disposed between the pixel definition layer and the light sensor.

Through the above configuration, in addition to integrating the photo sensor into the display panel to provide the function of recognizing the fingerprint pattern, since each pixel area of the display panel can provide the function of recognizing the fingerprint, the display panel can be improved The screen ratio, and also makes the display panel suitable for designing a full-screen display device.

10‧‧‧ finger

20‧‧‧ light

100A, 100B‧‧‧Display panel

102, 106 ‧‧‧ pixel area

104A, 104B, 104C, 108A, 108B, 108C

110‧‧‧Backlight module

200, 500‧‧‧ Lower substrate

210‧‧‧First polarizer

220‧‧‧The first substrate

222‧‧‧The first shading layer

224‧‧‧First buffer layer

230‧‧‧First thin film transistor

240‧‧‧ First gate insulating layer

242‧‧‧The first interlayer dielectric layer

244‧‧‧First source/drain contact layer

246‧‧‧First passivation layer

248‧‧‧Common electrode

250‧‧‧First dielectric layer

252‧‧‧Pixel electrode

300‧‧‧Display medium layer

400, 600‧‧‧upper substrate

410‧‧‧second dielectric layer

420‧‧‧Color filter layer

422‧‧‧Red filter layer

424‧‧‧Green filter layer

426‧‧‧Blue filter layer

430‧‧‧Second shading layer

432‧‧‧The first opening pattern

434‧‧‧Second opening pattern

440‧‧‧third dielectric layer

442‧‧‧Depression

450、620‧‧‧Light sensor

452、622‧‧‧Metal electrode layer

454,624‧‧‧Light sensing layer

456, 626‧‧‧Transparent electrode layer

462‧‧‧ Fourth dielectric layer

464‧‧‧Second source/drain contact layer

466‧‧‧second dielectric layer

468‧‧‧Second gate insulating layer

470‧‧‧Second Thin Film Transistor

480‧‧‧Second buffer layer

482‧‧‧The third shading layer

484‧‧‧Second substrate

486‧‧‧Second polarizer

502、602‧‧‧layer

510‧‧‧The third substrate

512‧‧‧third buffer layer

520‧‧‧third thin film transistor

530‧‧‧capacitor element

540‧‧‧The third gate insulating layer

542‧‧‧The first conductive layer

544‧‧‧The fourth gate insulating layer

546‧‧‧Second conductive layer

548‧‧‧ Third dielectric layer

550‧‧‧third source/drain contact layer

552‧‧‧fifth dielectric layer

554‧‧‧The third conductive layer

556‧‧‧Second passivation layer

560‧‧‧ pixel definition layer

567‧‧‧ opening

570, 570A, 570B

572‧‧‧Lower electrode

574‧‧‧luminous layer

576‧‧‧Upper electrode

610‧‧‧Sixth dielectric layer

630‧‧‧The seventh dielectric layer

632‧‧‧ Fourth source/drain contact layer

634‧‧‧Fourth dielectric layer

636‧‧‧ fifth gate insulating layer

640‧‧‧th thin film transistor

650‧‧‧Fourth buffer layer

652‧‧‧Fourth shading layer

654‧‧‧Fourth substrate

656‧‧‧third polarizer

700‧‧‧ gap

702‧‧‧Support structure

1B-1B’, 1C-1C’, 2B-2B’, 2C-2C’‧‧‧‧ line segment

D‧‧‧ Jiji District

G‧‧‧Gate

DH‧‧‧Horizontal

DV‧‧‧Vertical

L1‧‧‧Distance

L2‧‧‧Distance

S‧‧‧Source

S1‧‧‧Lower surface

S2‧‧‧Side surface

SC‧‧‧Channel area

TH1‧‧‧First contact hole

TH2‧‧‧The second contact hole

TH3‧‧‧The third contact hole

TH4‧‧‧The fourth contact hole

TH5‧‧‧The fifth contact hole

TH6‧‧‧The sixth contact hole

TH7‧‧‧The seventh contact hole

TH8‧‧‧Eighth contact hole

TH9‧‧‧Ninth contact hole

TH10‧‧‧Tenth contact hole

FIG. 1A is a schematic top view illustrating a plurality of pixel regions of a display panel according to the first embodiment of the present disclosure.

Fig. 1B is a schematic cross-sectional view taken along the line 1B-1B' of Fig. 1A.

Fig. 1C is a schematic cross-sectional view taken along the line 1C-1C' of Fig. 1A.

FIG. 1D is a schematic diagram of the display panel to which the first embodiment is applied.

FIG. 2A is a schematic top view illustrating a plurality of pixel regions of a display panel according to the second embodiment of the present disclosure.

Fig. 2B is a schematic cross-sectional view taken along the line 2B-2B' of Fig. 2A.

Fig. 2C is a schematic cross-sectional view taken along the line 2C-2C' of Fig. 2A.

FIG. 2D is a schematic diagram showing that the lower substrate and the upper substrate are assembled together.

FIG. 2E is a schematic diagram of the display panel to which the second embodiment is applied.

In the following, a plurality of embodiments of the present invention will be disclosed in the form of diagrams. For the sake of clarity, many practical details will be described together in the following description. However, it should be understood that these practical details should not be used to limit the present invention. That is to say, in some embodiments of the present invention, these practical details are unnecessary. In addition, in order to simplify the drawings, some conventional structures and elements will be shown in a simple schematic manner in the drawings.

In this article, the terms first, second, third, etc. are used to describe various elements, components, regions, and layers that can be understood. But these elements, components, regions, layers should not be limited by these terms. These vocabularies are limited to identifying single components, components, regions, and layers. Therefore, a first element, component, region, layer in the following may also be referred to as a second element, component, region, layer without departing from the original intention of the present invention.

Please refer to FIG. 1A, FIG. 1B and FIG. 1C, FIG. 1A is a schematic top view of a plurality of pixel regions 102 of the display panel 100A according to the first embodiment of the present disclosure, and FIG. 1B is along FIG. 1A Is a schematic cross-sectional view of the line segment 1B-1B'. FIG. 1C is a schematic cross-sectional view along the line segment 1C-1C' of FIG. 1A.

As shown in FIG. 1A, the display panel 100A has a plurality of pixel regions 102, and these pixel regions 102 can be arranged in an array along the horizontal direction DH and the vertical direction DV of FIG. 1A. For each pixel area 102, it can have three sub-pixel areas 104A, 104B, 104C, wherein the sub-pixel areas 104A, 104B, 104C can be used to provide different colors, such as red, green, and blue .

Please see FIGS. 1B and 1C. The display panel 100A includes a backlight module 110, a lower substrate 200, a display medium layer 300, and an upper substrate 400. The backlight module 110 is connected to the lower substrate 200, and the display medium layer 300 is located below Between the substrate 200 and the upper substrate 400. The backlight module 110 is used to emit a light beam toward the lower substrate 200, the display medium layer 300, and the upper substrate 400, and the upper surface of the upper substrate 400 can be used as the display surface of the display panel 100A.

The lower substrate 200 includes a first polarizer 210, a first substrate 220, a first light-shielding layer 222, a first buffer layer 224, a plurality of first thin film transistors 230, a first gate insulating layer 240, and a first interlayer dielectric Layer 242, first source/drain contact layer 244, first passivation layer 246, common electrode 248, first dielectric layer 250 and pixel electrode 252, wherein the first polarizer 210 is disposed on the backlight module 110 and Between the first substrates 220. In some embodiments, the materials of the buffer layer, insulating layer, dielectric layer and passivation layer of the lower substrate 200 may be organic materials or inorganic materials, such as epoxy resin, silicon oxide (SiOx), silicon nitride (SiNx) ), a composite layer composed of silicon oxide and silicon nitride or other suitable dielectric materials.

The first substrate 220 is disposed on the first polarizer 210, wherein the first substrate 220 can be used as a carrier substrate of the lower substrate 200 in the manufacturing process, which can be, for example, a glass substrate to facilitate other components or layers of the lower substrate 200 It is formed on the first substrate 220.

The first light-shielding layer 222, the first buffer layer 224, the plurality of first thin film transistors 230 and the first gate insulating layer 240 are disposed on the first substrate 220. The first buffer layer 224 is disposed on the first light-shielding layer 222, which can facilitate the formation of the first thin film transistor 230. The first thin-film transistor 230 is formed at a position corresponding to the first light-shielding layer 222, wherein the first light-shielding layer 222 has light-shielding properties, which may be, for example, metal, organic, or inorganic materials to shield the travel from below toward the first thin-film transistor 230 Light, thereby preventing the first thin film transistor 230 from deriving leakage current due to light.

Each first thin film transistor 230 includes a source region S, a drain region D, a channel region SC, and a gate G, wherein the source region S, the drain region D, and the channel region SC can be formed by the same layer body, and can be borrowed The position of each zone is defined by the diffusion process to adjust the carrier concentration of the same layer body, where the layer body may be crystalline silicon material. The first gate insulating layer 240 covers the source region S, the drain region D, and the channel region SC, and the gate G is disposed on the first gate insulating layer 240, and the location of the gate G is in contact with the channel region SC corresponds.

The first interlayer dielectric layer 242 is disposed on the first gate insulating layer 240 and covers the gate G, wherein the first gate insulating layer 240 and the first interlayer dielectric layer 242 share a first contact hole TH1. The first source/drain contact layer 244 is disposed on the first interlayer dielectric layer 242, where the first source/drain contact layer 244 may include a metal material. The first source/drain contact layer 244 may contact the source region S and the drain region D of the first thin film transistor 230 through the first contact hole TH1, so as to be electrically connected to the first thin film transistor 230. The gate G of the first thin film transistor 230 and the first source/drain contact layer 244 can be regarded as a circuit layer of the lower substrate 200.

The first passivation layer 246 is disposed on the first interlayer dielectric layer 242 and covers at least part of the first source/drain contact layer 244. The common electrode 248 and the first dielectric layer 250 are disposed on the first passivation layer 246, wherein the first dielectric layer 250 covers the common electrode 248, and the first dielectric layer 250 and the first passivation layer 246 may jointly have a second contact Hole TH2. The pixel electrode 252 is disposed on the first dielectric layer 250, and the pixel electrode 252 may contact the first source/drain contact layer 244 through the second contact hole TH2 of the first dielectric layer 250 and the first passivation layer 246 , So as to be electrically connected to the drain region D of the first thin film transistor 230 through the first source/drain contact layer 244. In some embodiments, the materials of the common electrode 248 and the pixel electrode 252 include transparent conductive materials, such as indium tin oxide, indium zinc oxide, zinc oxide, carbon nanotubes, indium gallium zinc oxide, or other suitable materials.

The display medium layer 300 is disposed on the common electrode 248 and the pixel electrode 252, and may have a display medium. For example, the display medium layer 300 may be a liquid crystal layer and have liquid crystal molecules. When the first thin film transistor 230 is driven so that the common electrode 248 and the pixel electrode 252 have different potentials, the common electrode 248 and the pixel electrode 252 can couple out an electric field, thereby controlling the display medium of the display medium layer 300 to control Polarization of light traveling from the lower substrate 200 to the upper substrate 400.

The upper substrate 400 includes a second dielectric layer 410, a color filter layer 420, a second light-shielding layer 430, a third dielectric layer 440, a light sensor 450, a fourth dielectric layer 462, and a second source/drain The contact layer 464, the second interlayer dielectric layer 466, the second gate insulating layer 468, the second thin film transistor 470, the second buffer layer 480, the third light shielding layer 482, the second substrate 484, and the second polarizer 486. In some embodiments, the materials of the buffer layer, insulating layer, dielectric layer and passivation layer of the upper substrate 400 may be organic materials or inorganic materials, such as epoxy resin, silicon oxide (SiOx), silicon nitride (SiNx) ), a composite layer composed of silicon oxide and silicon nitride or other suitable dielectric materials.

The second dielectric layer 410 is disposed on the display medium layer 300. The color filter layer 420 and the second light-shielding layer 430 are disposed on the second dielectric layer 410. The second light-shielding layer 430 has a first opening pattern 432 and a second opening pattern 434. The first opening pattern 432 and the second opening pattern 434 can be formed by a patterning process. For example, the layer body can be formed by using a light-shielding material, and then A patterning process is performed on this light-shielding material to form a second light-shielding layer 430 having a first opening pattern 432 and a second opening pattern 434. The vertical projection of the color filter layer 420 on the display medium layer 300 partially overlaps with the vertical projection of the first opening pattern 432 of the second light-shielding layer 430 on the display medium layer 300. Specifically, the color filter layer 420 includes a red filter layer 422, a green filter layer 424, and a blue filter layer 426, wherein the bottom of the red filter layer 422 is located in the second light-shielding layer 430 and the second dielectric layer 410, and the top of the red filter layer 422 is located in the first opening pattern 432, so the vertical projection of the red filter layer 422 in the first opening pattern 432 on the display medium layer 300 and the second light shielding The vertical projection of the first opening pattern 432 of the layer 430 on the display medium layer 300 overlaps. The arrangement of the green filter layer 424 and the blue filter layer 426 can be similar to that of the red filter layer 422, which will not be repeated here. Through this configuration, the light traveling from the display medium layer 300 to the upper substrate 400 can pass through the first opening pattern 432 of the second light-shielding layer 430 and the color filter layer 420 located therein, thereby having corresponding colors, and As a result, the display panel 100A displays images.

The third dielectric layer 440 is disposed on the color filter layer 420 and the second light-shielding layer 430, and a portion of the third dielectric layer 440 passes through the second opening pattern 434 of the second light-shielding layer 430 and extends toward the display medium layer 300 , To form the depressed portion 442. In other words, the third dielectric layer 440 may pass through the second opening pattern 434 of the second light-shielding layer 430 from a position higher than the second light-shielding layer 430 and extend to a position lower than the second light-shielding layer 430 to form the recessed portion 442 The recessed portion 442 formed therein can contact the second dielectric layer 410, and the interface between the recessed portion 442 and the second dielectric layer 410 is located under the second light-shielding layer 430. For example, the minimum vertical distance from the recessed portion 442 to the display medium layer 300 can be marked as the distance L1, and the minimum vertical distance from the second light-shielding layer 430 to the display medium layer 300 can be marked as the distance L2, and the distance L1 is less than the distance L2 .

The photo sensor 450 is disposed above the display medium layer 300, and the vertical projection of the photo sensor 450 on the display medium layer 300 and the vertical projection of the second opening pattern 434 of the second light-shielding layer 430 on the display medium layer 300 Partial overlap. Specifically, the light sensor 450 is located on the recessed portion 442 of the third dielectric layer 440 and is in contact with the third dielectric layer 440, wherein the light sensor 450 can communicate with the second through the third dielectric layer 440 The light shielding layer 430 is separated. By disposing the photo sensor 450 on the concave portion 442 of the third dielectric layer 440, since the concave portion 442 extends from a position higher than the second light-shielding layer 430 to a position lower than the second light-shielding layer 430, It is avoided that the thickness of the display panel 100A increases excessively due to the configuration of the light sensor 450.

In addition, the installation position of the light sensor 450 and the installation position of the color filter layer 420 are staggered from each other, so as to prevent the light sensor 450 from affecting the light output of the color filter layer 420 and affecting the image quality of the display panel 100A . Specifically, as shown in FIG. 1A, in each pixel area 102 of the display panel 100A, the three sub-pixel areas 104A, 104B, and 104C are respectively composed of the red filter layer 422 and the green color filter layer 420. The filter layer 424 and the blue filter layer 426 are defined, and each pixel region 102 is provided with a light sensor 450, wherein the light sensor 450 is located in the red filter layer 422 and the green filter layer 424 and the blue filter layer 426 are on the same side, so the light sensor 450 does not affect the light output of the color filter layer 420.

On the other hand, since the photo sensor 450 in each pixel region 102 is located on the same side of the red filter layer 422, the green filter layer 424, and the blue filter layer 426 of the color filter layer 420, It can be considered that the installation position of the light sensor 450 and the installation position of the color filter layer 420 are independent of each other. For example, even if the spacing between the red filter layer 422, the green filter layer 424, and the blue filter layer 426 of the color filter layer 420 changes or the respective widths increase or decrease, the light sensor 450 can still It is set at its original position without changing the setting position corresponding to the change of the pitch or width of the filter layer.

In the case where the installation position of the photo sensor 450 and the installation position of the color filter layer 420 are independent of each other, the photo sensor 450 of each pixel region 102 can adopt the same arrangement method, thereby facilitating the simplification of the manufacturing process For example, it is possible to simplify the mask pattern used to make the photo sensor 450. Furthermore, in the case where the photo sensors 450 in each pixel region 102 adopt the same arrangement, these photo sensors 450 can be connected to the circuit layer of the lower substrate 200 (including the gate G and the first source) /Drain contact layer 244) forms a plurality of overlapping areas (that is, areas that overlap with each other in a top view), and the plurality of overlapping areas are equal to each other, so as to avoid the unexpectedness between different pixel regions 102 This difference prevents unevenness in the image brightness of the display panel 100A.

Please go back to Figure 1B and Figure 1C again. The light sensor 450 includes a metal electrode layer 452, a light sensing layer 454, and a light-transmitting electrode layer 456, wherein the metal electrode layer 452 contacts the third dielectric layer 440, and the light-sensing layer 454 and the light-transmitting electrode layer 456 are stacked On the metal electrode layer 452, the light sensing layer 454 is located between the metal electrode layer 452 and the light-transmitting electrode layer 456. The material of the light-sensing layer 454 includes silicon rich oxide, and has the characteristics of generating electron hole pairs when exposed to light. With this characteristic, the light sensor 450 can achieve a light-sensing effect.

The metal electrode layer 452 can be conformal with the third dielectric layer 440 underneath and present a concave shape, wherein the vertical projection of the metal electrode layer 452 on the display medium layer 300 and the vertical direction of the first thin film transistor 230 on the display medium layer 300 The projections can partially overlap. Since the metal electrode layer 452 does not have light transmittance, the metal electrode layer 452 can shield the first thin film transistor 230 overlapping with the metal electrode layer 452. Therefore, when viewed from above, the display panel 100A is viewed from above (that is, from above FIGS. 1B and 1C) When facing toward the display panel 100A), the first thin film transistor 230 located under the second opening pattern 434 of the second light shielding layer 430 is not seen. In addition, the vertical projection of the metal electrode layer 452 on the display medium layer 300 may also overlap with the vertical projection of the second light-shielding layer 430 on the display medium layer 300. With this configuration, the light beam from the lower substrate 200 can be prevented from passing through the second The gap between the light shielding layer 430 and the metal electrode layer 452.

The light sensing layer 454 has a lower surface S1 and a side surface S2, wherein the lower surface S1 of the light sensing layer 454 faces the display medium layer 300 and is connected to the side surface S2 of the light sensing layer 454, and the lower surface of the light sensing layer 454 S1 and the side surface S2 are covered by the metal electrode layer 452, so that the light beam passing through the light sensing layer 454 from top to bottom will then travel toward the metal electrode layer 452, and the metal electrode layer 452 can prevent this from passing through the light sensing The light beam of the layer 454 travels to the display medium layer 300, thereby avoiding undesired influence of the elements or layer body of the lower substrate 200 due to illumination. In addition, the light-sensing layer 454 can be conformal with the metal electrode layer 452 underneath and also present a concave shape, wherein the light-transmitting electrode layer 456 can correspond to the depression of the light-sensing layer 454 and above the light-sensing layer 454 The surface and the upper surface of the transparent electrode layer 456 are substantially coplanar. In some embodiments, the material of the light-transmitting electrode layer 456 includes a transparent conductive material, such as indium tin oxide, indium zinc oxide, zinc oxide, carbon nanotubes, indium gallium zinc oxide, or other suitable materials.

The fourth dielectric layer 462, the second source/drain contact layer 464, the second interlayer dielectric layer 466, the second gate insulating layer 468, and the second thin film transistor 470 are disposed on the third dielectric layer 440 and the light Above the sensor 450. The fourth dielectric layer 462 covers the third dielectric layer 440 and the photo sensor 450, and has a third contact hole TH3, and a part of the metal electrode layer 452 of the photo sensor 450 is located in the third contact hole TH3 . The second source/drain contact layer 464 is disposed on the fourth dielectric layer 462 and is covered by the second interlayer dielectric layer 466, wherein the second source/drain contact layer 464 may include a metal material. The second source/drain contact layer 464 is located between the fourth dielectric layer 462 and the second interlayer dielectric layer 466. In addition, the second source/drain contact layer 464 may contact the metal electrode layer 452 located in the third contact hole TH3 to electrically connect the photo sensor 450.

The second gate insulating layer 468 and the second thin film transistor 470 are disposed on the second interlayer dielectric layer 466, wherein the second thin film transistor 470 includes a source region S, a drain region D, a channel region SC, and a gate G, wherein the source region S, the drain region D and the channel region SC can be formed by the same layer body, and the carrier concentration of this same layer body can be adjusted by a diffusion process to define the position of each region. The second gate insulating layer 468 covers the gate G, so that the gate G is located between the second interlayer dielectric layer 466 and the second gate insulating layer 468, and the gate G is disposed at the channel area SC Corresponding. The second gate insulating layer 468 and the second interlayer dielectric layer 466 may jointly have a fourth contact hole TH4, and the second source/drain contact layer 464 may contact the second thin film transistor 470 through the fourth contact hole TH4 The source region S and the drain region D, and thereby the second thin film transistor 470 is electrically connected to the photo sensor 450.

The second thin film transistor 470 may be located above the second light-shielding layer 430, and the second light-shielding layer 430 is located between the display dielectric layer 300 and the second thin-film transistor 470, so as to prevent the bottom substrate 200 from being projected and passing through The light beam of the display medium layer 300 will irradiate the second thin film transistor 470 to derive a leakage current. Specifically, the vertical projection of the channel area SC of the second thin film transistor 470 to the display medium layer 300 may overlap with the vertical projection of the second light-shielding layer 430 to the display medium layer 300, thereby preventing the light beam from the display medium layer 300 from being irradiated To the channel region SC of the second thin film transistor 470.

The second buffer layer 480 and the third light shielding layer 482 are disposed on the second gate insulating layer 468 and the second thin film transistor 470, wherein the second buffer layer 480 can facilitate the formation of the second thin film transistor 470, and the third light shielding The formation position of the layer 482 may correspond to at least the channel region SC of the second thin film transistor 470, thereby preventing the channel region SC of the second thin film transistor 470 from deriving leakage current due to the light from above.

The second substrate 484 is disposed on the second buffer layer 480 and the third light-shielding layer 482, and the second polarizer 486 is disposed on the second substrate 484. The second substrate 484 can be used as a carrier substrate in the manufacturing process of the upper substrate 400, which can be, for example, a glass substrate. For example, each layer or element of the upper substrate 400 may be formed on the second substrate 484 first. After the second light-shielding layer 430 and the color filter layer 420 are formed, the second dielectric layer 410 may be formed as Flat layer. After the second dielectric layer 410 is formed, the upper substrate 400 can be turned over so that the second dielectric layer 410 is on the bottom side, and then the upper substrate 400 is assembled on the lower substrate 200, wherein the display medium layer 300 It is filled between the lower substrate 200 and the upper substrate 400 to complete the architecture shown in FIGS. 1B and 1C.

Please refer to FIG. 1D again, which illustrates a schematic diagram of the display panel 100A according to the first embodiment. The left half frame and the right half frame of the display panel 100A depicted in FIG. 1D may be the same as those in FIG. 1B and FIG. 1C respectively. In order not to make the drawing too complicated, some components in FIG. 1D are not marked. There are symbol symbols.

The display panel 100A of the first embodiment can detect the fingerprint pattern of the user through the light sensor 450. For example, when the user's finger 10 covers and touches the display panel 100A, the light 20 emitted by the backlight module 110 can pass through the lower substrate 200 and the display medium layer 300 and enter and pass through the second light shielding The color filter layer 420 in the first opening pattern 432 of the layer 430 and then travels to the finger 10 and reflects from the finger 10. The light 20 reflected by the finger 10 can return to the upper substrate 400 and enter the light sensing layer 454 of the light sensor 450 after passing through the layer body in the upper substrate 400. Since the pattern of the finger 10 has pattern peaks and valleys, and the reflection direction of the light 20 on the pattern peaks and valleys will be different, different light sensors 450 of the display panel 100A will receive reflected light with different intensities. From these reflected lights with different intensities, the fingerprint pattern of the user's finger 10 can be resolved.

In summary, in this embodiment, the color filter layer 420, the second light-shielding layer 430, and the light sensor 450 can be integrated into the upper substrate 400 of the display panel 100A, so as to avoid the display caused by the light sensor 450 The situation where the thickness of the panel 100A has increased too much. Through this configuration, light sensors 450 can be respectively arranged in the plurality of pixel regions 102 of the display panel 100A, so that each pixel region 102 of the display panel 100A can provide the function of fingerprint recognition, that is, In addition to providing images, the display surface of the display panel 100A can also be used as a fingerprint recognition area of the user, thereby increasing the screen ratio of the display panel 100A, so that the display panel 100A is suitable for designing as a full-screen display device.

Please refer to FIG. 2A, FIG. 2B and FIG. 2C. FIG. 2A is a schematic top view illustrating a plurality of pixel regions 106 of the display panel 100B according to the second embodiment of the present disclosure. FIG. 2A is a schematic cross-sectional view of the line segment 2B-2B', and FIG. 2C is a schematic cross-sectional view along the line 2C-2C' of FIG. 2A. At least one difference between this embodiment and the first embodiment is that the display panel 100B of this embodiment emits light through the light-emitting layer to provide an image.

As shown in FIG. 2A, the display panel 100B has a plurality of pixel regions 106, and these pixel regions 106 can be arranged in an array along the horizontal direction DH and the vertical direction DV of FIG. 2A. For each pixel area 106, it can have three sub-pixel areas 108A, 108B, 108C, wherein the sub-pixel areas 108A, 108B, 108C can be used to provide different colors, such as red, green, and blue colors .

The display panel 100B includes a lower substrate 500 and an upper substrate 600, wherein the upper substrate 600 is located above the lower substrate 500, and the upper surface of the upper substrate 600 can be used as the display surface of the display panel 100B. The lower substrate 500 and the upper substrate 600 can be independently manufactured separately, and assembled after being manufactured separately.

For example, please see FIG. 2D first. FIG. 2D shows a schematic diagram of the lower substrate 500 and the upper substrate 600 assembled together. The lower substrate 500 and the upper substrate 600 respectively include a third substrate 510 and a fourth substrate 654, which may be, for example, glass substrates. In order not to make the drawings too complicated, the layered body formed on the third substrate 510 of the lower substrate 500 is represented by the layered body 502, and the layered body formed on the fourth substrate 654 of the upper substrate 600 is represented by the layered body 602. The third polarizer of the substrate 600 is arranged on the fourth substrate 654. The display panel 100B may further include a support structure 702, where the support structure 702 may be glass, ceramic, or other frame with sufficient support strength. The supporting structure 702 is disposed between the lower substrate 500 and the upper substrate 600 so that the upper substrate 600 can be fixed above the lower substrate 500 and a gap 700 can exist between the lower substrate 500 and the upper substrate 600. In the embodiment depicted in FIG. 2D, the gap 700 may be an air gap. In other embodiments, a solid dielectric material may be filled between the lower substrate 500 and the upper substrate 600.

Please return to Figure 2B and Figure 2C. The lower substrate 500 includes a third substrate 510, a third buffer layer 512, a plurality of third thin film transistors 520, a capacitive element 530, a third gate insulating layer 540, a first conductive layer 542, a fourth gate insulating layer 544, The second conductive layer 546, the third interlayer dielectric layer 548, the third source/drain contact layer 550, the fifth dielectric layer 552, the third conductive layer 554, the second passivation layer 556, the pixel definition layer 560 and Light emitting element 570. In some embodiments, the materials of the buffer layer, insulating layer, dielectric layer and passivation layer of the lower substrate 500 may be organic materials or inorganic materials, such as epoxy resin, silicon oxide (SiOx), silicon nitride (SiNx) ), a composite layer composed of silicon oxide and silicon nitride or other suitable dielectric materials.

The third substrate 510 can be used as a carrier substrate in the manufacturing process of the lower substrate 500, which can be, for example, a glass substrate, so that other elements or layers of the lower substrate 500 can be formed on the third substrate 510 in the manufacturing process.

The third buffer layer 512, the plurality of third thin film transistors 520, the third gate insulating layer 540, and the fourth gate insulating layer 544 are disposed on the third substrate 510, and the third thin film transistor 520 is located in the third buffer On the layer 512, the third buffer layer 512 can facilitate the formation of the third thin film transistor 520. Each third thin film transistor 520 includes a source region S, a drain region D, a channel region SC, and a gate G, where the source region S, the drain region D, and the channel region SC can be formed by the same layer body and can be borrowed The location of each zone is defined by the diffusion process adjusting the carrier concentration of this same layer. The third gate insulating layer 540 covers the source region S, the drain region D, and the channel region SC, and the gate G is disposed on the third gate insulating layer 540, and the position of the gate G is set to the channel region SC corresponds. The fourth gate insulating layer 544 is disposed on the third gate insulating layer 540 and covers the gate G.

The capacitive element 530 and the first conductive layer 542 are disposed on the third buffer layer 512. The source region S, the drain region D, and the channel region SC of the capacitive element 530 and the third thin film transistor 520 can be formed through the same layer body, and then the carrier concentration of each region can be adjusted by a diffusion process. It is a crystalline silicon material. The first conductive layer 542 is disposed on the third gate insulating layer 540, and the first conductive layer 542 and the gate G of the third thin film transistor 520 can be formed through the same layer body, for example, by patterning the same metal layer form. The capacitive element 530 and the first conductive layer 542 can provide electrical communication in the lower substrate 500.

The second conductive layer 546, the third interlayer dielectric layer 548, and the third source/drain contact layer 550 are disposed on the fourth gate insulating layer 544, wherein the third source/drain contact layer 550 may include a metal material . The third interlayer dielectric layer 548 covers the fourth gate insulating layer 544 and the second conductive layer 546. The third gate insulating layer 540, the fourth gate insulating layer 544 and the third interlayer dielectric layer 548 may jointly have a fifth contact hole TH5, and the fourth gate insulating layer 544 and the third interlayer dielectric layer 548 may jointly have The sixth contact hole TH6, and the third interlayer dielectric layer 548 may have a seventh contact hole TH7. The third source/drain contact layer 550 is disposed on the third interlayer dielectric layer 548, and can be electrically connected to the corresponding layer body through different contact holes. Specifically, the third source/drain contact layer 550 may extend through the fifth contact hole TH5 to the source region S or the drain region D of the third thin film transistor 520, so as to communicate with the source of the third thin film transistor 520 The pole region S or the drain region D is electrically connected. In addition, the third source/drain contact layer 550 can also extend to the capacitive element 530 through the fifth contact hole TH5 to be electrically connected to the capacitive element 530; the third source The electrode/drain contact layer 550 may extend through the sixth contact hole TH6 to the gate G of the third thin film transistor 520, thereby being electrically connected to the gate G of the third thin film transistor 520. In addition, the third source/ The drain contact layer 550 can also extend through the sixth contact hole TH6 to the first conductive layer 542 to be electrically connected to the first conductive layer 542; the third source/drain contact layer 550 can extend through the seventh contact hole TH7 To the second conductive layer 546, so as to be electrically connected to the second conductive layer 546.

The fifth dielectric layer 552, the third conductive layer 554 and the second passivation layer 556 are disposed on the third interlayer dielectric layer 548, wherein the fifth dielectric layer 552 covers the third source/drain contact layer 550 and has Eighth contact hole TH8. The third conductive layer 554 and the second passivation layer 556 are disposed on the fifth dielectric layer 552, wherein the second passivation layer 556 covers the third conductive layer 554, so that the third conductive layer 554 is positioned between the fifth dielectric layer 552 and Between the second passivation layer 556, and the third conductive layer 554 can extend to the third source/drain contact layer 550 through the eighth contact hole TH8, so as to be electrically connected to the third source/drain contact layer 550.

In the structure of the lower substrate 500, the gate G of the third thin film transistor 520, the first conductive layer 542, the second conductive layer 546, the third source/drain contact layer 550, and the third conductive layer 554 can be used together The circuit layer of the lower substrate 500 provides the purpose of electrical communication.

The pixel definition layer 560 and the light emitting element 570 are disposed on the second passivation layer 556. The light emitting element 570 includes a lower electrode 572, a light emitting layer 574, and an upper electrode 576. The lower electrode 572 of the light emitting element 570 is disposed on the second passivation layer 556 and is covered by the pixel definition layer 560, wherein the second passivation layer 556 may have a ninth contact hole TH9, and the lower electrode 572 may pass through the ninth contact hole TH9 It extends to the third conductive layer 554, so as to be electrically connected to the third thin film transistor 520. The lower electrode 572 can be formed by patterning the conductive layer. In some embodiments, in the process of forming the lower electrode 572, the patterning process may further form a fourth conductive layer 558 after the patterning process, wherein the fourth conductive layer 558 is located in the second passivation The layer 556 extends through the ninth contact hole TH9 to the third conductive layer 554. In addition, the fourth conductive layer 558 can also be used as a circuit layer of the lower substrate 500.

The light-emitting layer 574 of the light-emitting element 570 is disposed in the pixel definition layer 560, and is electrically connected to the lower electrode 572. Here, the "set in the pixel definition layer 560" means that after the pixel definition layer 560 is formed, an opening 567 can be formed in the pixel definition layer 560 by removing part of the pixel definition layer 560, And the opening 567 exposes the lower electrode 572, and then, the light emitting layer 574 is formed in the opening 567, and the light emitting layer 574 can be disposed in the pixel definition layer 560. The upper electrode 576 of the light emitting element 570 is disposed on the pixel definition layer 560 and the light emitting layer 574, and is electrically connected to the light emitting layer 574. In addition, the upper electrode 576 of the light-emitting element 570 may extend through the tenth contact hole TH10 of the pixel definition layer 560 to the fourth conductive layer 558, so as to be electrically connected to the circuit layer of the lower substrate 500. When a bias is applied to the light emitting layer 574 through the lower electrode 572 and the upper electrode 576 of the light emitting element 570, the light emitting layer 574 can emit light.

The material of the light-emitting layer 574 of the light-emitting element 570 may include an organic material. In other words, the light-emitting element 570 may be an organic light-emitting diode, and the wavelength of the colored light provided by the light-emitting element 570 may depend on the organic material of the light-emitting layer 574. For example, different organic materials of the light-emitting layer 574 can be selected to enable the light-emitting element 570 to provide red light, green light, or blue light. The materials of the lower electrode 572 and the upper electrode 576 of the light emitting element 570 may include transparent conductive materials, such as indium tin oxide, indium zinc oxide, zinc oxide, carbon nanotubes, indium gallium zinc oxide, or other suitable materials, or, It may also contain non-transparent conductive materials, such as metals, alloys, or other suitable materials. In addition, the materials of the lower electrode 572 and the upper electrode 576 of the light emitting element 570 may be different. For example, the lower electrode 572 is a non-transparent conductive material, and the upper electrode 576 is a transparent conductive material.

The structure of the upper substrate 600 of this embodiment is substantially the same as the structure of the upper substrate 400 of the first embodiment. However, the upper substrate 600 of this embodiment omits the color filter layer and the light shielding at the same horizontal position as the color filter layer Layer (for example, the color filter layer and the second light shielding layer of the first embodiment). Specifically, the upper substrate 600 of this embodiment includes a sixth dielectric layer 610, a photo sensor 620, a seventh dielectric layer 630, a fourth source/drain contact layer 632, and a fourth interlayer dielectric layer 634, a fifth gate insulating layer 636, a fourth thin film transistor 640, a fourth buffer layer 650, a fourth light shielding layer 652, a fourth substrate 654, and a third polarizer 656, wherein the photo sensor 620 includes a photometal electrode The layer 622, the light sensing layer 624 and the transparent electrode layer 626, and the fourth thin film transistor 640 includes a source region S, a drain region D, a channel region SC and a gate G. Since the detailed descriptions of these layer bodies or elements have been described in the first embodiment, they will not be repeated here.

Similar to the first embodiment, the position of the light sensor 620 in this embodiment can be staggered from the position of the light emitting element 570, so as to prevent the light sensor 620 from affecting the light emission of the light emitting element 570 and the display panel 100B Image quality. Specifically, as shown in FIG. 2A, in each pixel area 106 of the display panel, the three sub-pixel areas 108A, 108B, and 108C are respectively provided by three different colors of light (for example, red, green, and blue). A light-emitting element 570A, 570, 570B is defined, and each pixel area 106 is provided with a light sensor 620, wherein the light sensor 620 is located on the same side of the three light-emitting elements 570A, 570, 570B, Therefore, the light sensor 620 does not affect the light emitted by the light emitting elements 570A, 570, and 570B.

On the other hand, since the photo sensor 620 in each pixel area 106 is located on the same side of the light emitting element 570A, 570, 570B, it can be regarded as the installation position of the photo sensor 620 and the light emitting element 570A, 570, The installation positions of the 570B are independent of each other. Therefore, the photo sensor 620 of each pixel area 106 can be configured in the same manner, which is beneficial to simplify the manufacturing process.

Furthermore, in the case where the photo sensors 620 in each pixel region 106 adopt the same arrangement, these photo sensors 620 can form multiple overlapping areas with the circuit layer below, and the multiple overlapping areas are mutually equal. The circuit layer may be, for example, the gate G of the lower substrate 500 of FIGS. 2B and 2C, the first conductive layer 542, the second conductive layer 546, the third source/drain contact layer 550, and the third conductive layer 554 . In FIG. 2A, the area of the pixel region 106 outside the light sensor 620 and the light-emitting elements 570A, 570, and 570B shown with a mesh bottom can be regarded as a circuit layer under the light sensor 620, and each The circuit layer depicted in the pixel area 106 and the corresponding photo sensor 620 form an overlapping area. For two different pixel regions 106, the two overlapping areas formed by the two photo sensors 620 and the underlying circuit layer will be equal to each other, thus avoiding the existence of different pixel regions 106 Unexpected differences, thereby preventing unevenness in the image brightness of the display panel 100B.

Please refer to FIG. 2E again, which illustrates a schematic diagram of the display panel 100B according to the second embodiment. The left half frame and the right half frame of the display panel 100B depicted in FIG. 2E may be the same as those in FIGS. 2B and 2C. In order not to over complicate the drawings, some elements in FIG. 2E are not marked. There are symbol symbols.

The display panel 100B of the second embodiment can detect the fingerprint pattern of the user through the light sensor 620. For example, when the user's finger 10 covers and contacts the display panel 100B, the light 20 emitted by the light-emitting layer 574 of the light-emitting element 570 can be reflected from the finger 10 after passing through the upper substrate 600. The light 20 reflected by the finger 10 can return to the upper substrate 600 and enter the light sensing layer 624 of the light sensor 620 after passing through the layer in the upper substrate 400, so as to resolve the fingerprint pattern of the user. Similarly, since the photo sensors 620 are respectively arranged in the pixel regions 106 of the display panel 100B, each pixel region 106 of the display panel 100B can provide the function of fingerprint recognition, thereby increasing the screen occupation of the display panel 100B The comparison also makes the display panel 100B suitable for a full-screen display device.

In summary, the display panel of the present disclosure includes a lower substrate and an upper substrate, wherein the upper substrate includes a light sensor to provide a function of recognizing a user's fingerprint pattern. The display panel assembled from the lower substrate and the upper substrate may be a liquid crystal type display panel, or may be an organic light emitting type display panel.

When the display panel assembled by the lower substrate and the upper substrate is a liquid crystal display panel, the light sensor can be integrated with the light shielding layer and the color filter layer in the upper substrate, thereby avoiding the display caused by the arrangement of the light sensor The thickness of the panel has increased too much. In the case where the display panel assembled with the lower substrate and the upper substrate is an organic light-emitting type display panel, the installation position of the photo sensor and the installation position of the light-emitting element are independent of each other, thereby simplifying the manufacturing process and avoiding different pixel areas There are unexpected differences.

Through the above configuration, in addition to integrating the photo sensor into the display panel to provide the function of recognizing the fingerprint pattern, since each pixel area of the display panel can provide the function of recognizing the fingerprint, the display panel can be improved The screen-to-body ratio also makes the display panel suitable for a full-screen display device.

Although the present invention has been disclosed in various embodiments as above, it is not intended to limit the present invention. Anyone who is familiar with this skill can make various changes and modifications without departing from the spirit and scope of the present invention. The scope of protection shall be deemed as defined by the scope of the attached patent application.

10‧‧‧ finger

20‧‧‧ light

100A‧‧‧Display panel

110‧‧‧Backlight module

200‧‧‧Lower substrate

300‧‧‧Display medium layer

400‧‧‧Upper substrate

420‧‧‧Color filter layer

430‧‧‧Second shading layer

432‧‧‧The first opening pattern

450‧‧‧Light sensor

454‧‧‧Light sensing layer

Claims (10)

A display panel includes: a first thin film transistor; a pixel electrode electrically connected to the first thin film transistor; a display medium layer provided on the pixel electrode; and a light shielding layer provided on the display medium Layer, and includes at least one first opening pattern and at least one second opening pattern; a color filter layer is disposed on the display medium layer, wherein the vertical projection of the color filter layer on the display medium layer and the The vertical projection of the first opening pattern of the light shielding layer on the display medium layer partially overlaps; and at least one light sensor disposed on the display medium layer, wherein the light sensor is on the display medium layer The vertical projection partially overlaps with the vertical projection of the second opening pattern of the light shielding layer on the display medium layer. The display panel as described in item 1 of the patent application scope further includes: a second thin-film transistor electrically connected to the light sensor, wherein the light-shielding layer is located between the display medium layer and the second thin-film transistor between. The display panel as described in item 1 of the patent application scope, wherein the light sensor includes a metal electrode layer, a vertical projection of the metal electrode layer on the display medium layer and the first thin film transistor on the display medium layer The vertical projection on the part overlaps. The display panel as described in item 3 of the patent application range, wherein the light sensor further comprises a light sensing layer, the light sensing layer has a lower surface and at least one side surface, the lower surface faces the display medium layer and The side surface is connected, and the lower surface and the side surface are covered by the metal electrode layer. The display panel as described in item 1 of the patent application scope further includes: an insulating layer disposed on the light shielding layer and extending toward the display medium layer through the second opening pattern to form a recessed portion, wherein the The photo sensor is located in the recessed part and is separated from the light shielding layer through the insulating layer. The display panel as described in item 1 of the patent application range, wherein the vertical projection of the light sensor on the display medium layer partially overlaps with the vertical projection of the light shielding layer on the display medium layer. The display panel as described in item 1 of the patent application scope, wherein the light sensors are respectively located in a plurality of pixel regions of the display panel, the display panel further includes a circuit layer, and is located in the first thin film transistor Between the pixel electrode, the photo sensors and the light shielding layer form a plurality of overlapping areas, and the overlapping areas are equal to each other. A display panel, comprising: at least one thin film transistor; a circuit layer electrically connected to the thin film transistor; a pixel definition layer arranged on the circuit layer; a plurality of light emitting elements arranged on the circuit layer and transmitting The circuit layer is electrically connected to the thin film transistor, wherein the light-emitting elements respectively include a plurality of light-emitting layers located in the pixel-defining layer; and a plurality of light sensors are disposed on the pixel-defining layer, The display panel has a plurality of pixel areas, the photo sensors are located in the pixel areas, and form a plurality of overlapping areas with the circuit layer, and the overlapping areas are equal to each other. The display panel as described in item 8 of the patent application scope, wherein in each pixel area, the number of the light-emitting elements is three and is used to provide colored light of different wavelengths respectively, and the number of the light sensors is One, and the one light sensor will be located on the same side of the three light emitting elements. The display panel as described in item 8 of the patent application scope, wherein the thin film transistor, the circuit layer, the pixel definition layer and the light emitting elements are formed on a first substrate, and the light sensors are formed in a On the second substrate, the thin film transistor, the circuit layer, the pixel definition layer, the light emitting elements and the light sensors are located between the first substrate and the second substrate, and the display panel At least one dielectric layer is included between the pixel definition layer and the light sensors.

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