TW202008567A - Methods for forming three-dimensional memory devices - Google Patents
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Abstract
Description
本公開的實施例涉及三維(3D)記憶體裝置及其製造方法。Embodiments of the present disclosure relate to three-dimensional (3D) memory devices and methods of manufacturing the same.
通過改進製程技術、電路設計、程式設計演算法和製造製程,將平面儲存單元縮放到更小的尺寸。然而,隨著儲存單元的特徵尺寸接近下限,平面製程和製造技術變得具有挑戰性且成本高。結果,平面儲存單元的儲存密度接近上限。By improving process technology, circuit design, programming algorithms and manufacturing processes, the planar storage unit is scaled to a smaller size. However, as the feature size of the storage unit approaches the lower limit, planar manufacturing processes and manufacturing techniques become challenging and costly. As a result, the storage density of the planar storage unit approaches the upper limit.
3D記憶體架構可以解決平面儲存單元中的密度限制。3D記憶體架構包括儲存陣列和用於控制進出儲存陣列的信號的週邊設備。The 3D memory architecture can solve the density limitation in planar storage units. The 3D memory architecture includes a storage array and peripheral devices for controlling signals entering and exiting the storage array.
本文公開了用於形成3D記憶體裝置的方法的實施例。Disclosed herein is an embodiment of a method for forming a 3D memory device.
在一個示例中,公開了一種用於形成3D記憶體裝置的方法。週邊設備形成在第一襯底上。在第一襯底上的週邊設備之上形成第一互連層。在第二襯底上形成包括複數個介電/犧牲層對和複數個記憶體串的介電堆疊層,每個記憶體串垂直延伸穿過介電堆疊層。在第二襯底上的記憶體串之上形成第二互連層。將第一襯底和第二襯底鍵合,使得第一互連層在第二互連層之下並與該第二互連層接觸。在鍵合之後,將第二襯底減薄。通過用複數個導體層替換介電/犧牲層對中的犧牲層,將儲存堆疊層形成在減薄的第二襯底之下並包括複數個導體/介電層對。In one example, a method for forming a 3D memory device is disclosed. The peripheral device is formed on the first substrate. A first interconnect layer is formed on the peripheral device on the first substrate. A dielectric stack layer including a plurality of dielectric/sacrificial layer pairs and a plurality of memory strings is formed on the second substrate, and each memory string extends vertically through the dielectric stack layer. A second interconnect layer is formed on the memory string on the second substrate. The first substrate and the second substrate are bonded so that the first interconnect layer is below and in contact with the second interconnect layer. After bonding, the second substrate is thinned. By replacing the sacrificial layer in the dielectric/sacrificial layer pair with a plurality of conductor layers, the storage stack layer is formed under the thinned second substrate and includes a plurality of conductor/dielectric layer pairs.
在另一個示例中,公開了一種用於形成3D記憶體裝置的方法。週邊設備形成在第一襯底上。在第一襯底上的週邊設備之上形成第一互連層。每個垂直延伸的複數個記憶體串形成在第二襯底上。在第二襯底上的記憶體串之上形成第二互連層。將第一襯底和第二襯底鍵合,使得第一互連層在第二互連層之下並與第二互連層接觸。在鍵合之後,將第二襯底減薄。儲存堆疊層形成在減薄的第二襯底之下並包括複數個導體/介電層對。在儲存堆疊層的階梯結構中的沿著遠離第一襯底的垂直方向的導體/介電層對的邊緣朝向記憶體串橫向交錯排列。In another example, a method for forming a 3D memory device is disclosed. The peripheral device is formed on the first substrate. A first interconnect layer is formed on the peripheral device on the first substrate. A plurality of memory strings each extending vertically are formed on the second substrate. A second interconnect layer is formed on the memory string on the second substrate. The first substrate and the second substrate are bonded so that the first interconnect layer is below and in contact with the second interconnect layer. After bonding, the second substrate is thinned. The storage stack layer is formed under the thinned second substrate and includes a plurality of conductor/dielectric layer pairs. In the stepped structure of the storage stack layer, the edges of the conductor/dielectric layer pair along the vertical direction away from the first substrate are laterally staggered toward the memory string.
在又一個示例中,公開了一種用於形成3D記憶體裝置的方法。每個垂直延伸的複數個記憶體串形成在襯底上。在記憶體串之上形成互連層。將襯底上下翻轉,使得襯底位於記憶體串之上。在翻轉之後將襯底減薄。在減薄之後,將儲存堆疊層形成在減薄的襯底之下並且包括複數個導體/介電層對。形成複數個第一通孔觸點,使得每個第一通孔觸點在導體/介電層對中的一個導體/介電層對的導體層之上並與該導體層接觸。In yet another example, a method for forming a 3D memory device is disclosed. A plurality of memory strings each extending vertically are formed on the substrate. An interconnect layer is formed on the memory string. Turn the substrate upside down so that the substrate is above the memory string. After turning over, the substrate is thinned. After thinning, the storage stack layer is formed under the thinned substrate and includes a plurality of conductor/dielectric layer pairs. A plurality of first via contacts are formed such that each first via contact is above and in contact with the conductor layer of one conductor/dielectric layer pair of the conductor/dielectric layer pair.
儘管對具體配置和佈置進行了討論,但應當理解,這只是出於示例性目的而進行的。相關領域中的技術人員將認識到,可以使用其它配置和佈置而不脫離本公開的精神和範圍。對相關領域的技術人員顯而易見的是,本公開還可以用於多種其它應用中。Although specific configurations and arrangements have been discussed, it should be understood that this is for exemplary purposes only. Those skilled in the relevant art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the relevant art that the present disclosure can also be used in a variety of other applications.
要指出的是,在說明書中提到“一個實施例”、“實施例”、“示例性實施例”、“一些實施例”等指示所述的實施例可以包括特定特徵、結構或特性,但未必每個實施例都包括該特定特徵、結構或特性。此外,這樣的短語未必是指同一個實施例。另外,在結合實施例描述特定特徵、結構或特性時,結合其它實施例(無論是否明確描述)實現這種特徵、結構或特性應在相關領域技術人員的知識範圍內。It should be noted that references to "one embodiment", "embodiments", "exemplary embodiments", "some embodiments", etc. in the specification indicate that the described embodiments may include specific features, structures or characteristics, but Not every embodiment includes this particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. In addition, when a specific feature, structure, or characteristic is described in conjunction with an embodiment, it should be within the knowledge of those skilled in the relevant art to implement such feature, structure, or characteristic in combination with other embodiments (whether or not explicitly described).
通常,可以至少部分從上下文中的使用來理解術語。例如,至少部分取決於上下文,本文中使用的術語“一個或複數個”可以用於描述單數意義的特徵、結構或特性,或者可以用於描述複數意義的特徵、結構或特性的組合。類似地,至少部分取決於上下文,諸如“一”或“所述”的術語可以被理解為傳達單數使用或傳達複數使用。另外,術語“基於”可以被理解為不一定旨在傳達一組排他性的因素,而是可以替代地,至少部分地取決於上下文,允許存在不一定明確描述的其他因素。Generally, terminology can be understood at least in part from use in context. For example, depending at least in part on the context, the term "one or plural" as used herein may be used to describe features, structures, or characteristics in the singular, or may be used to describe combinations of features, structures, or characteristics in the plural. Similarly, depending at least in part on the context, terms such as "a" or "said" may be understood to convey singular or plural usage. In addition, the term "based on" may be understood as not necessarily intended to convey a set of exclusive factors, but may instead, depending at least in part on the context, allow other factors that are not necessarily explicitly described.
應當容易理解,本公開中的“在…上”、“在…之上”和“在…上方”的含義應當以最寬方式被解讀,以使得“在…上”不僅表示“直接在”某物“上”而且還包括在某物“上”且其間有居間特徵或層的含義,並且“在…之上”或“在…上方”不僅表示“在”某物“之上”或“上方”的含義,而且還可以包括其“在”某物“之上”或“上方”且其間沒有居間特徵或層(即,直接在某物上)的含義。It should be easily understood that the meanings of "on", "above", and "above" in this disclosure should be interpreted in the broadest way so that "on" not only means "directly on" "On" also includes "on" something with intervening features or layers in between, and "above" or "above" not only means "above" or "above" The meaning of "" may also include the meaning of "over" or "above" something without intervening features or layers (ie, directly on something).
此外,諸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空間相關術語在本文中為了描述方便可以用於描述一個元件或特徵與另一個或複數個元件或特徵的關係,如在附圖中示出的。空間相關術語旨在涵蓋除了在附圖所描繪的取向之外的在設備使用或操作中的不同取向。設備可以以另外的方式被定向(旋轉90度或在其它取向),並且本文中使用的空間相關描述詞可以類似地被對應解釋。In addition, space-related terms such as “below”, “below”, “lower”, “above”, “upper”, etc. are used herein to describe an element or feature and another for convenience of description The relationship of one or more elements or features is shown in the drawings. Spatially related terms are intended to cover different orientations in the use or operation of the device than those depicted in the drawings. The device can be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially related descriptors used herein can be similarly interpreted accordingly.
如本文中使用的,術語“襯底”是指向其上增加後續材料的材料。可以對襯底自身進行圖案化。增加在襯底的頂部上的材料可以被圖案化或可以保持不被圖案化。此外,襯底可以包括寬範圍的半導體材料,例如矽、鍺、砷化鎵、磷化銦等。替代地,襯底可以由諸如玻璃、塑膠或藍寶石晶圓的非導電材料製成。As used herein, the term "substrate" refers to a material on which subsequent materials are added. The substrate itself can be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic or sapphire wafer.
如本文中使用的,術語“層”是指包括具有厚度的區域的材料部分。層可以在下方或上方結構的整體之上延伸,或者可以具有小於下方或上方結構範圍的範圍。此外,層可以是厚度小於連續結構的厚度的均質或非均質連續結構的區域。例如,層可以位於在連續結構的頂表面和底表面之間或在頂表面和底表面處的任何水平面對之間。層可以水準、豎直或/及沿傾斜表面延伸。襯底可以是層,其中可以包括一個或複數個層,或/及可以在其上、其上方或/及其下方具有一個或複數個層。層可以包括複數個層。例如,互連層可以包括一個或複數個導體和接觸層(其中形成互連線或/及通孔觸點)和一個或複數個介電層。As used herein, the term "layer" refers to a portion of material that includes regions with thickness. The layer can extend over the entirety of the underlying or superstructure, or can have a range that is less than the extent of the underlying or superstructure. In addition, the layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than that of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure or between any horizontal faces at the top and bottom surfaces. The layer can extend horizontally, vertically or/and along inclined surfaces. The substrate may be a layer, which may include one or more layers, or/and may have one or more layers on, above, and/or below it. The layer may include a plurality of layers. For example, the interconnect layer may include one or more conductors and contact layers (where interconnect lines or/and via contacts are formed) and one or more dielectric layers.
如本文使用的,術語“標稱/標稱地”是指在生產或過程的設計階段期間設置的針對部件或過程操作的特性或參數的期望或目標值,以及高於或/及低於期望值的值的範圍。值的範圍可能是由於製造過程或容限中的輕微變化導致的。如本文使用的,術語“大約”指示可以基於與主題半導體裝置相關聯的特定技術節點而變化的給定量的值。基於特定技術節點,術語“大約”可以指示給定量的值,其例如在值的10%-30%(例如,值的±10%、±20%或±30%)內變化。As used herein, the term “nominal/nominally” refers to a desired or target value for a characteristic or parameter of a component or process operation set during the design phase of production or process, and above or/and below expected value Range of values. The range of values may be due to slight changes in the manufacturing process or tolerances. As used herein, the term "approximately" indicates a given amount of value that may vary based on the specific technology node associated with the subject semiconductor device. Based on a particular technology node, the term "about" may indicate a given amount of value, which varies, for example, within 10%-30% of the value (eg, ±10%, ±20%, or ±30% of the value).
如本文所使用的,術語“3D記憶體裝置”指的是在橫向取向的襯底上具有垂直取向的儲存單元電晶體串(在本文中稱為“記憶體串”,例如NAND記憶體串)使得記憶體串相對於襯底在垂直方向上延伸的半導體裝置。如本文所使用的,術語“垂直/垂直地”意味著標稱上正交於襯底的橫向表面。As used herein, the term "3D memory device" refers to a string of memory cell transistors having a vertical orientation on a laterally oriented substrate (referred to herein as a "memory string", such as a NAND memory string) A semiconductor device that makes the memory string extend in a vertical direction with respect to the substrate. As used herein, the term "vertically/vertically" means nominally orthogonal to the lateral surface of the substrate.
與其他3D記憶體裝置相比,根據本公開的各種實施例提供了用於形成具有更小晶粒尺寸、更高單元密度和改進性能的3D記憶體裝置的方法。通過在週邊設備晶片之上垂直堆疊儲存陣列元件晶片,可以增加所得到的3D記憶體裝置的單元密度。此外,通過使週邊設備處理和儲存陣列元件處理去耦,與處理儲存陣列元件相關聯的熱預算不受週邊設備的性能要求的限制。類似地,週邊設備性能不受儲存陣列元件處理的影響。例如,週邊設備和儲存陣列元件可以分別製造在不同的襯底上,使得用於製造儲存陣列元件的某些高溫製程不會不利地影響週邊設備的製造(例如,避免摻雜物的過度擴散,控制離子注入的摻雜濃度或/及厚度等)。Compared with other 3D memory devices, various embodiments according to the present disclosure provide a method for forming a 3D memory device having a smaller grain size, higher cell density, and improved performance. By vertically stacking storage array element wafers on peripheral device wafers, the cell density of the resulting 3D memory device can be increased. Furthermore, by decoupling peripheral device processing from storage array element processing, the thermal budget associated with processing the storage array element is not limited by the performance requirements of the peripheral device. Similarly, peripheral device performance is not affected by storage array element processing. For example, peripheral devices and storage array elements can be fabricated on different substrates, respectively, so that certain high-temperature processes used to manufacture storage array elements do not adversely affect the manufacture of peripheral devices (eg, to avoid excessive diffusion of dopants, Control the doping concentration or thickness of ion implantation, etc.).
第1圖示出了根據本公開的一些實施例的示例性3D記憶體裝置100的橫截面。3D記憶體裝置100表示非單片3D記憶體裝置的示例。術語“非單片”意指3D記憶體裝置100的元件(例如,週邊設備和儲存陣列元件)可以在不同的襯底上單獨形成,然後連接以形成3D記憶體裝置。3D記憶體裝置100可包括襯底102,襯底102可包括矽(例如,單晶矽)、矽鍺(SiGe)、砷化鎵(GaAs)、鍺(Ge)、絕緣體上矽(SOI)或任何其他合適的材料。FIG. 1 shows a cross-section of an exemplary
3D記憶體裝置100可以包括襯底102上的週邊設備。週邊設備可以形成在襯底102“上”,其中週邊設備的整體或部分形成在襯底102中(例如,在襯底102的頂表面之下)或/及直接形成在襯底102上。週邊設備可以包括形成在襯底102上的複數個電晶體104。隔離區(例如,淺溝槽隔離(STI),未示出)和摻雜區(例如,電晶體104的源極區和汲極區,未繪示出)也可以形成在襯底102中。The
在一些實施例中,週邊設備可以包括用於便於3D記憶體裝置100的操作的任何合適的數位、類比或/及混合信號週邊電路。例如,週邊設備可以包括一個或複數個頁面緩衝器、解碼器(例如,行解碼器和列解碼器)、讀出放大器、驅動器、電荷泵、電流或電壓基準源、或電路的任何主動或被動元件(例如,電晶體、二極體、電阻器或電容器)。在一些實施例中,使用互補金屬氧化物半導體(CMOS)技術(也稱為“CMOS晶片”)在襯底102上形成週邊設備。In some embodiments, the peripheral devices may include any suitable digital, analog, and/or mixed signal peripheral circuits for facilitating the operation of the
3D記憶體裝置100可包括電晶體104之上的互連層(本文稱為“週邊互連層106”)以將電信號傳輸到電晶體104和從電晶體104傳輸電信號。週邊互連層106可包括複數個互連(本文也稱為“觸點”),包括橫向互連線108和垂直互連接入(通孔)觸點110。如本文所用,術語“互連”可以廣泛地包括任何合適類型的互連,例如中段製程(MEOL)互連和後段製程(BEOL)互連。週邊互連層106還可以包括一個或複數個層間介電(ILD)層(也稱為“金屬間介電(IMD)層”),其中可以形成互連線108和通孔觸點110。也就是說,週邊互連層106可以包括複數個ILD層中的互連線108和通孔觸點110。週邊互連層106中的互連線108和通孔觸點110可包括導電材料,其包括但不限於鎢(W)、鈷(Co)、銅(Cu)、鋁(Al)、矽化物或其任何組合。週邊互連層106中的ILD層可以包括介電材料,其包括但不限於氧化矽、氮化矽、氮氧化矽、低介電常數(低k)介電材料或其任何組合。The
在一些實施例中,週邊互連層106還包括在週邊互連層106的頂表面處的複數個鍵合觸點112。鍵合觸點112可包括導電材料,其包括但不限於W、Co、Cu、Al、矽化物或其任何組合。週邊互連層106的頂表面處的剩餘區域可以用介電材料形成,介電材料包括但不限於氧化矽、氮化矽、氮氧化矽、低k介電材料或其任何組合。在週邊互連層106的頂表面處的(鍵合觸點112的)導電材料和介電材料可以用於混合鍵合,如下面詳細描述。In some embodiments, the
3D記憶體裝置100可以包括在週邊設備之上的儲存陣列元件。請注意,x軸和y軸被包括在第1圖中,以進一步示出3D記憶體裝置100中的元件的空間關係。襯底102包括在x方向(即,橫向方向或寬度方向)上橫向延伸的兩個橫向表面(例如,頂表面和底表面)。如本文所使用的,一個元件(例如,層或元件)是否在半導體裝置(例如,3D記憶體裝置100)的另一元件(例如,層或元件)“上”、“之上”或“之下”是在襯底在y方向上位於半導體裝置的最低部平面中時、相對於半導體裝置的襯底(例如,襯底102)在y方向(即,垂直方向或厚度方向)上所確定的。在整個本公開中均採用用於描述空間關係的相同概念。The
在一些實施例中,3D記憶體裝置100是NAND快閃記憶體裝置,其中儲存單元以NAND記憶體串114的陣列的形式提供,每個NAND記憶體串114在週邊設備(例如,電晶體104)和襯底102之上垂直延伸。儲存陣列元件可以包括NAND記憶體串114,其垂直延伸穿過多個對,每個對包括導體層116和介電層118(本文稱為“導體/介電層對”)。堆疊的導體/介電層對在本文也稱為“儲存堆疊層”120。儲存堆疊層120中的導體層116和介電層118在垂直方向上交替。換句話說,除了在儲存堆疊層120的頂部或底部處的導體/介電層對之外,每個導體層116可以在兩側與兩個介電層118鄰接,並且每個介電層118可以在兩側與兩個導體層116鄰接。導體層116可各自具有相同的厚度或不同的厚度。類似地,介電層118可各自具有相同的厚度或不同的厚度。導體層116可包括導體材料,其包括但不限於W、Co、Cu、Al、摻雜矽、矽化物或其任何組合。介電層118可包括介電材料,其包括但不限於氧化矽、氮化矽、氮氧化矽或其任何組合。In some embodiments, the
儲存堆疊層120可包括內部區域(也稱為“核心陣列區域”)和外部區域(也稱為“階梯區域”)。在一些實施例中,內部區域是儲存堆疊層120的中心區域,其中形成NAND記憶體串114的陣列,並且外部區域是儲存堆疊層120的圍繞內部區域的剩餘區域(包括側面和邊緣)。如第1圖所示,至少在一個側面上,儲存堆疊層120的外部區域可以包括階梯結構122。儲存堆疊層120的階梯結構122中的沿著遠離襯底102的垂直方向(正y方向)的導體/介電層對的邊緣朝向NAND記憶體串114的陣列橫向交錯排列。換句話說,階梯結構122中的儲存堆疊層120的邊緣可以隨著遠離襯底102(從底部到頂部)移動而朝向內部區域傾斜。階梯結構122的斜面可以背向襯底102。在一些實施例中,儲存堆疊層120的每個導體/介電層對的長度從頂部到底部增加。The
在一些實施例中,階梯結構122中的每兩個相鄰導體/介電層對在垂直方向上偏移標稱上相同的距離,並且在橫向方向上偏移標稱上相同的距離。因此,每個偏移可以形成用於垂直方向上字元線扇出的“著陸區域”。導體/介電層對中的一些導體層116可以用作3D記憶體裝置100的字元線,並且橫向延伸到階梯結構122中以用於互連。如第1圖所示,根據一些實施例,階梯結構122中的每個相鄰導體/介電層對的邊緣的偏移標稱上是相同的。In some embodiments, every two adjacent conductor/dielectric layer pairs in the stepped
如第1圖所示,每個NAND記憶體串114可以垂直延伸穿過儲存堆疊層120的內部區域,並且包括半導體通道124和介電層(也稱為“儲存膜”)。在一些實施例中,半導體通道124包括矽,例如非晶矽、多晶矽或單晶矽。在一些實施例中,儲存膜是複合層,包括穿隧層126、儲存層128(也稱為“電荷捕獲/儲存層”)和阻隔層(未示出)。每個NAND記憶體串114可以具有圓柱形狀(例如,柱形)。根據一些實施例,半導體通道124、穿隧層126、儲存層128和阻隔層依此順序從柱的中心朝向外表面徑向佈置。穿隧層126可包括氧化矽、氮氧化矽或其任意組合。儲存層128可包括氮化矽、氮氧化矽、矽或其任意組合。阻隔層可包括氧化矽、氮氧化矽、高介電常數(高k)介電材料或其任意組合。As shown in FIG. 1, each
在一些實施例中,NAND記憶體串114還包括複數個控制閘極(每個控制閘極是字元線的一部分)。儲存堆疊層120中的每個導體層116可以用作NAND記憶體串114的每個儲存單元的控制閘極。每個NAND記憶體串114可以包括在其上端的源極選擇閘極和在其下端的汲極選擇閘極。如本文所使用的,元件(例如,NAND記憶體串114)的“上端”是在y方向上遠離襯底102的端部,並且元件的“下端”(例如,NAND記憶體串114)是在y方向上靠近襯底102的端部。對於每個NAND記憶體串114,汲極選擇閘極可以設置在3D記憶體裝置100中的源極選擇閘極之下。In some embodiments, the
在一些實施例中,3D記憶體裝置100還包括設置在NAND記憶體串114之上並與其接觸的半導體層130,例如,在每個NAND記憶體串114的上端。儲存堆疊層120可以設置在半導體層130之下。半導體層130可以是其上形成儲存堆疊層120的減薄的襯底。在一些實施例中,半導體層130包括通過隔離區(例如,STI)電性隔離的複數個半導體插塞132。在一些實施例中,每個半導體插塞132設置在對應的NAND記憶體串114的上端,並且用作對應的NAND記憶體串114的源極,因此,可以被認為是對應的NAND記憶體串114的一部分。半導體插塞132可以包括單晶矽。半導體插塞132可以是未摻雜的、部分摻雜的(在厚度方向或/及寬度方向上),或者是由p型或n型摻雜物完全摻雜的。在一些實施例中,半導體插塞132可包括SiGe、GaAs、Ge或任何其他合適的材料。在一些實施例中,半導體層130(及其中的半導體插塞132)的厚度在約0.1μm和約50μm之間,例如在0.1μm和50μm之間。在一些實施例中,半導體層130(及其中的半導體插塞132)的厚度在約0.2μm和約5μm之間,例如在0.2μm和5μm之間(例如,0.2μm、0.3μm、0.4μm、0.5μm、0.6μm、0.7μm、0.8μm、0.9μm、1μm、2μm、3μm、4μm、5μm、由下端通過任何這些值限定的任何範圍、或處於由這些值中的任何兩個定義的任何範圍)。In some embodiments, the
在一些實施例中,3D記憶體裝置100還包括垂直延伸穿過儲存堆疊層120的閘極線縫隙(“GLS”)134。GLS 134可用於通過閘極替換製程在儲存堆疊層120中形成導體/介電層對。在一些實施例中,首先用介電材料(例如,氧化矽、氮化矽或其任何組合)填充GLS 134,以將NAND記憶體串陣列分成不同的區域(例如,儲存指狀物或/及儲存塊)。然後,根據一些實施例,GLS 134填充有導電或/及半導體材料(例如,W、Co、多晶矽或其任何組合),以電性控制陣列共通源極(ACS)。In some embodiments, the
在一些實施例中,3D記憶體裝置100包括形成於一個或複數個ILD層中並與儲存堆疊層120中的元件(例如字元線(例如,導體層116)和NAND記憶體串114)接觸的局部互連。互連在本文中稱為“局部互連”,因為它們直接與儲存堆疊層120中的元件接觸以扇出。如本文所使用的,術語“互連”可以廣泛地包括任何合適類型的互連,包括垂直互連接入(例如,通孔)觸點和橫向互連線。局部互連可以包括字元線通孔觸點136、位元線通孔觸點138和源極線通孔觸點140。每個局部互連可以包括填充有導電材料的開口(例如,通孔或溝槽),導電材料包括但不限於W、Co、Cu、Al、矽化物或其任何組合。In some embodiments, the
字元線通孔觸點136可以垂直延伸穿過一個或複數個ILD層。每個字元線通孔觸點136可以使其下端與儲存堆疊層120的階梯結構122中的對應導體層116(例如,在著陸區域處)接觸,以單獨定址3D記憶體裝置100的對應字元線。在一些實施例中,每個字元線通孔觸點136設置在對應的導體層116之上。每個位元線通孔觸點138可以設置在儲存堆疊層120之下,並使其上端與對應的NAND記憶體串114的下端(汲極端)接觸,以單獨定址對應的NAND記憶體串114。根據一些實施例,多個位元線通孔觸點138分別設置在複數個NAND記憶體串114之下並與其接觸。如第1圖所示,字元線通孔觸點136和位元線通孔觸點138將對應的儲存堆疊層元件朝向相反的垂直方向(正y方向和負y方向)扇出。源極線通孔觸點140可以垂直延伸穿過一個或複數個ILD層。每個源極線通孔觸點140可以使其下端與NAND記憶體串114的對應半導體插塞132(例如,源極)接觸。在一些實施例中,每個源極線通孔觸點140設置在對應的NAND記憶體串114之上。The word line via
與週邊設備類似,3D記憶體裝置100的儲存陣列元件還可以包括用於將電信號傳輸到NAND記憶體串114和從NAND記憶體串114傳輸電信號的互連層。如第1圖所示,3D記憶體裝置100可以包括NAND記憶體串114之下的互連層(本文稱為“陣列互連層142”)。陣列互連層142可以包括複數個互連,其包括一個或複數個ILD層中的互連線144和通孔觸點146。在一些實施例中,陣列互連層142包括在其底表面處的複數個鍵合觸點148。互連線144、通孔觸點146和鍵合觸點148可包括導電材料,其包括但不限於W、Co、Cu、Al、矽化物或其任何組合。陣列互連層142的底表面處的剩餘區域可以用介電材料形成,介電材料包括但不限於氧化矽、氮化矽、氮氧化矽、低k介電材料或其任何組合。在陣列互連層142的底表面處的(鍵合觸點148的)導電材料和介電材料可以用於混合鍵合,如下面詳細描述。Similar to peripheral devices, the storage array element of the
如第1圖所示,另一個互連層(本文稱為“BEOL互連層150”)可以設置在NAND記憶體串114和半導體層130之上,並且可以包括互連,例如一個或複數個ILD層中的互連線152和通孔觸點154。BEOL互連層150還可以包括在3D記憶體裝置100的頂表面處的接觸墊156和再分佈層(未示出),用於引線鍵合或/及與中介層的鍵合。BEOL互連層150和陣列互連層142可以形成在NAND記憶體串114的相對側。在一些實施例中,BEOL互連層150中的互連線152、通孔觸點154和接觸墊156可以在3D記憶體裝置100和外部電路之間傳輸電信號。BEOL互連層150可以通過局部互連電連接到儲存堆疊層元件。如第1圖所示,每個字元線通孔觸點136可以使其上端與BEOL互連層150接觸。類似地,每個源極線通孔觸點140可以使其上端與BEOL互連層150接觸。階梯結構122和半導體層130的佈置和配置允許通過局部互連(例如,字元線通孔觸點136和源極線通孔觸點140)和BEOL互連層150直接扇出字元線(例如,導體層116)和NAND記憶體串114的源極,而不繞過陣列互連層142。As shown in FIG. 1, another interconnection layer (referred to herein as "
在一些實施例中,3D記憶體裝置100還包括穿過儲存堆疊層120垂直延伸的一個或複數個貫穿陣列觸點(TAC,未示出)。每個TAC可以延伸穿過整個儲存堆疊層120(例如,所有其中的導體/介電層對),並使其上端與BEOL互連層150接觸並使其下端與陣列互連層142接觸。因此,TAC可以在週邊互連層106和BEOL互連層150之間形成電連接,並且將電信號從3D記憶體裝置100的週邊設備傳送到的BEOL互連。In some embodiments, the
鍵合界面158可以形成在週邊互連層106和陣列互連層142之間。鍵合觸點112可以在鍵合界面158處與鍵合觸點148鍵合。如第1圖所示,週邊設備(例如,電晶體104)可以在鍵合之後設置在3D記憶體裝置100中的儲存陣列元件(例如,NAND記憶體串114)之下。在3D記憶體裝置100中,根據一些實施例,鍵合界面158設置在儲存陣列元件(例如,NAND記憶體串114)和週邊設備(例如,電晶體104)之間。週邊互連層106可以在鍵合界面158和週邊設備(例如,電晶體104)之間,並且陣列互連層142可以在鍵合界面158和儲存陣列元件(例如,NAND記憶體串114)之間。The
在一些實施例中,包括NAND記憶體串114、半導體層130(例如,減薄的襯底)、陣列互連層142、BEOL互連層150、以及字元線通孔觸點136的第一半導體結構(例如,儲存陣列元件晶片160)以面對面的方式在鍵合界面158處鍵合到包括襯底102、週邊設備(例如,電晶體104)和週邊互連層106的第二半導體結構(例如,週邊設備晶片162)。陣列互連層142可以在鍵合界面158處接觸週邊互連層106。週邊設備晶片162和儲存陣列元件晶片160可以使用混合鍵合(也稱為“金屬/介電混合鍵合”)來鍵合,這是一種直接鍵合技術(例如,在不使用中間層的情況下在表面之間形成鍵合,例如焊料或黏合劑),並且可以同時獲得金屬-金屬鍵合和介電材料-介電材料鍵合。可以在鍵合觸點148和鍵合觸點112之間形成金屬-金屬鍵合,並且可以在鍵合界面158處的剩餘區域處的介電材料之間形成介電材料-介電材料鍵合。In some embodiments, the first including
第2A圖至第2B圖示出了根據一些實施例的用於形成示例性週邊設備晶片的製程。第3A圖至第3D圖示出了根據一些實施例的用於形成示例性儲存陣列元件晶片的製程。第4A圖至第4F圖示出了根據一些實施例的用於形成示例性3D記憶體裝置的製程,其中儲存陣列元件晶片鍵合到週邊設備晶片。第5圖是根據一些實施例的用於形成示例性週邊設備晶片的方法500的流程圖。第6圖是根據一些實施例的用於形成示例性儲存陣列元件晶片的方法600的流程圖。第7圖是根據一些實施例的用於形成示例性3D記憶體裝置的方法700的流程圖,其中儲存陣列元件晶片鍵合到週邊設備晶片。第2圖至第7圖中示出的3D記憶體裝置的示例包括第1圖中示出的3D記憶體裝置100。將一起描述第2圖至第7圖。應當理解,方法500、600和700中所示的操作不是詳盡的,並且也可以在所例舉的任何操作之前、之後或之間執行其他操作。此外,一些操作可以同時執行,或者以與第5圖至第7圖中所示不同的順序來執行。FIGS. 2A-2B illustrate a process for forming an exemplary peripheral device wafer according to some embodiments. FIGS. 3A to 3D illustrate a process for forming an exemplary memory array device wafer according to some embodiments. FIGS. 4A to 4F illustrate a process for forming an exemplary 3D memory device in which a storage array element wafer is bonded to a peripheral device wafer according to some embodiments. FIG. 5 is a flowchart of a
參照第5圖,方法500開始於操作502,其中將週邊設備形成在第一襯底上。襯底可以是矽襯底。如第2A圖所示,週邊設備形成在矽襯底202上。週邊設備可以包括形成在矽襯底202上的複數個電晶體204。電晶體204可以通過多種製程形成,包括但不限於微影、乾式/濕式蝕刻、薄膜沉積、熱生長、植入、化學機械研磨(CMP)和任何其他合適的製程。在一些實施例中,通過離子植入或/及熱擴散在矽襯底202中形成摻雜區(未示出),其例如用作電晶體204的源極區或/及汲極區。在一些實施例中,隔離區(例如,STI,未示出)也通過濕式/乾式蝕刻和薄膜沉積形成在矽襯底202中。Referring to FIG. 5, the
方法500前進到操作504,如第5圖所示,其中在週邊設備之上形成第一互連層(例如,週邊互連層)。週邊互連層可以包括一個或複數個ILD層中的第一複數個互連。方法500前進到操作506,如第5圖所示,其中第一複數個鍵合觸點形成在週邊互連層的頂表面處。The
如第2B圖所示,週邊互連層206可以形成在電晶體204之上。週邊互連層206可以包括互連,其包括複數個ILD層中的週邊設備晶片的MEOL或/及BEOL的互連線208和通孔觸點210,以製造與週邊設備(例如,電晶體204)的電連接。可以在週邊互連層206的頂表面處形成鍵合觸點212以用於混合鍵合。在一些實施例中,週邊互連層206包括由複數個製程形成的複數個ILD層和其中的互連。例如,互連線208、通孔觸點210和鍵合觸點212可包括通過一個或複數個薄膜沉積製程沉積的導電材料,薄膜沉積製程包括但不限於化學氣相沉積(CVD)、物理氣相沉積(PVD)、原子層沉積(ALD)、電鍍、化學鍍或其任何組合。形成互連線208、通孔觸點210和鍵合觸點212的製程還可以包括微影、CMP、濕式/乾式蝕刻或任何其他合適的製程。ILD層可包括通過一種或多種薄膜沉積製程沉積的介電材料,薄膜沉積製程包括但不限於CVD、PVD、ALD或其任何組合。第2B圖中所示的ILD層和互連可以統稱為“互連層”(例如,週邊互連層206)。As shown in FIG. 2B, the
參照第6圖,方法600包括操作602,其中在第二襯底上形成介電堆疊層。襯底可以是矽襯底。介電堆疊層可包括複數個介電/犧牲層對。如第3A圖所示,通過濕式/乾式蝕刻和薄膜沉積在矽襯底302中形成隔離區304(例如,STI),以電性隔離矽插塞306(例如,單晶矽插塞)。可以使用離子植入或/及熱擴散製程將矽插塞306圖案化並摻雜有n型或p型摻雜物。在一些實施例中,隔離區304和矽插塞306的厚度在約0.1μm和約50μm之間,例如在0.1μm和50μm之間。在一些實施例中,隔離區304和矽插塞306的厚度在約0.2μm和約5μm之間,例如在0.2μm和5μm之間(例如,0.2μm、0.3μm、0.4μm、0.5μm、0.6μm、0.7μm、0.8μm、0.9μm、1μm、2μm、3μm、4μm、5μm、由下端通過任何這些值限定的任何範圍、或處於由這些值中的任何兩個限定的任何範圍)。Referring to FIG. 6,
如第3B圖所示,在矽襯底302上形成成對的第一介電層310和第二介電層(稱為“犧牲層”)312(本文統稱為“介電層對”)。堆疊的介電層對可以形成介電堆疊層308。介電堆疊層308可以包括犧牲層312和與犧牲層312不同的介電層310的交替堆疊層。在一些實施例中,每個介電層對包括氮化矽層和氧化矽層。在一些實施例中,犧牲層312可各自具有相同的厚度或具有不同的厚度。類似地,介電層310可各自具有相同的厚度或具有不同的厚度。介電堆疊層308可以通過一種或多種薄膜沉積製程形成,薄膜沉積製程包括但不限於CVD、PVD、ALD或其任何組合。As shown in FIG. 3B, a pair of first
方法600前進到操作604,如第6圖所示,其中形成複數個記憶體串,每個記憶體串垂直延伸穿過介電堆疊層。如第3C圖所示,NAND記憶體串314形成在矽襯底302上,每個NAND記憶體串垂直延伸穿過介電堆疊層308。在一些實施例中,每個NAND記憶體串314可以與對應的矽插塞306對準。矽插塞306可以是NAND記憶體串314的一部分。在一些實施例中,形成NAND記憶體串314的製程包括形成垂直延伸穿過介電堆疊層308的半導體通道316。在一些實施例中,形成NAND記憶體串314的製程還包括在半導體通道316和介電堆疊層308中的複數個介電/犧牲層對之間形成複合介電層(儲存膜)。儲存膜可以是複數個介電層的組合,其包括但不限於穿隧層318、儲存層320和阻隔層。The
穿隧層318可包括介電材料,其包括但不限於氧化矽、氮化矽、氮氧化矽或其任何組合。儲存層320可以包括用於儲存用於記憶體操作的電荷的材料。儲存層材料可包括但不限於氮化矽、氮氧化矽、氧化矽和氮化矽的組合、或其任何組合。阻隔層可以包括介電材料,其包括但不限於氧化矽、或氧化矽/氧氮化矽/氧化矽(ONO)的組合。阻隔層還可以包括高k介電層,例如氧化鋁層。半導體通道316和儲存膜(包括穿隧層318和儲存層320)可以通過諸如ALD、CVD、PVD、任何其他合適的製程或其任何組合之類的製程形成。The
方法600前進到操作606,如第6圖所示,其中在記憶體串之上形成第二互連層(例如,陣列互連層)。陣列互連層可以包括一個或複數個ILD層中的第二複數個互連。方法600前進到操作608,如第6圖所示,其中第二複數個鍵合觸點形成在陣列互連層的頂表面處。如第3D圖所示,陣列互連層322可以形成在介電堆疊層308和NAND記憶體串314之上。陣列互連層322可以包括互連,其包括一個或複數個ILD層中的互連線324和通孔觸點326,以用於將電信號傳輸到NAND記憶體串314和從NAND記憶體串314傳輸電信號。在一些實施例中,位元線通孔觸點321可以在形成陣列互連層322之前形成在介電堆疊層308之上形成的ILD層中,使得每個位元線通孔觸點321在對應的NAND記憶體串314之上並與之接觸。鍵合觸點328可以形成在陣列互連層322的頂表面處,以用於混合鍵合。The
在一些實施例中,陣列互連層322包括在複數個製程中形成的複數個ILD層和其中的互連。例如,互連線324、通孔觸點326和鍵合觸點328可包括通過一個或複數個薄膜沉積製程沉積的導電材料,薄膜沉積製程包括但不限於CVD、PVD、ALD、電鍍、化學鍍或其任何組合。形成互連線324、通孔觸點326和鍵合觸點328的製程還可以包括微影、CMP、濕式/乾式蝕刻或任何其他合適的製程。ILD層可包括通過一種或多種薄膜沉積製程沉積的介電材料,薄膜沉積製程包括但不限於CVD、PVD、ALD或其任何組合。第3D圖中所示的ILD層和互連可以統稱為“互連層”(例如,陣列互連層322)。In some embodiments, the
參照第7圖,方法700包括操作702,其中其上形成記憶體串的第二襯底上下翻轉。結果,第二襯底位於記憶體串之上。方法700進行到操作704,如第7圖所示,其中第二襯底和其上形成有週邊設備的第一襯底以面對面的方式鍵合,使得週邊互連層在陣列互連層之下並與之接觸。鍵合可以是混合鍵合。Referring to FIG. 7, the
如第4A圖所示,矽襯底302和在其上形成的元件(例如,NAND記憶體串314)上下翻轉。面向下的陣列互連層322將與面向上的週邊互連層206鍵合,即,以面對面的方式,使得在所得到的3D記憶體裝置中陣列互連層322可以在週邊互連層206之上並與之接觸。在一些實施例中,陣列互連層322的鍵合觸點328在鍵合之前與週邊互連層206的鍵合觸點214對準。結果,當矽襯底302與矽襯底202連接時,鍵合觸點328可以與鍵合觸點214接觸。在一些實施例中,處理製程(例如等離子體處理、濕式處理或/及熱處理)在鍵合之前被應用到鍵合表面上。作為鍵合(例如,混合鍵合)的結果,鍵合觸點328可以與鍵合觸點214相互混合,從而在陣列互連層322和週邊互連層206之間形成鍵合界面402,如第4B圖所示。As shown in FIG. 4A, the
方法700進行到操作706,如第7圖所示,其中將第二襯底減薄。如第4B圖所示,矽襯底302在減薄之後變成單晶矽層404(包括矽插塞306和周圍的隔離區)。在一些實施例中,在減薄製程之後,單晶矽層404(及其中的矽插塞306)具有在約0.1μm和約50μm之間的厚度,例如在0.1μm和50μm之間。在一些實施例中,單晶矽層404(及其中的矽插塞306)的厚度在約0.2μm和約5μm之間,例如在0.2μm和5μm之間(例如,0.2μm、0.3μm、0.4μm、0.5μm、0.6μm、0.7μm、0.8μm、0.9μm、1μm、2μm、3μm、4μm、5μm、由下端通過任何這些值限定的任何範圍、或處於由這些值中的任何兩個限定的任何範圍)。矽襯底302可以通過包括但不限於晶片研磨、乾式蝕刻、濕式蝕刻、CMP、任何其他合適的製程或其任何組合之類的製程來減薄。The
方法700進行到操作708,如第7圖所示,其中在介電堆疊層的邊緣處形成階梯結構。可以通過對介電/犧牲層對朝向第一襯底執行複數個修整蝕刻循環來形成階梯結構。如第4C圖所示,在介電堆疊層308的邊緣處形成階梯結構406。介電堆疊層308的階梯結構406中的沿著遠離矽襯底202的垂直方向(正y方向)的介電/犧牲層對的邊緣朝向NAND記憶體串314橫向交錯排列。為了形成階梯結構406,可以圖案化光阻層以暴露介電/犧牲層對中頂部的一個介電/犧牲層對的一部分。圖案化的光阻層可以用作蝕刻遮罩,以通過濕式蝕刻或/及乾式蝕刻來蝕刻介電/犧牲層對中頂部的一個介電/犧牲層對的暴露部分。可以使用任何合適的蝕刻劑(例如,濕式蝕刻或/及乾式蝕刻的蝕刻劑)來去除介電/犧牲層對中頂部的一個介電/犧牲層對在暴露部分中的整個厚度(包括其中的犧牲層312和介電層310)。可以通過在介電/犧牲層對中使用的不同材料(例如,氮化矽和氧化矽)上的蝕刻停止來控制蝕刻的厚度。蝕刻介電/犧牲層對中頂部的一個介電/犧牲層對的暴露部分可暴露出在介電/犧牲層對中頂部的一個介電/犧牲層對下方的一個介電/犧牲層對的部分。
然後可以修整圖案化的光阻層(例如,經常從所有方向逐漸地且向內地蝕刻)以暴露介電/犧牲層對中頂部的一個介電/犧牲層對的另一部分。修整的光阻層的量可以通過修整速率或/及修整時間來控制,並且可以與所得到的臺階結構的尺寸直接相關(例如,決定因素)。可以使用任何合適的蝕刻製程,例如,等向性乾式蝕刻或濕式蝕刻,來執行光阻層的修整。使用修整的光阻層作為蝕刻遮罩來蝕刻介電/犧牲層對中頂部的一個介電/犧牲層對擴大的暴露部分和介電/犧牲層對中頂部的一個介電/犧牲層對下方的一個介電/犧牲層對的暴露部分,以形成階梯結構406中的一個臺階結構。可以使用任何合適的蝕刻劑(例如,濕式蝕刻或/及乾式蝕刻的蝕刻劑)來朝向矽襯底202去除暴露部分中的介電/犧牲層對的整個厚度(包括其中的犧牲層312和介電層310)。光阻層的修整製程之後是介電/犧牲層對的蝕刻製程,這在本文中稱為介電/犧牲層對的修整蝕刻循環。The patterned photoresist layer can then be trimmed (eg, often etched gradually and inward from all directions) to expose the other part of the dielectric/sacrificial layer pair on top of the dielectric/sacrificial layer pair. The amount of trimmed photoresist layer can be controlled by the trim rate or/and trim time, and can be directly related to the size of the resulting step structure (eg, determinant). Any suitable etching process may be used, for example, isotropic dry etching or wet etching, to perform trimming of the photoresist layer. Use the trimmed photoresist layer as an etch mask to etch an enlarged exposed portion of the dielectric/sacrificial layer pair on top of the dielectric/sacrificial layer pair and below the dielectric/sacrificial layer pair on top of the dielectric/sacrificial layer pair An exposed portion of a dielectric/sacrificial layer pair to form a stepped structure in the stepped
可以朝向矽襯底202(負y方向)重複介電/犧牲層對的修整-蝕刻循環,直到完成對介電/犧牲層對中底部的一個介電/犧牲層對的蝕刻。因此,可以形成在介電堆疊層308的邊緣處具有複數個臺階結構的階梯結構406。由於介電/犧牲層對的重複的修整-蝕刻循環,介電堆疊層308可以具有傾斜的側邊緣和比底部介電/犧牲層對短的頂部介電/犧牲層對,如第4C圖所示。The trimming-etching cycle of the dielectric/sacrificial layer pair may be repeated toward the silicon substrate 202 (negative y direction) until the etching of the dielectric/sacrificial layer pair at the bottom of the dielectric/sacrificial layer pair is completed. Therefore, a
方法700進行到操作710,如第7圖所示,其中通過用複數個導體層替換介電/犧牲層對中的犧牲層,在減薄的第二襯底之下形成儲存堆疊層。因此,儲存堆疊層包括複數個導體/介電層對。在一些實施例中,形成儲存堆疊層包括蝕刻穿過減薄的第二襯底和介電/犧牲層對的開口、穿過開口蝕刻介電/犧牲層對中的犧牲層、以及穿過開口沉積導體/介電層對中的導體層。結果,可以在儲存堆疊層的邊緣處形成階梯結構。儲存堆疊層的階梯結構中的沿著遠離第一襯底的垂直方向的導體/介電層對的邊緣可以朝向記憶體串橫向交錯排列。The
如第4D圖所示,GLS 408穿過單晶矽層404和介電堆疊層308的介電/犧牲層對而形成。可以通過濕式蝕刻或/及乾式蝕刻來圖案化和蝕刻GLS 408。然後可以穿過GLS 408蝕刻介電堆疊層308的每個犧牲層312(第4C圖中示出),並且可以穿過GLS 408沉積導體層410。也就是說,可以用導體層410替換介電堆疊層308的每個犧牲層312,從而在儲存堆疊層412中形成複數個導體/介電層對。用導體層410替換犧牲層312可以通過對介電層310有選擇地濕式/乾式蝕刻犧牲層312並用導體層410填充結構來執行。導體層410可包括導電材料,其包括但不限於W、Co、Cu、Al、摻雜矽、多晶矽、矽化物或其任何組合。導體層410可以通過諸如CVD、ALD、任何其他合適的製程、或其任何組合之類的薄膜沉積製程來填充。As shown in FIG. 4D,
結果,NAND記憶體串314每個均可以垂直延伸穿過儲存堆疊層412。在一些實施例中,儲存堆疊層412中的導體層410用於形成NAND記憶體串314的選擇閘極和字元線。儲存堆疊層412中的至少一些導體層410(例如,除了頂部和底部導體層410之外)可以各自用作NAND記憶體串314的字元線。作為閘極替換的結果,可以在儲存堆疊層412的邊緣處形成階梯結構414。儲存堆疊層412的階梯結構414中的沿著遠離矽襯底202的垂直方向(正y方向)的導體/介電層對的邊緣可以朝向NAND記憶體串314橫向交錯排列。As a result, the
方法700進行到操作712,如第7圖所示,其中形成儲存堆疊層和記憶體串的局部互連。局部互連可以包括形成在儲存堆疊層的階梯結構之上的字元線通孔觸點,並且包括形成在記憶體串之上的源極線通孔觸點。如第4E圖所示,可以通過介電材料的諸如CVD、ALD、任何其他合適的製程或其任何組合之類的薄膜沉積製程在單晶矽層404上形成ILD層416。源極線通孔觸點418可以分別穿過ILD層416形成並與記憶體串314的矽插塞306接觸。每個源極線通孔觸點418可以使其下端與對應的NAND記憶體串314的上端接觸。根據一些實施例,字元線通孔觸點420穿過一個或複數個ILD層(包括ILD層416)並在儲存堆疊層412的階梯結構414之上形成。字元線通孔觸點420的下端可以落在儲存堆疊層412的階梯結構414中的NAND記憶體串314(例如,導體層410)的字元線上,使得每個字元線通孔觸點420在對應的導體層410之上並與之接觸。The
在一些實施例中,形成源極線通孔觸點418和字元線通孔觸點420的製程包括使用乾式/濕式蝕刻製程形成垂直開口,之後用導電材料和其他材料(例如,阻隔層、黏合層或/及種子層)填充開口以用於導體填充、黏合或/及其他目的。源極線通孔觸點418和字元線通孔觸點420可包括導電材料,其包括但不限於W、Co、Cu、Al、摻雜矽、矽化物或其任何組合。源極線通孔觸點418和字元線通孔觸點420的開口可以用導電材料和其他材料、通過ALD、CVD、PVD、電鍍、任何其他合適的製程或其任何組合來進行填充。在一些實施例中,GLS 408可以通過CVD、PVD、ALD、任何其他合適的製程或其任何組合填充介電材料,其包括但不限於氧化矽、氮化矽、氮氧化矽或其任何組合。In some embodiments, the process of forming the source line via
方法700進行到操作714,如第7圖所示,其中在減薄的第二襯底之上形成第三互連層(例如,BEOL互連層)。BEOL互連層可以包括一個或複數個ILD層中的第三複數個互連。如第4F圖所示,BEOL互連層422可以形成在單晶矽層404和NAND記憶體串314之上。BEOL互連層422可以包括互連,其包括一個或複數個ILD層中的互連線424和通孔觸點426,以用於將電信號傳輸到3D記憶體裝置和從3D記憶體裝置傳輸電信號。在一些實施例中,接觸墊428和再分佈層(未示出)可以形成在BEOL互連層422的頂表面處,以用於引線鍵合或/及與中介層鍵合。The
在一些實施例中,BEOL互連層422包括在複數個製程中形成的複數個ILD層和其中的互連。例如,互連線424、通孔觸點426和接觸墊428可包括通過一種或多種薄膜沉積製程沉積的導電材料,薄膜沉積製程包括但不限於CVD、PVD、ALD、電鍍、化學鍍或其任何組合。形成互連線424、通孔觸點426和接觸墊428的製程還可包括微影、CMP、濕式/乾式蝕刻或任何其他合適的製程。ILD層可包括通過一種或多種薄膜沉積製程沉積的介電材料,薄膜沉積製程包括但不限於CVD、PVD、ALD或其任何組合。第4F圖中所示的ILD層和互連可以統稱為“互連層”(例如,BEOL互連層422)。In some embodiments, the
儘管未示出,但在一些實施例中,在鍵合之前,形成TAC,其垂直延伸穿過介電堆疊層308並與陣列互連層322中的互連接觸。在鍵合之後,可形成通孔觸點,其垂直延伸穿過一個或複數個ILD層並與TAC接觸,使得BEOL互連層422可以電連接到週邊互連層206。Although not shown, in some embodiments, before bonding, a TAC is formed that extends vertically through the
根據本公開的一個方面,公開了一種用於形成3D記憶體裝置的方法。週邊設備形成在第一襯底上。在第一襯底上的週邊設備之上形成第一互連層。在第二襯底上形成包括複數個介電/犧牲層對和複數個記憶體串的介電堆疊層,每個記憶體串垂直延伸穿過介電堆疊層。在第二襯底上的記憶體串之上形成第二互連層。將第一襯底和第二襯底鍵合,使得第一互連層在第二互連層之下並與第二互連層接觸。在鍵合之後,將第二襯底減薄。通過用複數個導體層替換介電/犧牲層對中的犧牲層,將儲存堆疊層形成在減薄的第二襯底之下並包括複數個導體/介電層對。According to an aspect of the present disclosure, a method for forming a 3D memory device is disclosed. The peripheral device is formed on the first substrate. A first interconnect layer is formed on the peripheral device on the first substrate. A dielectric stack layer including a plurality of dielectric/sacrificial layer pairs and a plurality of memory strings is formed on the second substrate, and each memory string extends vertically through the dielectric stack layer. A second interconnect layer is formed on the memory string on the second substrate. The first substrate and the second substrate are bonded so that the first interconnect layer is below and in contact with the second interconnect layer. After bonding, the second substrate is thinned. By replacing the sacrificial layer in the dielectric/sacrificial layer pair with a plurality of conductor layers, the storage stack layer is formed under the thinned second substrate and includes a plurality of conductor/dielectric layer pairs.
在一些實施例中,在鍵合之後,在介電堆疊層的邊緣處形成階梯結構。根據一些實施例,為了形成階梯結構,在形成儲存堆疊層之前,朝向第一襯底對介電/犧牲層對執行複數個修整蝕刻循環。In some embodiments, after bonding, a stepped structure is formed at the edge of the dielectric stack. According to some embodiments, to form a stepped structure, before forming the storage stack layer, a plurality of trimming etch cycles are performed toward the first substrate pair dielectric/sacrificial layer pair.
在一些實施例中,形成複數個第一通孔觸點,使得每個第一通孔觸點在導體/介電層對中的一個導體/介電層對的導體層之上並與該導體層接觸。在一些實施例中,形成複數個第二通孔觸點,使得每個第二通孔觸點在記憶體串之一之上並與其接觸。In some embodiments, a plurality of first via contacts are formed such that each first via contact is above and in contact with the conductor layer of one conductor/dielectric layer pair of the conductor/dielectric layer pair Layer contact. In some embodiments, a plurality of second via contacts are formed so that each second via contact is on and in contact with one of the memory strings.
在一些實施例中,在形成儲存堆疊層之後,在減薄的第二襯底之上形成第三互連層。In some embodiments, after forming the storage stack layer, a third interconnect layer is formed over the thinned second substrate.
在一些實施例中,鍵合包括混合鍵合。根據一些實施例,為了鍵合第一襯底和第二襯底,將第二襯底上下翻轉。In some embodiments, the bonding includes hybrid bonding. According to some embodiments, in order to bond the first substrate and the second substrate, the second substrate is turned upside down.
在一些實施例中,為了形成儲存堆疊層,蝕刻穿過減薄的第二襯底和複數個介電/犧牲層對的開口;穿過開口蝕刻複數個介電/犧牲層對中的犧牲層;並且穿過開口沉積複數個導體/介電層對中的導體層。In some embodiments, in order to form the storage stack layer, the opening through the thinned second substrate and the plurality of dielectric/sacrificial layer pairs is etched; the sacrificial layer in the plurality of dielectric/sacrificial layer pairs is etched through the opening ; And deposit a plurality of conductor layers in the conductor/dielectric layer pair through the opening.
根據本公開的另一方面,公開了一種用於形成3D記憶體裝置的方法。將週邊設備形成在第一襯底上。在第一襯底上的週邊設備之上形成第一互連層。每個垂直延伸的複數個記憶體串形成在第二襯底上。在第二襯底上的記憶體串之上形成第二互連層。將第一襯底和第二襯底鍵合,使得第一互連層在第二互連層之下並與第二互連層接觸。在鍵合之後,將第二襯底減薄。將儲存堆疊層形成在減薄的第二襯底之下並且包括複數個導體/介電層對。在儲存堆疊層的階梯結構中的沿著遠離第一襯底的垂直方向的導體/介電層對的邊緣朝向記憶體串橫向交錯排列。According to another aspect of the present disclosure, a method for forming a 3D memory device is disclosed. The peripheral device is formed on the first substrate. A first interconnect layer is formed on the peripheral device on the first substrate. A plurality of memory strings each extending vertically are formed on the second substrate. A second interconnect layer is formed on the memory string on the second substrate. The first substrate and the second substrate are bonded so that the first interconnect layer is below and in contact with the second interconnect layer. After bonding, the second substrate is thinned. The storage stack layer is formed under the thinned second substrate and includes a plurality of conductor/dielectric layer pairs. In the stepped structure of the storage stack layer, the edges of the conductor/dielectric layer pair along the vertical direction away from the first substrate are laterally staggered toward the memory string.
在一些實施例中,在鍵合之前形成包括複數個介電/犧牲層對的介電堆疊層,記憶體串穿過該等介電/犧牲層對垂直延伸。根據一些實施例,為了形成儲存堆疊層,階梯結構形成在介電堆疊層的邊緣處;並且介電/犧牲層對中的犧牲層由複數個導體層替換。根據一些實施例,為了替換犧牲層,蝕刻穿過減薄的第二襯底和複數個介電/犧牲層對的開口;穿過開口蝕刻複數個介電/犧牲層對中的犧牲層;並且穿過開口沉積複數個導體/介電層對中的導體層。在一些實施例中,為了形成階梯結構,朝向第一襯底對介電/犧牲層對執行複數個修整蝕刻循環。In some embodiments, a dielectric stack including a plurality of pairs of dielectric/sacrificial layers is formed before bonding, and the memory string extends vertically through the pairs of dielectric/sacrificial layers. According to some embodiments, in order to form a storage stack layer, a stepped structure is formed at the edge of the dielectric stack layer; and the sacrificial layer in the dielectric/sacrificial layer pair is replaced by a plurality of conductor layers. According to some embodiments, in order to replace the sacrificial layer, the opening through the thinned second substrate and the plurality of dielectric/sacrificial layer pairs is etched; the sacrificial layer in the plurality of dielectric/sacrificial layer pairs is etched through the opening; and Multiple conductor/dielectric layer centered conductor layers are deposited through the opening. In some embodiments, to form a stepped structure, a plurality of trimming etch cycles are performed toward the first substrate pair dielectric/sacrificial layer pair.
在一些實施例中,形成複數個第一通孔觸點,使得每個第一通孔觸點在導體/介電層對中的一個導體/介電層的導體層之上並與該導體層接觸。在一些實施例中,形成複數個第二通孔觸點,使得每個第二通孔觸點在記憶體串中的一個記憶體串之上並與該一個記憶體串接觸。In some embodiments, a plurality of first via contacts are formed such that each first via contact is above and in contact with the conductor layer of one conductor/dielectric layer in the conductor/dielectric layer pair contact. In some embodiments, a plurality of second via contacts are formed so that each second via contact is on and in contact with one of the memory strings.
在一些實施例中,在形成儲存堆疊層之後,在減薄的第二襯底之上形成第三互連層。In some embodiments, after forming the storage stack layer, a third interconnect layer is formed over the thinned second substrate.
在一些實施例中,鍵合包括混合鍵合。根據一些實施例,為了鍵合第一襯底和第二襯底,將第二襯底上下翻轉。In some embodiments, the bonding includes hybrid bonding. According to some embodiments, in order to bond the first substrate and the second substrate, the second substrate is turned upside down.
根據本公開的又一方面,公開了一種用於形成3D記憶體裝置的方法。每個垂直延伸的複數個記憶體串形成在襯底上。在記憶體串之上形成互連層。將襯底上下翻轉,使得襯底位於記憶體串之上。在翻轉後將襯底減薄。在減薄之後,將儲存堆疊層形成在減薄的襯底之下並且包括複數個導體/介電層對。形成複數個第一通孔觸點,使得每個第一通孔觸點在導體/介電層對中的一個導體/介電層對的導體層之上並與該導體層接觸。According to yet another aspect of the present disclosure, a method for forming a 3D memory device is disclosed. A plurality of memory strings each extending vertically are formed on the substrate. An interconnect layer is formed on the memory string. Turn the substrate upside down so that the substrate is above the memory string. After turning over, the substrate is thinned. After thinning, the storage stack layer is formed under the thinned substrate and includes a plurality of conductor/dielectric layer pairs. A plurality of first via contacts are formed such that each first via contact is above and in contact with the conductor layer of one conductor/dielectric layer pair of the conductor/dielectric layer pair.
在一些實施例中,在形成儲存堆疊層之後形成複數個第二通孔觸點,使得每個第二通孔觸點在記憶體串中的一個記憶體串之上並與該一個記憶體串接觸。In some embodiments, a plurality of second via contacts are formed after forming the storage stack layer, such that each second via contact is on and in contact with one of the memory strings in the memory string contact.
在一些實施例中,在減薄的襯底之上形成第二互連層,使得複數個第一和第二通孔觸點與第二互連層接觸。In some embodiments, a second interconnect layer is formed over the thinned substrate so that the plurality of first and second via contacts are in contact with the second interconnect layer.
在一些實施例中,在翻轉之前形成包括複數個介電/犧牲層對的介電堆疊層,記憶體串穿過該等介電/犧牲層對垂直延伸。根據一些實施例,為了形成儲存堆疊層,在介電堆疊層的邊緣處形成階梯結構;並且介電/犧牲層對中的犧牲層由複數個導體層替換。根據一些實施例,為了替換犧牲層,蝕刻穿過減薄的襯底和複數個介電/犧牲層對的開口;穿過開口蝕刻複數個介電/犧牲層對中的犧牲層;並且穿過開口沉積複數個導體/介電層對中的導體層。在一些實施例中,為了形成階梯結構,遠離減薄的襯底對介電/犧牲層對執行複數個修整蝕刻循環。In some embodiments, a dielectric stack including a plurality of pairs of dielectric/sacrificial layers is formed before flipping, and the memory string extends vertically through the pairs of dielectric/sacrificial layers. According to some embodiments, in order to form the storage stack layer, a stepped structure is formed at the edge of the dielectric stack layer; and the sacrificial layer in the dielectric/sacrificial layer pair is replaced by a plurality of conductor layers. According to some embodiments, to replace the sacrificial layer, etch through the opening of the thinned substrate and the plurality of dielectric/sacrificial layer pairs; etch the sacrificial layer of the plurality of dielectric/sacrificial layer pairs through the opening; and pass through The opening deposits a plurality of conductor layers in a conductor/dielectric layer pair. In some embodiments, to form a stepped structure, a plurality of trimming etch cycles are performed away from the thinned substrate pair dielectric/sacrificial layer pair.
對特定實施例的上述說明因此將揭示本公開的一般性質,使得他人能夠通過運用本領域技術範圍內的知識容易地對這種特定實施例進行修改或/及調整以用於各種應用,而不需要過度實驗,且不脫離本公開的一般概念。因此,基於本文呈現的教導和指導,這種調整和修改旨在處於所公開的實施例的等同物的含義和範圍內。應當理解,本文中的措辭或術語是用於說明的目的,而不是為了進行限制,從而本說明書的術語或措辭將由技術人員按照所述教導和指導進行解釋。The above description of specific embodiments will thus reveal the general nature of the present disclosure, enabling others to easily modify or/and adjust such specific embodiments for various applications by applying knowledge within the technical scope of the art, without Excessive experimentation is required without departing from the general concept of this disclosure. Therefore, based on the teachings and guidance presented herein, such adjustments and modifications are intended to be within the meaning and scope of equivalents of the disclosed embodiments. It should be understood that the wording or terminology herein is for illustrative purposes and not for limitation, so that the terminology or wording of this specification will be interpreted by the skilled person in accordance with the teaching and guidance.
上文已經借助於功能構建塊描述了本公開的實施例,功能構建塊例示了指定功能及其關係的實施方式。在本文中出於方便描述的目的任意地定義了這些功能構建塊的邊界。可以定義替代的邊界,只要適當執行指定的功能及其關係即可。The embodiments of the present disclosure have been described above with the help of function building blocks, which exemplify embodiments specifying functions and their relationships. The boundaries of these functional building blocks are arbitrarily defined in this article for the convenience of description. Alternative boundaries can be defined as long as the specified functions and their relationships are properly performed.
發明內容和摘要部分可以闡述發明人所設想的本公開的一個或複數個示例性實施例,但未必是所有示例性實施例,並且因此,並非旨在通過任何方式限制本公開和所附申請專利範圍。The summary and abstract sections may illustrate one or more exemplary embodiments of the present disclosure envisioned by the inventor, but not necessarily all exemplary embodiments, and therefore, it is not intended to limit the present disclosure and the attached patent applications in any way range.
本公開的廣度和範圍不應受任何上述示例性實施例的限制,並且應當僅根據所附發明申請專利範圍及其等同物來進行限定。 以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, and should be limited only in accordance with the scope of patent applications for the attached invention and their equivalents. The above are only the preferred embodiments of the present invention, and all changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the present invention.
100‧‧‧3D記憶體裝置102‧‧‧襯底104‧‧‧電晶體106‧‧‧週邊互連層108‧‧‧互連線110‧‧‧通孔觸點112‧‧‧鍵合觸點114‧‧‧NAND記憶體串116‧‧‧導體層118‧‧‧介電層120‧‧‧儲存堆疊層122‧‧‧階梯結構124‧‧‧半導體通道126‧‧‧穿隧層128‧‧‧儲存層130‧‧‧半導體層132‧‧‧半導體插塞134‧‧‧閘極線縫隙136‧‧‧字元線通孔觸點138‧‧‧位元線通孔觸點140‧‧‧源極線通孔觸點142‧‧‧陣列互連層144‧‧‧互連線146‧‧‧通孔觸點148‧‧‧鍵合觸點150‧‧‧BEOL互連層152‧‧‧互連線154‧‧‧通孔觸點156‧‧‧接觸墊158‧‧‧鍵合界面160‧‧‧儲存陣列元件晶片162‧‧‧週邊設備晶片202‧‧‧矽襯底204‧‧‧電晶體206‧‧‧週邊互連層208‧‧‧互連線210‧‧‧通孔觸點212‧‧‧鍵合觸點214‧‧‧鍵合觸點302‧‧‧矽襯底304‧‧‧隔離區306‧‧‧矽插塞308‧‧‧介電堆疊層310‧‧‧介電層312‧‧‧犧牲層314‧‧‧NAND記憶體串316‧‧‧半導體通道318‧‧‧穿隧層320‧‧‧儲存層321‧‧‧位元線通孔觸點322‧‧‧陣列互連層324‧‧‧互連線326‧‧‧通孔觸點328‧‧‧鍵合觸點402‧‧‧鍵合界面404‧‧‧單晶矽層406‧‧‧階梯結構408‧‧‧GLS410‧‧‧導體層412‧‧‧儲存堆疊層414‧‧‧階梯結構416‧‧‧ILD層418‧‧‧源極線通孔觸點422‧‧‧BEOL互連層424‧‧‧互連線426‧‧‧通孔觸點428‧‧‧接觸墊500‧‧‧方法502‧‧‧操作504‧‧‧操作506‧‧‧操作600‧‧‧方法602‧‧‧操作604‧‧‧操作606‧‧‧操作608‧‧‧操作700‧‧‧方法702‧‧‧操作704‧‧‧操作706‧‧‧操作708‧‧‧操作710‧‧‧操作712‧‧‧操作714‧‧‧操作100‧‧‧3D memory device 102‧‧‧‧substrate 104‧‧‧transistor 106‧‧‧peripheral interconnect layer 108‧‧‧ interconnect 110 110‧‧‧via contact 112‧‧‧bond contact Dot 114‧‧‧NAND memory string 116‧‧‧conductor layer 118‧‧‧dielectric layer 120‧‧‧storage stack layer 122‧‧‧ ladder structure 124‧‧‧semiconductor channel 126‧‧‧tunnel layer 128‧ ‧‧Storage layer 130‧‧‧Semiconductor layer 132‧‧‧Semiconductor plug 134‧‧‧Gate line gap 136‧‧‧Character line via contact 138‧‧‧Bit line via contact 140‧‧ ‧Source line via contact 142‧‧‧Array interconnect layer 144‧‧‧Interconnect line 146‧‧‧via contact 148‧‧‧bond contact 150‧‧‧BEOL interconnect layer 152‧‧ ‧Interconnect 154‧‧‧Through-hole contact 156‧‧‧Contact pad 158‧‧‧ Bonding interface 160‧‧‧Storage array element chip 162‧‧‧Peripheral device chip 202‧‧‧Silicon substrate 204‧‧ ‧Transistor 206‧‧‧Peripheral interconnect layer 208‧‧‧Interconnect 210 210‧‧‧Through-hole contact 212‧‧‧ Bonding contact 214‧‧‧ Bonding contact 302 ‧‧‧Isolated area 306‧‧‧Silicon plug 308‧‧‧ Dielectric stack 310‧‧‧‧Dielectric layer 312‧‧‧Sacrifice layer 314‧‧‧NAND memory string 316‧‧‧Semiconductor channel 318‧‧ ‧Tunnel layer 320‧‧‧Storage layer 321‧‧‧Bit line via contact 322‧‧‧Array interconnect layer 324‧‧‧Interconnect line 326‧‧‧Through contact 328‧‧‧bond Contact 402‧‧‧ Bonding interface 404‧‧‧Single crystal silicon layer 406‧‧‧Step structure 408‧‧‧GLS410‧‧‧Conductor layer 412‧‧‧Storage stack layer 414‧‧‧Step structure 416‧‧‧ ILD layer 418‧‧‧Source line via contact 422‧‧‧BEOL interconnect layer 424‧‧‧Interconnect line 426‧‧‧via contact 428‧‧‧Contact pad 500‧‧‧Method 502‧‧ ‧Operation 504‧‧‧Operation 506‧‧‧Operation 600‧‧‧Method 602‧‧‧Operation 604‧‧‧Operation 606‧‧‧Operation 608‧‧‧Operation 700‧‧‧Method 702‧‧‧Operation 704‧‧ ‧Operation 706‧‧‧Operation 708‧‧‧Operation 710‧‧‧Operation 712‧‧‧Operation 714‧‧‧Operation
併入本文中並且構成說明書的部分的附圖示出了本公開的實施例,並且與說明書一起進一步用來對本公開的原理進行解釋,並且使相關領域技術人員能夠實施和使用本公開。 第1圖示出了根據一些實施例的示例性3D記憶體裝置的橫截面。 第2A圖至第2B圖示出了根據一些實施例的用於形成示例性週邊設備晶片的製程。 第3A圖至第3D圖示出了根據一些實施例的用於形成示例性儲存陣列元件晶片的製程。 第4A圖至第4F圖示出了根據一些實施例的用於形成示例性3D記憶體裝置的製程,其中儲存陣列元件晶片鍵合到週邊設備晶片。 第5圖是根據一些實施例的用於形成示例性週邊設備晶片的方法的流程圖。 第6圖是根據一些實施例的用於形成示例性儲存陣列元件晶片的方法的流程圖。 第7圖是根據一些實施例的用於形成示例性3D記憶體裝置的方法的流程圖,其中儲存陣列元件晶片鍵合到週邊設備晶片。 將參考附圖來描述本公開的實施例。The drawings incorporated herein and constituting a part of the specification show embodiments of the present disclosure, and are used together with the specification to further explain the principles of the present disclosure and enable those skilled in the relevant art to implement and use the present disclosure. Figure 1 shows a cross-section of an exemplary 3D memory device according to some embodiments. FIGS. 2A-2B illustrate a process for forming an exemplary peripheral device wafer according to some embodiments. FIGS. 3A to 3D illustrate a process for forming an exemplary memory array device wafer according to some embodiments. FIGS. 4A to 4F illustrate a process for forming an exemplary 3D memory device in which a storage array element wafer is bonded to a peripheral device wafer according to some embodiments. FIG. 5 is a flowchart of a method for forming an exemplary peripheral device wafer according to some embodiments. FIG. 6 is a flowchart of a method for forming an exemplary storage array element wafer according to some embodiments. FIG. 7 is a flowchart of a method for forming an exemplary 3D memory device according to some embodiments, in which a storage array element wafer is bonded to a peripheral device wafer. The embodiments of the present disclosure will be described with reference to the drawings.
100‧‧‧3D記憶體裝置 100‧‧‧3D memory device
102‧‧‧襯底 102‧‧‧Substrate
104‧‧‧電晶體 104‧‧‧Transistor
106‧‧‧週邊互連層 106‧‧‧Peripheral interconnection layer
108‧‧‧互連線 108‧‧‧Interconnect
110‧‧‧通孔觸點 110‧‧‧Through hole contact
112‧‧‧鍵合觸點 112‧‧‧bond contact
114‧‧‧NAND記憶體串 114‧‧‧NAND memory string
116‧‧‧導體層 116‧‧‧Conductor layer
118‧‧‧介電層 118‧‧‧dielectric layer
120‧‧‧儲存堆疊層 120‧‧‧Storage stack
122‧‧‧階梯結構 122‧‧‧Ladder structure
124‧‧‧半導體通道 124‧‧‧Semiconductor channel
126‧‧‧穿隧層 126‧‧‧Tunnel layer
128‧‧‧儲存層 128‧‧‧Storage layer
130‧‧‧半導體層 130‧‧‧Semiconductor layer
132‧‧‧半導體插塞 132‧‧‧Semiconductor plug
134‧‧‧閘極線縫隙 134‧‧‧Gate line gap
136‧‧‧字元線通孔觸點 136‧‧‧Character line through-hole contact
138‧‧‧位元線通孔觸點 138‧‧‧bit line through hole contact
140‧‧‧源極線通孔觸點 140‧‧‧ source line through-hole contact
142‧‧‧陣列互連層 142‧‧‧Array interconnection layer
144‧‧‧互連線 144‧‧‧Interconnect
146‧‧‧通孔觸點 146‧‧‧Through hole contact
148‧‧‧鍵合觸點 148‧‧‧bond contact
150‧‧‧BEOL互連層 150‧‧‧BEOL interconnection layer
152‧‧‧互連線 152‧‧‧Interconnect
154‧‧‧通孔觸點 154‧‧‧Through hole contact
156‧‧‧接觸墊 156‧‧‧Contact pad
158‧‧‧鍵合界面 158‧‧‧bond interface
160‧‧‧儲存陣列元件晶片 160‧‧‧Storage array element chip
162‧‧‧週邊設備晶片 162‧‧‧Peripheral device chip
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI727761B (en) * | 2020-04-23 | 2021-05-11 | 旺宏電子股份有限公司 | Memory device and method of fabricating the same |
TWI751615B (en) * | 2020-05-25 | 2022-01-01 | 大陸商長江存儲科技有限責任公司 | Memory element and method for forming the same |
US11348941B2 (en) | 2020-04-23 | 2022-05-31 | Macronix International Co., Ltd. | Memory device and method of fabricating the same |
TWI777227B (en) * | 2020-03-16 | 2022-09-11 | 日商鎧俠股份有限公司 | Semiconductor memory device |
US11538827B2 (en) | 2020-07-23 | 2022-12-27 | Macronix International Co., Ltd. | Three-dimensional memory device with increased memory cell density |
Families Citing this family (40)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR102650996B1 (en) * | 2018-11-06 | 2024-03-26 | 삼성전자주식회사 | Semiconductor device |
EP3853893A4 (en) | 2019-02-11 | 2023-08-16 | Yangtze Memory Technologies Co., Ltd. | Bonded semiconductor structures having bonding contacts made of indiffusible conductive materials and methods for forming the same |
JP2020136644A (en) * | 2019-02-26 | 2020-08-31 | キオクシア株式会社 | Semiconductor storage device |
WO2020177048A1 (en) | 2019-03-04 | 2020-09-10 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory devices |
WO2020177049A1 (en) * | 2019-03-04 | 2020-09-10 | Yangtze Memory Technologies Co., Ltd. | Methods for forming three-dimensional memory devices |
CN109950238A (en) * | 2019-03-29 | 2019-06-28 | 长江存储科技有限责任公司 | Semiconductor devices and preparation method thereof |
KR102601225B1 (en) * | 2019-04-15 | 2023-11-10 | 양쯔 메모리 테크놀로지스 씨오., 엘티디. | Integration of 3D NAND memory devices with multiple functional chips |
EP3891806A4 (en) * | 2019-04-15 | 2022-10-12 | Yangtze Memory Technologies Co., Ltd. | Unified semiconductor devices having processor and heterogeneous memories and methods for forming the same |
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US10847523B1 (en) * | 2019-07-03 | 2020-11-24 | Macronix International Co., Ltd. | Stacked memory and ASIC device |
JP2022534538A (en) * | 2019-07-08 | 2022-08-01 | 長江存儲科技有限責任公司 | 3D memory device with deep isolation structure |
KR20210154834A (en) | 2019-07-16 | 2021-12-21 | 양쯔 메모리 테크놀로지스 씨오., 엘티디. | Self-aligned contacts in three-dimensional memory device and method of forming same |
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CN112768461B (en) | 2019-09-20 | 2023-10-20 | 长江存储科技有限责任公司 | Three-dimensional memory device and method of manufacturing the same |
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JP2021072313A (en) * | 2019-10-29 | 2021-05-06 | キオクシア株式会社 | Semiconductor storage device |
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US11183456B2 (en) * | 2020-01-15 | 2021-11-23 | Micron Technology, Inc. | Memory arrays and methods used in forming a memory array |
US11120852B2 (en) | 2020-02-18 | 2021-09-14 | Micron Technology, Inc. | Memory arrays and methods used in forming a memory array |
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US11963349B2 (en) | 2020-05-27 | 2024-04-16 | Yangtze Memory Technologies Co., Ltd. | Methods for forming three-dimensional memory devices with backside source contacts |
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CN111801799B (en) | 2020-05-27 | 2021-03-23 | 长江存储科技有限责任公司 | Method for forming three-dimensional memory device |
JP7305774B2 (en) * | 2020-05-27 | 2023-07-10 | 長江存儲科技有限責任公司 | 3D memory device |
CN112424934B (en) * | 2020-05-27 | 2024-04-09 | 长江存储科技有限责任公司 | Three-dimensional memory device |
CN113410243B (en) | 2020-05-27 | 2023-04-25 | 长江存储科技有限责任公司 | Method for forming three-dimensional memory device |
US11877448B2 (en) | 2020-05-27 | 2024-01-16 | Yangtze Memory Technologies Co., Ltd. | Methods for forming three-dimensional memory devices |
CN112585754A (en) * | 2020-05-27 | 2021-03-30 | 长江存储科技有限责任公司 | Method for forming three-dimensional memory device |
KR20210156014A (en) * | 2020-06-17 | 2021-12-24 | 삼성전자주식회사 | Memory device and system including the same |
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US20220059555A1 (en) * | 2020-08-18 | 2022-02-24 | Applied Material, Inc. | Selection gate separation for 3d nand |
JP2022040975A (en) * | 2020-08-31 | 2022-03-11 | キオクシア株式会社 | Semiconductor device and method for manufacturing the same |
KR20220045300A (en) | 2020-10-05 | 2022-04-12 | 삼성전자주식회사 | Nonvolatile memory device, nonvolatile memory device including the same, and method for fabricating the same |
CN112614853B (en) * | 2020-12-01 | 2023-05-12 | 长江存储科技有限责任公司 | Three-dimensional memory device and forming method thereof |
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US11844224B2 (en) * | 2021-01-13 | 2023-12-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory structure and method of forming the same |
CN113439335A (en) * | 2021-05-18 | 2021-09-24 | 长江先进存储产业创新中心有限责任公司 | Three-dimensional phase change memory device and forming method thereof |
US20230110367A1 (en) * | 2021-10-13 | 2023-04-13 | Micron Technology, Inc. | Methods of forming microelectronic devices, and related microelectronic devices, memory devices, and electronic systems |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR102192539B1 (en) * | 2014-05-21 | 2020-12-18 | 삼성전자주식회사 | Semiconductor Device and program method of the same |
US9586385B2 (en) * | 2014-08-27 | 2017-03-07 | 3M Innovative Properties Company | Inorganic multilayer lamination transfer films |
US9818693B2 (en) * | 2015-12-22 | 2017-11-14 | Sandisk Technologies Llc | Through-memory-level via structures for a three-dimensional memory device |
KR102609348B1 (en) * | 2016-10-26 | 2023-12-06 | 삼성전자주식회사 | Semiconductor device and method for fabricating the same |
US10002787B2 (en) * | 2016-11-23 | 2018-06-19 | Lam Research Corporation | Staircase encapsulation in 3D NAND fabrication |
CN106910746B (en) * | 2017-03-08 | 2018-06-19 | 长江存储科技有限责任公司 | A kind of 3D nand memories part and its manufacturing method, packaging method |
CN106920795B (en) * | 2017-03-08 | 2019-03-12 | 长江存储科技有限责任公司 | Memory construction and preparation method thereof, the test method of memory |
TW201843750A (en) * | 2017-05-03 | 2018-12-16 | 力成科技股份有限公司 | Method of packaging system in wafer-level package and semiconductor package manufactured from the same |
CN107658315B (en) * | 2017-08-21 | 2019-05-14 | 长江存储科技有限责任公司 | Semiconductor device and preparation method thereof |
CN110010620B (en) * | 2017-11-21 | 2021-04-13 | 长江存储科技有限责任公司 | Manufacturing method of 3D NAND flash memory with high stack number and 3D NAND flash memory |
CN107887395B (en) * | 2017-11-30 | 2018-12-14 | 长江存储科技有限责任公司 | NAND memory and preparation method thereof |
US10283493B1 (en) * | 2018-01-17 | 2019-05-07 | Sandisk Technologies Llc | Three-dimensional memory device containing bonded memory die and peripheral logic die and method of making thereof |
-
2018
- 2018-07-20 WO PCT/CN2018/096501 patent/WO2020014976A1/en active Application Filing
- 2018-07-20 CN CN201880001051.2A patent/CN109314116B/en active Active
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI777227B (en) * | 2020-03-16 | 2022-09-11 | 日商鎧俠股份有限公司 | Semiconductor memory device |
TWI727761B (en) * | 2020-04-23 | 2021-05-11 | 旺宏電子股份有限公司 | Memory device and method of fabricating the same |
US11348941B2 (en) | 2020-04-23 | 2022-05-31 | Macronix International Co., Ltd. | Memory device and method of fabricating the same |
TWI751615B (en) * | 2020-05-25 | 2022-01-01 | 大陸商長江存儲科技有限責任公司 | Memory element and method for forming the same |
US11538827B2 (en) | 2020-07-23 | 2022-12-27 | Macronix International Co., Ltd. | Three-dimensional memory device with increased memory cell density |
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US20200027892A1 (en) | 2020-01-23 |
US10580788B2 (en) | 2020-03-03 |
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WO2020014976A1 (en) | 2020-01-23 |
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