CN109950238A - Semiconductor devices and preparation method thereof - Google Patents
Semiconductor devices and preparation method thereof Download PDFInfo
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- CN109950238A CN109950238A CN201910252749.8A CN201910252749A CN109950238A CN 109950238 A CN109950238 A CN 109950238A CN 201910252749 A CN201910252749 A CN 201910252749A CN 109950238 A CN109950238 A CN 109950238A
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Abstract
This application discloses a kind of semiconductor devices and preparation method thereof.The first binder course and the second binder course of the semiconductor devices are in contact with each other to provide the first chip and the second chip and bond together, the contact surface of first binder course and the second binder course is bonding face, first composite channel includes filling the lower part in the first passage hole and first filled layer on top and the first contact layer respectively, second composite channel includes filling the lower part in the second channel hole and second filled layer on top and the second contact layer respectively, first contact layer and second contact layer are in contact with each other to provide the electrical connection between first chip and second chip.The semiconductor devices forms the composite channel being connected to each other to improve filling capacity and bonding performance, to improve bond strength and reliability.
Description
Technical field
The present invention relates to semiconductor technologies, more particularly, to semiconductor devices and preparation method thereof.
Background technique
The developing direction of semiconductor technology is the reduction of characteristic size and the raising of integrated level.For memory device,
The raising of the storage density of memory device and the progress of semiconductor fabrication process are closely related.With the spy of semiconductor fabrication process
Sign size is smaller and smaller, and the storage density of memory device is higher and higher.
In order to further increase storage density, the memory device (that is, 3D memory device) of three-dimensional structure has been developed.It should
3D memory device includes the multiple storage units stacked along vertical direction, can be doubled up on the chip of unit area
Integrated level, and cost can be reduced.Further, it has developed 3D memory device chip and drive circuit chip bonding
Semiconductor devices together.The semiconductor devices can provide the read or write speed of memory device, and improve integrated level, reduce
Device cost and raising reliability.
In above-mentioned semiconductor devices, the surface being in contact with each other between chip is bonding face.The bonding face of chip passes through
After cleaning and activation processing, reaches and clean smooth degree.The bonding face of at least two chips is in contact with each other, in certain temperature
Under degree and pressure condition, it is integrally formed bonding chip by molecular force or atomic force.
Fig. 1 shows the schematic cross-section of semiconductor devices according to prior art.Fig. 2 a and 2b show the semiconductor device of Fig. 1
The enlarged diagram of the conductive channel of part.
Semiconductor devices 100 includes chip 110 and 120.Chip 110 includes semiconductor substrate 111, in semiconductor substrate
The interlayer insulating film 112 and binder course 113 that are stacked gradually on 111 and the conductive channel 114 through binder course 113.Chip
120 include semiconductor substrate 121, the interlayer insulating film 122 that is stacked gradually in semiconductor substrate 121 and binder course 123 and
Through the conductive channel 124 of binder course 123.Wherein, semiconductor substrate and interlayer insulating film are referred to as substrate.It is risen in order to concise
See, in the rhythmic structure of the fence and inner conductive channel being not shown in the figure between semiconductor substrate and interlayer insulating film.In key
During conjunction, the binder course 113 of chip 110 and the binder course 123 of chip 120 are in contact with each other, conductive channel 114 and conductive channel
124 bond together to be formed electrically and mechanically.
However, the characteristic size with semiconductor fabrication process is smaller and smaller, the lateral dimension of conductive channel correspondingly subtracts
Small, depth-to-width ratio (aspect ratio) correspondingly increases.For example, the lateral dimension of conductive channel is decreased to less than 0.5 micron.Gold
The ability for belonging to layer filling channel hole is more and more difficult with the increase of depth-to-width ratio.As shown in Figure 2 a, in the transverse direction of conductive channel
Under larger-size situation, the metal in conductive channel can be filled up completely access opening.As shown in Figure 2 b, in the cross of conductive channel
To under the lesser situation of size, the metal filling capacity (filling property) in conductive channel is poor, to generate hole
10, the problem of leading to the bond strength and poor reliability of semiconductor devices.
Therefore, it is desirable to be further improved Wafer Bonding Process to improve bond strength and reliability.
Summary of the invention
The object of the present invention is to provide a kind of semiconductor devices and preparation method thereof, wherein brilliant in the first chip and second
The composite channel being connected to each other is formed in the binder course of piece to improve filling capacity and bonding performance, thus improve bond strength and
Reliability.
According to an aspect of the present invention, a kind of semiconductor devices is provided, comprising:
First chip, including the first substrate and positioned at first substrate surface the first binder course, pass through described first
The first passage hole of binder course and first composite channel in the filling first passage hole,
Second chip, including the second substrate and positioned at second substrate surface the second binder course, pass through described second
The second channel hole of binder course and second composite channel in the filling second channel hole,
Wherein, first composite channel includes the first filling for filling the lower part and top in the first passage hole respectively
Layer and the first contact layer, second composite channel include filling the lower part in the second channel hole respectively and the second of top is filled out
Layer and the second contact layer are filled, first binder course and second binder course combine, first contact layer and described second
Contact layer is bonded to each other.
Preferably, first substrate include the first semiconductor substrate and in first semiconductor substrate first
Functional layer, second substrate include the second semiconductor substrate and the second functional layer in second semiconductor substrate.
Preferably, first filled layer is made of from first contact layer different conductive materials, and described second fills out
It fills layer and is made of from second contact layer different conductive materials.
Preferably, first filled layer and second filled layer are respectively by any one group selected from polysilicon and tungsten
At.
Preferably, first contact layer and second contact layer respectively by selected from platinum, silver, copper, aluminium metal or its
In alloy any one at.
Preferably, the cross-sectional shape of first composite channel and second composite channel is respectively to be selected from following shape
Any one of shape: rectangle, rectangular, triangle, circle, ellipse and polygon.
Preferably, first chip and second chip are respectively to be selected from 3D memory device chip and driving circuit core
Any one in piece.
Preferably, at least one of first chip and second chip are 3D memory device chip, described the
Corresponding function layer in one functional layer and second functional layer includes: rhythmic structure of the fence and channel column, the rhythmic structure of the fence
Including the separation layer between multiple gate conductor layers and adjacent gate conductors layer, the channel column runs through the rhythmic structure of the fence.
Preferably, at least one of first chip and second chip be drive circuit chip, described first
Corresponding function layer in functional layer and second functional layer includes: rhythmic structure of the fence, and the rhythmic structure of the fence includes that grid is led
Body layer.
Preferably, described to be combined into bonding.
According to another aspect of the present invention, a kind of production method of semiconductor devices is provided, comprising:
Form the first chip, including the first substrate and positioned at first substrate surface the first binder course, pass through it is described
The first passage hole of first binder course and first composite channel in the filling first passage hole；
Form the second chip, including the second substrate and positioned at second substrate surface the second binder course, pass through it is described
The second channel hole of second binder course and second composite channel in the filling second channel hole；And
First chip and second chip are bonded together, first binder course and second binder course that
The contact surface of this contact, first binder course and second binder course is bonding face,
Wherein, first composite channel includes the first filling for filling the lower part and top in the first passage hole respectively
Layer and the first contact layer, second composite channel include filling the lower part in the second channel hole respectively and the second of top is filled out
Layer and the second contact layer are filled, first contact layer and second contact layer are in contact with each other to provide first chip and institute
State the electrical connection between the second chip.
Preferably, first filled layer is made of from first contact layer different conductive materials, and described second fills out
It fills layer and is made of from second contact layer different conductive materials.
Preferably, first filled layer and second filled layer are respectively by any one group selected from polysilicon and tungsten
At.
Preferably, first contact layer and second contact layer respectively by selected from platinum, silver, copper, aluminium metal or its
In alloy any one at.
Preferably, first composite channel and second composite channel divide in the cross sectional shape of bonding face exposure
It Wei not be selected from any one of following shape: rectangle, rectangular, triangle, circle, ellipse and polygon.
Preferably, first composite channel and second composite channel are respectively adopted metal filling processes and are formed, institute
Stating metal filling processes includes:
Form the access opening for running through first binder course and the corresponding binder course in second binder course；
The access opening is filled using conductive packing material；
The packing material is removed positioned at described accordingly in conjunction with the part of layer surface and positioned at the access opening top
Part, to form the filled layer of filling channel hole lower part；
The access opening is filled using conductive contact material；And
It removes the contact material and is located at the corresponding part in conjunction with layer surface, to be formed on the filling channel hole
The contact layer in portion.
Preferably, the packing material is removed using etch-back.
Preferably, the contact material is removed using chemical-mechanical planarization.
Semiconductor devices according to an embodiment of the present invention forms the composite channel for electrical connection in binder course.First
The composite channel of chip and the second chip is respectively aligned to, and further, composite channel is electrically connected with internal circuit.The semiconductor device
The composite channel of part includes the filled layer and contact layer for filling the lower part and top in channel hole respectively, and filled layer can choose filling
Filling defect caused by access opening of the packing material of good performance to avoid high-aspect-ratio, contact layer can choose bonding performance
Bond strength and reliability can be improved with the metal material of satisfactory mechanical property, to improve product yield.
Therefore, semiconductor devices according to an embodiment of the present invention improves product yield and reliability.
Detailed description of the invention
By referring to the drawings to the description of the embodiment of the present invention, above-mentioned and other purposes of the invention, feature and
Advantage will be apparent from.
Fig. 1 shows the schematic cross-section of semiconductor devices according to prior art.
Fig. 2 a and 2b show the enlarged diagram of the conductive channel of the semiconductor devices of Fig. 1.
The section that the different step of manufacturing method of semiconductor device according to an embodiment of the present invention is shown respectively in Fig. 3 to 11 shows
It is intended to.
Specific embodiment
Hereinafter reference will be made to the drawings, and the present invention will be described in more detail.In various figures, identical element is using similar attached
Icon is remembered to indicate.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.Furthermore, it is possible to be not shown certain
Well known part.For brevity, the semiconductor structure obtained after several steps can be described in a width figure.
It should be appreciated that being known as being located at another floor, another area when by a floor, a region in the structure of outlines device
When domain " above " or " top ", can refer to above another layer, another region, or its with another layer, it is another
Also comprising other layers or region between a region.Also, if device overturn, this layer, a region will be located at it is another
Layer, another region " following " or " lower section ".
If will use " directly exist ... herein to describe located immediately at another layer, another region above scenario
Above " or " ... abut above and therewith " form of presentation.
Many specific details of the invention, such as structure, material, size, the processing work of device is described hereinafter
Skill and technology, to be more clearly understood that the present invention.But it just as the skilled person will understand, can not press
The present invention is realized according to these specific details.
In this application, term " semiconductor structure " refers to that is formed in each step of manufacture memory device entirely partly leads
The general designation of body structure, including all layers formed or region.Hereinafter, unless otherwise indicated, " semiconductor structure " refers to
Be the intermediate structure for including chip and the rhythmic structure of the fence formed thereon.
The present invention can be presented in a variety of manners, some of them example explained below.
The section that the different step of manufacturing method of semiconductor device according to an embodiment of the present invention is shown respectively in Fig. 3 to 11 shows
It is intended to.
As shown in figure 3, this method starts from having been formed the chip 210 of main devices structure.
Chip 210 includes semiconductor substrate 211, and the functional layer 212 stacked in semiconductor substrate 211.Wherein, it partly leads
Body substrate 211 and the functional layer 212 stacked in semiconductor substrate 211 are referred to as substrate.
The internal structure of functional layer 212 is related with chip type.The functional layer 212 provides at least part of transistor
Structure.For example, forming source region and the drain region of transistor in the semiconductor substrate 211 of chip 210, crystal is formed in functional layer 212
The rhythmic structure of the fence of pipe.In the case of chip 210 is 3D memory device chip, the rhythmic structure of the fence in functional layer 212 includes
The gate conductor layer of many levels and multiple interlayer insulating films for space between adjacent gate conductor layer, and run through gate stack knot
The channel column of structure.In the case of chip 210 is drive circuit chip, the rhythmic structure of the fence in functional layer 212 is for example including list
The gate conductor layer of a level.
Then, binder course 213 is formed in the functional layer 212 of chip 210, as shown in Figure 4.
Binder course 213 is dielectric layer, such as is made of silica.Binder course 213 is formed for example, by using magnetron sputtering.
Then, resist layer 201 is formed on the surface of binder course 213, is formed in resist layer 201 using photoetching process
Multiple openings 202, to form exposure mask, as shown in Figure 5.Opening 202, which will be used to form, is used to provide the conductive channel of electrical connection.
Then, it is etched using resist layer 201 as exposure mask, forms multiple access openings 203 in binder course 213,
To which the pattern of resist layer 201 to be transferred in binder course 213, as shown in Figure 6.
The step is for example, by using dry etching (such as reactive ion etching) or wet etching process.Make in dry etching
Etchant is, for example, etching gas, and the etchant used in wet etching is, for example, etching solution.During etching, erosion
The surface that agent reaches binder course 213 via the opening 202 in resist layer 201 is carved, to gradually remove the exposure of binder course 213
Part forms access opening 203 in binder course.Using etchant selectivity and by control etching period, access opening 203 prolongs
Binder course 213 is extended through, the top surface for reaching functional layer 212 stops.Then, using ashing or solvent dissolution removal resist
Layer 201.
Then, filled layer 204 is deposited on binder course 213, as shown in Figure 7.
The step forms filled layer 204 for example, by using magnetron sputtering.The filled layer is for example good more selected from filling capacity
Crystal silicon or metal, such as tungsten.The filled layer 204 fills the access opening 203 in binder course 213, and on the surface of binder course 213
It is laterally extended.
Then, the part on 213 surface of binder course, and further etch-back are located at using etching removal filled layer 204
Filled layer 204, so that the lower part in the 214 filling channel hole 203 of filled layer of remainder, as Fig. 8 shows.
The step is for example, by using dry etching (such as reactive ion etching) or wet etching process.It is not necessarily in this step
Form exposure mask.Using the selectivity of etchant, a part of filled layer 204 is removed relative to binder course 213.It is etched by control
Time can control height of the remainder of filled layer 204 in access opening 203.
Then, the depositing contact layers 205 on binder course 213, as shown in Figure 9.
The step forms contact layer 205 for example, by using magnetron sputtering.The contact layer for example selected from platinum, silver, copper, aluminium metal
Or composition of alloy.The contact layer 205 contacts the top end surface of filled layer 204 in the access opening 203 of binder course 213, to fill out
The top of the access opening 203 in binder course 213 is filled, and is laterally extended on the surface of binder course 213.
Then, the part on 213 surface of binder course is located at using chemical mechanical planarization process removal contact layer 205, made
The top for obtaining the 215 filling channel hole 203 of contact layer of remainder, as Figure 10 shows.
The chemical mechanical planarization process that the step uses, using binder course 213 as stop-layer, so as to completely remove
Contact layer 205 is located at the part on 213 surface of binder course.
The step forms composite channel in chip 210, and binder course 213 includes perforative access opening 203, composite channel packet
Include the filled layer 214 and contact layer 215 of the lower part in filling channel hole 203 and top respectively.As described above, filled layer 214 uses
The good conductive material of filling capacity, contact layer 215 use the good conductive material of bonding performance.Since contact layer 215 is only filled out
Fill the top of channel layer 203, therefore, contact layer 215 will not due to access opening 203 depth-to-width ratio and cause filling difficult.Contact
The conductive material of layer 215 only needs to meet the requirement of metal bonding, thus can be selected from the higher metal material of bond strength.
Then, formation and the composite conducting channel aligned with each other and identical of chip 210 in chip 220, by 210 He of chip
220 binder course is in contact with each other to form semiconductor devices 200, as shown in figure 11.
Chip 220 includes semiconductor substrate 221, and in the functional layer 222 and binder course of the stacking of semiconductor substrate 221
223.Semiconductor substrate 221 is, for example, silicon substrate.Binder course 223 is dielectric layer, such as is made of silica.
The internal structure of functional layer 222 is related with chip type.The functional layer 222 provides at least part of transistor
Structure.For example, forming source region and the drain region of transistor in the semiconductor substrate 221 of chip 220, crystal is formed in functional layer 222
The rhythmic structure of the fence of pipe.In the case of chip 220 is 3D memory device chip, the rhythmic structure of the fence in functional layer 222 includes
The gate conductor layer of many levels and multiple interlayer insulating films for space between adjacent gate conductor layer, and run through gate stack knot
The channel column of structure.In the case of chip 220 is drive circuit chip, the rhythmic structure of the fence in functional layer 222 is for example including list
The gate conductor layer of a level.
Composite channel in chip 220 includes the filled layer 224 and contact layer of the lower part in filling channel hole and top respectively
225。
In bonding process, the composite channel of chip 210 and the composite channel of chip 220 are connected to each other, wherein chip
210 contact layer 215 and the contact layer 225 of chip 220 are in contact with each other and metal bonding, to provide between chip 210 and 220
Electrical connection.
The surface of the binder course 213 of chip 210 is bonding face.Multiple composite channels are distributed on bonding face.According to chip
The quantity of 210 and 220 circuit interconnection design composite channel and position, with provide internal circuit via bonding face electrical connection and
Mechanical connection.
The cross sectional shape of composite channel in chip 210 and 220 is for example rectangle.In alternate embodiments, this section
Face shape can be any one in rectangle, rectangular, triangle, circle, ellipse and polygon.
Semiconductor devices according to an embodiment of the present invention forms the composite channel for electrical connection in binder course.First
The composite channel of chip and the second chip is respectively aligned to, and further, composite channel is electrically connected with internal circuit.The semiconductor device
The composite channel of part includes the filled layer and contact layer for filling the lower part and top in channel hole respectively, and filled layer can choose filling
Filling defect caused by access opening of the packing material of good performance to avoid high-aspect-ratio, contact layer can choose bonding performance
Bond strength and reliability can be improved with the metal material of satisfactory mechanical property, to improve product yield.
In the above description, the technical details such as composition, the etching of each layer are not described in detail.But
It will be appreciated by those skilled in the art that can be by various technological means, come layer, the region etc. for forming required shape.In addition, being
Formation same structure, those skilled in the art can be devised by and process as described above not fully identical method.
In addition, although respectively describing each embodiment above, but it is not intended that the measure in each embodiment cannot be advantageous
Ground is used in combination.
The embodiment of the present invention is described above.But the purpose that these embodiments are merely to illustrate that, and
It is not intended to limit the scope of the invention.The scope of the present invention is limited by appended claims and its equivalent.This hair is not departed from
Bright range, those skilled in the art can make a variety of alternatives and modifications, these alternatives and modifications should all fall in of the invention
Within the scope of.
Claims (18)
1. a kind of semiconductor devices, comprising:
First chip is combined including the first substrate and positioned at the first binder course of first substrate surface, across described first
The first passage hole of layer and first composite channel in the filling first passage hole,
Second chip is combined including the second substrate and positioned at the second binder course of second substrate surface, across described second
The second channel hole of layer and second composite channel in the filling second channel hole,
Wherein, first composite channel include fill respectively the lower part and top in the first passage hole the first filled layer and
First contact layer, second composite channel include the second filled layer for filling the lower part and top in the second channel hole respectively
With the second contact layer, first binder course and second binder course are combined, first contact layer and second contact
Layer is bonded to each other.
2. semiconductor devices according to claim 1, wherein first substrate includes the first semiconductor substrate and is located at
The first functional layer in first semiconductor substrate, second substrate is including the second semiconductor substrate and positioned at described second
The second functional layer in semiconductor substrate.
3. semiconductor devices according to claim 1, wherein first filled layer and first contact layer are by difference
Conductive material composition, second filled layer is made of from second contact layer different conductive materials.
4. semiconductor devices according to claim 3, wherein first filled layer and second filled layer respectively by
It is formed selected from any one of polysilicon and tungsten.
5. semiconductor devices according to claim 3, wherein first contact layer and second contact layer respectively by
Selected from platinum, silver, copper, aluminium metal or its alloy in any one at.
6. semiconductor devices according to claim 1, wherein first composite channel and second composite channel
Cross-sectional shape is respectively any one for being selected from following shape: rectangle, rectangular, triangle, circle, ellipse and polygon.
7. semiconductor devices according to claim 1, wherein first chip and second chip are respectively selected from
Any one in 3D memory device chip and drive circuit chip.
8. the semiconductor devices according to claim 2 or 7, wherein in first chip and second chip extremely
Few one is 3D memory device chip, and the corresponding function layer in first functional layer and second functional layer includes: that grid are folded
Layer structure and channel column, the rhythmic structure of the fence include the separation layer between multiple gate conductor layers and adjacent gate conductors layer,
The channel column runs through the rhythmic structure of the fence.
9. semiconductor devices according to claim 7, wherein at least one in first chip and second chip
A is drive circuit chip, and the corresponding function layer in first functional layer and second functional layer includes: rhythmic structure of the fence,
The rhythmic structure of the fence includes gate conductor layer.
10. -9 described in any item semiconductor devices according to claim 1, wherein described to be combined into bonding.
11. a kind of production method of semiconductor devices, comprising:
Form the first chip, including the first substrate and positioned at first substrate surface the first binder course, pass through described first
The first passage hole of binder course and first composite channel in the filling first passage hole；
Form the second chip, including the second substrate and positioned at second substrate surface the second binder course, pass through described second
The second channel hole of binder course and second composite channel in the filling second channel hole；And
First chip and second chip are bonded together, first binder course and second binder course connect each other
The contact surface of touching, first binder course and second binder course is bonding face,
Wherein, first composite channel include fill respectively the lower part and top in the first passage hole the first filled layer and
First contact layer, second composite channel include the second filled layer for filling the lower part and top in the second channel hole respectively
With the second contact layer, first contact layer and second contact layer are in contact with each other to provide first chip and described
Electrical connection between two chips.
12. production method according to claim 11, wherein first filled layer and first contact layer are by difference
Conductive material composition, second filled layer is made of from second contact layer different conductive materials.
13. production method according to claim 12, wherein first filled layer and second filled layer respectively by
It is formed selected from any one of polysilicon and tungsten.
14. production method according to claim 12, wherein first contact layer and second contact layer respectively by
Selected from platinum, silver, copper, aluminium metal or its alloy in any one at.
15. production method according to claim 11, wherein first composite channel and second composite channel exist
The cross sectional shape of bonding face exposure is respectively any one for being selected from following shape: rectangle, rectangular, triangle, circle, ellipse
Round and polygon.
16. production method according to claim 11, wherein first composite channel and second composite channel point
It is not formed using metal filling processes, the metal filling processes include:
Form the access opening for running through first binder course and the corresponding binder course in second binder course；
The access opening is filled using conductive packing material；
Remove the packing material be located at it is described accordingly in conjunction with the part of layer surface and positioned at the part on the access opening top,
To form the filled layer of filling channel hole lower part；
The access opening is filled using conductive contact material；And
It removes the contact material and is located at the corresponding part in conjunction with layer surface, to form filling channel hole top
Contact layer.
17. production method according to claim 16, wherein remove the packing material using etch-back.
18. production method according to claim 16, wherein remove the contact material using chemical-mechanical planarization.
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| US20020070457A1 (en) * | 2000-12-09 | 2002-06-13 | Samsung Electronics Co., Ltd. | Metal contact structure in semiconductor device and method for forming the same |
| US20020113273A1 (en) * | 2001-02-22 | 2002-08-22 | Samsung Electronics Co., Ltd. | Semiconductor device having contact plug and method for manufacturing the same |
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Application publication date: 20190628 |